WO2024036723A1 - 计数电路及存储器 - Google Patents

计数电路及存储器 Download PDF

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Publication number
WO2024036723A1
WO2024036723A1 PCT/CN2022/124032 CN2022124032W WO2024036723A1 WO 2024036723 A1 WO2024036723 A1 WO 2024036723A1 CN 2022124032 W CN2022124032 W CN 2022124032W WO 2024036723 A1 WO2024036723 A1 WO 2024036723A1
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comparison
output
unit
decoding information
bit
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PCT/CN2022/124032
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English (en)
French (fr)
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黄泽群
孙凯
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长鑫存储技术有限公司
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Priority to US18/365,317 priority Critical patent/US11972789B2/en
Publication of WO2024036723A1 publication Critical patent/WO2024036723A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]

Definitions

  • the present disclosure relates to memory technology, and in particular, to a counting circuit and a memory.
  • DRAM Dynamic Random Access Memory
  • the memory usually needs to have a maximum counting function to support the work of the memory.
  • EpRC Error per Row Counter
  • ECS Error Checking and Clearing
  • Embodiments of the present disclosure provide a counting circuit and a memory.
  • the first aspect of the present disclosure provides a counting circuit, including: a counting module, configured to output the counting value when the counting value exceeds a predetermined threshold; and a decoding module, coupled to the counting module, for Decoding the count value to obtain decoding information corresponding to the count value; wherein the decoding information represents the numerical interval in which the count value is located; a comparison module coupled to the decoding module, Used to compare the decoding information with the historical maximum decoding information, and latch and output the current maximum decoding information.
  • a second aspect of the present disclosure provides a memory, including: a mode register and a counting circuit as described above; wherein the mode register is coupled to the counting circuit and is used to save the counting circuit The maximum decoding information output.
  • the counting module outputs a count value when the count value exceeds a predetermined threshold, and the decoding module decodes the count value output by the counting module to obtain a decoding representing the numerical interval where the count value is located.
  • Information the comparison module compares the decoding information with the historical maximum decoding information, latches and outputs the current maximum decoding information.
  • the decoding module first decodes the current count value, and the comparison module achieves always output by comparing the decoding information corresponding to the current count value and the decoding information corresponding to the historical maximum count value, that is, the historical maximum decoding information.
  • Count function for maximum results The above counting circuit can be well adapted to counting scenarios that need to maintain maximum output results, such as row error counting scenarios.
  • Figure 1 is an example diagram of the architecture of a memory according to an embodiment
  • Figure 2 is an example structural diagram of a memory unit according to an embodiment
  • Figure 3 is an example structural diagram of a counting circuit provided by an embodiment
  • Figure 4 is an example structural diagram of a counting circuit provided by an embodiment
  • Figure 5 is an example structural diagram of a counting circuit provided by an embodiment
  • Figures 6 to 8 are structural diagrams of a comparison unit provided in exemplary embodiments.
  • Figure 9 is a structural example diagram of the first signal generation unit
  • Figure 10 is a structural example diagram of a comparison unit provided by an embodiment
  • Figure 11 is a structural example diagram of the second signal generation unit
  • Figure 12 is a structural example diagram of a comparison unit provided by an embodiment
  • Figure 13 is a structural example diagram of a counting circuit provided by an embodiment
  • Figure 14 is a structural example diagram of a counting circuit provided by an embodiment
  • FIG. 15 is a schematic structural diagram of a memory provided by an embodiment.
  • FIG. 1 is an example diagram of an architecture of a memory according to an embodiment.
  • DRAM is used as an example, including a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a memory array.
  • the memory array is mainly composed of word lines, bit lines and memory cells.
  • the word lines in the memory array extend along the row direction, and the bit lines in the memory array extend along the column direction. The intersection of the word line and the bit line is the memory cell of the memory array.
  • FIG. 2 is an example structural diagram of a memory unit according to an embodiment.
  • the memory unit mainly consists of a transistor M and a capacitor C.
  • the capacitor is used to store data
  • the transistor is used to turn off or on according to the state of the word line.
  • a memory unit can be activated by controlling rows and columns to access the memory unit.
  • the reading scenario as an example: when you need to read the data in a memory unit, you can select the word line of the row where the memory unit is located through the row decoder. Correspondingly, the transistor M in the illustration is turned on, and the bit line signal is passed through. Sensing amplification can sense the state on the capacitor C at this time. For example, if the data stored in the memory cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the memory cell, and vice versa.
  • the writing scenario as an example: when data needs to be written to a certain storage unit, such as writing 1.
  • the word line of the row where the memory cell is located can be selected through the row decoder.
  • the transistor M in the corresponding diagram is turned on.
  • the logic level of the bit line By setting the logic level of the bit line to 1, the capacitor C is charged, that is, writing 1 to the memory cell. .
  • the logic level of the bit line is set to 0, causing the capacitor C to discharge, that is, writing 0 to the memory cell.
  • the maximum counting function needs to be used.
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • the DDR5JEDEC standard stipulates that in order to improve the error checking capability of DDR5DRAM, it is set to perform a complete error on the memory regularly. Check and clear, and record the address information of the row with the most errors in each row of the storage array and the specific number of errors. As an example, after the memory completes a complete error check and clearing, the address information of the row with the largest number of errors will be stored in the memory's mode register MR ⁇ 16:18>. As shown in Figure 1 and Figure 2, inside the memory , the storage unit is divided into rows and columns.
  • a storage bank An area composed of rows and columns is called a storage bank (BANK, referred to as BA).
  • the storage units in a memory share the addressing unit; in each storage group (BANK GROUP referred to as BG) Including multiple memory banks, the address information of the row with the largest number of errors includes but is not limited to the memory group address (BG0 ⁇ BG2) where the row is located, the memory bank address (BA0 ⁇ BA1) where the row is located, and the specific row address of the row. (R0 ⁇ R17);
  • the maximum number of errors will be stored in the mode register MR ⁇ 19>.
  • MR ⁇ 19> uses the error count REC ⁇ 5:0> to record the value range where the maximum number of errors is. Among them, REC ⁇ 5:0> represents the number of errors within the range, and each data bit in REC ⁇ 5:0> represents a decimal value interval. The corresponding relationship is shown in Table 1.
  • Figure 3 is a structural example diagram of a counting circuit provided by an embodiment.
  • the figure includes an EpRC module for counting the number of row errors. Specifically, after the EpRC module detects multiple errors on a line, the count value, the number of errors EpRC ⁇ 5:0>, begins to increase. Each time the number of errors increases by the preset threshold, EpRC ⁇ 5:0> increases by 1. As an example, error numbers EpRC ⁇ 5:0> are counted in binary. Specifically, the EpRC module resets the count value, such as clearing it to zero, every time the row address changes.
  • the decoding module decodes the count value output by the EpRC module and obtains the decoding information that can characterize the numerical range of the count value.
  • the comparison module compares the decoding information with the historical maximum number of row errors and records the larger of the two. The number of errors is used as the current maximum number of row errors, thereby achieving the maximum row error count.
  • the EpRC module will output the number of errors in the line detected this time (EpRC ⁇ 5:0>), and a signal indicating whether the number of errors is less than the threshold (RETC ⁇ 1:0>).
  • the comparison module first Compare this error number (EpRC ⁇ 5:0>) with the maximum number of errors in the previously detected row (REC ⁇ 5:0>) to determine the row address and row error number with the current largest number of errors. Specifically, after reading all the code words in a row each time, the number of errors in the row is compared with the maximum number of row errors in history.
  • the number of errors in the current row is The row address information corresponding to EpRC ⁇ 5:0> and EpRC ⁇ 5:0> will replace the previous maximum error number and row address information and be saved to the error number latch and address latch.
  • the error number of the current row is less than the error number of the previous row, the information of the previous row continues to be stored in the error number latch and address latch.
  • the decoder decodes the number of row errors in the count value latch to obtain decoded data for recording in the mode register.
  • the DDR5JEDEC standard stipulates that the row error count threshold (Row Error Threshold counter, referred to as RETC) can be set.
  • RETC Row Error Threshold counter
  • RETC can be set to 4.
  • a threshold can be set, that is, a row error count threshold.
  • the minimum value of the numerical interval represented by REC ⁇ 0> in REC ⁇ 5:0> is the value set by the RETC, and the maximum value is 2 ⁇ RETC-1. Still taking the RETC value as 4 as an example, the value range represented by REC ⁇ 0> is 4 to 7.
  • X is the data bit of REC.
  • the data bit of REC ⁇ 2> is 2.
  • the numerical range represented by REC ⁇ 1> is 8 ⁇ 15
  • the numerical range represented by REC ⁇ 2> is 16 ⁇ 31
  • the numerical range represented by REC ⁇ 3> is 32 ⁇ 63
  • the numerical range represented by REC ⁇ 4> is 64 ⁇ 127
  • the numerical range represented by REC ⁇ 5> is 128 ⁇ 255.
  • the REC data bit corresponding to the value range is set to 1. For example, assuming the designed value is 76, which falls within the range of 64 to 127, then REC ⁇ 4> is set to 1, and the remaining data bits REC ⁇ 3:0> and REC ⁇ 5> are 0.
  • the error count REC ⁇ 5:0> corresponds one-to-one with the data bits of OP ⁇ 5:0> of the mode register MR ⁇ 19>. If a data bit in REC ⁇ 5:0> is 1, Then the corresponding bit in OP ⁇ 5:0> of MR ⁇ 19> will be set to 1. Based on the above example, OP ⁇ 4> of MR ⁇ 19> is set to 1.
  • FIG 4 is an example structural diagram of a counting circuit provided by an embodiment. As shown in Figure 4, the counting circuit includes:
  • Counting module 11 configured to output the count value when the count value exceeds a predetermined threshold
  • the decoding module 12 is coupled to the counting module 11 and is used to decode the count value and obtain decoding information corresponding to the count value; wherein the decoding information represents the numerical interval in which the count value is located. ;
  • the comparison module 13 is coupled to the decoding module 12 and is used to compare the decoding information with the historical maximum decoding information, latch and output the current maximum decoding information.
  • the counting circuit provided in this embodiment can be applied to various memories. As an example, it can be applied to including but not limited to double-rate synchronous dynamic random access memory (DDR for short).
  • DDR double-rate synchronous dynamic random access memory
  • the counting module 11 is responsible for performing counting. After the counting is completed, if the current counting value exceeds a predetermined threshold, the counting value is output; the decoding module 12 first decodes the counting value output by the counting module 11 to obtain Corresponding decoding information, such as OP ⁇ 5:0>. Specifically, the decoding information represents the numerical interval in which the count value is located.
  • the comparison module 13 compares the current decoding information with the historical maximum decoding information, such as REG ⁇ 5:0>, latches the maximum decoding information between the two and outputs the maximum decoding information. , as the current historical maximum decoding information.
  • the historical maximum decoding information is the decoding information corresponding to the largest count value among the historically obtained count values.
  • the decoded information is a six-bit binary number. This example can be adapted to a row error counting scenario.
  • the decoding information represents the numerical interval in which the count value is located
  • the decoding information is a multi-bit binary number. Different bits of the decoding information correspond to different numerical intervals. The numerical interval corresponding to the high bit is larger than the numerical interval corresponding to the low bit. .
  • each data bit of the decoded information OP ⁇ 5:0> represents a numerical interval
  • OP ⁇ 5>, OP ⁇ 4>, OP ⁇ 3>, OP ⁇ 2>, OP ⁇ 1> and OP ⁇ 0> represents a numerical interval respectively.
  • the numerical intervals represented by each data bit do not overlap and can form a continuous larger numerical interval.
  • the numerical interval represented by the decoding information can be set in advance. For example, if it is suitable for a memory scenario, it can be set with reference to the relevant standards of the memory. Among them, the numerical interval corresponding to the high bit is larger than the numerical interval corresponding to the low bit.
  • the numerical interval corresponding to OP ⁇ 5> is the largest, and the numerical interval corresponding to OP ⁇ 4> is larger than the numerical interval corresponding to OP ⁇ 3>.
  • the size relationship between the numerical intervals here is determined according to the numerical range of the numerical interval. For example, assuming that one numerical interval is 8 to 15 and the other numerical interval is 16 to 31, then the latter is larger than the former.
  • the decoded information can accurately represent the numerical interval in which the count value is located, in one example, since the numerical intervals represented by different bits of the decoded information do not overlap with each other, there is only a one-bit value in the decoded information. Is 1, indicating that the count value corresponding to the decoded information is within the numerical interval corresponding to this bit.
  • decoding module 12 includes a one-hot decoder.
  • the main feature of the embodiment solution shown in Figure 4 is that first, a threshold is set for the output of the count value, that is, the counting module will only output the count value when the count value exceeds the threshold.
  • the count value is first decoded to obtain decoding information that can represent the numerical interval in which the count value is located, and then the decoding information is compared with the decoding information corresponding to the historical count value to determine the maximum decoding information. Information is subsequently recorded to the mode register.
  • the solution of this embodiment no longer needs the EpRC module to output a signal (RETC ⁇ 1:0>) indicating whether the count value is greater than the threshold, thereby reducing the amount of data that needs to be processed, and because the decoding information only needs to represent the count There is no need to know the specific value of the count value, so it is easy to use more simplified data to represent it. For example, only one bit of the decoded value is 1 to represent the numerical range of the count value, so that in the subsequent There is no need to compare all bits in the comparison, thereby simplifying the circuit structure of the comparison module.
  • the solution of this embodiment takes advantage of the above characteristics of the memory row error counting scenario and does not compare the size relationship of the specific count values EpRC ⁇ 5:0>. Instead, the decoding information is obtained by decoding first. Only one bit of the decoded information has a value of 1, and the other bits are all 0, and then comparison and recording are performed, thereby effectively simplifying the circuit structure and reducing the wiring and layout area. Therefore, the solution of this embodiment is particularly suitable for memory scenarios.
  • FIG. 5 is an example structural diagram of a counting circuit provided by an embodiment.
  • the comparison module 13 includes: a comparison unit 21 and a first latch. Unit 22;
  • the first input end of the comparison unit 21 is connected to the decoding module 12, and the second input end of the comparison unit 21 is connected to the output end of the first latch unit 22.
  • the comparison unit 21 is used to convert the decoding information OP ⁇ 5: 0> is compared with the historical maximum decoding information REG ⁇ 5:0> output by the first latch unit 22, and the enable signal MAX is output according to the comparison result;
  • the input terminal of the first latch unit 22 is connected to the decoding module 12 , the enable terminal of the first latch unit 22 is connected to the output terminal of the comparison unit 21 , and the first latch unit 22 is used to latch the signal in response to the enable signal MAX. Save and output the current maximum decoding information.
  • the historical maximum decoding information REG ⁇ 5:0> recorded in the first latch unit 22 is in an initial state, for example, it can be empty or each data bit is 0 by default.
  • the decoding module 12 obtains the first decoding information OP ⁇ 5:0> based on the count value output by the counting module 11 for the first time.
  • the comparison unit 21 compares the decoding information OP ⁇ 5:0> with the current output of the first latch unit 22.
  • the historical maximum decoding information REG ⁇ 5:0> (REG ⁇ 5:0> is empty or 0 at this time) is compared.
  • the comparison unit 21 outputs a valid enable signal, such as the high-level enable signal MAX.
  • the first latch unit 22 responds to the valid enable signal and performs latch processing, that is, the decoding information OP ⁇ 5:0 output by the decoding module 12 >Latch and output it as the new historical maximum decoding information REG ⁇ 5:0>. That is to say, at this time, the output REG ⁇ 5:0> of the first latch unit 22 is consistent with the aforementioned decoding information OP ⁇ 5:0>.
  • the decoding module 12 When counting again, the decoding module 12 obtains the corresponding decoding information OP ⁇ 5:0> based on the count value output by the counting module 11 each time and transmits it to the comparison unit 21; the comparison unit 21 transfers the current decoding information OP ⁇ 5 :0> is compared with the decoding information REG ⁇ 5:0> currently output by the first latch unit 22, if this time the decoding information OP ⁇ 5:0> is greater than the current historical maximum decoding information REG ⁇ 5: 0>, then a valid enable signal is output again to update the output REG ⁇ 5:0> of the first latch unit 22 to be consistent with the current decoding information OP ⁇ 5:0>.
  • the first latch unit 22 does not transmit the received decoding information internally, and the first latch unit 22 continues to latch and output the historical maximum decoding information REG ⁇ 5:0> internally. Subsequently, the above solution is executed for each count value output by the counting module 11 until the entire counting is completed. For example, all row error counts in the memory are completed. At this time, the output of the first latch unit 22 is the error count value of all rows. Maximum count value.
  • the comparison unit 21 is configured to output a valid enable signal when the decoding information output by the decoding module 12 is greater than the historical maximum decoding information output by the first latch unit 22, and when the decoding module 12 When the output decoding information is not greater than the historical maximum decoding information output by the first latch unit 22, an invalid enable signal is output; the first latch unit 22 is used to latch and output the decoded signal in response to a valid enable signal.
  • the decoding information output by the code module 12, and in response to the invalid enable signal maintains the output of the historical maximum decoding information.
  • a valid enable signal and an invalid enable signal can be characterized by different signal states, such as a high level state and a low level state.
  • the comparison unit outputs an enable signal based on the comparison result between the current decoding information and the historical maximum decoding information, so that the first latch unit selects whether to update the latch in response to the enable signal, thereby using a relatively simplified circuit. Achieve always outputting the current maximum decoding information.
  • Figure 6 is an example structural diagram of a comparison unit provided by an embodiment.
  • the comparison unit 21 includes: a plurality of comparison sub-units 31 and an output unit 32; wherein the plurality of comparison sub-units and decoding information Each bit corresponds to one-to-one;
  • Each comparison subunit 31 receives the corresponding bit signal and the corresponding characteristic signal in the decoded information, and is used to output a result signal according to the comparison result between the bit signal and the characteristic signal; wherein the value of the characteristic signal represents the Whether there is a bit in the historical maximum decoding information REG ⁇ 5:0> that has a value of 1 and is not lower than the corresponding bit of the comparison subunit 31;
  • the output unit 32 is used to determine whether to output a valid or invalid enable signal MAX according to the result signal output by each comparison subunit 31.
  • the characteristic information input to each comparison sub-unit represents whether there is a bit with a value of 1 and not lower than the corresponding bit of the comparison sub-unit in the currently recorded historical maximum decoding information. It can be understood that each bit of the decoded information represents a numerical interval, and the higher the bit, the larger the numerical interval. Combined with the characteristic that the bit with a value of 1 in the decoding information represents the numerical interval where the count value is located, by comparing the level of the bit with a value of 1 in the decoding information corresponding to the two count values, the two count values can be reflected The size relationship is thus determined to determine the decoding information corresponding to the maximum count value, that is, the maximum decoding information.
  • the decoding information corresponding to a certain count value A is 000010
  • the decoding information corresponding to another count value B is 010000
  • the comparison subunit corresponds to each bit of the decoded information one-to-one.
  • the decoded information is a six-bit binary number.
  • the six comparison subunits in the figure respectively correspond to six bits of the decoded information. As shown in the figure, it includes comparison subunits corresponding to OP ⁇ 5> ⁇ OP ⁇ 0>, and each comparison subunit receives corresponding decoding information bits OP ⁇ ...> and corresponding characteristic signals.
  • the comparison subunit receives the corresponding bit signal OP ⁇ 5> and the corresponding characteristic signal.
  • the characteristic signal represents whether there is a value of 1 and no less than 1 in the historical maximum decoding information.
  • the comparison subunit corresponds to the bit bit (that is, the highest bit).
  • the comparison subunit in the example corresponds to the highest bit of the decoding information. Therefore, the bits that are not lower than the highest bit in the historical maximum decoding information are only the historical bits.
  • the highest bit of the maximum decoding information is REG ⁇ 5>, so the characteristic signal received by the comparison subunit of the example represents whether the value of the highest bit of the historical maximum decoding information REG ⁇ 5> is 1.
  • the decoding information output by the decoding module Based on the decoding information output by the decoding module and the historical maximum decoding information, it can be compared through two comparison logics: one is to find the bits that are 1 in the two, and compare the bits that are 1 in the two, as The value of the decoding information with a higher bit of 1 is greater. If they are the same, it means that the decoding information output by the decoding module is equal to the historical maximum decoding information; the other is to compare the two bits in sequence from high to low. Value, whichever bit appears first as 1 will have a greater value. If they are the same, they are equal.
  • a characteristic signal of 1 can be used to indicate that there is a bit with a value of 1 and not lower than the corresponding bit of the comparison subunit in the historical maximum decoding information; a characteristic signal of 0 can be used to indicate that there is no such bit in the historical maximum decoding information.
  • the bits whose value is 1 and not lower than the corresponding bit of the comparison subunit, that is, the bits whose value is not lower than the corresponding bit of the comparison subunit are all 0. Still taking the comparison subunit corresponding to the highest bit as an example, in actual scenarios, the following situations may occur:
  • each bit is compared and judged by comparing whether each bit in the decoded information is 1 and whether there is a 1 in the same bit and a higher bit in the historical maximum decoded information.
  • the control output unit 32 outputs a valid or invalid enable signal.
  • the result signal output by any comparison sub-unit 31 represents the value of the corresponding bit of the comparison sub-unit 31: 1 and the values of bits not lower than this bit in the historical maximum decoding information are all 0, then a valid enable signal is output.
  • each comparison subunit 31 includes: a first NOT gate 311 and a first NOR gate 312;
  • the input terminal of the first NOT gate 311 receives the corresponding bit signal in the decoded information, and the output terminal of the first NOT gate 311 is connected to the first input terminal of the first NOR gate 312;
  • the second input terminal of the first NOR gate 312 receives the characteristic signal corresponding to the comparison sub-unit 31 , and the output terminal of the first NOR gate 312 is connected to the output unit 32 .
  • the first NOT gate 311 when the bit signal in the decoded information is 1, the first NOT gate 311 outputs 0. Whether the output of the first NOR gate 312 is 1 depends on the characteristic signal. If the characteristic signal represents the historical maximum decoded information that does not Bits lower than this bit are all 0. For example, if the characteristic signal is 0, then the result signal output by the first NOR gate 312 is 1. Correspondingly, the output unit outputs a valid enable signal. When the bit signal in the decoded information is 0, the first NOT gate 311 outputs 1. Regardless of whether the value of the characteristic signal is 1, the result signal output by the first NOR gate 312 is 0.
  • the output of the output unit Depending on the output of other first NOR gates, as long as there is a first NOR gate with an output of 1, it means that the bit signal received by the comparison subunit is 1 and the historical maximum decoding information is not lower than this bit.
  • the bits are all 0, which means that the bits with a value of 1 in the decoding information output by the decoding module are higher than the bits with a value of 1 in the historical maximum decoding information.
  • the decoding information output by the decoding module is greater than the historical maximum decoding. information, it is necessary to update the historical maximum decoding information to the decoding information output by the decoding module.
  • the output unit outputs a valid enable signal, otherwise it outputs an invalid enable signal.
  • the party outputs a result signal of 1; otherwise, for example, the bit with a value of 1 in the decoding information is higher than the bit with a value of 1 in the historical maximum decoding information.
  • the bits with a value of 1 are the same, or the bits with a value of 1 in the decoded information are lower than the bits with a value of 1 in the historical maximum decoded information, a result signal of 0 is output.
  • This example uses the characteristics of decoded information to implement the comparison subunit through NOT gates and NAND gates. Using conventional device structures can effectively simplify the circuit structure and reduce costs.
  • the number of characteristic signals corresponding to each comparison subunit is one. That is, a signal is used to represent whether there is a bit with a value of 1 among the bits that are not lower than the corresponding bit of the comparison subunit in the historical maximum decoding information.
  • conventional devices can be used to implement the comparison subunit. Therefore, in order to adapt the characteristic signals to conventional devices, in this example, the number of characteristic signals corresponding to each comparison subunit is one, thereby effectively reducing the device input ports and simplifying the circuit wiring.
  • each comparison sub-unit 31 also includes: a first signal generation unit 313; the input end of the first signal generation unit 313 receives the historical maximum decoding For all bit signals in the information that are not lower than the corresponding bits of the comparison subunit 31, the first signal generation unit 313 is configured to output a characteristic signal with a value of 1 when the value of any one of the received bit signals is 1.
  • each comparison subunit corresponds to a first signal generation unit.
  • Each first signal generation unit is used to generate a characteristic signal input to the corresponding comparison sub-unit, and the first signal generation unit only generates one characteristic signal. Specifically, the first signal generation unit is used to detect whether there is a bit with a value of 1 in all bit signals that are not lower than the corresponding bit of the comparison sub-unit in the historical maximum decoding information.
  • the first signal generation unit in the comparison subunit is used to detect whether there is a bit with a value of 1 in REG ⁇ 5> ⁇ REG ⁇ 3>. If any bit is 1, the first signal generation unit outputs 1 , otherwise output 0.
  • Figure 9 is a structural example diagram of the first signal generation unit.
  • the first signal generation unit 313 includes: at least one first generation sub-unit 41;
  • Each first generating subunit 41 includes: a second NOR gate 411 and a second NOT gate 412; the input terminal of the second NOR gate 411 serves as the input terminal of the first generating subunit 41, and the output of the second NOT gate 412 terminal serves as the output terminal of the first generating subunit 41, and the output terminal of the second NOR gate 411 is connected to the input terminal of the second NOT gate 412;
  • each first generation subunit 41 is connected to some or all bits in the historical maximum decoding information that are not lower than the corresponding bits of the comparison subunit.
  • the combination result of all the bits connected to the first generation subunit 41 is All bits in the historical maximum decoding information that are no less than the corresponding bits of the comparison subunit;
  • Each first generation subunit 41 except the first one is connected to the output end of the first generation subunit 41 of the previous stage, and the last first generation subunit 41 outputs the characteristic signal.
  • the number of the first generating sub-unit 41 can be set to only one, or it can be set to multiple according to the number of all bits not less than the corresponding bits of the comparison sub-unit and the number of input terminals of the second NOR gate, which are not used here.
  • the figure only illustrates the structure of the first signal generation unit by combining the characteristic signal of the comparison sub-unit corresponding to OP ⁇ 1> used to generate decoding information as an example, and does not limit other comparison sub-units. Structure of the first signal generating unit of the unit.
  • the first signal generation unit 313 corresponding to OP ⁇ 1> in the example in the figure includes two first generation sub-units 41, and the input signal of one of the first generation sub-units 41 includes REG ⁇ 5> ⁇ REG ⁇ 3> , the input signal of the other first generation sub-unit 41 includes REG ⁇ 2> ⁇ REG ⁇ 1>.
  • three first generating sub-units 41 may also be provided, in which the input signal of one first generating sub-unit 41 includes REG ⁇ 5> ⁇ REG ⁇ 4>, and the input signal of the other first generating sub-unit 41
  • the signals include REG ⁇ 3> ⁇ REG ⁇ 2>, and the last input signal of the first generation subunit 41 includes REG ⁇ 1>.
  • the second NOR gate outputs 0, and the corresponding second NOT gate outputs 1. Since the outputs of the first generation subunits of the previous stages are also used as the input of the first generation subunit of the subsequent stage, if the signal output by any first generation subunit is 1, then the final output of the first signal generation unit will be The characteristic signal is 1, so that if it is detected that the value of any bit in all bit signals not lower than the corresponding bit of the comparison subunit in the historical maximum decoding information is 1, then the characteristic signal with the value 1 is output.
  • a first signal generation unit is provided in each comparison subunit to provide each comparison subunit with one characteristic signal.
  • the enable signal is output through the result signal of the comparison between the characteristic signal and the decoding signal. , to achieve the update of maximum decoding information.
  • the number of characteristic signals corresponding to at least one comparison subunit is multiple.
  • the number of characteristic signals corresponding to each comparison subunit can be determined according to the number of bits that the characteristic signal corresponding to the comparison subunit needs to represent. For example, assume that a certain comparison subunit (such as OP ⁇ 5> corresponds to The characteristic signal of the comparison subunit) needs to represent whether the value of a bit in the historical maximum decoding information is 1, then the number of corresponding characteristic signals is one (for example, REG ⁇ 5>); and when the bit corresponding to the comparison subunit When the bit is lower and the corresponding characteristic signal needs to represent the value of one bit in the historical maximum decoding information, the number of characteristic signals can be multiple, thereby effectively simplifying the circuit structure by using devices with multiple input ports.
  • a certain comparison subunit such as OP ⁇ 5> corresponds to The characteristic signal of the comparison subunit
  • the comparison unit 21 also includes a second signal generation unit 33;
  • the second signal generating unit 33 is configured to output a corresponding characteristic signal according to whether there is a bit with a value of 1 and not lower than a predetermined bit in the historical maximum decoding information.
  • the second signal generation unit 33 is responsible for providing characteristic signals of part of the comparison subunits.
  • the predetermined bits can be selected randomly. For example, for REG ⁇ 5:0>, the predetermined bits can be selected as REG ⁇ 3> and REG ⁇ 1>.
  • the characteristic signal output by the second signal generation unit 33 includes REG ⁇ 345> and REG ⁇ 12345>, where REG ⁇ 345> represents whether there is a bit with a value of 1 in the historical maximum decoding information REG ⁇ 5:0> that is not lower than REG ⁇ 3>, REG ⁇ 12345 >Indicates whether there is a bit with a value of 1 in the bits not lower than REG ⁇ 1> in the historical maximum decoding information REG ⁇ 5:0>. It should be noted that the figure is only an example. In actual applications, any comparison subunit can directly input all bit signals (as characteristic signals) that are not lower than the bit corresponding to the comparison subunit.
  • the plurality of comparison sub-units 31 include a first comparison sub-unit 311 and a second comparison sub-unit 312; wherein the characteristic signal corresponding to the first comparison sub-unit 311 includes no less than the first one in the historical maximum decoding information. All bit signals of the bits corresponding to the comparison sub-unit 311; the characteristic signal corresponding to the second comparison sub-unit 312 includes the signal output by the second signal generation unit 33, and the predetermined bit is the bit corresponding to the second comparison sub-unit 312 in the decoded information.
  • the characteristic signal of the comparison sub-unit includes REG ⁇ 5>; for the comparison sub-unit corresponding to OP ⁇ 4>, the characteristics of the comparison sub-unit The signal includes REG ⁇ 5> and REG ⁇ 4> and REG ⁇ 5>; for the comparison subunit corresponding to OP ⁇ 3>, the characteristic signal of the comparison subunit includes REG ⁇ 345> provided by the second signal generation unit 33; for the comparison subunit corresponding to OP ⁇ 2>, the characteristic signal of the comparison subunit includes REG ⁇ 2> and REG ⁇ 345> provided by the second signal generation unit 33; for the comparison subunit corresponding to OP ⁇ 1>, the comparison subunit The characteristic signal of the unit includes REG ⁇ 12345> provided by the second signal generation unit 33; for the comparison subunit corresponding to OP ⁇ 0>, the characteristic signal of the comparison subunit includes REG ⁇ 0> and the REG ⁇ 12345> provided by the second signal generation unit 33.
  • the first comparison subunit includes a comparison subunit corresponding to OP ⁇ 5> and a comparison subunit corresponding to OP ⁇ 4>;
  • the second comparison subunit includes a comparison subunit corresponding to OP ⁇ 3> and The comparison subunit corresponding to OP ⁇ 1>.
  • the second signal generation unit provides the characteristic signals of part of the comparison subunits. Taking advantage of the multi-port characteristics of some devices, the comparison subunits with sufficient number of ports can be directly connected to the historical maximum decoding information.
  • the characteristic signal provided by the second signal generation unit can be used, and there is no need to generate a special characteristic signal for each comparison subunit. Thereby, the structure of the second signal generating circuit is simplified and the complexity of the overall circuit is reduced.
  • the plurality of comparison sub-units 31 include: a third comparison sub-unit 313;
  • the characteristic signal corresponding to the third comparison sub-unit 313 includes the signal output by the second signal generation unit 33 and the bit signal corresponding to the third comparison sub-unit 313 in the historical maximum decoding information.
  • the predetermined position is the third comparison sub-unit in the decoding information.
  • the characteristic signal received by the comparison subunit not only includes the characteristic signal REG ⁇ 345> provided by the second signal generation unit 33, but also receives the signal of the corresponding bit of the comparison subunit in the historical maximum decoding information, that is, REG ⁇ 2> .
  • the circuit structure of the signal generation unit can be simplified, and the comparison subunit can be implemented.
  • the unit compares the characteristic signal and the decoded signal to implement subsequent processing.
  • Figure 11 is an example of the structure of the second signal generation unit. As shown in Figure 11, it still includes REG ⁇ 3> and REG ⁇ 1 in predetermined bits. >As an example, the second signal generation unit 33 includes: a second NOR gate 331, a second NOT gate 332, and a third NOR gate 333 and a third NOT gate 334;
  • the input terminals of the second NOR gate 331 are respectively connected to the first three bit signals REG ⁇ 5> ⁇ REG ⁇ 3> of the historical maximum decoded information, and the output terminals of the second NOR gate 331 are connected to the input terminals of the second NOT gate 332 , the output terminal of the second NOT gate 332 outputs the signal REG ⁇ 345>;
  • the input terminals of the third NOR gate 333 are respectively connected to the output terminals of the second NOT gate 332 and the bit signals REG ⁇ 2> ⁇ REG ⁇ among the bits whose historical maximum decoding information is not less than the predetermined bits, except for the first three bits. 1>, the output terminal of the third NOR gate 333 is connected to the input terminal of the third NOT gate 334, and the output terminal of the third NOT gate 334 outputs the signal REG ⁇ 12345>.
  • the combination of the second signal generation unit and the signal of each bit in the historical maximum decoding information provides a characteristic signal for each comparison sub-unit, and comparison is performed through the characteristic signal and the decoding signal.
  • the result signal outputs the enable signal to realize the update of the maximum decoding information.
  • the output unit is controlled to output a valid or invalid enable signal.
  • the output unit 32 is specifically used if the result signal output by any comparison sub-unit 31 is the first value, a valid enable signal is output; wherein, the first value represents the value of the corresponding bit signal in the decoding information received by the comparison subunit 31 is 1 and the bit in the historical maximum decoding information is not lower than this bit.
  • the bit values are all 0.
  • the first value can be 1.
  • the result signal output by a certain comparison subunit when the result signal output by a certain comparison subunit is 1, it means that the value of the corresponding bit of the comparison subunit is 1, and all bits not lower than this bit in the historical maximum decoding information are 0.
  • the output unit detects that any result signal is 1, that is A valid enable signal is output, so that the first latch unit 22 updates the maximum decoding information to the decoding information output by the decoding module this time, thereby outputting the current maximum decoding information.
  • FIG. 12 is a structural example diagram of an output unit provided by an embodiment.
  • the output unit 32 includes: a plurality of fourth NOR gates 321 and a first NAND gate 322;
  • the input terminals of the four NOR gates 321 are respectively connected to the output terminals of the comparison subunits 31 corresponding to the adjacent bits of the decoded information, and the output terminals of each fourth NOR gate 321 are connected to the input terminals of the first NAND gate 322 , the output terminal of the first NAND gate 322 outputs an enable signal.
  • conventional device NOR gates and NAND gates are used to output a valid enable signal when any result signal is detected to be 1, thereby effectively simplifying the circuit and reducing costs.
  • the figure is only an example, and the illustrated structure of the output unit can also be implemented in combination with other implementation structures of the comparison unit.
  • FIG. 13 is an example structural diagram of a counting circuit provided by an embodiment.
  • the first latch unit 22 includes: a first latch 221; an input terminal of the first latch 221. Connected to the decoding module 12 , the enable terminal of the first latch 221 is connected to the output terminal of the comparison unit 21 , and the output terminal of the first latch 221 is connected to the second input terminal of the comparison unit 21 .
  • the latch is used to update the latched decoding information or maintain the original decoding information in response to the validity or invalidation of the enable signal, so that the maximum decoding information is always output based on the simplified circuit.
  • the circuit further includes: an address module 14; the comparison module 13 further includes: a second latch unit 23;
  • the address module 14 is used to output address information corresponding to the count value; where the address information includes but is not limited to: storage group address, storage bank address and row address.
  • the input end of the second latch unit 23 is connected to the address module 14, the enable end of the second latch unit 23 is connected to the output end of the comparison unit 21, and the second latch unit 23 is used to respond to a valid enable signal, Output the address information output by the address module 14; and, in response to the invalid enable signal, maintain the address information corresponding to the historical maximum number of row errors.
  • whether the enable signal output by the comparison unit is valid is determined based on the size relationship between the decoding information output by the decoding module this time and the historical maximum decoding information in the first latch unit.
  • the enable signal is used to control whether the first latch unit updates the latched error number and also controls whether the second latch unit updates the row address information.
  • the enable signal when the enable signal is valid, it means that the decoding information this time is greater than the historical maximum decoding information, then while updating the maximum row error number, the second latch unit responds to the valid enable signal and changes the row address
  • the row address information corresponding to the decoding information output by the module this time is updated to the internal latch output, replacing the row address information corresponding to the historical maximum decoding information.
  • the maximum error number counting function in the row error counting scenario of the memory can be realized.
  • the counting module outputs a count value when the count value exceeds a predetermined threshold.
  • the decoding module decodes the count value output by the counting module to obtain decoding information that represents the numerical interval where the count value is located. Compare The module compares the decoding information with the historical maximum decoding information, latches and outputs the current maximum decoding information. In the above scheme, the decoding module first decodes the current count value. Only one bit in the obtained decoding information is 1 to represent the numerical interval where the count value is located. The comparison module compares the decoding corresponding to the current count value.
  • the circuit structure of the comparison module can be greatly simplified, and the maximum count can be determined
  • the decoding information corresponding to the result is stored in the register, so that the maximum count can be achieved through a circuit with a more simplified structure. It can be well suited for counting scenarios that need to maintain the output of the maximum result, such as row error counting scenarios.
  • Figure 15 is a schematic structural diagram of a memory provided by an embodiment. As shown in Figure 15, the memory includes: a mode register 1 and a counting circuit 2 as described in any of the previous examples; wherein,
  • the mode register 1 is coupled to the counting circuit 2 and is used to store the maximum decoding information output by the counting circuit 2.
  • the mode register 1 is also used to store the address information of the row corresponding to the maximum decoding information.
  • DRAM is used as an example: Based on the foregoing solution, the counting circuit decodes the number of row errors based on the detection status of the current row when the number of row errors exceeds a predetermined threshold, and uses the decoded value obtained by the decoding. The decoding information is compared with the historical maximum decoding information; if the decoding information obtained this time is greater than the historical maximum decoding information, the current decoding information will be used as the current maximum decoding information, otherwise the historical maximum decoding information will continue to be used as the current maximum decoding information.
  • the maximum decoding information is obtained until the detection of all rows is completed, and the final maximum decoding information is obtained.
  • the maximum decoding information represents the numerical interval in which the maximum number of line errors is located.
  • the counting circuit transmits the maximum decoding information without further decoding to the mode register used to record the maximum number of line errors.
  • the counting circuit also transmits the address information of the line corresponding to the maximum decoding information to the user. In the mode register that records the row address information corresponding to the maximum number of row errors, the scenario of counting the number of row errors in the memory is implemented.
  • the counting circuit outputs the number of row errors when the number of row errors exceeds a predetermined threshold, decodes the number of row errors, obtains decoding information representing the numerical interval in which the number of row errors is located, and decodes the number of row errors.
  • the information is compared with the historical maximum decoding information, latches and outputs the current maximum decoding information and the corresponding row address information to the mode register.
  • the current count value is first decoded, and by comparing the decoding information corresponding to the current line error number and the decoding information corresponding to the historical maximum line error number, only one bit of the decoding information obtained is 1, that is, It can represent the numerical interval in which the count value is located.
  • the comparison module compares the decoding information corresponding to the current count value and the decoding information corresponding to the historical maximum count value, that is, the historical maximum decoding information, since both of them have only 1 bit, 1 data, so the circuit structure of the comparison module can be greatly simplified, and the decoding information corresponding to the maximum counting result can be determined and stored in the register, so that the maximum counting can be achieved through a circuit with a more simplified structure, which can be well adapted to row errors. Counting scenes.

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Abstract

本公开提供一种计数电路及存储器，计数电路包括：计数模块，用于在计数值超过预定阈值时，输出所述计数值；译码模块，耦接于所述计数模块，用于对所述计数值进行译码，获得所述计数值对应的译码信息；其中，所述译码信息表征所述计数值所在的数值区间；比较模块，耦接于所述译码模块，用于将所述译码信息和历史最大译码信息进行比较，锁存并输出当前最大的译码信息。

Description

计数电路及存储器
本公开要求于2022年8月17日提交中国专利局、申请号为202210989367.5、申请名称为“计数电路及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器技术，尤其涉及一种计数电路及存储器。
背景技术
伴随存储器技术的发展，存储器被广泛应用在多种领域，比如，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的使用非常广泛。
实际应用中，存储器通常需要具备最大计数功能，以支持存储器的工作。比如，集成电路设计中错误检查与清除(简称ECS)中进行行错误计数(Error per Row Counter，简称EpRC)时，需要根据多次的错误计数结果，始终输出错误数最大的结果。因此，需要提供一种计数电路来实现上述计数功能。
发明内容
本公开的实施例提供一种计数电路及存储器。
根据一些实施例，本公开第一方面提供一种计数电路，包括：计数模块，用于在计数值超过预定阈值时，输出所述计数值；译码模块，耦接于所述计数模块，用于对所述计数值进行译码，获得所述计数值对应的译码信息；其中，所述译码信息表征所述计数值所在的数值区间；比较模块，耦接于所述译码模块，用于将所述译码信息和历史最大译码信息进行比较，锁存并输出当前最大的译码信息。
根据一些实施例，本公开第二方面提供一种存储器，包括：模式寄存器以及如前所述的计数电路；其中，所述模式寄存器，耦接于所述计数电路，用于保存所述计数电路输出的最大译码信息。
本公开实施例提供的计数电路及存储器中，计数模块在计数值超过预定阈值时输出计数值，译码模块对计数模块输出的计数值进行译码，获得表征计数值所在的数值区间的译码信息，比较模块将所述译码信息和历史最大译码信息进行比较，锁存并输出当前最大的译码信息。上述方案中，译码模块先对当前的计数值进行译码，比较模块通过比较当前计数值对应的译码信息和历史最大计数值对应的译码信息，即历史最大译码信息，实现始终输出最大结果的计数功能。上述计数电路能够很好地适用于需要保持输出最大结果的计数场景，比如行错误计数场景。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开实施例的原理。
图1为一实施例示出的存储器的架构示例图；
图2为一实施例示出的存储单元的结构示例图；
图3为一实施例提供的计数电路的结构示例图；
图4为一实施例提供的计数电路的结构示例图；
图5为一实施例提供的计数电路的结构示例图；
图6～图8为示例的实施例提供的比较单元的结构示例图；
图9为第一信号生成单元的结构示例图；
图10为一实施例提供的比较单元的结构示例图；
图11为第二信号生成单元的结构示例图；
图12为一实施例提供的比较单元的结构示例图；
图13为一实施例提供的计数电路的结构示例图；
图14为一实施例提供的计数电路的结构示例图；
图15为一实施例提供的一种存储器的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开中的用语“包括”和“具有”用以表示开放式的包括在内的意思，并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记或区分使用，不是对其对象的先后顺序或数量限制。此外，附图中的不同元件和区域只是示意性示出，因此不限于附图中示出的尺寸或距离。
下面以具体的实施例对技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同 或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图1为一实施例示出的存储器的架构示例图，如图1所示，以DRAM作为示例，包括数据输入/输出缓冲、行解码器、列解码器、感测放大器以及存储阵列。存储阵列主要由字线、位线和存储单元组成。存储阵列中的字线沿行方向延伸，存储阵列中的位线沿列方向延伸，字线与位线的交叉处为存储阵列的存储单元。
其中，每个存储单元用于存储一个位(bit)的数据。如图2所示，图2为一实施例示出的存储单元的结构示例图，存储单元主要由晶体管M和电容C组成。其中，电容用于存储数据，晶体管用于根据字线状态，关断或导通。
可以通过控制行和列来激活某个存储单元，以实现对该存储单元的访问。结合读取场景作为示例：需要读取存储单元中的数据时，可以通过行解码器选中该存储单元所在行的字线，相应的，图示中的晶体管M导通，通过对位线信号的感测放大就可以感知到此时电容C上的状态。例如，如果存储单元中存储的数据为1，那么晶体管M导通后就会从存储单元的位线上读到1，反之也是同样的道理。另外，结合写入场景作为示例：需要向某存储单元中写入数据时，比如写入1。可以通过行解码器选中该存储单元所在行的字线，相应的图示中的晶体管M导通，通过将位线的逻辑电平设为1，使得电容C充电，即向存储单元写入1。反之，如果要写入0，那么位线的逻辑电平设为0，使得电容C放电，即向存储单元写入0。
实际应用中，为了支持存储器的工作，需要使用最大计数功能。比如，以双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，简称DDR SDRAM)示例，在DDR5JEDEC标准中规定，为了提高DDR5DRAM进行错误检查的能力，设置定期对存储器进行一次完整的错误检查与清除，并记录存储阵列的各行中存在最多错误的行的地址信息以及具体的错误数。作为示例，等到存储器完成一次完整的错误检查与清除后，错误数最大的行的地址信息将会保存在存储器的模式寄存器MR<16:18>，结合图1和图2所示，在存储器内部，存储单元被划分成行和列，一片由行和列组成的区域称为存储体(BANK，简称BA)，一个存储器中的存储单元共用寻址单元；每个存储组(BANK GROUP简称BG)中包括多个存储体，错误数最大的行的地址信息包括但不限于该行所在的存储组地址(BG0～BG2)、该行所在的存储体地址(BA0～BA1)以及该行的具体行地址(R0～R17)；此外，最大错误数将会保存在模式寄存器MR<19>中，MR<19>中通过错误计数REC<5:0>来记录最大错误数所在的数值区间。其中，REC<5:0>表示在范围内的错误数，REC<5:0>中的每个数据位代表一个十进制的数值区间，其对应关系如表1所示。
表1
错误计数的数据位 数值区间
REC<0> 4～7
REC<1> 8～15
REC<2> 16～31
REC<3> 32～63
REC<4> 64～127
REC<5> 128～255
结合DDR5中错误检查与清除的场景进行方案示例：实际应用中，图3为一实施例提供的计数电路的结构示例图，图中包括用于执行行错误数的计数的EpRC模块。具体的，EpRC模块检测到行上多个错误后，计数值即错误数EpRC<5:0>开始增加，每增加预设阈值的错误数，EpRC<5:0>加1。作为示例，错误数EpRC<5:0>采用二进制计数。具体的，EpRC模块在每次行地址换行时都会重置计数值，比如清零。译码模块对EpRC模块输出的计数值进行译码，得到能够表征计数值所在数值区间的译码信息之后，比较模块将该译码信息与历史最大行错误数进行比较，记录两者中较大的错误数，作为当前的最大行错误数，从而实现最大行错误计数。
如图3所示，EpRC模块会输出本次检测的行中的错误数(EpRC<5:0>)，以及表征该错误数是否小于阈值的信号(RETC<1:0>)，比较模块先将该错误数(EpRC<5:0>)与之前检测的行中的最大错误数(REC<5:0>)进行比较，确定当前错误数最大的行地址和行错误数。具体的，在每次读取完一行中所有码字后，将该行中的错误数与历史最大行错误数进行比较，如果历史最大行错误数小于当前行的错误数，那么当前行的错误数EpRC<5:0>和EpRC<5:0>对应的行地址信息将会替代之前的最大错误数和行地址信息，保存到错误数锁存器和地址锁存器中。反之，如果当前行的错误数小于之前行的错误数，那么之前行的信息继续保存在错误数锁存器和地址锁存器中。之后，译码器对计数值锁存器中的行错误数进行译码得到译码数据，以便记录在模式寄存器中。
实际应用中，为了避免一些非必要的故障修正，比如错误数量很少不会影响存储器正常工作的情况，在DDR5JEDEC标准中规定了，可以设置行错误计数阈值(Row Error Threshold counter，简称RETC)。作为示例，RETC可以设置为4。当行错误数小于行错误计数阈值时，该计数值将不会被记录在模式寄存器中。作为示例，本方案实施例中可以设定阈值，即行错误计数阈值。通过设置RETC的值，可以屏蔽小于RETC的错误数。比如，假设检查出的错误数不超过RETC的话，则计数模块不再输出计数值，相应也无需执行后续处理。
基于上述情形，REC<5:0>中REC<0>代表的数值区间的最小值为所述RETC设置的值，最大值为2×RETC‐1。仍结合RETC的值为4进行举例，REC<0>代表的数值区间为4～7。此外，对于REC<5:1>中的每个数据位，每一数据位代表的数值区间的最小值被定义为REC<X> min＝RETC×2 X，最大值被定义为REC<X> max＝2×(RETC×2 X)-1。其中，X为REC的数据位，例如，REC<2>的数据位为2。结 合RETC的值为4进行举例，如上表所示，REC<1>代表的数值区间为8～15，REC<2>代表的数值区间为16～31，REC<3>代表的数值区间为32～63，REC<4>代表的数值区间为64～127，REC<5>代表的数值区间为128～255。根据计数模块输出的计数值落在哪个数值区间，该数值区间对应的REC数据位被置1。举例来说，假设计数值为76，落在64～127的数值区间，则REC<4>被设置为1，其余数据位REC<3:0>以及REC<5>为0。另外，在模式寄存器中，错误计数REC<5:0>与模式寄存器MR<19>的OP<5:0>的数据位一一对应，如果REC<5:0>中某数据位为1，则MR<19>的OP<5:0>中对应的位将被设置为1。基于上述举例，MR<19>的OP<4>被设置为1。
本公开实施例的一些方面涉及上述考虑。以下结合本公开的一些实施例对方案进行示例介绍。
实施例一
图4为一实施例提供的计数电路的结构示例图，如图4所示，该计数电路包括：
计数模块11，用于在计数值超过预定阈值时，输出所述计数值；
译码模块12，耦接于计数模块11，用于对所述计数值进行译码，获得所述计数值对应的译码信息；其中，所述译码信息表征所述计数值所在的数值区间；
比较模块13，耦接于译码模块12，用于将所述译码信息和历史最大译码信息进行比较，锁存并输出当前最大的译码信息。
实际应用中，本实施例提供的计数电路可应用在各种存储器，作为示例，可以应用在包括但不限双倍速率同步动态随机存储器(简称DDR)等。
结合图4所示，计数模块11负责执行计数，计数完成后若本次的计数值超过预定的阈值，则输出计数值；译码模块12对计数模块11输出的计数值先进行译码，获得对应的译码信息，比如OP<5:0>。具体的，译码信息表征了计数值所在的数值区间。经过译码后，比较模块13将本次的译码信息与历史最大译码信息，比如REG<5:0>，进行比较，锁存两者中最大的译码信息并输出最大的译码信息，作为当前的历史最大译码信息。其中，历史最大译码信息为历史获得的计数值中最大的计数值对应的译码信息。需要说明的是，这里只是一种示例，可以理解，译码信息的数据长度还存在其它可能的实现方式，具体可以根据计数的需要确定。在一个示例中，译码信息为六位二进制数。该示例可适用于行错误计数场景。
为了实现译码信息表征计数值所在的数值区间，在一个示例中，译码信息为多位二进制数，译码信息的不同位对应不同的数值区间，高位对应的数值区间大于低位对应的数值区间。
举例来说，译码信息OP<5:0>的每个数据位表示一个数值区间，OP<5>、OP<4>、OP<3>、OP<2>、OP<1>和OP<0>分别代表一个数值区间，各数据位代表的数值区间不重叠，可以组成一个连续的更大的数值区间。具体的，译码信息代表的数值区间可以预先设定，比如适用于存储器场景，可以参照存储器的相关标准进行设定。其中，高位对应的数值区间大于低位对应的数值区间，结合示例举例说明，即OP<5>对应的数值区间最大，OP<4>对应的数值区间大于OP<3>对应的数值区间。这里数值区间之间的大小关 系按照数值区间的数值范围确定，举例来说，假设一个数值区间为8～15，另一个数值区间为16～31，那么后者大于前者。通过对计数值进行译码，获得的译码信息的不同位可以代表不同的数值区间，且各数值区间不重叠，以实现译码信息代表计数值所在的数值区间，从而便于后续比较模块进行比较。
需要说明的是，为了确保译码信息能够准确表征计数值所在的数值区间，在一个示例中，由于译码信息的不同位代表的数值区间互不重叠，因此译码信息中仅有一位的值为1，表征译码信息对应的计数值位于该位对应的数值区间内。
本示例中，当计数模块输出计数值后，译码模块译码得到的译码信息中仅存在一个数据位的值为1。此外，在其它的场景下，例如，假设计数模块得到的计数值小于所述阈值，不输出本次的计数值时，则译码模块不执行译码处理。实际应用中，由于译码信息的不同位对应不同的数值区间，因此，计数模块输出的计数值通过译码模块进行译码后，得到仅有一个数据位为1的译码信息，该译码信息能够准确表征计数值所在的数值区间。具体的，在译码信息中，值为1的数据位代表的数值区间即为计数值所在的数值区间。在一个示例中，译码模块12包括独热译码器。
相比于图3所示的方案，图4所示的实施例方案的主要特点在于，首先，对计数值的输出设定阈值，即在计数值超过阈值时，计数模块才会输出计数值。另外，本实施例中先对计数值进行译码得到能够表征计数值所在数值区间的译码信息，之后再对该译码信息与历史计数值对应的译码信息进行比较，确定出最大译码信息，后续记录至模式寄存器。本实施例的方案，基于上述特点，EpRC模块无需再输出表征计数值是否大于阈值的信号(RETC<1:0>)，从而减少需进行处理的数据量，并且由于译码信息只需表征计数值所在的数值区间，而无需知晓计数值的具体数值，因此便于采用更为简化的数据来表示，比如，译码值仅有1位为1来表征计数值所在的数值区间，从而在后续的比较中无需对所有比特位比较，从而简化比较模块的电路结构。
可以理解，存储器场景下，由于最终模式寄存器中记录的REC<5:0>用于确定最大计数值所在的数值范围，也就是说，假设有两次的计数值，即便大小不同，但如果两者位于同一个数值区间内，则最终在模式寄存器的记录内容是相同的。因此，本实施例的方案，利用存储器的行错误计数场景的上述特点，未对具体的计数值EpRC<5:0>的大小关系进行比较，而是采用先进行译码得到译码信息，该译码信息只有一位的值是1，其它位均为0，再进行比较和记录的方式，从而有效简化电路结构，减少绕线和版图面积，故本实施例的方案尤其适用于存储器场景。
此外，为了实现对译码信息的比较，在一个示例中，图5为一实施例提供的计数电路的结构示例图，如图5所示，比较模块13包括：比较单元21和第一锁存单元22；
比较单元21的第一输入端与译码模块12连接，比较单元21的第二输入端与第一锁存单元22的输出端连接，比较单元21用于将所述译码信息OP<5:0>和第一锁存单元22输出的历史最大译码信息REG<5:0>进行比较，并根据比较结果输出使能信号MAX；
第一锁存单元22的输入端与译码模块12连接，第一锁存单元22的使能端与比较单元21的输出端连接，第一锁存单元22用于响应于使能信号MAX锁存并输出当前最大的译码信息。
结合示例：首次计数时，第一锁存单元22中记录的历史最大译码信息REG<5:0>处于初始状态，比如可以为空或者默认各数据位均为0。译码模块12基于计数模块11首次输出的计数值得到首个译码信息OP<5:0>，比较单元21将该译码信息OP<5:0>与第一锁存单元22当前输出的历史最大译码信息REG<5:0>(此时REG<5:0>为空或0)进行比较。作为示例，经过首次比较后，将确定相比于初始的REG<5:0>，译码模块本次输出的译码信息OP<5:0>更大，故比较单元21输出有效的使能信号，比如高电平状态的使能信号MAX，相应的，第一锁存单元22响应于有效的使能信号，执行锁存处理，即将译码模块12输出的译码信息OP<5:0>进行锁存，作为新的历史最大译码信息REG<5:0>输出。也就是说，此时第一锁存单元22的输出REG<5:0>与前述的译码信息OP<5:0>一致。
之后再次计数时，译码模块12基于计数模块11每次输出的计数值得到对应的译码信息OP<5:0>传输给比较单元21；比较单元21将本次的译码信息OP<5:0>与第一锁存单元22当前输出的译码信息REG<5:0>进行比较，如果本次的译码信息OP<5:0>大于当前的历史最大译码信息REG<5:0>，则再次输出有效的使能信号，以更新第一锁存单元22的输出REG<5:0>与本次的译码信息OP<5:0>一致。相反的，假设本次的译码信息OP<5:0>不大于当前的历史最大译码信息REG<5:0>，则不输出有效的使能信号，比如输出低电平状态的使能信号。相应的，第一锁存单元22则不将接收到的本次的译码信息传输至内部，第一锁存单元22内部仍继续锁存和输出历史最大译码信息REG<5:0>。后续针对计数模块11每次输出的计数值均执行上述方案，直至整个计数结束，比如存储器的所有行错误计数完成，则此时第一锁存单元22的输出即为所有行错误计数值中的最大计数值。
在一个示例中，比较单元21，用于在译码模块12输出的译码信息大于第一锁存单元22输出的历史最大译码信息时，输出有效的使能信号，以及在译码模块12输出的译码信息不大于第一锁存单元22输出的历史最大译码信息时，输出无效的使能信号；第一锁存单元22用于响应于有效的使能信号，锁存并输出译码模块12输出的译码信息，以及响应于无效的使能信号，维持输出历史最大译码信息。作为示例，有效的使能信号和无效的使能信号可以通过不同的信号状态表征，比如高电平状态和低电平状态。
本示例中，比较单元根据本次译码信息和历史最大译码信息的比较结果输出使能信号，以使第一锁存单元响应于使能信号选择是否更新锁存，从而通过较为简化的电路实现始终输出当前最大的译码信息。
图6为一实施例提供的比较单元的结构示例图，如图6所示，比较单元21包括：多个比较子单元31和输出单元32；其中，所述多个比较子单元与译码信息的各个位一一对应；
每个比较子单元31接收译码信息中对应的位信号和对应的特征信号，并用于根据所述位信号与所述特征信号的比较结果，输出结果信号；其中，特征信号的值表征所述历史最大译码信息REG<5:0>中是否存在值为1且不低于所述比较子单元31对应位的比特位；
输出单元32，用于根据每个比较子单元31输出的结果信号，确定输出有效或无效的使能信号MAX。
其中，输入每个比较子单元的特征信息表征在当前记录的历史最大译码信息中，是否存在值为1且不低于该比较子单元对应位的比特位。可以理解，译码信息的每个比特位代表一个数值区间，并且比特位越高代表的数值区间越大。结合译码信息中值为1的比特位表征计数值所在的数值区间的特点，通过比较两个计数值对应的译码信息中值为1的比特位的高低，可反映出这两个计数值的大小关系，从而确定最大计数值对应的译码信息，即最大译码信息。举例来说，假设某计数值A对应的译码信息为000010，另一计数值B对应的译码信息为010000，则可判定计数值B大于计数值A，计数值B对应的译码信息大于计数值A对应的译码信息。
本示例中，比较子单元与译码信息的各比特位一一对应。结合图6的示例，以译码信息为六位二进制数进行举例，图中六个比较子单元分别对应译码信息的六个比特位。如图所示，包括OP<5>～OP<0>对应的比较子单元，每个比较子单元接收对应译码信息位OP<…>和对应的特征信号。
以最高位对应的比较子单元作为示例，该比较子单元接收到对应的位信号OP<5>和对应的特征信号，该特征信号表征历史最大译码信息中是否存在值为1且不低于所述比较子单元对应位(即最高位)的比特位，示例的所述比较子单元对应译码信息的最高位，故历史最大译码信息中不低于最高位的比特位即仅有历史最大译码信息的最高位REG<5>，因此示例的比较子单元接收到的特征信号表征历史最大译码信息的最高位REG<5>的值是否为1。
基于译码模块输出的译码信息和历史最大译码信息，可以通过两种比较逻辑进行比较：一种为找出两者中为1的比特位，比较两者中为1的比特位，为1的比特位更高的译码信息的值更大，若相同则说明译码模块输出的译码信息和历史最大译码信息相等；另一种为从高至低依次比较两者比特位的值，谁先出现为1的比特位，谁的值就更大，若相同则相等。
举例来说，可以用特征信号为1，表征历史最大译码信息中存在值为1且不低于比较子单元对应位的比特位；用特征信号为0，表征历史最大译码信息中不存在值为1且不低于比较子单元对应位的比特位，即不低于比较子单元对应位的比特位均为0。仍以最高位对应的比较子单元作为示例，实际场景中，可能出现以下几种情况：
(1)如果译码模块本次输出的译码信息的最高位OP<5>为1，而历史最大译码信息的最高位REG<5>不为1，则可直接确定，本次输出的译码信息更大，故输出处于某状态的结果信号，以使输出单元输出有效的使能信号；
(2)如果译码信息的最高位OP<5>不为1，而历史最大译码信息的最高位REG<5>为1，则可直接确定，历史最大译码信息更大，故输出处于另一状态的结果信号，以使输出单元输出无效的使能信号；
(3)如果译码信息的最高位OP<5>和历史最大译码信息的最高位REG<5>两者均为1，则译码模块输出的译码信息和历史最大译码信息相等；
(4)如果译码信息的最高位OP<5>和历史最大译码信息的最高位REG<5>两者均为0，则基于其它位对应的比较子单元的结果信息确定最大的译码信息，其中其它比较子单元的比较原理与上述类似。总的来说，即通过对比译码信息中每个位是否为1与历史最大译码信息中的相同位和更高位中是否存在1，进行每个位的比较判断。
进一步的，根据比较得到的结果信息，控制输出单元32输出有效或无效的使能信号，在一个示例中，若任一比较子单元31输出的结果信号表征比较子单元31对应的位的值为1且历史最大译码信息中不低于该位的比特位的值均为0，则输出有效的使能信号。
在一个示例中，如图7所示，每个比较子单元31包括：第一非门311和第一或非门312；
第一非门311的输入端接收所述译码信息中对应的位信号，第一非门311的输出端连接至第一或非门312的第一输入端；
第一或非门312的第二输入端接收比较子单元31对应的特征信号，第一或非门312的输出端连接至输出单元32。
具体的，当译码信息中的位信号为1时，第一非门311输出0，第一或非门312的输出是否为1取决于特征信号，如果特征信号表征历史最大译码信息中不低于该位的比特位均为0，比如特征信号为0，则第一或非门312输出的结果信号为1，相应的，输出单元输出有效的使能信号。当译码信息中的位信号为0时，第一非门311输出1，则无论特征信号的值是否为1，第一或非门312输出的结果信号为0，相应的，输出单元的输出视其它第一或非门的输出情况，只要存在输出为1的第一或非门，则表征该比较子单元接收到的位信号为1且历史最大译码信息中不低于该位的比特位均为0，即表征译码模块输出的译码信息中值为1的比特位相比历史最大译码信息中为1的比特位更高，译码模块输出的译码信息大于历史最大译码信息，需要将历史最大译码信息更新为译码模块输出的译码信息，输出单元输出有效的使能信号，否则输出无效的使能信号。
也就是说，对于每个比较子单元来说，只有当译码信息中的位信号为1，历史最大译码信息中不低于该位的比特位均为0时，即译码信息中值为1的比特位高于历史最大译码信息中值为1的比特位时，方输出为1的结果信号；否则，比如，译码信息中值为1的比特位和历史最大译码信息中值为1的比特位相同，或者译码信息中值为1的比特位低于历史最大译码信息中值为1的比特位时，均输出为0的结果信号。
本示例利用译码信息的特点，通过非门和与非门实现比较子单元，采用常规的器件结构能够有效简化电路结构，并且降低成本。
在一些实施例中，每个比较子单元对应的特征信号的数量为一个。即通过一个信号表征历史最大译码信息中，不低于比较子单元对应位的比特位中是否存在值为1的比特位。具体的，为了简化电路结构，可以采用常规器件实现比较子单元。故为了使特征信号适配常规器件，本示例中，每个比较子单元对应 的特征信号数量为一个，从而有效减少器件输入端口，简化电路布线。
为了将特征信号实现为单个信号，在一个示例中，如图8所示，每个比较子单元31还包括：第一信号生成单元313；第一信号生成单元313的输入端接收历史最大译码信息中不低于比较子单元31对应位的所有比特位信号，第一信号生成单元313用于在接收到的任意一个所述比特位信号的值为1时，输出值为1的特征信号。
本示例中，每个比较子单元对应一个第一信号生成单元。每个第一信号生成单元用于生成输入至对应的比较子单元的特征信号，且第一信号生成单元仅生成一个特征信号。具体的，第一信号生成单元用于检测历史最大译码信息中，不低于所在比较子单元对应位的所有比特位信号中，是否存在值为1的位。举例来说，历史最大译码信息中，不低于译码信息的OP<3>对应位的所有比特位为REG<5>～REG<3>，故译码信息的OP<3>对应的比较子单元中的第一信号生成单元用于检测REG<5>～REG<3>中是否存在值为1的比特位，若存在任一比特位为1，则该第一信号生成单元输出1，否则输出0。
同样出于电路简化和成本考虑，倾向于采用常规器件实现第一信号生成单元。作为示例，图9为第一信号生成单元的结构示例图，如图9所示，第一信号生成单元313包括：至少一个第一生成子单元41；
每个第一生成子单元41包括：第二或非门411和第二非门412；第二或非门411的输入端作为第一生成子单元41的输入端，第二非门412的输出端作为第一生成子单元41的输出端，第二或非门411的输出端与第二非门412的输入端连接；
每个第一生成子单元41的输入端连接历史最大译码信息中不低于比较子单元对应位的部分比特位或者全部比特位，所有第一生成子单元41连接的比特位的组合结果为历史最大译码信息中不低于比较子单元对应位的所有比特位；
其中，除首个以外的每个第一生成子单元41连接上一级第一生成子单元41的输出端，最后一级第一生成子单元41输出所述特征信号。
结合场景对上述电路的工作原理进行示例：以译码信息的OP<1>为例，输入至第一信号生成单元313的所有第一生成子单元41的比特位的组合结果，为历史最大译码信息中不低于OP<1>的所有比特位，即REG<5>～REG<1>。以译码信息的OP<3>为例，输入至第一信号生成单元313的所有第一生成子单元41的比特位的组合结果，为历史最大译码信息中不低于OP<3>的所有比特位，即REG<5>～REG<3>。其中，第一生成子单元41的数量可以仅设置一个，也可根据不低于比较子单元对应位的所有比特位的数量和第二或非门的输入端数量设置多个，在此不对其进行限制，图中仅是结合用于生成译码信息的OP<1>对应的比较子单元的特征信号作为举例，对第一信号生成单元的结构进行一种示例，而并未限制其它比较子单元的第一信号生成单元的结构。
比如，图中示例的OP<1>对应的第一信号生成单元313中包括两个第一生成子单元41，其中一个第一生成子单元41的输入信号包括REG<5>～REG<3>，另一第一生成子单元41的输入信号包括 REG<2>～REG<1>。但在其它方式中，也可以设置三个第一生成子单元41，其中一个第一生成子单元41的输入信号包括REG<5>～REG<4>，另一第一生成子单元41的输入信号包括REG<3>～REG<2>，最后一个第一生成子单元41的输入信号包括REG<1>。
结合图示可知，对于每个第一生成子单元来说，只要输入的信号中存在值为1的任一信号，则第二或非门输出0，相应的第二非门输出1。由于前几级的第一生成子单元的输出还作为后一级第一生成子单元的输入，故如果存在任一第一生成子单元输出的信号为1，则最终第一信号生成单元输出的特征信号为1，从而实现若检测到历史最大译码信息中，不低于所在比较子单元对应位的所有比特位信号中任一位的值为1，则输出值为1的特征信号。
本示例中，通过在每个比较子单元中设置第一信号生成单元，为每个比较子单元提供数量为一个的特征信号，通过特征信号和译码信号进行比较的结果信号，输出使能信号，实现最大译码信息的更新。
在一些实施例中，至少一个比较子单元对应的特征信号的数量为多个。本示例中，每个比较子单元对应的特征信号的数量可以根据该比较子单元对应的特征信号需要表征的比特位的数量确定，举例来说，假设某比较子单元(比如OP<5>对应的比较子单元)的特征信号需表征历史最大译码信息中一个比特位的值是否为1，则对应的特征信号数量为一个(比如，REG<5>)；而当比较子单元对应的比特位较低，相应的特征信号需要表征历史最大译码信息中一个比特位的取值情况时，则特征信号的数量可以为多个，从而利用具有多输入端口的器件，有效简化电路结构。
在一个示例中，如图10所示，图10为一实施例提供的比较单元的结构示例图，比较单元21还包括第二信号生成单元33；
第二信号生成单元33，用于根据所述历史最大译码信息中是否存在值为1且不低于预定位的比特位，输出相应的特征信号。
本示例中，第二信号生成单元33负责提供部分比较子单元的特征信号。其中，所述预定位可以随机选取，比如，对于REG<5：0>，可以选取预定位为REG<3>和REG<1>，相应的，第二信号生成单元33输出的特征信号包括REG<345>和REG<12345>，其中，REG<345>表征历史最大译码信息REG<5：0>中不低于REG<3>的比特位中是否存在值为1的位，REG<12345>表征历史最大译码信息REG<5：0>中不低于REG<1>的比特位中是否存在值为1的位。需要说明的是，图中仅为一种示例，实际应用中，任何一个比较子单元都可以将不低于所述比较子单元对应的位的所有位信号(作为特征信号)直接输入。
在一个示例中，多个比较子单元31包括第一比较子单元311和第二比较子单元312；其中，第一比较子单元311对应的特征信号包括历史最大译码信息中不低于第一比较子单元311对应的位的所有位信号；第二比较子单元312对应的特征信号包括第二信号生成单元33输出的信号，预定位为译码信息中第二比较子单元312对应的位。
作为示例，如图10所示，对于OP<5>对应的比较子单元，该比较子单元的特征信号包括REG<5>； 对于OP<4>对应的比较子单元，该比较子单元的特征信号包括REG<5>和REG<4>和REG<5>；对于OP<3>对应的比较子单元，该比较子单元的特征信号包括第二信号生成单元33提供的REG<345>；对于OP<2>对应的比较子单元，该比较子单元的特征信号包括REG<2>和第二信号生成单元33提供的REG<345>；对于OP<1>对应的比较子单元，该比较子单元的特征信号包括第二信号生成单元33提供的REG<12345>；对于OP<0>对应的比较子单元，该比较子单元的特征信号包括REG<0>和第二信号生成单元33提供的REG<12345>。
需要说明的时，上述只是一种示例，可以理解，预定位的选取可以根据实际情况进行选取。结合上述举例，图10中，第一比较子单元包括OP<5>对应的比较子单元和OP<4>对应的比较子单元；第二比较子单元包括OP<3>对应的比较子单元和OP<1>对应的比较子单元。上述示例，通过设定预定位，由第二信号生成单元提供部分比较子单元的特征信号，利用某些器件具有多端口的特点，对于端口数充足的比较子单元可直接连接历史最大译码信息中不低于所述比较子单元对应的位的所有位信号，对于端口数有限的比较子单元可采用第二信号生成单元提供的特征信号，无需针对每个比较子单元生成专门的特征信号，从而简化第二信号生成电路的结构，降低整体电路的复杂性。
在一个示例中，多个比较子单元31包括：第三比较子单元313；
第三比较子单元313对应的特征信号包括第二信号生成单元33输出的信号和历史最大译码信息中对应第三比较子单元313的位信号，预定位为译码信息中第三比较子单元313对应的位的相邻高位。
结合前述示例说明，针对预定位的相邻低位对应的比较子单元，比如，预定位为REG<3>时，预定位的相邻低位即REG<2>，故针对REG<2>对应的比较子单元，该比较子单元接收的特征信号除了包括第二信号生成单元33提供的特征信号REG<345>，还接收历史最大译码信息中该比较子单元对应位的信号，即REG<2>。
上述示例中，通过将第二信号生成单元提供的特征信号和历史最大译码信息中的位信号进行组合，共同作为比较子单元的特征信号，能够简化信号生成单元的电路结构，并且实现比较子单元基于特征信号和译码信号进行比较，实现后续处理。
以下对第二信号生成电路的结构进行举例说明：在一个示例中，图11为第二信号生成单元的结构示例图，如图11所示，仍以预定位包括REG<3>和REG<1>作为示例，第二信号生成单元33包括：第二或非门331、第二非门332以及第三或非门333和第三非门334；
第二或非门331的输入端分别连接至历史最大译码信息的前三位信号REG<5>～REG<3>，第二或非门331的输出端连接第二非门332的输入端，第二非门332的输出端输出信号REG<345>；
第三或非门333的输入端分别连接第二非门332的输出端和历史最大译码信息不低于预定位的比特位中除前三位信号以外的位信号REG<2>～REG<1>，所述第三或非门333的输出端连接第三非门334的输入端，第三非门334的输出端输出信号REG<12345>。
需要说明的是，上述只是通过举例的方式给出第二信号生成电路的结构实现，可以理解，还可以通过其它可能的方式实现第二信号生成电路。
本示例中，通过设置第二信号生成单元，基于第二信号生成单元和历史最大译码信息中各比特位的信号，组合为各比较子单元提供特征信号，通过特征信号和译码信号进行比较的结果信号输出使能信号，实现最大译码信息的更新。
进一步的，为了实现根据比较得到的结果信息，控制输出单元输出有效或无效的使能信号，在一个示例中，输出单元32，具体用于若任一比较子单元31输出的结果信号为第一值，则输出有效的使能信号；其中，第一值表征比较子单元31接收的所述译码信息中对应的位信号的值为1且历史最大译码信息中不低于该位的比特位的值均为0。
可选的，第一值可以为1。作为示例，当某个比较子单元输出的结果信号为1，即表明该比较子单元对应位的值为1，且历史最大译码信息中不低于该位的所有比特位均为0。结合译码信息的比特位越高，反映计数值越大的特点，可以判定译码模块输出的译码信息大于历史最大译码信息，故输出单元在检测到任一结果信号为1时，即输出有效的使能信号，以使第一锁存单元22将最大译码信息更新为译码模块本次输出的译码信息，从而输出当前最大的译码信息。
在一个示例中，图12为一实施例提供的输出单元的结构示例图，如图12所示，输出单元32包括：多个第四或非门321和第一与非门322；每个第四或非门321的输入端分别与译码信息的相邻位对应的比较子单元31的输出端连接，每个第四或非门321的输出端连接至第一与非门322的输入端，第一与非门322的输出端输出使能信号。本示例中，通过常规器件或非门和与非门，实现当检测到任一结果信号为1时输出有效的使能信号，从而有效简化电路，降低成本。需要说明的是，图中只是一种示例，输出单元的图示结构还可以和比较单元的其它实现结构结合实施。
在一个示例中，图13为一实施例提供的计数电路的结构示例图，如图13所示，第一锁存单元22包括：第一锁存器221；第一锁存器221的输入端与译码模块12连接，第一锁存器221的使能端与比较单元21的输出端连接，第一锁存器221的输出端与比较单元21的第二输入端连接。本示例中，通过锁存器，实现响应于使能信号的有效或无效，更新锁存的译码信息或维持原有的译码信息，从而基于简化的电路实现始终输出最大译码信息。
结合行错误计数的场景进行示例：上述计数值为行错误数，历史最大译码信息为历史最大行错误数对应的译码信息。结合前述对存储器的行错误计数场景的介绍，除了实现最大行错误数的记录外，还需记录最大行错误数对应的地址信息。故在一个示例中，如图14所示，所述电路还包括：地址模块14；比较模块13还包括：第二锁存单元23；
地址模块14，用于输出计数值对应的地址信息；其中，地址信息包括但不限于：存储组地址、存储体地址和行地址。
第二锁存单元23的输入端与地址模块14连接，第二锁存单元23的使能端与比较单元21的输出端连接，第二锁存单元23用于响应于有效的使能信号，输出地址模块14输出的地址信息；以及，响应于无效的使能信号，维持历史最大行错误数对应的地址信息。
具体的，比较单元输出的使能信号是否有效，基于本次译码模块输出的译码信息和第一锁存单元中历史最大译码信息的大小关系确定。在存储器的行错误计数场景下，使能信号除了用于控制第一锁存单元是否更新锁存的错误数以外，还用于控制第二锁存单元是否更新行地址信息。作为示例，当使能信号有效时，说明本次的译码信息大于历史最大译码信息，则在更新最大行错误数的同时，第二锁存单元响应于有效的使能信号，将行地址模块本次输出的本次译码信息对应的行地址信息，更新至内部锁存输出，替代历史最大译码信息对应的行地址信息。
通过设置行地址模块和第二锁存单元，能够实现存储器的行错误计数场景下的最大错误数计数功能。
本实施例提供的计数电路中，计数模块在计数值超过预定阈值时输出计数值，译码模块对计数模块输出的计数值进行译码，获得表征计数值所在的数值区间的译码信息，比较模块将所述译码信息和历史最大译码信息进行比较，锁存并输出当前最大的译码信息。上述方案中，译码模块先对当前的计数值进行译码，获得的译码信息中仅有1位为1即可表征计数值所在的数值区间，比较模块在比较当前计数值对应的译码信息和历史最大计数值对应的译码信息，即历史最大译码信息时，由于两者均为仅有1位为1的数据，故可大大简化比较模块的电路结构，即可确定实现最大计数结果对应的译码信息并存至寄存器，从而通过结构更为简化的电路实现最大计数，能够很好地适用于需要保持输出最大结果的计数场景，比如行错误计数场景。
实施例二
图15为一实施例提供的一种存储器的结构示意图，如图15所示，该存储器包括：模式寄存器1以及如前述任一示例所述的计数电路2；其中，
模式寄存器1，耦接于计数电路2，用于保存计数电路2输出的最大译码信息。
作为示例，模式寄存器1还用于保存最大译码信息对应的行的地址信息。结合前述实施例的方案，以DRAM作为示例：基于前述方案，计数电路根据当前行的检测情况，在行错误数超过预定阈值时，对该行错误数进行译码，并将译码获得的译码信息和历史最大译码信息进行比较；若本次获得的译码信息大于历史最大译码信息，则将本次译码信息作为当前的最大译码信息，否则将历史最大译码信息继续作为最大译码信息，直至所有行的检测结束，得到最终的最大译码信息。该最大译码信息表征最大行错误数所在的数值区间。相应的，计数电路将最大译码信息无需再进行译码，传输至用于记录最大行错误数的模式寄存器中，另外，计数电路还将最大译码信息对应的行的地址信息，传输至用于记录最大行错误数对应的行地址信息的模式寄存器中，实现存储器的行错误数计数场景。
本实施例提供的存储器中，计数电路在行错误数超过预定阈值时输出行错误数，对行错误数进行译码，获得表征行错误数所在的数值区间的译码信息，将所述译码信息和历史最大译码信息进行比较，锁存并向模式寄存器输出当前最大的译码信息以及对应的行的地址信息。上述方案中，先对当前的计数值进行译码，通过比较当前行错误数对应的译码信息和历史最大行错误数对应的译码信息，获得的译码信息中仅有1位为1即可表征计数值所在的数值区间，比较模块在比较当前计数值对应的译码信息和历史最大计数值对应的译码信息，即历史最大译码信息时，由于两者均为仅有1位为1的数据，故可大大简化比较模块的电路结构，即可确定实现最大计数结果对应的译码信息并存至寄存器，从而通过结构更为简化的电路实现最大计数，能够很好地适用于行错误计数场景。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (23)

  1. 一种计数电路，包括：
    计数模块，用于在计数值超过预定阈值时，输出所述计数值；
    译码模块，耦接于所述计数模块，用于对所述计数值进行译码，获得所述计数值对应的译码信息；其中，所述译码信息表征所述计数值所在的数值区间；
    比较模块，耦接于所述译码模块，用于将所述译码信息和历史最大译码信息进行比较，锁存并输出当前最大的译码信息。
  2. 根据权利要求1所述的电路，其中，所述译码信息为多位二进制数，所述译码信息的不同位对应不同的数值区间，高位对应的数值区间大于低位对应的数值区间。
  3. 根据权利要求2所述的电路，其中，所述译码信息中仅有一位的值为1，表征所述译码信息对应的计数值位于该位对应的数值区间内。
  4. 根据权利要求2所述的电路，其中，所述比较模块包括：比较单元和第一锁存单元；
    所述比较单元的第一输入端与所述译码模块连接，所述比较单元的第二输入端与所述第一锁存单元的输出端连接，所述比较单元用于将所述译码信息和所述第一锁存单元输出的历史最大译码信息进行比较，并根据比较结果输出使能信号；
    所述第一锁存单元的输入端与所述译码模块连接，所述第一锁存单元的使能端与所述比较单元的输出端连接，所述第一锁存单元用于响应于所述使能信号锁存并输出当前最大的译码信息。
  5. 根据权利要求4所述的电路，其中，
    所述比较单元，用于在所述译码信息大于所述第一锁存单元输出的历史最大译码信息时，输出有效的使能信号，以及在所述译码信息不大于所述第一锁存单元输出的历史最大译码信息时，输出无效的使能信号；
    所述第一锁存单元用于响应于所述有效的使能信号，锁存并输出所述译码模块输出的译码信息，以及响应于所述无效的使能信号，维持输出历史最大译码信息。
  6. 根据权利要求5所述的电路，其中，所述比较单元包括：多个比较子单元和输出单元；其中，所述多个比较子单元与所述译码信息的各个位一一对应；
    每个所述比较子单元接收所述译码信息中对应的位信号和对应的特征信号，并用于根据所述位信号与所述特征信号的比较结果，输出结果信号；其中，所述特征信号的值表征所述历史最大译码信息中是否存在值为1且不低于所述比较子单元对应位的比特位；
    所述输出单元，用于根据每个所述比较子单元输出的结果信号，确定输出有效或无效的使能信号。
  7. 根据权利要求6所述的电路，其中，
    所述输出单元，具体用于若任一比较子单元输出的结果信号为第一值，则输出有效的使能信号；其中，所述第一值表征所述比较子单元接收的所述译码信息中对应的位信号的值为1且所述历史最大译码信息中不低于该位的比特位的值均为0。
  8. 根据权利要求7所述的电路，其中，每个所述比较子单元包括：第一非门和第一或非门；
    所述第一非门的输入端接收所述译码信息中对应的位信号，所述第一非门的输出端连接至所述第一或非门的第一输入端；
    所述第一或非门的第二输入端接收所述比较子单元对应的特征信号，所述第一或非门的输出端连接至所述输出单元。
  9. 根据权利要求6所述的电路，其中，每个比较子单元对应的特征信号的数量为一个。
  10. 根据权利要求9所述的电路，其中，每个所述比较子单元还包括：第一信号生成单元；
    所述第一信号生成单元的输入端接收所述历史最大译码信息中不低于所述比较子单元对应位的所有比特位信号，所述第一信号生成单元用于在接收到的任意一个所述比特位信号的值为1时，输出值为1的特征信号。
  11. 根据权利要求10所述的电路，其中，所述第一信号生成单元包括：至少一个第一生成子单元；
    每个所述第一生成子单元包括：第二或非门和第二非门；所述第二或非门的输入端作为所述第一生成子单元的输入端，所述第二非门的输出端作为所述第一生成子单元的输出端，所述第二或非门的输出端与所述第二非门的输入端连接；
    每个第一生成子单元的输入端连接所述历史最大译码信息中不低于所述比较子单元对应位的部分比特位或者全部比特位，所有第一生成子单元连接的比特位的组合结果为所述历史最大译码信息中不低于所述比较子单元对应位的所有比特位；
    除首个以外的每个第一生成子单元连接上一级第一生成子单元的输出端，最后一级第一生成子单元输出所述特征信号。
  12. 根据权利要求6所述的电路，其中，至少一个比较子单元对应的特征信号的数量为多个。
  13. 根据权利要求12所述的电路，其中，所述比较单元还包括第二信号生成单元；
    所述第二信号生成单元，用于根据所述历史最大译码信息中是否存在值为1且不低于预定位的比特位，输出相应的特征信号。
  14. 根据权利要求13所述的电路，其中，所述多个比较子单元包括第一比较子单元和第二比较子单元；
    所述第一比较子单元对应的特征信号包括所述历史最大译码信息中不低于所述第一比较子单元对应的位的所有位信号；
    所述第二比较子单元对应的特征信号包括所述第二信号生成单元输出的信号，所述预定位为所述译 码信息中所述第二比较子单元对应的位。
  15. 根据权利要求13所述的电路，其中，所述多个比较子单元包括：第三比较子单元；
    所述第三比较子单元对应的特征信号包括所述第二信号生成单元输出的信号和所述历史最大译码信息中对应所述第三比较子单元的位信号，所述预定位为所述译码信息中所述第三比较子单元对应的位的相邻高位。
  16. 根据权利要求7所述的电路，其中，所述输出单元包括：多个第四或非门和第一与非门；
    每个第四或非门的输入端分别与所述译码信息的相邻位对应的比较子单元的输出端连接，每个所述第四或非门的输出端连接至所述第一与非门的输入端，所述第一与非门的输出端输出所述使能信号。
  17. 根据权利要求4所述的电路，其中，所述第一锁存单元包括：第一锁存器；
    所述第一锁存器的输入端与所述译码模块连接，所述第一锁存器的使能端与所述比较单元的输出端连接，所述第一锁存器的输出端与所述比较单元的第二输入端连接。
  18. 根据权利要求1所述的电路，其中，所述译码模块包括独热译码器。
  19. 根据权利要求4-18中任一项所述的电路，其中，所述计数值为行错误数，所述历史最大译码信息为历史最大行错误数对应的译码信息。
  20. 根据权利要求19所述的电路，其中，所述译码信息为六位二进制数。
  21. 根据权利要求20所述的电路，其中，所述电路还包括：地址模块；所述比较模块还包括：第二锁存单元；
    所述地址模块，用于输出所述计数值对应的地址信息；
    所述第二锁存单元的输入端与所述地址模块连接，所述第二锁存单元的使能端与所述比较单元的输出端连接，所述第二锁存单元用于响应于有效的使能信号，输出所述地址模块输出的地址信息；以及，响应于无效的使能信号，维持历史最大行错误数对应的地址信息。
  22. 根据权利要求21所述的电路，其中，所述地址信息包括存储组地址、存储体地址和行地址。
  23. 一种存储器，包括：模式寄存器以及如权利要求1-22中任一项所述的计数电路；其中，
    所述模式寄存器，耦接于所述计数电路，用于保存所述计数电路输出的最大译码信息。
PCT/CN2022/124032 2022-08-17 2022-10-09 计数电路及存储器 WO2024036723A1 (zh)

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