WO2024036719A1 - 一种数据接收电路和存储器 - Google Patents

一种数据接收电路和存储器 Download PDF

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Publication number
WO2024036719A1
WO2024036719A1 PCT/CN2022/123902 CN2022123902W WO2024036719A1 WO 2024036719 A1 WO2024036719 A1 WO 2024036719A1 CN 2022123902 W CN2022123902 W CN 2022123902W WO 2024036719 A1 WO2024036719 A1 WO 2024036719A1
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Prior art keywords
signal
voltage
voltage signal
output
weak
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PCT/CN2022/123902
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English (en)
French (fr)
Inventor
韦冰心
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/448,944 priority Critical patent/US12482516B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits

Definitions

  • the present disclosure relates to the field of semiconductor memory technology, and in particular, to a data receiving circuit and a memory.
  • the semiconductor device receives data through a data receiving circuit therein that uses a reference voltage to determine the logic level of the received data signal.
  • the level state of the previous data signal will have some impact on the level state of the following data signal. Therefore, it is necessary to use the decision feedback balance principle to eliminate the adverse effects of the previous data signal and avoid data Signal misjudgment.
  • the process of decision feedback balance is time-consuming and affects the performance of the data receiving circuit.
  • the present disclosure provides a data receiving circuit and memory, which can not only ensure the accuracy of data reception, but also shorten the signal feedback time.
  • an embodiment of the present disclosure provides a data receiving circuit.
  • the data receiving circuit includes a voltage generating circuit configured to output a first reference voltage signal and a second reference voltage signal in a first mode, and the The first reference voltage signal and the second reference voltage signal have different voltage values;
  • a data circuit configured to receive a data signal, the first reference voltage signal and the second reference voltage signal, compare the data signal and the first reference voltage signal, and output a first target signal; The data signal is compared with the second reference voltage signal to output a second target signal; wherein the data signal is one of several data signals arranged in series;
  • a selection circuit configured to receive the first target signal and the second target signal, and select the first target signal and the second target signal based on the level state of a previous data signal of the data signal. One of the two is determined as the target data signal.
  • the voltage generation circuit is further configured to output a third reference voltage signal in the second mode; wherein the voltage value of the third reference voltage signal is located at a voltage value of the first reference voltage signal. between the value and the voltage value of the second reference voltage signal; the data circuit is further configured to receive the third reference voltage signal, compare the data signal with the third reference voltage signal, and output a target data signal.
  • the voltage generation circuit includes: a first voltage generation module configured to receive a first control signal group; in the first mode, based on the first control signal group, output a first weak voltage signal and a second weak voltage signal; a second voltage generation module configured to receive a second control signal group; in the first mode, based on the second control signal group, output a first strong voltage signal and a second strong voltage signal.
  • a first selector configured to receive a strong and weak selection signal, the first weak voltage signal and the first strong voltage signal; when the strong and weak selection signal is in a first state, the first The strong voltage signal is output as the first reference voltage signal; or, when the strong and weak selection signal is in the second state, the first weak voltage signal is output as the first reference voltage signal; the second selector , configured to receive the strong and weak selection signal, the second weak voltage signal and the second strong voltage signal, and when the strong and weak selection signal is in the first state, the second strong voltage signal Output as the second reference voltage signal; or, when the strong and weak selection signal is in the second state, output the second weak voltage signal as the second reference voltage signal; wherein, the third The driving strength of a strong voltage signal is greater than the driving strength of the first weak voltage signal, and the driving strength of the second strong voltage signal is greater than the driving strength of the second weak voltage signal.
  • the voltage generation circuit further includes: a first code generator configured to generate the first control signal group; a second code generator configured to generate the second control signal group; wherein, In the first mode, the voltage difference between the first weak voltage signal and the second weak voltage signal is a first value, and the first value is determined by the first control signal group; The voltage difference between the first strong voltage signal and the second strong voltage signal is a second value, and the second value is determined by the second control signal group; the first value and the second The values are the same.
  • the voltage generation circuit further includes: a calibration module configured to receive the first strong voltage signal and the first weak voltage signal in the first mode, and perform a calibration on the first strong voltage signal. Compare the voltage value with the first weak voltage signal and output a first comparison signal; the first code generator is also configured to receive the first comparison signal in the first mode, based on the first comparison The signal adjusts the first control signal group to adjust the voltage value of the first weak voltage signal step by step, so that the voltage values of the first strong voltage signal and the first weak voltage signal are the same, and the voltage value of the first weak voltage signal is the same.
  • the second strong voltage signal and the second weak voltage signal have the same voltage value.
  • the first voltage generation module is further configured to output a third weak voltage signal based on the first control signal group in the second mode; the second voltage generation module is further configured to output a third strong voltage signal based on the second control signal group in the second mode; the first selector is further configured to receive the strong and weak selection signal, the third weak voltage signal and the third strong voltage signal, when the strong or weak selection signal is in the first state, the third strong voltage signal is output as the third reference voltage signal; or, when the strong or weak selection signal is in the first state, When the selection signal is in the second state, the third weak voltage signal is output as the third reference voltage signal; wherein the driving strength of the third strong voltage signal is greater than the driving strength of the third weak voltage signal. strength.
  • the calibration module is further configured to receive the third strong voltage signal and the third weak voltage signal, and perform a voltage value calculation on the third strong voltage signal and the third weak voltage signal. Compare and output a second comparison signal; the first code generator is also configured to receive the second comparison signal, adjust the first control signal group based on the second comparison signal, and adjust the The voltage value of the third weak voltage signal is such that the voltage values of the third strong voltage signal and the third weak voltage signal are the same.
  • the first voltage generation module includes a first voltage division adjustment module, and the first voltage division adjustment module includes a first main resistance chain and a first auxiliary resistance chain; in the first mode, the The first main resistance chain and the first auxiliary resistance chain are connected through a first connection point and a second connection point, and the first connection point is connected in series to the second connection point and the first main resistance chain. between the ground terminals; wherein the first voltage division adjustment module is configured to adjust the resistance distribution state of the first main resistance chain based on the first control signal group to output a third voltage through the first connection point.
  • a weak voltage signal is used to adjust the resistance distribution state of the first auxiliary resistance chain to output a second weak voltage signal through the second connection point.
  • the first main resistance chain and the first auxiliary resistance chain are in an isolated state; wherein the first voltage division adjustment module is further configured to be based on the first The control signal group adjusts the resistance distribution state of the first main resistance chain to output a third weak voltage signal through the voltage output node of the first main resistance chain.
  • the first main resistor chain includes a plurality of first resistors arranged in series. One end of the first first resistor is connected to the first power supply terminal, and the other end of the last first resistor is connected to the first power supply terminal.
  • the ground terminal is connected;
  • the first main resistance chain also includes A first switch tubes close to the first power supply terminal and A first switch tubes close to the ground terminal, and A first switch tubes close to the first power supply terminal.
  • the first ends of the first switching tubes are all connected to the first power terminal, and the first ends of the A first switching tubes close to the grounding terminal are connected to the grounding terminal; note that the first switching tubes are close to the grounding terminal.
  • a first resistors at a power supply terminal and A first resistors close to the ground terminal are first edge resistors; in the direction close to the first power supply terminal, the a-th first switch tube is used to short-circuit a The first edge resistor; in the direction away from the first power supply terminal, the a-th first switch tube is used to short-circuit the a-th first edge resistor; a and A are both positive integers, and a is less than Or equal to A, A is less than half of the total number of first resistors; in the part of the first main resistor chain that does not include the first edge resistor, every C first resistors lead to a voltage output node, so
  • the first voltage generation module also includes a first selection output module, the input end of the first selection output module is connected to all the voltage output nodes, the first selection output module controls based on the first control signal group The first switch tube is turned on or off; in the second mode, the first selection output module also selects one of the voltage output nodes to output the prese
  • a second switch tube is connected in series between the two first resistors corresponding to each voltage output node;
  • the first auxiliary resistor chain It includes N ⁇ B second resistors connected in series, the first auxiliary resistance chain also includes B third switching tubes, one end of the B third switching tubes is connected to the same end of the first auxiliary resistance chain,
  • the b-th third switch tube is used to short-circuit N ⁇ b second resistors, N, B and b are all positive integers, and b is less than or equal to B, N ⁇ C;
  • the first voltage generation module also includes A second selection output module, the second selection output module is used to control the conduction or cutoff of the second switch tube and the third switch tube based on the first control signal group; in the first mode, the The second selection output module is specifically used to control any one of the second switching tubes to turn off, so that the first auxiliary resistance chain replaces one of the second resistors and is connected in series to the first main resistance chain, and forms the first main resistance chain.
  • the first voltage division adjustment module further includes a first constant current power supply and a first constant voltage power supply; the first voltage division adjustment module is configured to, in the first mode, The first constant current power supply is determined as the first power supply terminal; or, in the second mode, the first constant voltage power supply is determined as the first power supply terminal.
  • the second voltage generation module includes a second voltage division adjustment module, a first operational amplifier and a second operational amplifier, and the second voltage division adjustment module includes a second main resistor chain and a second auxiliary Resistor chain; in the first mode, the second main resistance chain and the second auxiliary resistance chain are connected through a third connection point and a fourth connection point, and the third connection point is connected in series to the fourth connection between the point and the ground end of the second main resistance chain; wherein the second voltage division adjustment module is configured to adjust the resistance distribution state of the second main resistance chain based on the second control signal group To output the first voltage signal through the third connection point, adjust the resistance distribution state of the second auxiliary resistance chain to output a second voltage signal through the fourth connection point; the first operational amplifier, The second operational amplifier is configured to receive the first voltage signal, amplify the first voltage signal, and output the first strong voltage signal; the second operational amplifier is configured to receive the second voltage signal, and amplify the first voltage signal.
  • the two voltage signals are amplified and the second strong voltage signal
  • the second main resistance chain and the second auxiliary resistance chain are in an isolated state; wherein the second voltage division adjustment module is also configured to be based on the second The control signal group adjusts the resistance distribution state of the second main resistance chain to output a third voltage signal through the voltage output node of the second main resistance chain; the first operational amplifier is configured to receive the third Three voltage signals, amplifying the third voltage signal and outputting the third strong voltage signal.
  • an embodiment of the present disclosure provides a memory, which at least includes the data receiving circuit as described in the first aspect.
  • Embodiments of the present disclosure provide a data receiving circuit and memory.
  • the voltage generating circuit can generate two reference voltage signals with different voltage values. It only needs to select the appropriate judgment result, and there is no need to compare the reference voltage according to the level state of the previous data signal. Real-time feedback adjustment of the voltage signal not only ensures the accuracy of data reception, but also shortens the signal feedback time.
  • Figure 1 is a schematic structural diagram of a resistance chain
  • Figure 2 is a schematic structural diagram of a selection output module
  • Figure 3 is a schematic structural diagram of a data receiving circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another data receiving circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a specific structural schematic diagram of a data receiving circuit provided by an embodiment of the present disclosure.
  • Figure 6A is a schematic partial structural diagram of the first voltage dividing adjustment module provided by an embodiment of the present disclosure
  • Figure 6B is a schematic diagram 2 of the partial structure of the first voltage division adjustment module provided by an embodiment of the present disclosure
  • Figure 6C is a schematic diagram 3 of the partial structure of the first voltage dividing adjustment module provided by an embodiment of the present disclosure
  • Figure 6D is a schematic diagram 4 of the partial structure of the first voltage dividing adjustment module provided by an embodiment of the present disclosure
  • Figure 6E is a schematic diagram 5 of the partial structure of the first voltage division adjustment module provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of simulation test results provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Double Data Rate SDRAM (DDR)
  • the 5th generation DDR standard (DDR5 Specification, DDR5);
  • Low Power DDR Low Power DDR (Low Power DDR, LPDDR);
  • LPDDR5 The fifth generation LPDDR standard (LPDDR5 Specification, LPDDR5);
  • DFE Decision Feedback Equalizer
  • the data receiving circuit (DQ RX) of the semiconductor device needs to determine the logic level of the received data signal based on the reference voltage.
  • the level state of the previous data signal will affect the level state of the subsequent data signal.
  • the size of the reference voltage can be feedback adjusted according to the level state of the previous data signal (or the level state of multiple previous data signals), thereby compensating the impact of the previous data signal on the current data signal. The impact caused by the level state of the data signal.
  • the data receiving circuit can generate a reference voltage through a resistor chain and a selected output module. See Figure 1, which shows a schematic structural diagram of a resistor chain. Refer to Figure 2, which shows a schematic structural diagram of a selection output module.
  • the resistor chain includes multiple series-connected resistors and an enable switch. The first resistor is connected to the power signal vddq, and the last resistor is connected to the ground signal gnd. The control end of the enable switch receives the enable Signal En to control whether the resistor chain works.
  • the resistance chain also includes 32 control switch tubes.
  • the first control switch tube is used to short-circuit a resistor close to the power signal vddq
  • the second control switch tube is used to short-circuit two resistors close to the power signal vddq.
  • the 16 control switch tubes are used to short-circuit the 16 resistors close to the power signal vddq, and their control terminals receive the first signals EnV ⁇ 0> ⁇ EnV ⁇ 15> respectively;
  • the penultimate control switch tube is used to short-circuit the ground signal gnd. 1 resistor, the second to last control switch tube is used to short-circuit the two resistors close to the ground signal gnd...
  • the 16th control switch tube to the last is used to short-circuit the 16 resistors close to the ground signal gnd, and its control terminals receive the first
  • the inverted signal of the signal is EnVN ⁇ 0> ⁇ EnVN ⁇ 15>.
  • the selection output module is based on the second signal R0GrpEn ⁇ 15:0> and its inverted signal R0GrpEnN ⁇ 15:0>, the third signal R1GrpEn ⁇ 7:0> and its inverted signal R1GrpEnN ⁇ 7:0 >Select a voltage output node to output the reference voltage signal Vref, which can realize programmable changes in the voltage value of the reference voltage signal.
  • the voltage difference across each resistor can be set to 2.5 millivolts (mv). Therefore, the voltage value of the reference voltage signal derived from div4 to div188 can be 10 to 490 mV.
  • the data receiving circuit needs to adjust the working state of the resistor chain based on the level state feedback of the previous data signal, and select an appropriate voltage output node to output the reference voltage signal Vref.
  • the above-mentioned feedback adjustment process takes a certain amount of time, it affects the speed improvement of the memory.
  • FIG. 3 shows a schematic structural diagram of a data receiving circuit 10 provided by an embodiment of the present disclosure.
  • data receiving circuit 10 As shown in Figure 3, data receiving circuit 10:
  • the voltage generation circuit 11 is configured to output a first reference voltage signal and a second reference voltage signal in the first mode, and the voltage values of the first reference voltage signal and the second reference voltage signal are different;
  • the data circuit 12 is configured to receive a data signal, a first reference voltage signal and a second reference voltage signal, compare the data signal with the first reference voltage signal, and output a first target signal; compare the data signal and the second reference voltage signal. Compare and output a second target signal; wherein the data signal is one of several data signals arranged in series;
  • the selection circuit 13 is configured to receive the first target signal and the second target signal, and determine one of the first target signal and the second target signal as the target data signal based on the level state of the previous data signal of the data signal. .
  • the data receiving circuit 10 of the embodiment of the present disclosure can be applied to, but is not limited to, memories such as DRAM, SDRAM, DDR, etc.
  • the signal receiving function can be realized through the data receiving circuit 10 provided by the embodiment of the present disclosure.
  • the subsequent description is based on the assumption that the voltage value of the first reference voltage signal is smaller than the voltage value of the second reference voltage signal.
  • the target data signal is generated based on the comparison result between the current data signal and the first reference voltage signal; if the previous data signal is high level, the target data signal is generated based on the current data signal.
  • the comparison result of the data signal and the second reference voltage signal generates the target data signal.
  • the voltage generation circuit 11 can simultaneously generate two reference voltage signals with different voltage values. There is no need to perform real-time feedback adjustment of the reference voltage signal according to the level state of the previous data signal. It only needs to be based on the level state of the previous data signal. Selecting an appropriate one from the first target signal and the second target signal to generate the target data signal not only ensures the accuracy of data reception, but also shortens the signal feedback time, which is conducive to further improvement of memory speed.
  • the voltage generation circuit 11 is also configured to output a third reference voltage signal in the second mode; wherein the voltage value of the third reference voltage signal is located between the first reference voltage signal and the third reference voltage signal. between the voltage value and the voltage value of the second reference voltage signal;
  • the data circuit 12 is also configured to receive a third reference voltage signal, compare the data signal with the third reference voltage signal, and output a target data signal.
  • the voltage generation circuit 11 only generates a third reference voltage signal, and then the voltage of the third reference voltage signal is subsequently calculated based on the level state of the previous data signal (previous data bit). The value is adjusted to compensate for the impact of the previous data signal on the current data signal, and is used to determine the logic level of the current data signal.
  • voltage generation circuit 11 includes:
  • the first voltage generation module 111 is configured to receive a first control signal group; in the first mode, based on the first control signal group, output a first weak voltage signal weakout1 and a second weak voltage signal weakout2;
  • the second voltage generation module 112 is configured to receive the second control signal group; in the first mode, based on the second control signal group, output the first strong voltage signal strgout1 and the second strong voltage signal strgout2;
  • the first selector 113 is configured to receive the strong and weak selection signal, the first weak voltage signal weakout1 and the first strong voltage signal strgout1; when the strong and weak selection signal is in the first state, output the first strong voltage signal strgout1 as the first Reference voltage signal Vref1; or, when the strong and weak selection signal is in the second state, output the first weak voltage signal weakout1 as the first reference voltage signal Vref1;
  • the second selector 114 is configured to receive the strong and weak selection signal, the second weak voltage signal weakout2 and the second strong voltage signal strgout2, and when the strong and weak selection signal is in the first state, output the second strong voltage signal strgout2 as the second Reference voltage signal Vref2; or, when the strong and weak selection signal is in the second state, the second weak voltage signal weakout2 is output as the second reference voltage signal Vref2.
  • the driving strength of the first strong voltage signal strgout1 is greater than the driving strength of the first weak voltage signal weakout1
  • the driving strength of the second strong voltage signal strgout2 is greater than the driving strength of the second weak voltage signal weakout2.
  • the first strong voltage signal strgout1/the second strong voltage signal strgout2 with greater driving intensity as the first reference voltage signal Vref1/the second reference voltage signal Vref2;
  • the first weak voltage signal weakout1/the second weak voltage signal weakout2 with smaller driving intensity can be used as the first reference voltage signal Vref1/the second reference voltage signal Vref2 to achieve the power saving effect.
  • the strong and weak selection signal may include a pair of inverted signals Otamux and Weakmux.
  • the strong and weak selection signal being in the first state means: Otamux is at a high level and Weakmux is at a low level;
  • the strong and weak selection signals may include only one signal.
  • the voltage generation circuit 11 further includes:
  • the first code generator 115 is configured to generate a first control signal group
  • a second code generator 116 configured to generate a second set of control signals
  • the voltage difference between the first weak voltage signal weakout1 and the second weak voltage signal weakout2 is a first value.
  • the first value is determined by the first control signal group, and the first strong voltage signal strgout1
  • the voltage difference between strgout2 and the second strong voltage signal strgout2 is a second value, and the second value is determined by the second control signal group.
  • the first value is the same as the second value, that is, "the voltage difference between the first strong voltage signal strgout1 and the second strong voltage signal strgout2" and “the voltage difference between the first weak voltage signal weakout1 and the second weak voltage signal weakout2" "pressure difference" is always equal.
  • the second code generator 116 includes a mapping module 116a, a mode register 116b, an adder 116c and an adder 116d.
  • the mapping module 116a generates StrgTrm ⁇ 5 based on Trmfs ⁇ 4:0>: 0>, the mode register 116b outputs MRVref ⁇ 6:0>, the adder 116c adds StrgTrm ⁇ 5:0> and MRVref ⁇ 6:0>, and the adder 116d adds the output result of the adder 116c to Calcode ⁇ 5: 0>Perform addition processing to obtain the first control signal group;
  • the first code generator 115 includes a calculation module 115a and an adder 115b, the calculation module 115a is configured to generate Wktrm ⁇ 5:0>, and the adder 115b pairs Wktrm ⁇ 5:0 > Perform addition processing with the output of the adder 116c to obtain the second control signal group.
  • the first control signal group and the second control signal group will produce similar changes, ensuring that "the first strong voltage signal strgout1 and the second The voltage difference between the strong voltage signal strgout2 is equal to the voltage difference between the first weak voltage signal weakout1 and the second weak voltage signal weakout2.
  • voltage generation circuit 11 further includes:
  • the calibration module 117 is configured to receive the first strong voltage signal strgout1 and the first weak voltage signal weakout1 in the first mode, compare the voltage values of the first strong voltage signal strgout1 and the first weak voltage signal weakout1, and output the first comparison Signal;
  • the first code generator 115 is further configured to receive a first comparison signal in the first mode, adjust the first control signal group based on the first comparison signal, and adjust the voltage value of the first weak voltage signal weakout1 step by step,
  • the first strong voltage signal strgout1 and the first weak voltage signal weakout1 have the same voltage value
  • the first strong voltage signal strgout1 and the second weak voltage signal weakout2 have the same voltage value.
  • the calibration module 117 can directly realize that the first strong voltage signal strgout1 and the first weak voltage signal weakout1 have the same voltage, due to the aforementioned "voltage difference between the first strong voltage signal strgout1 and the second strong voltage signal strgout2" ” is equal to “the voltage difference between the first weak voltage signal weakout1 and the second weak voltage signal weakout2”, so the voltage values of the second strong voltage signal strgout2 and the second weak voltage signal weakout2 are also the same.
  • the first voltage generation module 111 is also configured to output a third weak voltage signal weakout3 based on the first control signal group in the second mode;
  • the second voltage generation module 112 is further configured to output the third strong voltage signal strgout3 based on the second control signal group in the second mode;
  • the first selector 113 is also configured to receive the strong and weak selection signal, the third strong voltage signal strgout3 and the third weak voltage signal weakout3, and when the strong and weak selection signal is in the first state, output the third strong voltage signal strgout3 as the third strong voltage signal strgout3.
  • the driving strength of the third strong voltage signal strgout3 is greater than the driving strength of the third weak voltage signal weakout3.
  • the first weak voltage signal weakout1 and the third weak voltage signal weakout3 may share the same signal path; for the second voltage generation module 112, the first strong voltage signal strgout1 and the third strongest voltage signal strgout3 can share the same signal path, thereby reducing the number of signal paths and reducing control costs.
  • the second selector 114 selects the first strong voltage signal strgout1 and the first weak voltage signal weakout1 based on the strong and weak selection signals; in the second mode, the second selector 114 selects the first strong voltage signal strgout1 and the first weak voltage signal weakout1 based on the strong and weak selection signals.
  • the strong and weak selection signals select the third strong voltage signal strgout3 and the third weak voltage signal weakout3.
  • the calibration module 117 is also configured to receive the third strong voltage signal strgout3 and the third weak voltage signal weakout3, and compare the voltage values of the third strong voltage signal strgout3 and the third weak voltage signal weakout3, Output the second comparison signal;
  • the first code generator 115 is also configured to receive a second comparison signal, adjust the first control signal group based on the second comparison signal, and adjust the voltage value of the third weak voltage signal weakout3 step by step, so that the third strong voltage signal
  • the voltage values of strgout3 and the third weak voltage signal weakout3 are the same.
  • the first voltage generation module 111 includes a first voltage division adjustment module 111a, and the first voltage division adjustment module 111a includes a first main resistance chain 21 and a first auxiliary resistance chain 22, See Figure 6A and Figure 6B for details.
  • the first main resistance chain 21 and the first auxiliary resistance chain 22 are connected through the first connection point and the second connection point, and the first connection point is connected in series to the second connection point and the first main resistance chain. 21 between the ground terminals.
  • the first auxiliary resistance chain 22 is connected in series in the first main resistance chain 21, and the first connection point refers to the "first auxiliary resistance chain 22 and the first main resistance chain” close to the ground.
  • the connection point of the resistance chain 21" refers to "the connection point of the first auxiliary resistance chain 22 and the first main resistance chain 21" close to the power end.
  • the first voltage division adjustment module 111a is configured to adjust the resistance distribution state of the first main resistance chain 21 to output the first weak voltage signal through the first connection point based on the first control signal group, and adjust the first auxiliary resistance.
  • the resistance distribution state of the chain 22 is such that a second weak voltage signal is output through the second connection point.
  • the first voltage division adjustment module 111a is also configured to adjust the resistance distribution state of the first main resistance chain 21 based on the first control signal group to output the third weak voltage through the voltage output node of the first main resistance chain 21. voltage signal.
  • the first auxiliary resistance chain 22 is connected in series to the first main resistance chain 21 and forms the first connection point and the second connection point, respectively outputting the first weak voltage signal weakout1 and the second weak voltage signal. weakout2;
  • the first auxiliary resistance chain 22 is not connected to the first main resistance chain 21, that is, the first auxiliary resistance chain 22 does not play a role, and the voltage output node of the first main resistance chain 21 outputs the third weakest value. Voltage signal weakout3.
  • FIGS. 6A to 6E Please refer to FIGS. 6A to 6E to describe the specific circuit structure of the first main resistor chain 21 below.
  • the first main resistor chain 21 includes a plurality of first resistors arranged in series (including the shaded resistors and the unshaded resistors in FIG. 6A ). One end of the first first resistor is connected to the first power end. connection, the other end of the last first resistor is connected to the ground terminal gnd.
  • the first main resistance chain 21 also includes A first switching tubes close to the first power supply terminal and A first switching tubes close to the ground terminal. The first ends of the A first switching tubes close to the first power supply terminal are connected to the first power supply terminal. terminals are connected, and the first terminals of the A first switch tubes close to the ground terminal are connected to the ground terminal.
  • a first resistors close to the first power supply terminal and A first resistors close to the ground terminal are recorded as first edge resistors, that is, the hatched resistors in FIG. 6A .
  • the a-th first switching tube is used to short-circuit the a first edge resistor; in the direction away from the first power supply terminal, the a-th first switching tube is used to short-circuit the a first edge resistor.
  • Resistance; a and A are both positive integers, and a is less than or equal to A, and A is less than half of the total number of first resistors.
  • every C first resistors lead to a voltage output node, such as div4, div12...div92 in Figure 6A , div100...div188.
  • the first main resistance chain 21 is provided with 16 first edge resistors and 16 first switching tubes (the control terminal of which receives The first signal EnV ⁇ 15:0>), the first first switch tube is short-circuited to the first resistor, the second first switch tube is short-circuited to the first to second first edge resistors...the 16th The first switching tube shorts the 1st to 16th first edge resistors; 16 first edge resistors and 16 first switching tubes are also provided near the ground end (the control terminals respectively receive the inverted phase of the first signal).
  • Signal EnVN ⁇ 0:15> the working principle is similar.
  • the first signal EnV ⁇ 15:0> and its inverted signal EnVN ⁇ 15:0> both come from the first control signal group.
  • every eight first resistors lead to a voltage output node, that is, div4, div12...div188.
  • every eight first resistors are actually connected in series with a second switch tube (the control end of which receives the fourth signal R0pwlpEn ⁇ 15:0> and the fifth signal R1pwlpEn ⁇ 7: 0>), since all the second switch tubes are turned on in the second mode, the second switch tubes can be temporarily regarded as wires.
  • the first voltage generation module 111 also includes a first selection output module.
  • the input terminal of the first selection output module is connected to all voltage output nodes.
  • the first selection output module controls the first switching tube based on the first control signal group. On or off; in the second mode, the first selection output module also selects a voltage output node to output the preset third weak voltage signal weakout3 based on the first control signal group.
  • the first power terminal in the second mode is a constant voltage power supply.
  • a voltage output node can be determined from different voltage output nodes div4, div12...div188 through the first selection output module, thereby outputting the required third voltage signal.
  • the two first edge resistors near the first power supply terminal can be short-circuited by controlling the working state of the first switch tube, and the two first edge resistors far away from the ground terminal can be controlled. Additional connections are made (that is, the number of overall resistors of the first main resistor chain 21 remains unchanged), so that the voltage output node div12 is equivalent to the voltage output node div14 to achieve the output of a specific voltage value.
  • the resistance of the first edge resistor is R/2, and the resistance of the other first resistors except the first edge resistor is R.
  • 200 equivalent resistors with a resistance of R are fixedly connected to the first main resistor chain 21.
  • the divided voltage of each equivalent resistor is 2.5mV.
  • the third weak voltage signal weakout3 is derived from any one of div4 to div188, its voltage value can achieve a programmable change of 10 to 490mV.
  • the first selection output module refers to the conceptual module that implements the control function in the second mode, and its corresponding hardware circuit at least includes a plurality of first data selectors 23 and a plurality of second data selectors as shown in Figure 6C 24.
  • the control end of the first data selector 23 and the control end of the second data selector 24 receive the same signal, that is, the second signal R0GrpEn ⁇ 15:0> and the third signal R1GrpEn ⁇ 7:0>.
  • R0GrpEn ⁇ 15:0> and R1GrpEn ⁇ 7:0> is high level (it can also be low level in some scenarios), so the first data selector 23 selects the corresponding voltage output node to output The third weak voltage signal.
  • the second signal R0GrpEn ⁇ 15:0> and the third signal R1GrpEn ⁇ 7:0> both come from the first control signal group.
  • the second data selectors 24 actually also have signal output, but The output signal of the second data selector 24 is not used in the second mode, and the second data selector 24 may not be enabled to save energy consumption.
  • a second switch tube is connected in series between the two first resistors corresponding to each voltage output node.
  • the first auxiliary resistance chain 22 includes N ⁇ B second resistors connected in series.
  • the first auxiliary resistance chain 22 also includes B third switching tubes. One end of the B third switching tubes is connected to the third switching tube.
  • the b-th third switch tube is used to short-circuit N ⁇ b second resistors, N, B and b are all positive integers, and b is less than or equal to B, N ⁇ C.
  • the second auxiliary resistor chain includes a total of 28 second resistors and 7 third switch tubes (the control end receives the sixth signal dfeN ⁇ 7:1> ).
  • the first third switch tube can short-circuit the first to fourth second resistors
  • the second third switch tube can short-circuit the first to eighth resistors
  • the seventh third switch tube can short-circuit Connect the 1st to 28th second resistor.
  • the sixth signal dfeN ⁇ 7:1> comes from the first control signal group.
  • the first voltage generation module 111 also includes a second selection output module, which is used to control the conduction or cutoff of the second switch tube and the third switch tube based on the first control signal group.
  • the second selection output module is specifically used to control any second switching tube to turn off, so that the first auxiliary resistance chain 22 replaces a first resistor and is connected in series to the first main resistance chain 21 and forms a first The connection point and the second connection point; and, the preset first weak voltage signal is output through the first connection point, and the preset second weak voltage signal is output through the second connection point.
  • first auxiliary resistance chain 22 there are physical connection lines between the first end of the first auxiliary resistance chain 22 and all voltage output nodes (such as div4, div12...), and the second end of the first auxiliary resistance chain 22 is connected to all voltage output nodes. There is a physical connection line for the next node (such as div5, div13). Please note that when the second switch tube is turned on, it is equivalent to the corresponding first resistor "short-circuiting" the first auxiliary resistance chain 22. At this time, the first auxiliary resistance chain 22 is not connected to the first main resistance chain 21. .
  • the first auxiliary resistor chain 22 is equivalent to replacing the corresponding second resistor in series.
  • the node div101 is connected to the first end of the first auxiliary resistance chain 22 to form a second connection point
  • the node div100 is connected to the second end of the first auxiliary resistance chain 22 to form the first connection point.
  • the first connection point in the first mode may be any voltage output node in the second mode.
  • the first power terminal in the first mode is a constant current power supply.
  • a second switch tube for example, the second switch tube corresponding to R0pwlpEn ⁇ 12>
  • the first auxiliary resistor chain 22 and The first main resistance chain 21 is connected in series to form a path, and the node 100 serves as the first connection point to output the first weak voltage signal weakout1, and the node div101 serves as the second connection point to output the second weak voltage signal weakout2.
  • the divided voltage of each second resistor is fixed (for example, 2.5mV).
  • the second selection output module refers to the conceptual module that implements the control function in the first mode, and its corresponding hardware circuit also includes at least a plurality of first data selectors 23 and a plurality of second data selections as shown in Figure 6C 24.
  • the node selected by the first data selector 23 is the location of the first connection point
  • the node selected by the second data selector 24 is the location of the second connection point, thereby outputting the first weak voltage signal. weakout1 and the second weak voltage signal weakout2.
  • the first main resistor chain 21 is also connected in series with a fourth switch tube, which receives the enable signal En and is used to control whether the first voltage dividing adjustment module 111a works or not.
  • the first voltage division adjustment module 111a also includes a first constant current power supply and a first constant voltage power supply; the first voltage division adjustment module 111a is configured to, in the first mode, The first constant current power supply is determined as the first power supply terminal; or, in the second mode, the first constant voltage power supply vddq is determined as the first power supply terminal.
  • the first voltage division adjustment module 111a also includes a switch tube 231 and a switch tube 232, which are used to switch the power supply type according to the mode selection signal dfeEn and its inversion signal dfeEnN.
  • the first constant current power supply may include two switch tubes.
  • the control terminal of the first switch tube receives the seventh signal Pbias
  • the control terminal of the second transistor receives the eighth signal Pcasc
  • the control terminal of the second transistor receives the eighth signal Pcasc.
  • the two transistors mainly play the role of isolating noise and preventing the series circuit from affecting the output voltage of the first switching transistor, causing the output voltage of the first switching transistor to fluctuate.
  • the first voltage division adjustment module 111a also includes a plurality of OR gates 25 and a plurality of OR gates 26, respectively used to perform an OR operation on the mode selection signal dfeEn and the second signal ROGrpEbN ⁇ 15:0>.
  • the fourth signal R0pwlpEn ⁇ 15:0> is obtained
  • the fifth signal R1pwlpEn ⁇ 7:0> is obtained by ORing the mode selection signal dfeEn and the third signal R1GrpEbN ⁇ 7:0>.
  • the second switch tubes in the first main resistance chain 21 are both turned on, and the first signal EnV ⁇ 15:0> and its inverted signal EnVN ⁇ 15:0> control the resistance distribution state of the first main resistance chain 21, and use the fourth signal R0GrpEbN ⁇ 15:0> and the fifth signal R1GrpEbN ⁇ 7:0> to select one
  • the voltage output node outputs a third weak voltage signal weakout3.
  • the second voltage generation module 112 includes a second voltage division adjustment module 112a, a first operational amplifier 112b and a second operational amplifier 112c, and the second voltage division adjustment module 112a includes a second voltage division adjustment module 112a.
  • Main resistor chain and second auxiliary resistor chain are examples of main resistor chain and second auxiliary resistor chain.
  • the second main resistance chain and the second auxiliary resistance chain are connected through the third connection point and the fourth connection point, and the third connection point is connected in series between the fourth connection point and the ground terminal of the second main resistance chain.
  • the second voltage division adjustment module 112a is configured to adjust the resistance distribution state of the second main resistance chain to output the first voltage signal through the third connection point based on the second control signal group, and adjust the second auxiliary resistance chain
  • the resistance distribution state is to output the second voltage signal through the fourth connection point
  • the first operational amplifier 112b is configured to receive the first voltage signal, amplify the first voltage signal, and output the first strong voltage signal strgout1
  • the second operation The amplifier 112c is configured to receive the second voltage signal, amplify the second voltage signal, and output the second strong voltage signal strgout2.
  • the second main resistance chain and the second auxiliary resistance chain are in an isolated state;
  • the second voltage division adjustment module is also configured to adjust the resistance distribution of the second main resistance chain based on the second control signal group. state, to output the third voltage signal through the voltage output node of the second main resistor chain;
  • the first operational amplifier 112b is configured to receive the third voltage signal, amplify the third voltage signal, and output the third strong voltage signal strgout3.
  • the structure of the second partial voltage adjustment module 112a can be understood and implemented with reference to the first partial voltage adjustment module 111a.
  • the second voltage generation module 112 is additionally provided with an operational amplifier, thereby outputting a reference voltage signal with higher driving strength.
  • the first voltage division adjustment module (and the second voltage division adjustment module) may also adopt a two-stage main resistance chain structure, thereby generating two different voltage signals in the first mode.
  • the structure of the main and auxiliary resistance chains ie, the circuit structure of FIG. 6A to FIG. 6E
  • Figure 7 shows a schematic diagram of simulation test results provided by an embodiment of the present disclosure.
  • curve (a) refers to the voltage changes corresponding to the structure of the main and auxiliary resistance chains
  • curve (b) refers to the voltage changes corresponding to the circuit structure of the two-stage main resistance chain.
  • Embodiments of the present disclosure provide a data receiving circuit, in which the voltage generating circuit has two working modes.
  • the voltage generating circuit can generate two reference voltage signals with different voltage values, and then determines the data signal.
  • the appropriate reference voltage signal can be selected to compensate for the voltage impact of the previous data signal on the current data signal, which not only improves the accuracy of data signal reception but also makes it faster;
  • the voltage generation circuit can generate a reference voltage signal, and at the same time, the reference voltage signal can be adjusted according to the level state of the previous data signal to compensate for the voltage impact of the previous data signal on the current data signal.
  • FIG. 8 shows a schematic structural diagram of a memory 30 provided by an embodiment of the present disclosure.
  • the memory 30 includes the aforementioned data receiving circuit 10 .
  • the voltage generating circuit adopts the structure of FIG. 6A to FIG. 6E to generate two/one reference voltage signals.
  • the first main resistance chain uses the constant voltage power supply vddq, and the first auxiliary resistance chain is not connected, leaving only one output for subsequent generation of the third reference voltage signal;
  • the first main resistance chain uses a constant current power supply, that is, the change in the number of resistors will not affect the current of the first main resistance chain.
  • the first auxiliary resistance chain is connected to the first main resistance chain, and there are two outputs and the voltage of the two outputs.
  • the difference is the divided voltage of the first auxiliary resistor chain, so as to subsequently generate the first reference voltage signal and the second reference voltage signal.
  • the second reference voltage signal or the third reference voltage signal
  • the voltage difference between the first reference voltage signal and the second reference voltage signal can also achieve a certain range of programmable changes;
  • the structure of Figures 6A to 6E uses a wider voltage range than the bias current compensation method, and generates a larger current value and a shorter settling time than the structure of the two-stage main resistor chain.
  • Embodiments of the present disclosure provide a data receiving circuit and memory.
  • the voltage generating circuit can generate two reference voltage signals with different voltage values. It only needs to select the appropriate judgment result, and there is no need to compare the reference voltage according to the level state of the previous data signal. Real-time feedback adjustment of the voltage signal not only ensures the accuracy of data reception, but also shortens the signal feedback time.

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Abstract

本公开实施例提供了一种数据接收电路和存储器，该电路包括：电压产生电路，配置为在第一模式下，输出第一参考电压信号和第二参考电压信号；数据电路，配置为对数据信号和第一参考电压信号进行比较，输出第一目标信号；对数据信号和第二参考电压信号进行比较，输出第二目标信号；其中，数据信号是串行排列的若干个数据信号的其中一个；选择电路，配置为基于数据信号的前一数据信号的电平状态，将第一目标信号和第二目标信号的二者之一确定为目标数据信号。

Description

一种数据接收电路和存储器
相关申请的交叉引用
本公开基于申请号为202210998008.6、申请日为2022年08月19日、发明名称为“一种数据接收电路和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种数据接收电路和存储器。
背景技术
半导体装置通过其中的数据接收电路来接收数据，数据接收电路使用参考电压来确定所接收的数据信号的逻辑电平。对于数据接收电路而言，在前的数据信号的电平状态会对在后的数据信号的电平状态产生一些影响，所以需要利用判决反馈平衡原理消除在前的数据信号的不利影响，避免数据信号的误判。然而，判决反馈平衡的过程存在较大耗时，影响了数据接收电路的性能。
发明内容
本公开提供了一种数据接收电路和存储器，不仅能够保证数据接收的正确性，而且缩短了信号反馈时间。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种数据接收电路，所述数据接收电路包括电压产生电路，配置为在第一模式下，输出第一参考电压信号和第二参考电压信号，且所述第一参考电压信号和所述第二参考电压信号的电压值不同；
数据电路，配置为接收数据信号、所述第一参考电压信号和所述第二参考电压信号，对所述数据信号和所述第一参考电压信号进行比较，输出第一目标信号；对所述数据信号和所述第二参考电压信号进行比较，输出第二目标信号；其中，所述数据信号是串行排列的若干个数据信号的其中一个；
选择电路，配置为接收所述第一目标信号和所述第二目标信号，基于所述数据信号的前一数据信号的电平状态，将所述第一目标信号和所述第二目标信号的二者之一确定为目标数据信号。
在一些实施例中，所述电压产生电路，还配置为在第二模式下，输出第三参考电压信号；其中，所述第三参考电压信号的电压值位于所述第一参考电压信号的电压值和所述第二参考电压信号的电压值之间；所述数据电路，还配置为接收所述第三参考电压信号，对所述数据信号和所述第三参考电压信号进行比较，输出目标数据信号。
在一些实施例中，所述电压产生电路包括：第一电压产生模块，配置为接收 第一控制信号组；在所述第一模式下，基于所述第一控制信号组，输出第一弱电压信号和第二弱电压信号；第二电压产生模块，配置为接收第二控制信号组；在所述第一模式下，基于所述第二控制信号组，输出第一强电压信号和第二强电压信号；第一选择器，配置为接收强弱选择信号、所述第一弱电压信号和所述第一强电压信号；在所述强弱选择信号处于第一状态时，将所述第一强电压信号输出为所述第一参考电压信号；或者，在所述强弱选择信号处于第二状态时，将所述第一弱电压信号输出为所述第一参考电压信号；第二选择器，配置为接收所述强弱选择信号、所述第二弱电压信号和所述第二强电压信号，在所述强弱选择信号处于所述第一状态时，将所述第二强电压信号输出为所述第二参考电压信号；或者，在所述强弱选择信号处于所述第二状态时，将所述第二弱电压信号输出为所述第二参考电压信号；其中，所述第一强电压信号的驱动强度大于所述第一弱电压信号的驱动强度，且所述第二强电压信号的驱动强度大于所述第二弱电压信号的驱动强度。
在一些实施例中，所述电压产生电路还包括：第一编码发生器，配置为产生所述第一控制信号组；第二编码发生器，配置为产生所述第二控制信号组；其中，在第一模式下，所述第一弱电压信号和所述第二弱电压信号之间的电压差为第一值，所述第一值是由所述第一控制信号组确定的；所述第一强电压信号和所述第二强电压信号之间的电压差为第二值，所述第二值是由所述第二控制信号组确定的；所述第一值与所述第二值相同。
在一些实施例中，所述电压产生电路还包括：校准模块，配置为在第一模式下，接收所述第一强电压信号和所述第一弱电压信号，对所述第一强电压信号和所述第一弱电压信号进行电压值比较，输出第一比较信号；所述第一编码发生器，还配置为在第一模式下，接收所述第一比较信号，基于所述第一比较信号对所述第一控制信号组进行调整，以步进调整所述第一弱电压信号的电压值，使得所述第一强电压信号和所述第一弱电压信号的电压值相同，且所述第二强电压信号和所述第二弱电压信号的电压值相同。
在一些实施例中，所述第一电压产生模块，还配置为在所述第二模式下，基于所述第一控制信号组，输出第三弱电压信号；所述第二电压产生模块，还配置为在所述第二模式下，基于所述第二控制信号组，输出第三强电压信号；所述第一选择器，还配置为接收所述强弱选择信号、所述第三弱电压信号和所述第三强电压信号，在所述强弱选择信号处于所述第一状态时，将所述第三强电压信号输出为所述第三参考电压信号；或者，在所述强弱选择信号处于所述第二状态时，将所述第三弱电压信号输出为所述第三参考电压信号；其中，所述第三强电压信号的驱动强度大于所述第三弱电压信号的驱动强度。
在一些实施例中，所述校准模块，还配置为接收所述第三强电压信号和所述第三弱电压信号，对所述第三强电压信号和所述第三弱电压信号进行电压值比较，输出第二比较信号；所述第一编码发生器，还配置为接收所述第二比较信号，基于所述第二比较信号对所述第一控制信号组进行调整，以步进调整所述第三弱电压信号的电压值，使得所述第三强电压信号和所述第三弱电压信号的电压值相同。
在一些实施例中，所述第一电压产生模块包括第一分压调整模块，且所述第一分压调整模块包括第一主电阻链和第一辅电阻链；在第一模式下，所述第一主 电阻链和所述第一辅电阻链通过第一连接点和第二连接点连接，所述第一连接点串接于所述第二连接点和所述第一主电阻链的接地端之间；其中，所述第一分压调整模块，配置为基于所述第一控制信号组，调整所述第一主电阻链的阻值分布状态以通过所述第一连接点输出第一弱电压信号，调整所述第一辅电阻链的阻值分布状态以通过所述第二连接点输出第二弱电压信号。
在一些实施例中，在第二模式下，所述第一主电阻链和所述第一辅电阻链处于隔离状态；其中，所述第一分压调整模块，还配置为基于所述第一控制信号组，调整所述第一主电阻链的阻值分布状态，以通过所述第一主电阻链的电压输出节点输出第三弱电压信号。
在一些实施例中，所述第一主电阻链包括串联设置的多个第一电阻，首个所述第一电阻的一端与第一电源端连接，末个所述第一电阻的另一端与接地端连接；所述第一主电阻链还包括A个靠近所述第一电源端的第一开关管以及A个靠近所述接地端的所述第一开关管，靠近所述第一电源端的A个所述第一开关管的第一端均与所述第一电源端连接，靠近所述接地端的A个所述第一开关管的第一端均与所述接地端连接；记靠近所述第一电源端的A个第一电阻以及靠近接地端的A个所述第一电阻为第一边缘电阻；在靠近所述第一电源端的方向上，第a个所述第一开关管用于短接a个所述第一边缘电阻；在远离所述第一电源端的方向上，第a个所述第一开关管用于短接a个所述第一边缘电阻；a、A均为正整数，且a小于或等于A，A小于第一电阻总数量的一半；在不包含所述第一边缘电阻的部分所述第一主电阻链中，每隔C个所述第一电阻引出一个电压输出节点，所述第一电压产生模块还包括第一选择输出模块，所述第一选择输出模块的输入端与所有的所述电压输出节点连接，所述第一选择输出模块基于所述第一控制信号组控制所述第一开关管的导通或截止；在第二模式下，所述第一选择输出模块还基于所述第一控制信号组选择一所述电压输出节点输出预设的所述第三弱电压信号。
在一些实施例中，在所述第一主电阻链中，每一所述电压输出节点对应的两个所述第一电阻之间串接有一个第二开关管；所述第一辅电阻链包括串联的N×B个第二电阻，所述第一辅电阻链还包括B个第三开关管，B个所述第三开关管的一端连接于所述第一辅电阻链的同一端，第b个所述第三开关管用于短接N×b个第二电阻，N、B以及b均为正整数，且b小于或等于B，N≠C；所述第一电压产生模块还包括第二选择输出模块，所述第二选择输出模块用于基于所述第一控制信号组控制所述第二开关管以及所述第三开关管的导通或截止；在第一模式下，所述第二选择输出模块具体用于控制任意一个所述第二开关管截止，以使得所述第一辅电阻链代替一个所述第二电阻串联接入所述第一主电阻链，并形成所述第一连接点和所述第二连接点；以及，通过所述第一连接点输出预设的所述第一弱电压信号，通过所述第二连接点输出预设的所述第二弱电压信号。
在一些实施例中，所述第一分压调整模块还包括第一恒流电源和第一恒压电源；所述第一分压调整模块，配置为在所述第一模式下，将所述第一恒流电源确定为所述第一电源端；或者，在所述第二模式下，将所述第一恒压电源确定为所述第一电源端。
在一些实施例中，所述第二电压产生模块包括第二分压调整模块、第一运算放大器和第二运算放大器，且所述第二分压调整模块包括第二主电阻链和第二辅 电阻链；在第一模式下，所述第二主电阻链和所述第二辅电阻链通过第三连接点和第四连接点连接，所述第三连接点串接于所述第四连接点和所述第二主电阻链的接地端之间；其中，所述第二分压调整模块，配置为基于所述第二控制信号组，调整所述第二主电阻链的阻值分布状态以通过所述第三连接点输出所述第一电压信号，调整所述第二辅电阻链的阻值分布状态以通过所述第四连接点输出第二电压信号；所述第一运算放大器，配置为接收所述第一电压信号，对所述第一电压信号进行放大，输出所述第一强电压信号；所述第二运算放大器，配置为接收所述第二电压信号，对所述第二电压信号进行放大，输出所述第二强电压信号。
在一些实施例中，在第二模式下，所述第二主电阻链和所述第二辅电阻链处于隔离状态；其中，所述第二分压调整模块，还配置为基于所述第二控制信号组，调整所述第二主电阻链的阻值分布状态，以通过所述第二主电阻链的电压输出节点输出第三电压信号；所述第一运算放大器，配置为接收所述第三电压信号，对所述第三电压信号进行放大，输出所述第三强电压信号。
第二方面，本公开实施例提供了一种存储器，所述存储器至少包括如第一方面所述的数据接收电路。
本公开实施例提供了一种数据接收电路和存储器，通过电压产生电路能够产生电压值不同的2个参考电压信号，仅需要选择合适的判决结果，无需根据前一数据信号的电平状态对参考电压信号进行实时反馈调整，不仅能够保证数据接收的正确性，而且缩短了信号反馈时间。
附图说明
图1为一种电阻链的结构示意图；
图2为一种选择输出模块的结构示意图；
图3为本公开实施例提供的一种数据接收电路的结构示意图；
图4为本公开实施例提供的另一种数据接收电路的结构示意图；
图5为本公开实施例提供的一种数据接收电路的具体结构示意图；
图6A为本公开实施例提供的第一分压调整模块的局部结构示意图一；
图6B为本公开实施例提供的第一分压调整模块的局部结构示意图二；
图6C为本公开实施例提供的第一分压调整模块的局部结构示意图三；
图6D为本公开实施例提供的第一分压调整模块的局部结构示意图四；
图6E为本公开实施例提供的第一分压调整模块的局部结构示意图五；
图7为本公开实施例提供的仿真测试结果示意图；
图8为本公开实施例提供的一种存储器的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是 为了描述本公开实施例的目的，不是旨在限制本公开。在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
动态随机存取存储器(Dynamic Random Access Memory，DRAM)；
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)；
双倍数据速率内存(Double Data Rate SDRAM，DDR)；
第5代DDR标准(DDR5 Specification，DDR5)；
低功率DDR(Low Power DDR，LPDDR)；
第5代LPDDR标准(LPDDR5 Specification，LPDDR5)；
判决反馈均衡器(Decision Feedback Equalizer，DFE)；
目前，半导体装置的数据接收电路(DQ RX)需要依据参考电压确定所接收的数据信号的逻辑电平，此时在前的数据信号的电平状态会对在后的数据信号的电平状态产生一些影响。因此，可以根据前一数据信号的电平状态(也可以是前面多个数据信号的电平状态)反馈调整(用于判决当前数据信号的)参考电压的大小，从而补偿前一数据信号对当前数据信号的电平状态造成的影响。
数据接收电路可以通过电阻链和选择输出模块产生参考电压，参见图1，其示出了一种电阻链的结构示意图。参见图2，其示出了一种选择输出模块的结构示意图。如图1所示，电阻链包括多个串联的电阻和一个使能开关管，第1个电阻与电源信号vddq连接，最后一个电阻与地信号gnd连接，使能开关管的控制端接收使能信号En以控制电阻链是否工作。另外，电阻链还包括32个控制开关管，第1个控制开关管用于短接靠近电源信号vddq的1个电阻，第2个控制开关管用于短接靠近电源信号vddq的2个电阻……第16个控制开关管用于短接靠近电源信号vddq的16个电阻，其控制端分别接收第一信号EnV<0>～EnV<15>；倒数第1个控制开关管用于短接靠近地信号gnd的1个电阻，倒数第2个控制开关管用于短接靠近地信号gnd的2个电阻……倒数第16个控制开关管用于短接靠近地信号gnd的16个电阻，其控制端分别接收第一信号的反相信号EnVN<0>～EnVN<15>。在电阻链的中间部分，将相邻电阻之间的节点分别命令为div0、div1……div192，将div4、div12、div20……div188作为电压输出节点进行引出，即从div4开始每8个节点产生一个电压输出节点。如图2所示，选择输出模块根据第二信号R0GrpEn<15:0>及其反相信号R0GrpEnN<15:0>、第三信号R1GrpEn<7:0>及其反相信号R1GrpEnN<7:0>选择一个电压输出节点输出参考电压信号Vref，能够实现参考电压信号电压值的可编程变化。在这里，R0GrpEn<15:0>、R1GrpEn<7:0>中仅有一个信号处于指定状态(高电平或低电平)，以选择出相应的电压输出节点。在一些实施例中，在预设电流条件下，每个电阻两端的压差可设置为2.5毫伏(mv)，因此，从div4～div188引出的参考电压信号的电压值可以为10～490mV。
也就是说，数据接收电路需要根据前一数据信号的电平状态反馈调整电阻链的工作状态，并且选择合适的电压输出节点输出参考电压信号Vref。然而，由于上述的反馈调整过程需要占据一定的时间，影响了存储器的速度提高。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图3，其示出了本公开实施例提供的一种数据接收电路10的结构示意图。如图3所示，数据接收电路10：
电压产生电路11，配置为在第一模式下，输出第一参考电压信号和第二参考电压信号，且第一参考电压信号和第二参考电压信号的电压值不同；
数据电路12，配置为接收数据信号、第一参考电压信号和第二参考电压信号，对数据信号和第一参考电压信号进行比较，输出第一目标信号；对数据信号和第二参考电压信号进行比较，输出第二目标信号；其中，数据信号是串行排列的若干个数据信号的其中一个；
选择电路13，配置为接收第一目标信号和第二目标信号，基于数据信号的前一数据信号的电平状态，将第一目标信号和第二目标信号的二者之一确定为目标数据信号。
需要说明的是，本公开实施例的数据接收电路10可以应用但不限于存储器，例如DRAM、SDRAM、DDR等。另外，在其他模拟电路/数字电路中，均可通过本公开实施例提供的数据接收电路10实现信号接收功能。
在本公开实施例以第一参考电压信号的电压值小于第二参考电压信号的电压值进行后续说明。在第一模式中，如果前一数据信号为低电平，则根据当前的数据信号和第一参考电压信号的比较结果产生目标数据信号；如果前一数据信号为高电平，则根据当前的数据信号和第二参考电压信号的比较结果产生目标数据信号。这样，通过电压产生电路11能够同时产生电压值不同的2个参考电压信号，无需根据前一数据信号的电平状态对参考电压信号进行实时反馈调整，仅需要根据前一数据信号的电平状态从第一目标信号和第二目标信号中选择合适的一个产生目标数据信号，不仅能够保证数据接收的正确性，而且缩短了信号反馈时间，有利于存储器速度的进一步提高。
在一些实施例中，如图4所示，电压产生电路11，还配置为在第二模式下，输出第三参考电压信号；其中，第三参考电压信号的电压值位于第一参考电压信号的电压值和第二参考电压信号的电压值之间；
数据电路12，还配置为接收第三参考电压信号，对数据信号和第三参考电压信号进行比较，输出目标数据信号。
需要说明的是，在第二模式下，电压产生电路11仅产生一个第三参考电压信号，后续再基于前一数据信号(前一数据位)的电平状态对该第三参考电压信号的电压值进行调整，以补偿前一数据信号对当前的数据信号产生的影响，用于判断当前的数据信号的逻辑电平。
在一些实施例中，如图5所示，电压产生电路11包括：
第一电压产生模块111，配置为接收第一控制信号组；在第一模式下，基于第一控制信号组，输出第一弱电压信号weakout1和第二弱电压信号weakout2；
第二电压产生模块112，配置为接收第二控制信号组；在第一模式下，基于第二控制信号组，输出第一强电压信号strgout1和第二强电压信号strgout2；
第一选择器113，配置为接收强弱选择信号、第一弱电压信号weakout1和第一强电压信号strgout1；在强弱选择信号处于第一状态时，将第一强电压信号strgout1输出为第一参考电压信号Vref1；或者，在强弱选择信号处于第二状态时，将第一弱电压信号weakout1输出为第一参考电压信号Vref1；
第二选择器114，配置为接收强弱选择信号、第二弱电压信号weakout2和第二强电压信号strgout2，在强弱选择信号处于第一状态时，将第二强电压信号strgout2输出为第二参考电压信号Vref2；或者，在强弱选择信号处于第二状态时，将第二弱电压信号weakout2输出为第二参考电压信号Vref2。
在这里，第一强电压信号strgout1的驱动强度大于第一弱电压信号weakout1的驱动强度，且第二强电压信号strgout2的驱动强度大于第二弱电压信号weakout2的驱动强度。
需要说明的是，在数据接收电路10开始工作时，需要由驱动强度较大的第一强电压信号strgout1/第二强电压信号strgout2作为第一参考电压信号Vref1/第二参考电压信号Vref2；在数据接收电路10趋于稳定时，可以由驱动强度较小的第一弱电压信号weakout1/第二弱电压信号weakout2作为第一参考电压信号Vref1/第二参考电压信号Vref2，达到省电的效果。
示例性的，如图5所示，强弱选择信号可以包括一对反相信号Otamux和Weakmux，强弱选择信号处于第一状态是指：Otamux处于高电平，Weakmux处于低电平；强弱选择信号处于第二状态是指：Otamux处于低电平，Weakmux处于高电平。当然，在其他实施例中，强弱选择信号可以仅包括一个信号。
在一些实施例中，如图4所示，电压产生电路11还包括：
第一编码发生器115，配置为产生第一控制信号组；
第二编码发生器116，配置为产生第二控制信号组；
其中，在第一模式下，第一弱电压信号weakout1和第二弱电压信号weakout2之间的电压差为第一值，第一值是由第一控制信号组确定的，第一强电压信号strgout1和第二强电压信号strgout2之间的电压差为第二值，第二值是由第二控制信号组确定的。特别地，第一值与第二值相同，即“第一强电压信号strgout1和第二强电压信号strgout2之间的压差”与“第一弱电压信号weakout1和第二弱电压信号weakout2之间的压差”始终相等。
需要说明的是，第一编码发生器115和第二编码发生器116的内部结构需要根据实际应用场景进行设计，并非为本公开实施例的重点且不影响本公开实施例的理解。因此，仅以图5为例进行简单描述：第二编码发生器116包括映射模块116a、模式寄存器116b、加法器116c和加法器116d，映射模块116a基于Trmfs<4:0>产生StrgTrm<5:0>，模式寄存器116b输出MRVref<6:0>，加法器116c对StrgTrm<5:0>和MRVref<6:0>进行加法处理，加法器116d对加法器116c的输出结果和Calcode<5:0>进行加法处理以得到第一控制信号组；第一编码发生器115包括计算模块115a和加法器115b，计算模块115a配置为产生Wktrm<5:0>，加法器115b对Wktrm<5:0>和加法器116c的输出进行加法处理以得到第二控制信号组。这样，第一控制信号组和第二控制信号组的来源有一部分是相同的，即第一控制信号组和第二控制信号组会产生类似的变化，保证“第一强电压信号strgout1和第二强电压信号strgout2之间的压差”与“第一弱电压信号weakout1和第二弱 电压信号weakout2之间的压差”相等。
在一些实施例中，电压产生电路11还包括：
校准模块117，配置为在第一模式下，接收第一强电压信号strgout1和第一弱电压信号weakout1，对第一强电压信号strgout1和第一弱电压信号weakout1进行电压值比较，输出第一比较信号；
第一编码发生器115，还配置为在第一模式下，接收第一比较信号，基于第一比较信号对第一控制信号组进行调整，以步进调整第一弱电压信号weakout1的电压值，使得第一强电压信号strgout1和第一弱电压信号weakout1的电压值相同，且第一强电压信号strgout1和第二弱电压信号weakout2的电压值相同。
换句话说，通过校准模块117能够直接实现第一强电压信号strgout1和第一弱电压信号weakout1的电压相同，由于前述的“第一强电压信号strgout1和第二强电压信号strgout2之间的压差”与“第一弱电压信号weakout1和第二弱电压信号weakout2之间的压差”相等，所以第二强电压信号strgout2和第二弱电压信号weakout2的电压值也是相同的。
在一些实施例中，如图5所示，第一电压产生模块111，还配置为在第二模式下，基于第一控制信号组，输出第三弱电压信号weakout3；
第二电压产生模块112，还配置为在第二模式下，基于第二控制信号组，输出第三强电压信号strgout3；
第一选择器113，还配置为接收强弱选择信号、第三强电压信号strgout3和第三弱电压信号weakout3，在强弱选择信号处于第一状态时，将第三强电压信号strgout3输出为第三参考电压信号Vref3；或者，在强弱选择信号处于第二状态时，将第三弱电压信号weakout3输出为第三参考电压信号Vref3。在这里，第三强电压信号strgout3的驱动强度大于第三弱电压信号weakout3的驱动强度。
需要说明的是，对于第一电压产生模块111来说，第一弱电压信号weakout1和第三弱电压信号weakout3可以共享同一个信号路径；对于第二电压产生模块112来说，第一强电压信号strgout1和第三强电压信号strgout3可以共享同一个信号路径，从而减少信号路径的数量且降低控制成本。相应的，在第一模式下，第二选择器114是基于强弱选择信号对第一强电压信号strgout1和第一弱电压信号weakout1进行选择；在第二模式下，第二选择器114是基于强弱选择信号对第三强电压信号strgout3和第三弱电压信号weakout3进行选择。
类似的，在一些实施例中，校准模块117，还配置为接收第三强电压信号strgout3和第三弱电压信号weakout3，对第三强电压信号strgout3和第三弱电压信号weakout3进行电压值比较，输出第二比较信号；
第一编码发生器115，还配置为接收第二比较信号，基于第二比较信号对第一控制信号组进行调整，以步进调整第三弱电压信号weakout3的电压值，使得第三强电压信号strgout3和第三弱电压信号weakout3的电压值相同。
在一些实施例中，如图5所示，第一电压产生模块111包括第一分压调整模块111a，且第一分压调整模块111a包括第一主电阻链21和第一辅电阻链22，具体参见图6A和图6B。
首先，在第一模式下，第一主电阻链21和第一辅电阻链22通过第一连接点和第二连接点连接，第一连接点串接于第二连接点和第一主电阻链21的接地端 之间。换句话说，在第一模式下，第一辅电阻链22是串接在第一主电阻链21中的，且第一连接点是指靠近接地端的“第一辅电阻链22与第一主电阻链21的连接点”，第二连接点是指靠近电源端的“第一辅电阻链22与第一主电阻链21的连接点”。相应的，第一分压调整模块111a，配置为基于第一控制信号组，调整第一主电阻链21的阻值分布状态以通过第一连接点输出第一弱电压信号，调整第一辅电阻链22的阻值分布状态以通过第二连接点输出第二弱电压信号。
其次，在第二模式下，第一主电阻链21和第一辅电阻链22处于隔离状态，即第一辅电阻链22并没有接入第一主电阻链21。相应的，第一分压调整模块111a，还配置为基于第一控制信号组，调整第一主电阻链21的阻值分布状态，以通过第一主电阻链21的电压输出节点输出第三弱电压信号。
这样，在第一模式下，第一辅电阻链22串接于第一主电阻链21中并形成第一连接点和第二连接点，分别输出第一弱电压信号weakout1和第二弱电压信号weakout2；在第二模式下，第一辅电阻链22不接入第一主电阻链21，即第一辅电阻链22不发挥作用，由第一主电阻链21的电压输出节点输出第三弱电压信号weakout3。
请参考图6A～图6E，以下对第一主电阻链21的具体电路结构进行说明。
如图6A所示，第一主电阻链21包括串联设置的多个第一电阻(包括图6A中填充阴影的电阻和未填充阴影的电阻)，首个第一电阻的一端与第一电源端连接，末个第一电阻的另一端与接地端gnd连接。第一主电阻链21还包括A个靠近第一电源端的第一开关管以及A个靠近接地端的第一开关管，靠近第一电源端的A个第一开关管的第一端均与第一电源端连接，靠近接地端的A个第一开关管的第一端均与接地端连接。
为了方便说明，记靠近第一电源端的A个第一电阻以及靠近接地端的A个第一电阻为第一边缘电阻，即图6A中填充阴影的电阻。在靠近第一电源端的方向上，第a个第一开关管用于短接a个第一边缘电阻；在远离第一电源端的方向上，第a个第一开关管用于短接a个第一边缘电阻；a、A均为正整数，且a小于或等于A，A小于第一电阻总数量的一半。在不包含第一边缘电阻的部分第一主电阻链21(即图6A的虚线框部分)中，每隔C个第一电阻引出一个电压输出节点，例如图6A中的div4、div12……div92、div100……div188。
以A＝16、C＝8为例，如图6A所示，在靠近第一电源端的部分，第一主电阻链21设置16个第一边缘电阻和16个第一开关管(其控制端接收第一信号EnV<15:0>)，第1个第一开关管短接第1个电阻，第2个第一开关管短接第1个～第2个第一边缘电阻……第16个第一开关管短接第1个～第16个第一边缘电阻；在靠近接地端的部分同样设置16个第一边缘电阻和16个第一开关管(其控制端分别接收第一信号的反相信号EnVN<0：15>)，工作原理类似。第一信号EnV<15:0>及其反相信号EnVN<15:0>均来自于第一控制信号组。
在第一主电阻链21的中间部分，即图6A中的放大部分，每隔8个第一电阻引出一个电压输出节点，即div4、div12……div188。特别说明的是，如图6A所示，每隔8个第一电阻实际上还串联有一个第二开关管(其控制端接收第四信号R0pwlpEn<15：0>、第五信号R1pwlpEn<7：0>中的一位)，由于所有的第二开关管在第二模式中均是接通的，可以暂时将第二开关管视为导线。
以下对第二模式中的电路控制原理进行具体说明。
特别地，第一电压产生模块111还包括第一选择输出模块，第一选择输出模块的输入端与所有的电压输出节点连接，第一选择输出模块基于第一控制信号组控制第一开关管的导通或截止；在第二模式下，第一选择输出模块还基于第一控制信号组选择一电压输出节点输出预设的第三弱电压信号weakout3。
需要说明的是，第二模式中的第一电源端为恒压电源。此时，根据所需要的电压值大小，通过第一选择输出模块可以从不同的电压输出节点div4、div12……div188中确定一个电压输出节点，从而输出所需要的第三电压信号。同时，如果需要div14处的电压，那么可以通过控制第一开关管的工作状态来短接靠近第一电源端处的2个第一边缘电阻，并控制远离接地端处的2个第一边缘电阻进行额外接入(即保证第一主电阻链21的整体电阻数量不变)，从而电压输出节点div12等效成为电压输出节点div14，实现特定电压值的输出。
在一种具体的实施例中，第一边缘电阻的阻值为R/2，除了第一边缘电阻的其他第一电阻的阻值为R，在第一主电阻链21的工作过程中，每次均存在偶数个(例如0、2、4……16)第一边缘电阻被短接。以第一电源端为恒压电源且电压为500mV为例，此时第一主电阻链21中固定接入200个阻值为R的等效电阻，此时每个等效电阻的分压为2.5mV。相应的，由于第三弱电压信号weakout3是从div4～div188中的任意一个进行引出的，所以其电压值可以实现10～490mV可编程的变化。
应理解，第一选择输出模块是指第二模式中实现控制功能的概念模块，其对应的硬件电路至少包括如图6C所示的多个第一数据选择器23和多个第二数据选择器24，第一数据选择器23的控制端和第二数据选择器24的控制端接收相同的信号，即第二信号R0GrpEn<15:0>、第三信号R1GrpEn<7:0>。在这里，R0GrpEn<15:0>、R1GrpEn<7:0>仅有一个为高电平(某些场景下也可以为低电平)，从而第一数据选择器23选择相应的电压输出节点输出第三弱电压信号。在这里，第二信号R0GrpEn<15:0>、第三信号R1GrpEn<7:0>均来自于第一控制信号组。
还需要说明的是，在第二模式下，由于多个第一数据选择器23和多个第二数据选择器24的控制信号是相同的，第二数据选择器24其实也存在信号输出，只是第二数据选择器24的输出信号在第二模式中不作使用，也可以不使能第二数据选择器24以节省能耗。
在一些实施例中，如前面提及的，在第一主电阻链21中，每一电压输出节点对应的两个第一电阻之间串接有一个第二开关管。另外，请参考图6B，第一辅电阻链22包括串联的N×B个第二电阻，第一辅电阻链22还包括B个第三开关管，B个第三开关管的一端连接于第一辅电阻链22的同一端，第b个第三开关管用于短接N×b个第二电阻，N、B以及b均为正整数，且b小于或等于B，N≠C。
以N＝4、B＝7为例，如图6B所示，第二辅电阻链一共包括28个第二电阻和7个第三开关管(其控制端接收第六信号dfeN<7：1>)。第1个第三开关管可以短接第1个～第4个第二电阻，第2个第三开关管可以短接第1个～第8个电阻……第7个第三开关管可以短接第1～第28个第二电阻。第六信号dfeN<7：1>来自于第一控制信号组。
特别地，第一电压产生模块111还包括第二选择输出模块，第二选择输出模块用于基于第一控制信号组控制第二开关管以及第三开关管的导通或截止。在第一模式下，第二选择输出模块具体用于控制任意一个第二开关管截止，以使得第一辅电阻链22代替一个第一电阻串联接入第一主电阻链21，并形成第一连接点和第二连接点；以及，通过第一连接点输出预设的第一弱电压信号，通过第二连接点输出预设的第二弱电压信号。
也就是说，第一辅电阻链22的第一端与所有的电压输出节点(例如div4、div12……)存在物理连接线，且第一辅电阻链22的第二端与所有的电压输出节点的下一节点(例如div5、div13……)存在物理连接线。请注意，在第二开关管接通的时候，相当于对应的第一电阻将第一辅电阻链22“短接”，此时第一辅电阻链22并没有接入第一主电阻链21。然而，如果第一主电阻链21中的一个第二开关管(例如R0pwlpEn<12>对应的第二开关管)断开，此时第一辅电阻链22相当于代替相应的第二电阻串接于节点div101和节点div100之间，节点div101和第一辅电阻链22的第一端接通以形成第二连接点，节点div100和第一辅电阻链22的第二端接通以形成第一连接点。换句话说，第一模式中的第一连接点可以是第二模式中的任意一个电压输出节点。
需要说明的是，第一模式中的第一电源端为恒流电源。此时，根据所需要的电压值大小，选择第一主电阻链21中的一个第二开关管(例如R0pwlpEn<12>对应的第二开关管)断开，此时第一辅电阻链22和第一主电阻链21串联形成通路，且节点100作为第一连接点输出第一弱电压信号weakout1，节点div101作为第二连接点输出第二弱电压信号weakout2。同时，以第二弱电压信号weakout2为基准，由于第一主电阻链21的电流大小不变(原因为采用恒流电源)，每一第二电阻的分压固定(例如2.5mV)，通过控制第一辅电阻链22的电阻分布状态，第一弱电压信号和第二弱电压信号的压差可以实现10～70mv可编程变化。
应理解，第二选择输出模块是指第一模式中实现控制功能的概念模块，其对应的硬件电路同样至少包括如图6C所示的多个第一数据选择器23和多个第二数据选择器24，此时第一数据选择器23所选择的节点就是第一连接点的所在位置，第二数据选择器24所选择的节点就是第二连接点的所在位置，从而输出第一弱电压信号weakout1和第二弱电压信号weakout2。
还需要说明的是，如图6A所示，第一主电阻链21中还串接有第四开关管，其接收使能信号En，用于控制第一分压调整模块111a的工作与否。
在一些实施例中，如图6D所示，第一分压调整模块111a还包括第一恒流电源和第一恒压电源；第一分压调整模块111a，配置为在第一模式下，将第一恒流电源确定为第一电源端；或者，在第二模式下，将第一恒压电源vddq确定为第一电源端。
还需要说明的是，如图6D所示，第一分压调整模块111a还包括开关管231和开关管232，用于根据模式选择信号dfeEn及其反相信号dfeEnN进行电源类型的切换。
示例性的，请参考图6D，第一恒流电源可以包括2个开关管，第1个开关管的控制端接收第七信号Pbias，第2个晶体管的控制端接收第八信号Pcasc，且第2个晶体管主要起到隔离噪声的作用，避免串联电路对第1个开关晶体管的输 出电压造成影响，使得第1个开关晶体管的输出电压造成波动。
另外，如图6E所示，第一分压调整模块111a还包括多个或门25和多个或门26，分别用于对模式选择信号dfeEn和第二信号R0GrpEbN<15:0>进行或运算后得到第四信号R0pwlpEn<15:0>，以及对模式选择信号dfeEn和第三信号R1GrpEbN<7:0>进行或运算后得到第五信号R1pwlpEn<7:0>。
以下对第一模式和第二模式的切换原理进行说明。
在第二模式下，dfeEn＝1，dfeEnN＝0。如图6D所示，开关管231截止，开关管232导通，第一恒压电源vddq作为第一电源端，所有的或门25和所有的或门26的结果均为1，即第二信号R0pwlpEn<15：0>、第三信号R1pwlpEn<7：0>均为1；如图6A所示，此时第一主电阻链21中的第二开关管均导通，利用第一信号EnV<15:0>及其反相信号EnVN<15:0>控制第一主电阻链21的电阻分布状态，且利用第四信号R0GrpEbN<15:0>、第五信号R1GrpEbN<7:0>选择一个电压输出节点输出第三弱电压信号weakout3。
在第一模式下，dfeEn＝0，dfeEnN＝1。如图6D所示，开关管231导通，开关管232截止，第一恒流电源作为第一电源端，第二信号R0pwlpEn<15：0>对应等于第四信号R0GrpEbN<15:0>，第三信号R1pwlpEn<7：0>对应等于第五信号R1GrpEbN<7:0>，即第二信号R0pwlpEn<15：0>和第三R1pwlpEn<7：0>中同样仅有1个信号为0，以控制图6A中相应的一个第二开关管断开，且选择该第二开关管两侧的节点(即第一连接点和第二连接点)分别输出第一弱电压信号weakout1和第二弱电压信号weakout2。
在一些实施例中，如图5所示，第二电压产生模块112包括第二分压调整模块112a、第一运算放大器112b和第二运算放大器112c，且第二分压调整模块112a包括第二主电阻链和第二辅电阻链。
在第一模式下，第二主电阻链和第二辅电阻链通过第三连接点和第四连接点连接，第三连接点串接于第四连接点和第二主电阻链的接地端之间；其中，第二分压调整模块112a，配置为基于第二控制信号组，调整第二主电阻链的阻值分布状态以通过第三连接点输出第一电压信号，调整第二辅电阻链的阻值分布状态以通过第四连接点输出第二电压信号；第一运算放大器112b，配置为接收第一电压信号，对第一电压信号进行放大，输出第一强电压信号strgout1；第二运算放大器112c，配置为接收第二电压信号，对第二电压信号进行放大，输出第二强电压信号strgout2。
在第二模式下，第二主电阻链和第二辅电阻链处于隔离状态；其中，第二分压调整模块，还配置为基于第二控制信号组，调整第二主电阻链的阻值分布状态，以通过第二主电阻链的电压输出节点输出第三电压信号；第一运算放大器112b，配置为接收第三电压信号，对第三电压信号进行放大，输出第三强电压信号strgout3。
需要说明的是，第二分压调整模块112a的结构可以参照第一分压调整模块111a进行理解并予以实施。另外，相比于第一电压产生模块111，第二电压产生模块112额外设置了运算放大器，从而输出驱动强度较高的参考电压信号。
在另一种实施例中，第一分压调整模块(及第二分压调整模块)也可以采用两级主电阻链的结构，从而在第一模式中分别产生2个不同的电压信号。然而， 相比较于两级主电阻链的结构，主辅电阻链的结构(即图6A～图6E的电路结构)所产生的电流值更大，建立时间更短。参见图7，其示出了本公开实施例提供的仿真测试结果示意图。如图7所示，曲线(a)是指主辅电阻链的结构对应的电压变化情况，曲线(b)是指两级主电阻链的电路结构对应的电压变化情况。如曲线(a)和曲线(b)所示在主辅电阻链稳定输出254mV、两级主电阻链稳定输出258mV的前提下，相比于两级主电阻链，主辅电阻链的建立时间缩短85.5纳秒。
本公开实施例提供了一种数据接收电路，其中的电压产生电路具有两种工作模式，在第一模式下，电压产生电路能够产生2个电压值不同的参考电压信号，在对数据信号进行判决时可以选择合适的参考电压信号，从而补偿前一数据信号对当前数据信号的电压影响，不仅提高数据信号的接收正确性而且速度较快；在第二模式下，电压产生电路能够产生1个参考电压信号，同时根据前一数据信号的电平状态可以对参考电压信号进行调整，补偿前一数据信号对当前数据信号的电压影响。
在本公开的另一实施例中，参见图8，其示出了本公开实施例提供的一种存储器30的结构示意图。如图8所示，存储器30包括前述的数据接收电路10。
需要说明的是，对于数据接收电路10，其中的电压产生电路采用图6A～图6E的结构产生两路/一路参考电压信号。具体来说，在第二模式下，第一主电阻链采用恒压电源vddq，第一辅电阻链不接入，仅保留一路输出，以便后续产生第三参考电压信号；在第一模式下，第一主电阻链采用恒流电源，即电阻数量的变化不会影响第一主电阻链的电流，此时第一辅电阻链接入第一主电阻链，存在两路输出且两路输出的压差为第一辅电阻链的分压，以便后续产生第一参考电压信号和第二参考电压信号。这样，第二参考电压信号(或第三参考电压信号)不仅可以实现一定范围的可编程变化，而且第一参考电压信号和第二参考电压信号的压差也可以实现一定范围的可编程变化；同时，图6A～图6E的结构相比于偏置电流补偿方法使用的电压范围更广，而且比两级主电阻链的结构产生的电流值大，建立时间也更短。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保 护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种数据接收电路和存储器，通过电压产生电路能够产生电压值不同的2个参考电压信号，仅需要选择合适的判决结果，无需根据前一数据信号的电平状态对参考电压信号进行实时反馈调整，不仅能够保证数据接收的正确性，而且缩短了信号反馈时间。

Claims (15)

  1. 一种数据接收电路，所述数据接收电路包括：
    电压产生电路，配置为在第一模式下，输出第一参考电压信号和第二参考电压信号，且所述第一参考电压信号和所述第二参考电压信号的电压值不同；
    数据电路，配置为接收数据信号、所述第一参考电压信号和所述第二参考电压信号，对所述数据信号和所述第一参考电压信号进行比较，输出第一目标信号；对所述数据信号和所述第二参考电压信号进行比较，输出第二目标信号；其中，所述数据信号是串行排列的若干个数据信号的其中一个；
    选择电路，配置为接收所述第一目标信号和所述第二目标信号，基于所述数据信号的前一数据信号的电平状态，将所述第一目标信号和所述第二目标信号的二者之一确定为目标数据信号。
  2. 根据权利要求1所述的数据接收电路，其中，
    所述电压产生电路，还配置为在第二模式下，输出第三参考电压信号；其中，所述第三参考电压信号的电压值位于所述第一参考电压信号的电压值和所述第二参考电压信号的电压值之间；
    所述数据电路，还配置为接收所述第三参考电压信号，对所述数据信号和所述第三参考电压信号进行比较，输出目标数据信号。
  3. 根据权利要求2所述的数据接收电路，其中，所述电压产生电路包括：
    第一电压产生模块，配置为接收第一控制信号组；在所述第一模式下，基于所述第一控制信号组，输出第一弱电压信号和第二弱电压信号；
    第二电压产生模块，配置为接收第二控制信号组；在所述第一模式下，基于所述第二控制信号组，输出第一强电压信号和第二强电压信号；
    第一选择器，配置为接收强弱选择信号、所述第一弱电压信号和所述第一强电压信号；在所述强弱选择信号处于第一状态时，将所述第一强电压信号输出为所述第一参考电压信号；或者，在所述强弱选择信号处于第二状态时，将所述第一弱电压信号输出为所述第一参考电压信号；
    第二选择器，配置为接收所述强弱选择信号、所述第二弱电压信号和所述第二强电压信号，在所述强弱选择信号处于所述第一状态时，将所述第二强电压信号输出为所述第二参考电压信号；或者，在所述强弱选择信号处于所述第二状态时，将所述第二弱电压信号输出为所述第二参考电压信号；
    其中，所述第一强电压信号的驱动强度大于所述第一弱电压信号的驱动强度，且所述第二强电压信号的驱动强度大于所述第二弱电压信号的驱动强度。
  4. 根据权利要求3所述的数据接收电路，其中，所述电压产生电路还包括：
    第一编码发生器，配置为产生所述第一控制信号组；
    第二编码发生器，配置为产生所述第二控制信号组；
    其中，在第一模式下，所述第一弱电压信号和所述第二弱电压信号之间的电压差为第一值，所述第一值是由所述第一控制信号组确定的；所述第一强电压信号和所述第二强电压信号之间的电压差为第二值，所述第二值是由所述第二控制信号组确定的；所述第一值与所述第二值相同。
  5. 根据权利要求4所述的数据接收电路，其中，所述电压产生电路还包括：
    校准模块，配置为在第一模式下，接收所述第一强电压信号和所述第一弱电压信号，对所述第一强电压信号和所述第一弱电压信号进行电压值比较，输出第一比较信号；
    所述第一编码发生器，还配置为在第一模式下，接收所述第一比较信号，基于所述第一比较信号对所述第一控制信号组进行调整，以步进调整所述第一弱电压信号的电压值，使得所述第一强电压信号和所述第一弱电压信号的电压值相同，且所述第二强电压信号和所述第二弱电压信号的电压值相同。
  6. 根据权利要求5所述的数据接收电路，其中，
    所述第一电压产生模块，还配置为在所述第二模式下，基于所述第一控制信号组，输出第三弱电压信号；
    所述第二电压产生模块，还配置为在所述第二模式下，基于所述第二控制信号组，输出第三强电压信号；
    所述第一选择器，还配置为接收所述强弱选择信号、所述第三弱电压信号和所述第三强电压信号，在所述强弱选择信号处于所述第一状态时，将所述第三强电压信号输出为所述第三参考电压信号；或者，在所述强弱选择信号处于所述第二状态时，将所述第三弱电压信号输出为所述第三参考电压信号；
    其中，所述第三强电压信号的驱动强度大于所述第三弱电压信号的驱动强度。
  7. 根据权利要求6所述的数据接收电路，其中，
    所述校准模块，还配置为接收所述第三强电压信号和所述第三弱电压信号，对所述第三强电压信号和所述第三弱电压信号进行电压值比较，输出第二比较信号；
    所述第一编码发生器，还配置为接收所述第二比较信号，基于所述第二比较信号对所述第一控制信号组进行调整，以步进调整所述第三弱电压信号的电压值，使得所述第三强电压信号和所述第三弱电压信号的电压值相同。
  8. 根据权利要求7所述的数据接收电路，其中，所述第一电压产生模块包括第一分压调整模块，且所述第一分压调整模块包括第一主电阻链和第一辅电阻链；
    在第一模式下，所述第一主电阻链和所述第一辅电阻链通过第一连接点和第二连接点连接，所述第一连接点串接于所述第二连接点和所述第一主电阻链的接地端之间；其中，
    所述第一分压调整模块，配置为基于所述第一控制信号组，调整所述第一主电阻链的阻值分布状态以通过所述第一连接点输出第一弱电压信号，调整所述第一辅电阻链的阻值分布状态以通过所述第二连接点输出第二弱电压信号。
  9. 根据权利要求8所述的数据接收电路，其中，在第二模式下，所述第一主电阻链和所述第一辅电阻链处于隔离状态；其中，
    所述第一分压调整模块，还配置为基于所述第一控制信号组，调整所述第一主电阻链的阻值分布状态，以通过所述第一主电阻链的电压输出节点输出第三弱电压信号。
  10. 根据权利要求9所述的数据接收电路，其中，
    所述第一主电阻链包括串联设置的多个第一电阻，首个所述第一电阻的一端与第一电源端连接，末个所述第一电阻的另一端与接地端连接；所述第一主电阻 链还包括A个靠近所述第一电源端的第一开关管以及A个靠近所述接地端的所述第一开关管，靠近所述第一电源端的A个所述第一开关管的第一端均与所述第一电源端连接，靠近所述接地端的A个所述第一开关管的第一端均与所述接地端连接；
    记靠近所述第一电源端的A个第一电阻以及靠近接地端的A个所述第一电阻为第一边缘电阻；在靠近所述第一电源端的方向上，第a个所述第一开关管用于短接a个所述第一边缘电阻；在远离所述第一电源端的方向上，第a个所述第一开关管用于短接a个所述第一边缘电阻；a、A均为正整数，且a小于或等于A，A小于第一电阻总数量的一半；
    在不包含所述第一边缘电阻的部分所述第一主电阻链中，每隔C个所述第一电阻引出一个电压输出节点，所述第一电压产生模块还包括第一选择输出模块，所述第一选择输出模块的输入端与所有的所述电压输出节点连接，所述第一选择输出模块基于所述第一控制信号组控制所述第一开关管的导通或截止；
    在第二模式下，所述第一选择输出模块还基于所述第一控制信号组选择一所述电压输出节点输出预设的所述第三弱电压信号。
  11. 根据权利要求10所述的数据接收电路，其中，
    在所述第一主电阻链中，每一所述电压输出节点对应的两个所述第一电阻之间串接有一个第二开关管；所述第一辅电阻链包括串联的N×B个第二电阻，所述第一辅电阻链还包括B个第三开关管，B个所述第三开关管的一端连接于所述第一辅电阻链的同一端，第b个所述第三开关管用于短接N×b个第二电阻，N、B以及b均为正整数，且b小于或等于B，N≠C；
    所述第一电压产生模块还包括第二选择输出模块，所述第二选择输出模块用于基于所述第一控制信号组控制所述第二开关管以及所述第三开关管的导通或截止；
    在第一模式下，所述第二选择输出模块具体用于控制任意一个所述第二开关管截止，以使得所述第一辅电阻链代替一个所述第二电阻串联接入所述第一主电阻链，并形成所述第一连接点和所述第二连接点；以及，通过所述第一连接点输出预设的所述第一弱电压信号，通过所述第二连接点输出预设的所述第二弱电压信号。
  12. 根据权利要求10所述的数据接收电路，其中，所述第一分压调整模块还包括第一恒流电源和第一恒压电源；
    所述第一分压调整模块，配置为在所述第一模式下，将所述第一恒流电源确定为所述第一电源端；或者，在所述第二模式下，将所述第一恒压电源确定为所述第一电源端。
  13. 根据权利要求7所述的数据接收电路，其中，所述第二电压产生模块包括第二分压调整模块、第一运算放大器和第二运算放大器，且所述第二分压调整模块包括第二主电阻链和第二辅电阻链；
    在第一模式下，所述第二主电阻链和所述第二辅电阻链通过第三连接点和第四连接点连接，所述第三连接点串接于所述第四连接点和所述第二主电阻链的接地端之间；其中，
    所述第二分压调整模块，配置为基于所述第二控制信号组，调整所述第二主 电阻链的阻值分布状态以通过所述第三连接点输出所述第一电压信号，调整所述第二辅电阻链的阻值分布状态以通过所述第四连接点输出第二电压信号；
    所述第一运算放大器，配置为接收所述第一电压信号，对所述第一电压信号进行放大，输出所述第一强电压信号；
    所述第二运算放大器，配置为接收所述第二电压信号，对所述第二电压信号进行放大，输出所述第二强电压信号。
  14. 根据权利要求13所述的数据接收电路，其中，在第二模式下，所述第二主电阻链和所述第二辅电阻链处于隔离状态；其中，
    所述第二分压调整模块，还配置为基于所述第二控制信号组，调整所述第二主电阻链的阻值分布状态，以通过所述第二主电阻链的电压输出节点输出第三电压信号；
    所述第一运算放大器，配置为接收所述第三电压信号，对所述第三电压信号进行放大，输出所述第三强电压信号。
  15. 一种存储器，所述存储器包括如权利要求1-14任一项所述的数据接收电路。
PCT/CN2022/123902 2022-08-19 2022-10-08 一种数据接收电路和存储器 Ceased WO2024036719A1 (zh)

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CN105304137A (zh) * 2014-07-18 2016-02-03 北京兆易创新科技股份有限公司 存储器的读取电路、存储装置及存储器的读取方法
CN112951286A (zh) * 2019-12-10 2021-06-11 三星电子株式会社 数据接收装置、存储器装置及其操作方法
US20220020419A1 (en) * 2020-07-20 2022-01-20 Mediatek Inc. Transmitter with voltage level adjustment mechanism in memory controller
CN114078557A (zh) * 2020-08-11 2022-02-22 三星电子株式会社 存储器系统及其操作方法以及使用存储器系统的存储装置
CN114121062A (zh) * 2020-08-31 2022-03-01 三星电子株式会社 多电平信号接收器、存储器系统和电子设备

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CN105304137A (zh) * 2014-07-18 2016-02-03 北京兆易创新科技股份有限公司 存储器的读取电路、存储装置及存储器的读取方法
CN112951286A (zh) * 2019-12-10 2021-06-11 三星电子株式会社 数据接收装置、存储器装置及其操作方法
US20220020419A1 (en) * 2020-07-20 2022-01-20 Mediatek Inc. Transmitter with voltage level adjustment mechanism in memory controller
CN114078557A (zh) * 2020-08-11 2022-02-22 三星电子株式会社 存储器系统及其操作方法以及使用存储器系统的存储装置
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