WO2024035151A1

WO2024035151A1 - Circuit board and semiconductor package comprising same

Info

Publication number: WO2024035151A1
Application number: PCT/KR2023/011824
Authority: WO
Inventors: 신종배; 심우섭; 정재훈; 정지철
Original assignee: 엘지이노텍 주식회사
Priority date: 2022-08-10
Filing date: 2023-08-10
Publication date: 2024-02-15
Also published as: KR20240022056A

Abstract

A circuit board according to an embodiment comprises a first insulating layer, a second insulating layer arranged on the first insulating layer, and a circuit pattern layer arranged between the first and second insulating layers, wherein the second insulating layer includes a cavity penetrating an upper surface and a lower surface, and the circuit pattern layer includes an electrode pattern extending from the inside of the cavity to the outside of the cavity.

Description

Circuit board and semiconductor package containing the same

The embodiment relates to a circuit board and a semiconductor package including the same.

As the performance of electrical/electronic products progresses, technologies for attaching a greater number of packages to a limited-sized substrate are being proposed and researched.

A typical semiconductor package has a structure in which multiple chips are arranged. In addition, the size of semiconductor packages is increasing due to recent higher specifications of products to which the semiconductor packages are applied and the adoption of a large number of chips such as HBM (High Bandwidth Memory). Through this, the semiconductor package includes an interposer to connect multiple chips.

In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), self-driving cars, and high-performance servers require high performance and reliability in accordance with the trend toward high integration.

Furthermore, a semiconductor package has a vertical connection structure between multiple substrates, interposers, and semiconductor devices. Accordingly, the thickness of the semiconductor package in the vertical direction may increase depending on the thickness and number of the substrate, interposer, and semiconductor elements.

Accordingly, the thickness of the semiconductor package in the vertical direction is reduced by using a substrate with a cavity. The cavity can be formed by processing the substrate with a laser. For this purpose, a dummy pattern is provided on the substrate. Then, a laser process is performed using the dummy pattern as a stopper to form the cavity.

Accordingly, according to the prior art, a process of forming the dummy pattern and a process of removing the dummy pattern must be performed, thereby complicating the manufacturing process.

Additionally, the prior art substrate includes a pad exposed through the cavity. At this time, only the pad exists in the area exposed through the cavity. This is because, when an electrode pattern such as a trace exists in the area exposed through the cavity, a circuit short problem occurs in which the traces are electrically connected to each other due to the dummy pattern. Accordingly, the substrate of the prior art has a problem of lowering the circuit integration.

(Patent Document 1) KR 10-2012-0045639 A

Embodiments provide a circuit board with a new structure and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board that can be slimmed and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board that can minimize the length of a signal line connected to a connection member and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board that includes a thermosetting resin and can place an electrode pattern in the cavity area, and a semiconductor package including the same.

Additionally, embodiments provide a circuit board with improved circuit integration and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board with improved adhesion to a molding member and a semiconductor package including the same.

The technical challenges to be achieved in the proposed embodiment are not limited to the technical challenges mentioned above, and other technical challenges not mentioned are clear to those skilled in the art from the description below. It will be understandable.

A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; and a circuit pattern layer disposed between the first and second insulating layers, wherein the second insulating layer has a cavity penetrating an upper and lower surface, and the circuit pattern layer is formed on the inside of the cavity. It includes an electrode pattern extending outwardly.

Additionally, the circuit pattern layer includes: a first pad provided inside the cavity and overlapping in a vertical direction with the cavity; and a second pad provided outside the cavity that does not vertically overlap the cavity.

Additionally, the second insulating layer has a concave portion that is concave in a direction from the bottom of the side wall of the cavity toward the outer surface of the second insulating layer.

In addition, the concave portion includes a first part that does not overlap the electrode pattern in the vertical direction, and a second part that overlaps the electrode pattern in the vertical direction.

Additionally, the circuit pattern layer is provided to protrude onto the first insulating layer, and the first portion of the concave portion is provided along a lower edge of the side wall of the cavity.

Additionally, the first and second portions of the concave portion have a step.

Additionally, each of the first pad, the second pad, and the electrode pattern includes: a first metal layer disposed on the first insulating layer; and a second metal layer disposed on the first metal layer, wherein a vertical length of the first concave portion corresponds to a thickness of the first metal layer.

Additionally, the horizontal distance from the lower end of the side wall of the cavity to the innermost end of the first portion of the concave portion satisfies the range of 5 μm to 17 μm.

Additionally, the horizontal length of the first portion of the concave portion is different from the horizontal length of the second portion of the concave portion.

Additionally, the thickness of the first pad is different from the thickness of the second pad.

Additionally, the vertical length of the first portion of the concave portion satisfies the range of 1.0 μm to 4.0 μm.

Additionally, the horizontal length of the first portion of the concave portion is smaller than the horizontal length of the second portion of the concave portion.

Additionally, the thickness of the first pad is smaller than the thickness of the second pad.

Additionally, the electrode pattern includes a region that overlaps the sidewall of the cavity in the vertical direction and whose thickness changes along the horizontal direction.

Additionally, the first pad, the second pad, and the electrode pattern are buried in the upper surface of the first insulating layer, and the upper surface of the first region of the first insulating layer is the second pad of the first insulating layer. It is located lower than the top surface of the area.

Additionally, the concave portion is provided concavely from the upper surface of the first region of the first insulating layer toward the inside of the first insulating layer.

Additionally, at least one of the first pad, the second pad, and the electrode pattern has a layer structure different from at least the other one.

Additionally, the first circuit pattern layer includes a first metal layer and a second metal layer, the first pad of the first circuit pattern layer includes a second metal layer excluding the first metal layer, and the first circuit pattern layer includes a second metal layer excluding the first metal layer. The second pad of the layer includes both the first metal layer and the second metal layer, and the electrode pattern includes a first portion including only the second metal layer and a second portion including both the first and second metal layers. Includes part.

Additionally, the second insulating layer having the cavity includes a thermosetting resin.

The circuit board of the embodiment includes a first insulating layer, a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer. At this time, the second insulating layer includes a cavity penetrating the upper and lower surfaces. And, the first circuit pattern layer includes: a first pad disposed in a first area vertically overlapping with the cavity; a second pad disposed in a second area that does not vertically overlap the cavity; and an electrode pattern disposed in the first area and the second area and connecting the first pad and the second pad.

That is, in the embodiment, an electrode pattern that directly connects the first pad and the second pad is disposed on the first insulating layer. Through this, the embodiment can reduce the signal transmission distance between the first pad and the second pad. Furthermore, the embodiment can minimize signal transmission loss due to a decrease in the signal transmission distance. Accordingly, the embodiment can improve the electrical characteristics of the circuit board and the semiconductor package including the same.

Additionally, the embodiment may improve circuit integration by arranging the electrode pattern in an area corresponding to the cavity.

Meanwhile, the second insulating layer including the cavity includes a thermosetting resin. And, in the embodiment, the electrode pattern can be arranged while the second insulating layer includes a thermosetting resin. In an embodiment, the adhesion between a plurality of insulating layers can be improved by configuring the insulating layer using a thermosetting resin. Accordingly, the embodiment can improve the physical characteristics of the circuit board and the semiconductor package including the same.

Meanwhile, a concave portion may be provided at the bottom of the side wall of the cavity along the circumferential direction of the bottom surface of the cavity. The concave portion may have a closed loop shape along the circumferential direction of the bottom surface of the cavity. At this time, the concave portion may include a portion having a step in one embodiment, and may not have a step in another embodiment.

Accordingly, the embodiment disposes a connecting member and a molding member for molding the connecting member in the cavity. Additionally, the molding member may fill the concave portion provided in the cavity. At this time, the embodiment may allow the portion disposed within the concave portion of the entire area of the molding member to function as an anchor. Accordingly, the embodiment can improve adhesion between the circuit board and the molding member. Accordingly, the embodiment can protect the connecting member more reliably. And, the embodiment can further improve product reliability of semiconductor packages.

1A is a cross-sectional view showing a semiconductor package according to a first embodiment.

FIG. 1B is a cross-sectional view showing a semiconductor package according to a second embodiment.

Figure 1C is a cross-sectional view showing a semiconductor package according to a third embodiment.

Figure 1D is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment.

Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

Figure 2 is a cross-sectional view showing the circuit board of the first embodiment.

FIG. 3 is a plan view showing a first insulating layer and a first circuit pattern layer in the circuit board of FIG. 2.

FIG. 4 is a plan view of the circuit board of FIG. 3 with some components removed.

Figure 5 is a cross-sectional view taken along the A-A' direction of Figures 3 and 4.

Figure 6 is an optical micrograph of the actual product corresponding to Figure 5.

Figure 7 is a cross-sectional view taken along the B-B' direction of Figures 3 and 4.

Figure 8 is a cross-sectional view showing a circuit board according to a second embodiment.

Figure 9 is an enlarged view of a portion of the cavity of Figure 8.

FIG. 10 is an enlarged view of another portion of the cavity of FIG. 8.

Figure 11 is a diagram showing a package substrate according to an embodiment.

12 to 22 are diagrams showing the manufacturing method of the circuit board of FIG. 2 according to an embodiment in process order.

Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. However, identical or similar components will be assigned the same reference numbers regardless of reference numerals, and duplicate descriptions thereof will be omitted. The suffixes “module” and “part” for components used in the following description are given or used interchangeably only for the ease of preparing the specification, and do not have distinct meanings or roles in themselves. Additionally, in describing the embodiments disclosed in this specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed descriptions will be omitted. In addition, the attached drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and all changes included in the spirit and technical scope of the present invention are not limited. , should be understood to include equivalents or substitutes.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

-전자 디바이스--Electronic Device-

Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various semiconductor devices may be mounted on the semiconductor package.

The semiconductor device may include active devices and/or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one chip. Semiconductor devices may be logic chips, memory chips, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.

The memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

Meanwhile, the product lines to which the semiconductor package of the embodiment is applied include Chip Scale Package (CSP), Flip Chip-Chip Scale Package (FC-CSP), Flip Chip Ball Grid Array (FC-BGA), Package On Package (POP), and SIP ( System In Package), but is not limited to this.

In addition, the electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, and network systems. ), computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive It may be, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board, which will be described later.

And in one embodiment, the circuit board may be a first board described below.

Additionally, in another embodiment, the circuit board may be a second board described below.

FIG. 1A is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 1B is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 1C is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 1D is a cross-sectional view showing a semiconductor package according to a fourth embodiment, FIG. 1E is a cross-sectional view showing a semiconductor package according to a fifth embodiment, FIG. 1F is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and FIG. 1G is a cross-sectional view showing a semiconductor package according to a sixth embodiment. This is a cross-sectional view showing a semiconductor package according to Example 7.

Referring to FIG. 1A , the semiconductor package of the first embodiment may include a first substrate 1100, a second substrate 1200, and a semiconductor device 1300.

The first substrate 1100 refers to a package substrate.

For example, the first substrate 1100 may provide a space where at least one external substrate is coupled. The external substrate may refer to a second substrate 1200 coupled to the first substrate 1100. Additionally, the external substrate may refer to a main board included in an electronic device coupled to the lower portion of the first substrate 1100.

Additionally, although not shown in the drawing, the first substrate 1100 may provide a space where at least one semiconductor device is mounted. To this end, the first substrate 1100 may include a cavity. Also, at least one semiconductor device may be disposed in the cavity of the first substrate 1100.

The first substrate 1100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a penetration portion penetrating the at least one insulating layer.

A second substrate 1200 is disposed on the first substrate 1100.

The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide a space where at least one semiconductor device is mounted. The second substrate 1200 may be connected to the at least one semiconductor device 1300. For example, the second substrate 1200 may provide a space where the first semiconductor device 1310 and the second semiconductor device 1320 are mounted. The second substrate 1200 electrically connects the first semiconductor device 1310 and the second semiconductor device 1320, and connects the first and

second semiconductor devices

1310 and 1320 to the first substrate ( 1100) can be electrically connected. That is, the second substrate 1200 can function as a horizontal connection between a plurality of semiconductor devices and a vertical connection between the semiconductor devices and the package substrate.

In FIG. 1A, two

semiconductor devices

1310 and 1320 are shown disposed on the second substrate 1200, but the present invention is not limited thereto. For example, one semiconductor device may be disposed on the second substrate 1200, or alternatively, three or more semiconductor devices may be disposed on the second substrate 1200.

The second substrate 1200 may be disposed between the semiconductor device 1300 and the first substrate 1100.

In one embodiment, the second substrate 1200 may be an active interposer that functions as a semiconductor device. When the second substrate 1200 functions as a semiconductor device, the package of the embodiment may have a vertical stacked structure and a plurality of logic chips may be mounted on the first substrate 1100. And among the logic chips, a first logic chip corresponding to the active interposer functions as the corresponding logic chip and performs a signal transmission function between the second logic chip disposed on top of the logic chip and the first substrate 1100. You can.

According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may function as a signal relay between the semiconductor device 1300 and the first substrate 1100. That is, the number of terminals of the semiconductor device 1300 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 1300 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced. At this time, the first substrate 1100 is connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate 1100 to have a width and spacing for being connected to the semiconductor device 1300 and the main board, the thickness of the first substrate 1100 must be increased, or the thickness of the first substrate 1100 must be increased. There is a problem that the layer structure of the first substrate 1100 becomes complicated. Accordingly, in the first embodiment, the second substrate 1200 is disposed on the first substrate 1100 and the semiconductor device 1300. And the second substrate 1200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device 1300.

The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an AP that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application -specific IC), etc., or it may be a chip set containing a specific combination of those listed so far. And the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

Meanwhile, the second substrate 1200 may include at least one cavity. Additionally, the semiconductor device 1300 may be disposed in the cavity of the second substrate 1200.

Meanwhile, the semiconductor package of the first embodiment may include a connection member.

For example, the semiconductor package includes a first connection member 1410 disposed between the first substrate 1100 and the second substrate 1200. The first connection member 1410 couples the second substrate 1200 to the first substrate 1100 and electrically connects them.

For example, the semiconductor package may include a second connection member 1420 disposed between the second substrate 1200 and the semiconductor device 1300. The second connection member 1420 may couple the semiconductor device 1300 to the second substrate 1200 and electrically connect them.

The semiconductor package includes a third connection member 1430 disposed on the lower surface of the first substrate 1100. The third connection member 1430 can connect the first substrate 1100 to the main board and electrically connect them.

At this time, the first connection member 1410, the second connection member 1420, and the third connection member 1430 are connected to a plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. can be electrically connected. That is, because the first connection member 1410, the second connection member 1420, and the third connection member 1430 have a function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package can be understood as a part that is electrically connected, rather than solder or wire.

The wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu. In addition, the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. . And, the direct bonding method between metals may refer to a bonding method using the second connection member 1420. In this case, the second connection member 1420 may refer to a metal layer formed between a plurality of components through recrystallization.

Specifically, the first connection member 1410, the second connection member 1420, and the third connection member 1430 may be connected to a plurality of components using a TC (Thermal Compression) bonding method. The TC bonding may refer to a method of combining a plurality of components by applying heat and pressure to the first connection member 1410, the second connection member 1420, and the third connection member 1430.

At this time, in at least one of the first substrate 1100 and the second substrate 1200, the electrodes on which the first connection member 1410, the second connection member 1420, and the third connection member 1430 are disposed A protrusion may be disposed. The protrusion may protrude outward from the first substrate 1100 or the second substrate 1200.

The protrusion may mean a bump. The protrusion may mean a post. The protrusion may mean a pillar. Preferably, the protrusion may refer to an electrode of the second substrate 1200 on which the second connection member 1420 for coupling to the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur in the second connection members 1420 respectively connected to the terminals of the semiconductor device 1300. Accordingly, in the embodiment, in order to reduce the volume of the second connection member 1420, the electrode of the second substrate 1200 on which the second connection member 1420 is disposed includes a protrusion. The protrusion may prevent the matching between the electrode of the second substrate 1200 and the terminal of the semiconductor device 1300 and diffusion of the second connection member 1420.

Meanwhile, referring to FIG. 1B, the semiconductor package of the second embodiment may be different from the semiconductor package of the first embodiment in that the connection substrate 1210 is disposed on the second substrate 1200. The connection substrate 1210 may be referred to as a bridge substrate. For example, the connection substrate 1210 may include a redistribution layer.

In one embodiment, the connection substrate 1210 may be a silicon bridge. That is, the connection substrate 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

In another embodiment, the connection substrate 1210 may be an organic bridge. For example, the connection substrate 1210 may include an organic material. For example, the connection substrate 1210 includes an organic substrate containing an organic material instead of the silicon substrate.

The connection substrate 1210 may be embedded in the second substrate 1200, but is not limited thereto. For example, the connection substrate 1210 may be disposed on the second substrate 1200 to have a protruding structure.

Preferably, the second substrate 1200 may include a cavity, and the connection substrate 1210 may be disposed within the cavity of the second substrate 1200.

The connection substrate 1210 may horizontally connect a plurality of semiconductor devices disposed on the second substrate 1200.

Referring to FIG. 1C, the semiconductor package of the third embodiment includes a second substrate 1200 and a semiconductor device 1300. At this time, the semiconductor package of the third embodiment may have a structure in which the first substrate 1100 is removed compared to the semiconductor package of the second embodiment.

That is, the second substrate 1200 of the third embodiment can function as an interposer and a package substrate.

The first connection member 1410 disposed on the lower surface of the second substrate 1200 may couple the second substrate 1200 to the main board of the electronic device.

Referring to FIG. 1D , the semiconductor package of the fourth embodiment includes a first substrate 1100 and a semiconductor device 1300.

At this time, the semiconductor package of the fourth embodiment may have a structure in which the second substrate 1200 is removed compared to the semiconductor package of the second embodiment.

That is, the first substrate 1100 of the fourth embodiment can function as a package substrate and an interposer that connects the semiconductor device 1300 and the main board. To this end, the first substrate 1100 may include a connection substrate 1110 for connecting a plurality of semiconductor devices. The connection substrate 1110 may be a silicon bridge or an organic bridge connecting a plurality of semiconductor devices.

Referring to FIG. 1E, the semiconductor package of the fifth embodiment further includes a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

To this end, a fourth connection member 1440 may be disposed on the lower surface of the first substrate 1100.

Additionally, a third semiconductor device 1330 may be disposed on the fourth connection member 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.

At this time, the third semiconductor device 1330 may have a structure disposed on the lower surface of the second substrate 1200 in the semiconductor package of FIG. 1C.

Referring to FIG. 1F, the semiconductor package of the sixth embodiment includes a first substrate 1100.

A first semiconductor device 1310 may be disposed on the first substrate 1100. To this end, a first connection member 1410 may be disposed between the first substrate 1100 and the first semiconductor device 1310.

Additionally, the first substrate 1100 may include a conductive coupling portion 1450. The conductive coupling portion 1450 may protrude further from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump or, alternatively, may be referred to as a post. The conductive coupling portion 1450 may be disposed with a protruding structure on the electrode disposed on the uppermost side of the first substrate 1100.

A second semiconductor device 1320 is disposed on the conductive coupling portion 1450 of the first substrate 1100. At this time, the second semiconductor device 1320 may be connected to the first substrate 1100 through the conductive coupling portion 1450. Additionally, a second connection member 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

Accordingly, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection member 1420.

That is, the second semiconductor device 1320 is connected to the first substrate 1100 through the conductive coupling portion 1450, and can also be connected to the first semiconductor device 1310 through the second connection member 1420. .

At this time, the second semiconductor device 1320 can receive a power signal through the conductive coupling portion 1450. Additionally, the second semiconductor device 1320 may exchange communication signals with the first semiconductor device 1310 through the second connection member 1420.

The semiconductor package of the sixth embodiment may provide sufficient power to drive the second semiconductor device 1320 by providing a power signal to the second semiconductor device 1320 through the conductive coupling portion 1450. Accordingly, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power supplied to the second semiconductor device 1320. Furthermore, the embodiment allows the power signal and communication signal of the second semiconductor device 1320 to be provided through different paths through the conductive coupling portion 1450 and the second connection member 1420. Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, embodiments may minimize mutual interference between power signals and communication signals.

Meanwhile, the second semiconductor device 1320 in the sixth embodiment may have a POP structure and be disposed on the first substrate 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. And the memory package may be coupled to the conductive coupling portion 1450. At this time, the memory package may not be connected to the first semiconductor device 1310.

Meanwhile, the semiconductor package in the sixth embodiment may include a molding member 1460. The molding member 1460 may be disposed between the first substrate 1100 and the second semiconductor device 1320. For example, the molding member 1460 may mold the first connection member 1410, the second connection member 1420, the first semiconductor device 1310, and the conductive coupling portion 1450.

Referring to FIG. 1G, the semiconductor package of the seventh embodiment includes a first substrate 1100, a first connection member 1410, a first connection member 1410, a semiconductor device 1300, and a third connection member 1430. It can be included.

At this time, the semiconductor package of the seventh embodiment may be different from the semiconductor package of the fourth embodiment in that the connection substrate 1110 is omitted and the first substrate 1100 includes a plurality of substrate layers.

The first substrate 1100 includes a plurality of substrate layers. For example, the first substrate 1100 may include a first substrate layer 1100A corresponding to a package substrate and a second substrate layer 1100B corresponding to a redistribution layer of a connection substrate.

That is, in the embodiment, the first substrate 1100 may be configured by disposing the second substrate layer 1100B corresponding to the redistribution layer on the first substrate layer 1100A.

In other words, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B formed integrally. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photocurable material. For example, the second substrate layer 1100B may be a photo imageable dielectric (PID). In addition, since the second substrate layer 1100B contains a photocurable material, the electrode can be miniaturized. Therefore, in the seventh embodiment, an insulating layer of a photo-curable material is sequentially stacked on the first substrate layer 1100A, and a micronized electrode is formed on the insulating layer of the photo-curable material, thereby forming a second substrate layer ( 1100B) can be formed. Through this, the second substrate 1100B may be a redistribution layer including miniaturized electrodes.

- 회로 기판 --Circuit board-

Below, the circuit board of the embodiment will be described.

FIG. 2 is a cross-sectional view showing the circuit board of the first embodiment, FIG. 3 is a plan view showing the first insulating layer and the first circuit pattern layer in the circuit board of FIG. 2, and FIG. 4 is a partial configuration of the circuit board of FIG. 3. It is a removed top view, Figure 5 is a cross-sectional view cut along the A-A' direction of Figures 3 and 4, Figure 6 is an optical micrograph of the actual product corresponding to Figure 5, and Figure 7 is a cross-sectional view taken along the line B-B' of Figures 3 and 4. This is a cross-sectional view cut along the direction.

Before describing the circuit board of the embodiment, the circuit board described below may refer to any one of a plurality of substrates included in the semiconductor package.

Preferably, the circuit board of an embodiment described below may be one of the first substrate 1100 and the second substrate 1200 included in the semiconductor package. Additionally, at least one of the first substrate 1100 and the second substrate 1200 may include a cavity described below.

At this time, a connecting member may be disposed in the cavity.

When the circuit board is the first board 1100, the connecting member may be any one of a connecting board, a second board, and a semiconductor device.

Additionally, when the circuit board is the second board 1200, the connecting member may be either a semiconductor device or a connecting board.

Referring to Figure 2, the circuit board of the embodiment includes a plurality of insulating layers. Each of the plurality of insulating layers may have a single-layer structure or, alternatively, may be composed of a plurality of layers.

Specifically, the circuit board may include a first insulating layer 111 and a second insulating layer 112.

At this time, the first insulating layer 111 may have a single-layer structure as shown in FIG. 2, or alternatively, it may have a plurality of layer structure.

The second insulating layer 112 is disposed on the first insulating layer 111. The second insulating layer 112 may have a single-layer structure or, alternatively, may have a multiple-layer structure. The second insulating layer 112 includes a cavity 150. Also, when the second insulating layer 112 has a plurality of layer structure, the cavity 150 may penetrate the plurality of second insulating layers.

However, for convenience of explanation, hereinafter, the first insulating layer 111 and the second insulating layer 112 will each be described as having a one-layer structure.

In one embodiment, the first insulating layer 111 and the second insulating layer 112 may include the same insulating material.

In another embodiment, the first insulating layer 111 and the second insulating layer 112 may include different insulating materials. At this time, when the first insulating layer 111 has a plurality of layer structure, the plurality of first insulating layers may all include the same insulating material or, alternatively, may include different insulating materials. Additionally, when the second insulating layer 112 has a plurality of layer structure, the plurality of second insulating layers may all include the same insulating material or, alternatively, may include different insulating materials.

At least one of the first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass. . For example, at least one of the first insulating layer 111 and the second insulating layer 112 is polyimide (PI), polyethylene terephthalate (PET), or propylene glycol (PPG). It may include reinforced or soft plastics such as polycarbonate (PC). For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include sapphire. For example, the insulating layer 110 of the substrate 100 may include an optically isotropic film. For example, at least one of the first insulating layer 111 and the second insulating layer 112 is COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), wide isotropic polycarbonate (PC), or wide isotropic polycarbonate (PC). May contain polymethyl methacrylate (PMMA). For example, at least one of the first insulating layer 111 and the second insulating layer 112 may be formed of a material containing an inorganic filler and an insulating resin. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may have a structure in which an inorganic filler of silica or alumina is disposed on a thermosetting resin or thermoplastic resin.

Specifically, in one embodiment, the first insulating layer 111 may be a core layer including reinforcing fibers, and the second insulating layer 112 may not include reinforcing fibers. Accordingly, the circuit board may be a core board.

In another embodiment, the circuit board may be a coreless board that does not include a core layer.

The first insulating layer 111 and the second insulating layer 112 of one embodiment have excellent processability, excellent rigidity, enable slimming of the circuit board, and do not include reinforcing members that enable miniaturization of the circuit pattern layer. May contain organic substances that are not The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

For example, the first insulating layer 111 and the second insulating layer 112 may be made of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or BT.

At this time, when the first insulating layer 111 and the second insulating layer 112 of the circuit board are made of Ajinomoto Build-up Film (ABF), the bending characteristics of the circuit board may be deteriorated.

Therefore, in another embodiment, the first insulating layer 111 and the second insulating layer 112 are composed of ABF (Ajinomoto Build-up Film), and at least one of the ABFs constituting the plurality of insulating layers of the circuit board ABF may contain reinforcing materials that can improve flexural properties.

For example, the circuit board may include a layer composed of a first ABF and a layer composed of a second ABF in which the ABF further includes a reinforcing material. At this time, the reinforcing material included in the second ABF may be glass fiber and may include a GCP (Glass Core Primer) material, but is not limited thereto.

Meanwhile, in the embodiment, a cavity 150 is provided in the second insulating layer 112, and an electrode pattern such as a trace is disposed in an area exposed through the cavity 150. At this time, when the second insulating layer 112 including the cavity 150 includes a photo-curable resin, there may be no significant restrictions on the arrangement of the electrode pattern.

This is because a cavity can be formed in the photo-curable resin through an exposure and development process, and thus a stopper required in the cavity formation process is not required.

However, when the second insulating layer 112 includes a photo-curable resin, the adhesion between the plurality of insulating layers of the circuit board may decrease. Specifically, when all of the plurality of insulating layers included in the circuit board are made of photo-curable resin, the rigidity of the circuit board may be reduced and the bending characteristics thereof may be greatly reduced. In addition, when the first insulating layer 111 is made of a thermosetting resin and the second insulating layer 112 is made of a photo-curing resin, the physical properties of the photo-curing resin make it different from the thermosetting resin. Adhesion may decrease. That is, the photo-curable resin has a higher curing shrinkage rate compared to the thermo-curable resin. Furthermore, the content of ceramic particles such as SiO ₂ included in the photo-curable resin is higher than the content of ceramic particles included in the thermo-curable resin. Due to this difference in physical properties, the adhesion between the thermosetting resin and the photocurable resin may be reduced.

Also, when both the first insulating layer 111 and the second insulating layer 112 include thermosetting resin, it is difficult to place an electrode pattern in the area exposed through the cavity 150. That is, in order to form the cavity 150, a stopper must be included. Additionally, when an electrode pattern is placed in an area exposed through the cavity 150, a circuit short circuit problem occurs when a plurality of electrode patterns are electrically connected by the stopper. Therefore, conventionally, when a cavity is provided in a thermosetting resin, it has been difficult to place an electrode pattern in the area exposed through the cavity.

In contrast, in the embodiment, the second insulating layer 112 includes a thermosetting resin, and a pad is formed in the area exposed through the cavity 150 of the second insulating layer 112 and an electrode pattern connected to the pad. Allow this to be placed. This is explained in more detail below.

The first insulating layer 111 and the second insulating layer 112 may each have a thickness ranging from 10 μm to 60 μm. For example, the first insulating layer 111 and the second insulating layer 112 may each have a thickness ranging from 15 ㎛ to 55 ㎛. For example, the first insulating layer 111 and the second insulating layer 112 may each have a thickness ranging from 20 μm to 50 μm. If the thickness of the first insulating layer 111 and the second insulating layer 112 is less than 10㎛, the circuit pattern layer included in the circuit board may not be stably protected. If the thickness of each of the first and second insulating

layers

111 and 112 exceeds 60 μm, the overall thickness of the circuit board may increase. In addition, when the thickness of each of the first insulating layer 111 and the second insulating layer 112 exceeds 60㎛, the thickness of the circuit pattern layer or the through electrode increases correspondingly, and the circuit pattern accordingly increases. Loss of transmitted signals may increase.

At this time, the thickness of the first insulating layer 111 and the second insulating layer 112 may correspond to the distance in the thickness direction between circuit pattern layers arranged in different layers.

For example, the thickness of the first insulating layer 111 may mean the vertical distance between the lower surface of the first circuit pattern layer 121 and the upper surface of the third circuit pattern layer 123. For example, the thickness of the second insulating layer 112 may mean a vertical straight line distance in the thickness direction between the upper surface of the first circuit pattern layer 121 and the lower surface of the second circuit pattern layer 122.

The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the upper and lower surfaces of the second insulating layer 112.

The cavity 150 may include a bottom surface 150-1 adjacent to the lower surface of the second insulating layer 112. At this time, the cavity 150 penetrates the second insulating layer 112. Accordingly, the bottom surface 150-1 of the cavity 150 may be a part of the top surface of the first insulating layer 111 that vertically overlaps the cavity 150.

The cavity 150 may include a side wall 150-2 extending at an angle from the bottom surface 150-1 toward the top surface of the second insulating layer 112. At this time, the side wall 150 - 2 may have an inclination in which the width of the cavity 150 increases from the lower surface of the second insulating layer 112 to the upper surface of the second insulating layer 112 . However, the embodiment is not limited to this. For example, the side wall 150-2 may have an inclination in which the width of the cavity 150 decreases from the lower surface of the second insulating layer 112 to the upper surface of the second insulating layer 112. . Furthermore, although the side wall 150-2 is shown in the drawing as having one slope, it is not limited thereto. For example, the side wall 150-2 may include at least one inflection portion, and may be inclined at different inclinations at the inflection portion.

The cavity 150 may include a concave portion 150-3 extending in a direction away from the cavity 150 at the lower end of the side wall 150-2 connected to the bottom surface 150-1. For example, the concave portion 150-3 extends from the bottom of the side wall 150-2 of the second insulating layer 112 constituting the cavity 150 inward toward the second insulating layer 112. may collapse. Accordingly, the concave portion 150-3 may also be referred to as an undercut, cavity expansion area, or depression.

The concave portion 150-3 is located adjacent to the edge area of the bottom surface 150-1. The concave portion 150-3 may be connected to the bottom surface 150-1. Accordingly, an area of the upper surface of the first insulating layer 111 that vertically overlaps the concave portion 150-3 may not be covered with the second insulating layer 112.

The concave portion 150-3 may be provided in an edge area of the bottom surface 150-1 along the edge direction of the bottom surface 150-1. For example, the bottom surface 150-1 is a region of the top surface of the first insulating layer 111 that vertically overlaps the cavity 150 and does not vertically overlap the first circuit pattern layer 121. It can mean. Additionally, the concave portion 150-3 may be provided entirely along the edge direction of the bottom surface 150-1.

Accordingly, the first insulating layer 111 can be divided into a plurality of regions based on the horizontal direction. For example, the first insulating layer 111 may include a first region R1 that vertically overlaps the cavity 150 . At this time, when the cavity 150 has different widths in the thickness direction of the second insulating layer 112, the first region R1 is the cavity corresponding to the lower end of the side wall 150-2 ( 150) may refer to an area that vertically overlaps with the lower area.

Additionally, the first insulating layer 111 may include a second region R2 that does not vertically overlap the cavity 150 . The second region R2 may refer to an area of the upper surface of the first insulating layer 111 covered with the second insulating layer 112.

Additionally, the first insulating layer 111 may include a third region (R3) between the first region (R1) and the second region (R2). The third area R3 may mean a boundary area between the first area R1 and the second area R2. Preferably, the third region R3 may mean a region that vertically overlaps the concave portion 150-3.

Meanwhile, a circuit pattern layer is disposed on the surfaces of the first and second insulating

layers

111 and 112.

For example, the first circuit pattern layer 121 may be disposed between the upper surface of the first insulating layer 111 and the lower surface of the second insulating layer 112. For example, the second circuit pattern layer 122 may be disposed on the upper surface of the second insulating layer 112. For example, the third circuit pattern layer 123 may be disposed on the lower surface of the first insulating layer 111.

The first circuit pattern layer 121 in the first embodiment may be disposed on the first insulating layer 111. For example, the first circuit pattern layer 121 may protrude above the top surface of the first insulating layer 111.

The second circuit pattern layer 122 may protrude above the top surface of the second insulating layer 112. The second circuit pattern layer 122 may refer to the uppermost circuit pattern layer disposed on the uppermost side of the circuit board.

The third circuit pattern layer 123 may protrude below the lower surface of the first insulating layer 111. The third circuit pattern layer 123 may refer to the lowermost circuit pattern layer disposed on the lowermost side of the circuit board.

The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each include pads and traces (or electrode patterns) depending on their functions. The pad may be a mounting pad on which devices or chips are mounted, or a terminal pad connected to an external board. The trace may be a long signal wiring line connecting a plurality of pads. The trace is a fine pattern with a width smaller than the pad. For example, in an embodiment, the spacing between a plurality of traces may range from 2 ㎛ to 15 ㎛, and the line width of each trace may range from 2 ㎛ to 15 ㎛.

The above circuit pattern layers are made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). can be formed. In addition, the circuit pattern layers are made of at least one material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding power. It may be formed of a paste containing a metal material or a solder paste. Preferably, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness ranging from 10 μm to 25 μm. For example, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness ranging from 10 μm to 23 μm. The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness ranging from 10 μm to 20 μm.

When the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10㎛, the resistance of the circuit pattern increases, and thus the signal transmission efficiency This may decrease. For example, when each of the first circuit pattern layer 121, second circuit pattern layer 122, and third circuit pattern layer 123 has a thickness of less than 10 μm, signal transmission loss may increase. For example, when the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 exceeds 25㎛, the line width of the circuit patterns increases. And, as a result, the overall volume of the circuit board may increase.

The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 are formed using an additive process or a subtractive process (additive process, which is a typical printed circuit board manufacturing process). Subtractive Process), MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process) methods, etc., and detailed descriptions are omitted here.

The first circuit pattern layer 121 may include a plurality of pads and electrode patterns.

The first circuit pattern layer 121 may include a first pad 121-1 disposed on the first region R1 of the first insulating layer 111. The first pad 121-1 may vertically overlap the cavity 150. Accordingly, the first pad 121-1 may not contact the second insulating layer 112.

The first circuit pattern layer 121 may include a second pad 121-2 disposed on the second region R2 of the first insulating layer 111. The second pad 121-2 may not vertically overlap the cavity 150. Accordingly, the second pad 121-2 may be covered with the second insulating layer 112.

The first circuit pattern layer 121 may include the electrode pattern 121-3. The electrode pattern 121-3 may be disposed in the first region (R1), second region (R2), and third region (R3) of the first insulating layer 111.

At this time, the first circuit pattern layer 121 may include multiple electrode patterns. In addition, the electrode pattern 121-3 described above may refer to an electrode pattern directly connected to the first pad 121-1 among the plurality of electrode patterns.

The electrode pattern 121-3 directly connects the first pad 121-1 disposed in the first region R1 and the second pad 121-2 disposed in the second region R2. You can. That is, in the embodiment, a cavity 150 is formed in the second insulating layer 112 containing the thermosetting resin, and the electrode is formed on the upper surface of the first insulating layer 111 exposed through the formed cavity 150. Place the pattern (121-3). Accordingly, in the embodiment, the first pad 121-1 of the first region R1 and the second pad 121-2 of the second region R2 are formed on the upper surface of the first insulating layer 111. They can be directly connected to each other through the electrode pattern 121-3. Accordingly, in the embodiment, the first insulating layer 111 and the second insulating layer 112 include a thermosetting resin, thereby improving adhesion between the plurality of insulating layers of the circuit board. Additionally, the embodiment can improve the adhesion and simultaneously improve circuit integration. That is, conventionally, when a cavity is provided in a thermosetting resin, the first pad 121-1 and the second pad 121-2 are connected to each other through at least one through electrode. Accordingly, the signal transmission distance between the first pad 121-1 and the second pad 121-2 increased, and signal transmission loss accordingly increased. In contrast, the embodiment uses the electrode pattern 121-3 to directly connect the first pad 121-1 and the second pad 121-2 without the through electrode. Accordingly, the embodiment can reduce the signal transmission distance and thereby minimize signal transmission loss. Accordingly, the embodiment can improve the electrical reliability of the circuit board.

At this time, at least a portion of the electrode pattern 121-3 is connected to the concave portion 150-3. Here, being connected to the concave portion 150-3 may mean that the concave portion 150-3 and the electrode pattern 121-3 overlap each other along the edge direction. For example, the concave portion 150 - 3 vertically overlaps the third region R3 of the first insulating layer 111 . Additionally, the electrode pattern 121-3 includes a portion disposed in the third region R3. At this time, the side surface of the portion of the electrode pattern 121-3 disposed in the third region R3 may be exposed through the concave portion 150-3. For example, at this time, the side surface of the portion disposed in the third region R3 of the electrode pattern 121-3 is not covered with the second insulating layer 112 through the concave portion 150-3. It may not be possible.

Meanwhile, in one embodiment, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 may have the same thickness.

In another embodiment, at least one of the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 may have a thickness different from at least the other one. For example, the thickness of the first pad 121-1 may be different from the thickness of the second pad 121-2. For example, the thickness of the first pad 121-1 may be smaller than the thickness of the second pad 121-2. This may be because the etching amount of the seed layer of the first pad 121-1 is greater than the etching amount of the seed layer of the second pad 121-2. That is, the first pad 121-1 and the second pad 121-2 include seed layers of the same thickness. In addition, the thickness of the first pad 121-1 and the second pad 121-2 may be reduced during the etching process of the seed layer, respectively. At this time, the etching process of the seed layer of the first pad 121-1 is performed together with the etching process of the stopper corresponding to the concave portion 150-3. At this time, the embodiment may etch the stopper with a relatively large etching amount to prevent the stopper from remaining during the stopper etching process. Accordingly, the thickness of the first pad 121-1 may be smaller than the thickness of the second pad 121-2.

The circuit board of the embodiment includes a through electrode. The through electrode may function to electrically connect circuit pattern layers arranged in different layers to each other. The through electrode may also be referred to as a ‘via’.

The through electrode penetrates the first and second insulating

layers

111 and 112 included in the circuit board, thereby making it possible to electrically connect circuit patterns disposed on different layers. At this time, the through electrode may be formed to penetrate only one insulating layer, or alternatively, may be formed to commonly penetrate at least two or more insulating layers.

For example, the circuit board includes a first through electrode 131. The first through electrode 131 may be formed to penetrate the first insulating layer 111. The first through electrode 131 may electrically connect the first circuit pattern layer 121 and the third circuit pattern layer 123. For example, the upper surface of the first through electrode 131 may be directly connected to the lower surface of the first circuit pattern layer 121. For example, the lower surface of the first through electrode 131 may be directly connected to the third circuit pattern layer 123.

Accordingly, the first circuit pattern layer 121 and the third circuit pattern layer 123 are electrically connected to each other through the first through electrode 131 and can transmit signals.

For example, the circuit board includes a second through electrode 132. The second through electrode 132 may be formed to penetrate the second insulating layer 112 . The second through electrode 132 may electrically connect the first circuit pattern layer 121 and the second circuit pattern layer 122. For example, the lower surface of the second through electrode 132 may be directly connected to the first circuit pattern layer 121. For example, the upper surface of the second through electrode 132 may be directly connected to the second circuit pattern layer 122. Accordingly, the first circuit pattern layer 121 and the second circuit pattern layer 122 are directly electrically connected to each other through the second through electrode 132 and can transmit signals.

The first through electrode 131 and the second through electrode 132 form a through hole penetrating the first insulating layer 111 and the second insulating layer 112, and the inside of the formed through hole is filled with a conductive material. It can be formed by filling with .

The through hole may be formed by any one of mechanical, laser, and chemical processing. If the through hole is formed by machining, methods such as milling, drilling, and routing can be used. If the through hole is formed by laser processing, UV or CO ₂ laser methods can be used. When formed through chemical processing, at least one insulating layer among the plurality of insulating layers can be opened using chemicals containing aminosilanes, ketones, etc.

Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the first through electrode 131 and the second through electrode 132. Metal materials forming the first through electrode 131 and the second through electrode 132 include copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). ), and the conductive material filling may be any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink jetting, and dispensing. Or, a combination of these methods can be used.

Meanwhile, the circuit board of the embodiment may include a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 may be disposed on the outermost side of the circuit board.

For example, the first protective layer 141 may be disposed on the first outermost or lowermost side of the circuit board. For example, the first protective layer 141 may be disposed on the lower surface of the first insulating layer 111.

For example, the second protective layer 142 may be disposed on the second outermost or uppermost side of the circuit board. For example, the second protective layer 142 may be disposed on the upper surface of the second insulating layer 112.

The first protective layer 141 may include at least one opening (not shown). For example, the first protective layer 141 may include an opening that vertically overlaps at least one of the third circuit pattern layers 123 . For example, the first protective layer 141 may include an opening that vertically overlaps a terminal pad (not shown) of the third circuit pattern layer 123 where a conductive coupling portion for connection to an external substrate is to be disposed. there is.

The second protective layer 142 may include at least one opening (not shown). For example, the second protective layer 142 may include an opening that vertically overlaps at least one of the second circuit pattern layers 122 . For example, the second protective layer 142 has an opening that vertically overlaps the terminal pad (not shown) of the second circuit pattern layer 122 where the conductive coupling portion for connection to the memory substrate or the interposer substrate is disposed. It can be included. Additionally, the second protective layer 142 may include a through hole (not shown) that vertically overlaps the cavity 121 of the second insulating layer 112.

The first protective layer 141 and the second protective layer 142 may include an insulating material. The first protective layer 141 and the second protective layer 142 may include various materials that can be applied and then heated to protect the surfaces of the insulating layers and the surfaces of the circuit pattern layers. The first protective layer 141 and the second protective layer 142 may be resist layers. For example, the first protective layer 141 and the second protective layer 142 may be a solder resist layer containing an organic polymer material. As an example, the first protective layer 141 and the second protective layer 142 may include an epoxy acrylate-based resin. In detail, the first protective layer 141 and the second protective layer 142 may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. However, the embodiment is not limited to this, and the first protective layer 141 and the second protective layer 142 may be any one of a photo solder resist layer, a cover-lay, and a polymer material. am.

The first protective layer 141 and the second protective layer 142 may have a thickness of 1 μm to 20 μm. The first protective layer 141 and the second protective layer 142 may have a thickness of 1 μm to 15 μm. For example, the first protective layer 141 and the second protective layer 142 may have a thickness of 5 μm to 20 μm. When the first protective layer 141 and the second protective layer 142 have a thickness of more than 20㎛, the thickness of the circuit board may increase. If the thickness of the first protective layer 141 and the second protective layer 142 is less than 1㎛, the electrical or physical reliability may be reduced as the circuit pattern layers included in the circuit board are not stably protected. .

At this time, although not shown in the drawing, an opening that vertically overlaps the second circuit pattern layer 122 and the third circuit pattern layer 123 among the openings of the first protective layer 141 and the second protective layer 142 A surface treatment layer (not shown) may be disposed within. The surface treatment layer includes a third circuit pattern layer 123 vertically overlapping with the opening of the first protective layer 141 and a second circuit pattern layer vertically overlapping with the opening of the second protective layer 142 ( 122) can be formed to improve soldering properties while preventing corrosion and oxidation of the surface.

The surface treatment layer may be an Organic Solderability Preservative (OSP) layer. For example, the surface treatment layer may be an organic layer formed of an organic material such as benzimidazole.

However, the embodiment is not limited to this. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

Hereinafter, the structure of the cavity 150 of the embodiment and the arrangement structure of the first circuit pattern layer 121 accordingly will be described in more detail.

Referring to FIG. 3, a first circuit pattern layer 121 may be disposed on the first insulating layer 111. And, as described above, the first circuit pattern layer 121 may include a first pad 121-1, a second pad 121-2, and an electrode pattern 121-3.

The first pad 121-1 may be disposed in a first region R1 that vertically overlaps the cavity 150.

Additionally, the second pad 121-2 may be disposed in the second region R2 that does not vertically overlap the cavity 150.

Additionally, the electrode pattern 121-3 may be disposed on the first region (R1), second region (R2), and third region (R3). The electrode pattern 121-3 may directly connect the first pad 121-1 and the second pad 121-2 on the first insulating layer 111. For example, one end of the electrode pattern 121-3 is directly connected to the first pad 121-1, and the other end of the electrode pattern 121-3 is directly connected to the second pad 121-2. can be connected

At this time, the drawing shows that there are six first pads 121-1, second pads 121-2, and six electrode patterns 121-3 each, but the present invention is not limited thereto. For example, they may have five or fewer or seven or more. Additionally, the number of first pads 121-1, second pads 121-2, and electrode patterns 121-3 may be different. Accordingly, at least one of the plurality of first pads 121-1 may not be directly connected to the second pad 121-2.

Additionally, referring to FIG. 4, a second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the second insulating layer 112.

Accordingly, the first pad 121-1 may not vertically overlap the second insulating layer 112. For example, the first pad 121-1 may vertically overlap the cavity 150.

Additionally, the second pad 121-2 may vertically overlap the second insulating layer 112. For example, the second pad 121-2 may not vertically overlap the cavity 150.

Meanwhile, the electrode pattern 121-3 can be divided into a plurality of parts depending on the location. At this time, being divided into a plurality of parts may mean that one electrode pattern directly connecting one first pad and one second pad is divided into a plurality of parts.

The electrode pattern 121-3 may vertically overlap the cavity 150 and include a first portion 121-31 connected to the first pad 121-1. The first portion 121-31 of the electrode pattern 121-3 may not vertically overlap the second insulating layer 112. For example, the first portion 121-31 of the electrode pattern 121-3 may not be covered with the second insulating layer 112.

Additionally, the electrode pattern 121-3 may include a second portion 121-32 that vertically overlaps the second insulating layer 112. The second portion 121-32 of the electrode pattern 121-3 may not vertically overlap the cavity 150. For example, the second portion 121-32 of the electrode pattern 121-3 may be covered with the second insulating layer 112.

The electrode pattern 121-3 may further include a third part 121-33 between the first part 121-31 and the second part 121-32.

The third portion 121-33 of the electrode pattern 121-3 may refer to a portion adjacent to the edge area of the bottom surface 150-1 of the cavity 150. For example, the third part 121-33 of the electrode pattern 121-3 may refer to a part located at the boundary area of the cavity 150. For example, the third portion 121-33 of the electrode pattern 121-3 may refer to a portion located adjacent to the concave portion 150-3. For example, the third portion 121-33 of the electrode pattern 121-3 is disposed in the third region R3, which is a boundary region between the first region R1 and the second region R2. It can mean the part that has been done.

Meanwhile, the concave portion 150-3 may be provided in an edge area of the bottom surface 150-1 along the edge direction of the bottom surface 150-1. For example, the concave portion 150-3 is recessed in the inner direction of the second insulating layer 112 at the lower end of the side wall 150-2 adjacent to the edge area of the bottom surface 150-1. You can. To summarize, the lower end of the side wall 150-2 of the second insulating layer 112 constituting the cavity 150 has a concave portion 150 recessed inward along the edge direction of the bottom surface 150-1. -3) may be provided.

At this time, the drawing shows that the concave portion 150-3 is not provided in a region of the lower portion of the side wall 150-2 that vertically overlaps the electrode pattern 121-3, but the present invention is not limited to this. This is explained as follows.

Referring to FIGS. 5 to 7 , the first circuit pattern layer 121 includes a plurality of metal layers.

The first circuit pattern layer 121 includes a first metal layer 121a disposed on the first insulating layer 111. The first metal layer 121a may represent a seed layer for electroplating the second metal layer 121b of the first circuit pattern layer 121.

For example, the first metal layer 121a may be a chemical copper plating layer. For example, the first metal layer 121a may be a copper foil layer (Cu foil).

In one embodiment, the first metal layer 121a may include only one of the chemical copper plating layer and the copper foil layer.

In another embodiment, the first metal layer 121a may include both the chemical copper plating layer and the copper foil layer.

The thickness T1 of the first metal layer 121a may satisfy the range of 1.0 μm to 4.0 μm. Preferably, the thickness T1 of the first metal layer 121a may satisfy the range of 1.2㎛ to 3.5㎛. More preferably, the thickness T1 of the first metal layer 121a may satisfy the range of 1.5 ㎛ to 3.0 ㎛.

If the thickness T1 of the first metal layer 121a is less than 1.0 μm, the first metal layer 121a may not function as a seed layer. If the thickness T1 of the first metal layer 121a is less than 1.0 μm, it may be difficult to form the first metal layer 121a with a uniform thickness on the upper surface of the first insulating layer 111.

If the thickness T1 of the first metal layer 121a exceeds 4.0 μm, the time required to etch the first metal layer 121a may increase. If the thickness T1 of the first metal layer 121a exceeds 4.0 μm, deformation of the second metal layer 121b may occur when the first metal layer 121a is etched. Deformation of the second metal layer 121b may mean that the side of the first metal layer 121a is also etched, thereby increasing the difference between the width of the upper and lower surfaces of the second metal layer 121b. In addition, if the thickness T1 of the first metal layer 121a exceeds 4.0 μm, the reliability of the etching process of the first metal layer 121a, which is used as a stopper in the cavity formation process, may decrease. For example, a portion of the first metal layer 121a is used as a stopper in the cavity forming process. And, the first metal layer 121a used as the stopper is removed after the formation of the cavity 150 is completed. At this time, if the thickness T1 of the first metal layer 121a exceeds 4.0 μm, a part of the stopper in the portion corresponding to the concave portion 150-3 is not removed during the etching process of the stopper. It may not be possible. In addition, if a part of the stopper is not removed, an electrical short problem may occur in which a plurality of electrode patterns adjacent to each other are connected to each other by the stopper.

A second metal layer 121b is disposed on the first metal layer 121a. The second metal layer 121b may be an electrolytic plating layer obtained by electroplating the first metal layer 121a as a seed layer.

The thickness T2 of the second metal layer 121b may correspond to a value obtained by subtracting the thickness of the first metal layer 121a from the total thickness of the first circuit pattern layer 121. Since the overall thickness of the first circuit pattern layer 121 has already been described above, detailed description thereof will be omitted.

Meanwhile, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 of the first circuit pattern layer 121 are each formed of the first metal layer 121a and the second electrode pattern 121-3. It includes a metal layer 121b. At this time, the first pad (121-1), the second pad (121-2), and the electrode pattern (121-3) are one piece including the same first metal layer (121a) and second metal layer (121b). It refers to a circuit pattern, and may simply be classified according to placement location and function.

As described above, the electrode pattern 121-3 includes a first part 121-31, a second part 121-32, and a third part 121-33.

At this time, the third portion 121-33 of the electrode pattern 121-3 may include a region where the thickness changes. For example, at least a portion of the third portion 121-31 of the electrode pattern 121-3 may include a portion having a thickness greater than that of the first portion 121-31. For example, at least a portion of the third portion 121-33 of the electrode pattern 121-3 may include a portion having a thickness greater than that of the second portion 121-32.

For example, at least a portion of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may include a portion located higher than the upper surface of the first portion 121-31. For example, at least a portion of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may include a portion located higher than the upper surface of the second portion 121-32.

For example, the third part 121-32 of the electrode pattern 121-3 moves from the first part 121-31 to the second part 121-32 or the second part (121-32). It may include a protrusion 121-3P whose thickness or height changes as it goes from 121-32) to the first part 121-31.

In addition, the protrusion 121-3P includes a first part whose height or thickness increases from the first part 121-31 to the second part 121-32, and a height relative to the first part. Alternatively, it may include a second part whose thickness decreases.

At this time, in the embodiment, the first metal layer 121a of the first circuit pattern layer 121 is etched in a plurality of steps in the circuit board manufacturing process.

That is, in the embodiment, the first metal layer disposed in the second region R2 among the first metal layers 121a of the first circuit pattern layer 121 is the cavity 150 of the second insulating layer 112. It is removed in a first etching process before it is formed.

And, of the first metal layer 121a of the first circuit pattern layer 121, the first metal layer disposed in the first region (R1) and the third region (R3) is formed after the cavity 150 is formed. It is removed in the second etching process.

At this time, the second metal layer of the electrode pattern 121-3 may also be etched in two stages corresponding to the first metal layer. And, under ideal conditions, part of the second metal layer of the electrode pattern 121-3 may be removed in the first etching process, and the remaining part may be removed in the second etching process. However, due to process errors in the electrode pattern 121-3, it may be difficult to accurately distinguish between a portion where the first etching process is performed and a portion where the second etching process is performed.

Accordingly, some of the second metal layers of the electrode pattern 121-3 may not be etched in both the first and second etching processes. And, the portion that has not been etched may be provided as the protrusion 121-3P. The protrusion 121-3P may be provided at the boundary between the third region R3 and the second region R2 in the third portion 121-32 of the electrode pattern 121-3.

Additionally, in contrast, some of the second metal layers of the electrode pattern 121-3 may be etched in both the first etching process and the second etching process. In the case of the above conditions, the third portion 121-32 of the electrode pattern 121-3 may be provided with a concave portion (not shown) rather than the protruding portion 121-3P.

Additionally, the third portion 121-33 of the electrode pattern 121-3 is adjacent to the concave portion 150-3.

At this time, at least a portion of the upper surface of the third portion 121-33 of the electrode pattern 121-3 vertically overlaps the second insulating layer 112 and does not contact the second insulating layer 112. It may not be possible.

For example, a second concave portion 150-4 is formed in an area vertically overlapping with the electrode pattern 121-3 of the lower end of the side wall 150-2 of the cavity 150 of the second insulating layer 112. ) may be provided. Accordingly, the above-described concave portion 150-3 may be referred to as a first concave portion. Hereinafter, the concave portion 150-3 will be described as a 'first concave portion'.

The first concave portion 150-3 and the second concave portion 150-4 are formed on the side wall 150-2 of the second insulating layer 112 adjacent to the edge area of the bottom surface 150-1. It is provided at the bottom.

At this time, the first concave portion 150-3 and the second concave portion 150-4 may have a step. That is, the first concave portion 150-3 is provided in an area of the lower end of the side wall 150-2 that does not vertically overlap the electrode pattern 121-3.

In contrast, the second concave portion 150-4 is provided in a region of the lower end of the side wall 150-2 that vertically overlaps the electrode pattern 121-3. Accordingly, the first concave portion 150-3 and the second concave portion 150-4 may have a step equal to the thickness of the electrode pattern 121-3.

Accordingly, the first concave portion 150-3 and the second concave portion 150-4 are formed along the edge direction of the bottom surface 150-1 in the entire area of the lower end of the side wall 150-2. It may be depressed toward the inside of the second insulating layer 112.

The first concave portion 150-3 may have a first horizontal distance W1.

The first horizontal distance W1 refers to the horizontal distance from the lower end of the side wall 150-2 adjacent to the first recess 150-3 to the innermost side of the first recess 150-3. can do. And, the first concave portion 150-3 is a location where the first metal layer used as a stopper in the process for forming the cavity 150 was removed.

The first horizontal distance W1 may satisfy the range of 5㎛ to 17㎛. Preferably, the first horizontal distance W1 may satisfy the range of 7㎛ to 15㎛. More preferably, the first horizontal distance W1 may satisfy the range of 8㎛ to 13㎛.

If the first horizontal distance W1 is less than 5 μm, the cavity 150 may be processed to an area where a stopper is not provided due to process errors in the process of forming the cavity 150. In this case, a portion of the upper surface of the first insulating layer 111 may also be processed in the cavity forming process. At this time, the first insulating layer 111 includes reinforcing fibers. Additionally, the reinforcing fibers may be exposed through the processing, which may cause physical and electrical reliability problems.

Additionally, if the first horizontal distance W1 exceeds 17㎛, a part of the stopper may not be removed in the stopper removal process after the cavity 150 is formed. For example, in the embodiment, all of the stoppers are removed using an overetching phenomenon in the stopper removal process. That is, when an etching process to remove the stopper is performed after the cavity 150 is formed, only the portion that vertically overlaps the cavity 150 is removed by etching under general conditions. However, in the embodiment, in the process for removing the stopper, over-etching conditions are set, and the stopper is removed according to the set over-etching conditions. In addition, when the stopper is removed according to the over-etching conditions, the stopper covered by the second insulating layer 112 in the area adjacent to the cavity 150 is also removed. At this time, the fact that the first horizontal distance W1 exceeds 17㎛ may mean that damage to the first pad 121-1 may occur as the overetching condition is set too excessively. Additionally, the fact that the first horizontal distance W1 exceeds 17㎛ may mean that a part of the stopper may not be removed even under overetching conditions for removing the stopper. And, if part of the stopper is not removed, electrical reliability problems such as circuit short may occur.

Meanwhile, the first concave portion 150-3 is a location where the first metal layer 121a was removed, and accordingly, the vertical distance T1 of the first concave portion 150-3 is the first metal layer ( It can correspond to the thickness (T1) of 121a).

Additionally, the second concave portion 150-4 may have a second horizontal distance W2. At this time, the second horizontal distance W2 of the second concave part 150-4 may be greater than or equal to the first horizontal distance W1 of the first concave part 150-3. Preferably, the second horizontal distance W2 of the second concave part 150-4 may be greater than the first horizontal distance W1 of the first concave part 150-3.

This means that the first horizontal distance (W1) and the second horizontal distance (W2) are equal to each other, which means that under overetching conditions for removing the stopper, overetching occurred exactly up to the portion where the stopper is located. there is. In this case, a problem may occur in which part of the stopper is not removed in some cases. Accordingly, in the embodiment, the second horizontal distance (W2) is greater than the first horizontal distance (W1). In addition, the fact that the second horizontal distance (W2) is greater than the first horizontal distance (W1) means that under overetching conditions for removing the stopper, overetching occurred beyond the portion where the stopper is located. You can. Accordingly, the stopper can be completely removed, thereby improving the electrical reliability of the circuit board.

FIG. 8 is a cross-sectional view showing a circuit board according to the second embodiment, FIG. 9 is an enlarged view of a portion of the cavity of FIG. 8, and FIG. 10 is an enlarged view of another portion of the cavity of FIG. 8. .

8 to 10, the circuit board of the second embodiment includes a first insulating layer 211, a second insulating layer 212, a first circuit pattern layer 221, a second circuit pattern layer 222, It includes a third circuit pattern layer 223, a first through electrode 231, a second through electrode 232, a first protective layer 241, and a second protective layer 242. Additionally, the second insulating layer 212 may be provided with a cavity 250 including a bottom surface 250-1 and a side wall 250-2.

At this time, the circuit board of the second embodiment may have a structure in which the circuit board of the first embodiment is turned upside down and a cavity is provided in the first insulating layer of the first embodiment.

Accordingly, the circuit board of the second embodiment may be different in the location of the first concave portion 250-3 and the layer structure of the first circuit pattern layer 221.

Specifically, the first concave portion in the first embodiment was provided on the side wall of the second insulating layer.

Alternatively, the first concave portion 250-3 in the second embodiment may be provided on the upper surface of the first insulating layer 211.

That is, the first circuit pattern layer 221 includes a first metal layer 221a and a second metal layer 221b.

At this time, in the circuit board of the first embodiment, the second metal layer of the first circuit pattern layer was located closer to the cavity than the first metal layer.

On the contrary, in the circuit board of the second embodiment, the first metal layer 221a is located closer to the cavity 250 than the second metal layer 221b of the first circuit pattern layer 221.

Accordingly, the circuit board of the second embodiment may have a step on the upper surface of the first insulating layer 211. For example, among the top surfaces of the first insulating layer 211, the top surface of a region that vertically overlaps the cavity 250 may have a first height. Also, the top surface of the area of the first insulating layer 211 that does not vertically overlap the cavity 250 may have a second height that is higher than the first height. At this time, a portion of the upper surface of the first insulating layer 211 that does not vertically overlap the cavity 250 and is adjacent to the cavity 250 may include a first concave portion 250-3 having the first height. You can. That is, the cavity 250 is formed with the first metal layer 221a of the first circuit pattern layer 221 disposed at a position corresponding to the first concave portion 250-3. Additionally, as a portion of the first metal layer 221a is removed after the cavity 250 is formed, the upper surface of the first insulating layer 211 may have a step corresponding to the concave portion 250-3. .

That is, the first concave portion 250-3 of the second embodiment may be recessed into the first insulating layer 211 at the bottom of the side wall 150-2 of the cavity 250.

To summarize, the first concave portion and the second concave portion of the first embodiment have a structure that is depressed from the bottom of the side wall of the cavity toward the inside of the second insulating layer. Accordingly, the lower surface of the second insulating layer of the first embodiment has a step corresponding to the first and second concave portions.

Differently, the first concave portion 250-3 of the second embodiment may have a structure that is recessed from the bottom of the side wall 150-2 of the cavity 250 toward the inside of the first insulating layer 211. Accordingly, the upper surface of the first insulating layer 211 may have a step corresponding to the first concave portion 250-3.

Meanwhile, the first circuit pattern layer 221 includes a first pad 221-1, a second pad 221-2, and an electrode pattern 221-3. And, the electrode pattern 221-3 may include a first part 221-31, a second part 221-32, and a third part 221-33.

At this time, the first pad 221-1, the second pad 221-2, and the electrode pattern 221-3 may have different thicknesses. For example, the first pad 221-1, the second pad 221-2, and the electrode pattern 221-3 may have different layer structures.

Preferably, the first circuit pattern layer 221 may include a first metal layer 221a and a second metal layer 221b.

At this time, the first metal layer of the first pad 221-1 is used as a stopper in the process of forming the cavity 250. Accordingly, the first pad 221-1 may include only the second metal layer excluding the first metal layer.

Differently, the second pad 221-2 may include both the first metal layer 221a and the second metal layer 221b.

Meanwhile, the electrode pattern 221-3 may have different layer structures or thicknesses depending on the location.

The first portion 221-31 of the electrode pattern 221-3 may include only the second metal layer 221b. This is because the first metal layer 221a of the first portion 221-31 of the electrode pattern 221-3 was used as a stopper in the process of forming the cavity 250.

Additionally, the second portion 221-32 of the electrode pattern 221-3 may include both the first metal layer 221a and the second metal layer 221b.

Meanwhile, the third portion 221-33 of the electrode pattern 221-3 may include only the second metal layer 221b. This is because overetching occurs in the process of removing the first metal layer of the first portion 221-31 of the electrode pattern 221-3 by etching, and accordingly, the first metal layer of the first portion 221-31 of the electrode pattern 221-3 is This is because the first metal layer 221a of the three parts 221-33 was removed.

Figure 11 is a diagram showing a package substrate according to an embodiment.

Referring to FIG. 11 , the package substrate may include a connection member 310 disposed on the first pad 121-1 and a connection member 320 disposed on the connection member 310.

The connecting member may be any one of the second substrate, semiconductor device, and connecting substrate described in FIGS. 1A to 1G.

Meanwhile, a molding member 330 may be disposed in the cavity 150. The molding member 330 may be disposed within the cavity 150 by molding the connecting member 320.

At this time, at least a portion of the molding member 330 may be disposed to fill the first concave portion 150-3 and the second concave portion 150-4 provided in the cavity 150. Among the molding members 330, portions disposed in the first concave portion 150-3 and the second concave portion 150-4 may function as anchors. Accordingly, the embodiment can further improve the adhesion between the molding member 330 and the circuit board.

Hereinafter, the manufacturing method of the circuit board of the embodiment will be described.

Referring to Figure 12, the embodiment prepares the insulating member based on the manufacture of the circuit board.

For example, the embodiment includes an insulating member including a first insulating layer 111 and a metal layer on the first insulating layer 111.

The metal layer may include a metal layer 121a disposed on the first insulating layer 111 and a metal layer 123a disposed under the first insulating layer 111. Additionally, the metal layer 121a can be used as a seed layer for forming the first circuit pattern layer 121 by electrolytic plating. Additionally, the metal layer 123a can be used as a seed layer for forming the third circuit pattern layer 123 by electroplating.

Next, referring to FIG. 13, in the embodiment, electrolytic plating is performed using the

metal layers

121a and 123a as a seed layer, and the second metal layer 121b of the first circuit pattern layer 121 and the third metal layer are formed. A first through electrode 131 that penetrates the second metal layer 123b of the circuit pattern layer 123 and the first insulating layer 111 is formed.

At this time, the substrate manufactured up to the process of FIG. 13 may include a first region (R1), a second region (R2), and a third region (R3). The first area R1 may be an area corresponding to the actual size of the cavity 150. Additionally, the second region R2 may be a region in which the cavity 150 is not formed. And, the third area R3 refers to a boundary area between the first area R1 and the second area R2. The third area R3 may be an area that takes process errors in the cavity forming process into consideration.

Next, referring to FIG. 14 , in the embodiment, a dry film DF1 is disposed on the first region R1 and the third region R3 of the first circuit pattern layer 121. The dry film DF1 can prevent the first metal layer 121a, which will be used as a stopper in the first etching process, from being removed.

Next, referring to FIG. 15, the embodiment shows the first metal layer 121a and the third circuit pattern layer 123 of the first circuit pattern layer 121 in the area where the dry film DF1 is not disposed. A process of removing the first metal layer 123a may be performed. Through this, the embodiment can form the second pad 121-2 and the third circuit pattern layer 123 of the first circuit pattern layer 121.

That is, referring to FIG. 16, all portions of the first metal layer 121a disposed in the second region R1 that do not vertically overlap the second metal layer 121b may be removed. Accordingly, the second pad 121-2 of the first circuit pattern layer 121 and a portion of the electrode pattern 221-3 (for example, the second portion 121-32) can be formed. In this case, The first metal layer 121a disposed in the first region R1 and the third region R3 may be used as a first stopper S1 in the process of forming the cavity 150.

Next, referring to FIG. 17 , in the embodiment, the second insulating layer 112 may be disposed on the first insulating layer 111. At this time, the first metal layer 122a of the second circuit pattern layer 122, which is a seed layer of the second circuit pattern layer 122, may be disposed on the upper surface of the second insulating layer 112.

Next, referring to FIG. 18, in the embodiment, electrolytic plating is performed using the first metal layer 122a of the second circuit pattern layer 122 as a seed layer, and the second metal layer 122a of the second circuit pattern layer 122 is formed. A metal layer 122b may be formed. At this time, a second through electrode 132 penetrating the second insulating layer 112 may be formed together with the second metal layer 122b.

Next, referring to FIG. 19 , the embodiment may proceed with a process of removing the first metal layer 122a of the second circuit pattern layer 122 by etching. At this time, the embodiment does not remove all of the first metal layer 122a of the second circuit pattern layer 122, but leaves some of it. For example, in the embodiment, all portions of the first metal layer 122a of the second circuit pattern layer 122 disposed in the first region R1 are removed. In addition, the embodiment is a portion of the first metal layer 122a of the second circuit pattern layer 122 disposed in the third region R3 and the second region R2 adjacent to the third region R3. Do not remove some. This can be used as a second stopper (S2) in the process of forming the cavity 150. At this time, the first stopper (S1) and the second stopper (S2) may at least partially overlap vertically. For example, the first stopper S1 and the second stopper S2 may vertically overlap in the third region R3. Through this, the embodiment can prevent the size of the cavity 150 from expanding during the process of forming the cavity 150.

Next, referring to FIG. 20, in the embodiment, the cavity 150 penetrating the second insulating layer 112 may be formed using the first stopper (S1) and the second stopper (S2).

At this time, the cavity 150 at the bottom of the side wall 150-2 of the cavity 150 may not vertically overlap the third region R3.

Thereafter, referring to FIG. 21, the embodiment may proceed with a process of removing the first stopper (S1) and the second stopper (S2) by etching. At this time, the second stopper S2 can be easily removed because there is no insulating layer covering the top.

In contrast, the portion corresponding to the third region R3 of the entire area of the first stopper S1 is covered with the second insulating layer 112. At this time, if the portion corresponding to the first region (R1) of the entire region of the first stopper (S1) is etched, overetching may occur. Also, in the embodiment, the first stopper S1 in the third region R3 can be easily removed by using the over-etching process. Accordingly, a first concave portion 150-3 may be provided at the lower end of the side wall 150-2 of the cavity 150, where the first stopper S1 was removed.

Next, referring to FIG. 22, in the embodiment, a first protective layer 141 is formed under the first insulating layer 111, and a second protective layer 142 is formed on the second insulating layer 112. The forming process can proceed.

Meanwhile, when a circuit board having the characteristics of the above-described invention is used in IT devices such as smartphones, server computers, TVs, or home appliances, functions such as signal transmission or power supply can be stably performed. For example, when a circuit board having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems such as leakage current or electrical short circuits between terminals. Alternatively, the problem of electrical opening of the terminal supplying the semiconductor chip can be solved. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved. Through this, the circuit board having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

When a circuit board having the characteristics of the above-mentioned invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of signals transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside and prevent leakage. The stability of the transport device can be further improved by solving the problem of electrical short-circuiting between currents or terminals, or the problem of electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

Although the above description focuses on the embodiment, this is only an example and does not limit the embodiment, and those skilled in the art will understand that there are various options not exemplified above without departing from the essential characteristics of the present embodiment. You will see that variations and applications of branches are possible. For example, each component specifically shown in the examples can be modified and implemented. And these variations and differences related to application should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims

first insulating layer;

a second insulating layer disposed on the first insulating layer; and

It includes a circuit pattern layer disposed between the first and second insulating layers,

The second insulating layer has a cavity penetrating the upper and lower surfaces,

The circuit pattern layer includes an electrode pattern extending from the inside of the cavity to the outside of the cavity.
According to paragraph 1,

The circuit pattern layer is

a first pad provided inside the cavity and overlapping in a vertical direction with the cavity; and

A circuit board further comprising a second pad provided on the outside of the cavity that does not vertically overlap the cavity.
According to paragraph 2,

A circuit board, wherein the electrode pattern is directly connected between the first pad and the second pad,
According to paragraph 1,

The circuit board wherein the second insulating layer has a concave portion that is concave in a direction from the bottom of the side wall of the cavity toward the outside of the cavity.
According to paragraph 4,

A circuit board wherein the concave portion includes a first part that does not overlap the electrode pattern in a vertical direction, and a second part that overlaps the electrode pattern in the vertical direction.
According to paragraph 3,

The circuit pattern layer is provided to protrude onto the first insulating layer,

A circuit board wherein the first portion of the concave portion is provided along a lower edge of a side wall of the cavity.
According to clause 5,

A circuit board, wherein the first and second portions of the concave portion have a step.
According to clause 5,

Each of the first pad, the second pad, and the electrode pattern,

a first metal layer disposed on the first insulating layer; and

Comprising a second metal layer disposed on the first metal layer,

A circuit board wherein the length of the first concave portion in the vertical direction corresponds to the thickness of the first metal layer.
According to clause 5,

A circuit board, wherein the horizontal distance from the lower end of the side wall of the cavity to the innermost end of the first portion of the concave portion satisfies the range of 5 μm to 17 μm.
According to clause 5,

A circuit board, wherein the horizontal length of the first part of the recess is different from the horizontal length of the second part of the recess.