WO2024032136A1 - Offset calibration circuit and memory - Google Patents

Abstract

Disclosed in embodiments of the present disclosure are an offset calibration circuit and a memory. The offset calibration circuit comprises an adjustable delay circuit, a phase detection circuit and a phase adjustment control circuit. The adjustable delay circuit is used for receiving an initial differential signal and calibrating the initial differential signal to an i-th differential signal according to an i-th delay amount. The phase detection circuit is used for performing preset delay processing on the i-th differential signal to obtain a reference differential signal, and performing logic processing and comparison on the i-th differential signal and the reference differential signal to obtain a comparison result. The phase adjustment control circuit is used for determining an (i+1)-th differential signal having a minimum offset and a corresponding (i+1)-th delay amount from the i-th differential signal and the reference differential signal on the basis of the comparison result. The adjustable delay circuit is further used for updating the i-th delay amount to the (i+1)-th delay amount to calibrate the initial differential signal to the (i+1)-th differential signal.

Description

An offset calibration circuit and memory

Cross-references to related applications

This disclosure is based on a Chinese patent application with application number 202210959979.

Technical field

The present disclosure relates to, but is not limited to, an offset calibration circuit and a memory.

Background technique

In integrated circuits, some signals need to be transmitted in the form of differential signals. Since the differential signal includes two signals, the two signals may offset during the transmission process, thus affecting the accuracy of the differential signal.

Contents of the invention

In view of this, embodiments of the present disclosure provide an offset calibration circuit and a memory, which can improve the quality of differential signals and reduce design costs.

The technical solution of the embodiment of the present disclosure is implemented as follows:

Embodiments of the present disclosure provide an offset calibration circuit, including: an adjustable delay circuit, a phase detection circuit and a phase adjustment control circuit;

The adjustable delay circuit is used to receive an initial differential signal and calibrate the initial differential signal to the i-th differential signal according to the i-th delay amount; i is greater than or equal to 1;

The input end of the phase detection circuit is electrically connected to the output end of the adjustable delay circuit, and is used to perform preset delay processing on the i-th differential signal to obtain a reference differential signal, and to perform preset delay processing on the i-th differential signal. Perform logical processing and comparison with the reference differential signal to obtain a comparison result;

The input end of the phase adjustment control circuit is electrically connected to the output end of the phase detection circuit, and the first output end is electrically connected to the control end of the adjustable delay circuit, and is used to determine the first step based on the comparison result. Determine the i+1th differential signal with the smallest offset among the i differential signal and the reference differential signal, and determine the i+1th delay corresponding to the i+1th differential signal;

The adjustable delay circuit is also used to update the i-th delay amount to the i+1-th delay amount under the control of the phase adjustment control circuit, so as to calibrate the initial differential signal to the i-th delay amount. i+1 differential signal.

In the above solution, if the i-th differential signal is not determined to be the i+1-th differential signal, the offset calibration circuit is also used to continue offset calibration until the N-1-th differential signal is determined to be Nth differential signal.

In the above scheme, the phase detection circuit includes: a precision configuration register, a preset delay circuit, an exclusive OR circuit, an integrating circuit and a comparison circuit;

The output terminal of the precision configuration register is electrically connected to the configuration terminal of the preset delay circuit, and is used to store the preset delay amount and send the preset delay amount to the preset delay circuit;

The input end of the preset delay circuit is electrically connected to the output end of the adjustable delay circuit, and is used to delay the i-th differential signal according to the preset delay amount to obtain the reference differential signal;

The input end of the XOR circuit is electrically connected to the output end of the preset delay circuit and the output end of the adjustable delay circuit respectively, and is used to perform simultaneous operation on the i-th differential signal and the reference differential signal respectively. Or processing, obtaining multiple same-OR results;

The input terminal of the integrating circuit is electrically connected to the output terminal of the XOR circuit, and is used for integrating multiple XOR results to obtain corresponding multiple integrated voltages;

The input terminal of the comparison circuit is electrically connected to the output terminal of the integrating circuit, and is used to compare two of the plurality of integrated voltages to obtain the comparison result.

In the above scheme, the second output end of the phase adjustment control circuit is electrically connected to the control end of the AND circuit, the control end of the integrating circuit and the control end of the comparison circuit respectively; the phase adjustment control circuit, It is also used to send an enable signal to the exclusive OR circuit, the integrating circuit and the comparing circuit to control the running or stopping of the exclusive OR circuit, the integrating circuit and the comparing circuit.

In the above solution, the third output terminal of the phase adjustment control circuit is electrically connected to the control terminal of the precision configuration register; the phase adjustment control circuit is also used to determine the i-th differential signal as the i-th differential signal. In the case of a +1 differential signal, the accuracy configuration register is controlled to reduce the preset delay amount.

In the above solution, the initial differential signal includes an initial clock signal and an initial complementary clock signal; the i-th differential signal includes an i-th clock signal and an i-th complementary clock signal; the adjustable delay circuit includes: a first delay unit and a second delay unit; the first delay unit is configured to receive the initial clock signal, delay the initial clock signal to the i-th clock signal; and delay the initial clock signal to the i+1-th clock signal ; The second delay unit is used to receive the initial complementary clock signal, delay the initial complementary clock signal to the i-th complementary clock signal; and, delay the initial complementary clock signal to the i+1-th complementary clock Signal.

In the above solution, the reference differential signal includes: a first reference differential signal and a second reference differential signal; the preset delay circuit includes: a third delay unit and a fourth delay unit; the third delay unit has an input The terminal is electrically connected to the output terminal of the first delay unit, and is used to delay the i-th clock signal into a clock reference signal according to the preset delay amount; the clock reference signal and the i-th complementary clock signal are composed of The first reference differential signal; the fourth delay unit, the input end of which is electrically connected to the output end of the second delay unit, is used to delay the i-th complementary clock signal into a complementary clock according to the preset delay amount Reference signal; the i-th clock signal and the complementary clock reference signal constitute the second reference differential signal.

In the above solution, the XOR circuit includes: a first XOR gate, a second XOR gate and a third XOR gate; the input terminals of the first XOR gate are respectively electrically connected to the second delay unit. The output terminal and the output terminal of the third delay unit are used to perform XOR processing on the first reference differential signal to obtain a first XOR result; the input terminals of the second XOR gate are electrically connected to the The output end of the first delay unit and the output end of the second delay unit are used to perform XOR processing on the i-th differential signal to obtain a second XOR result; the input of the third XOR gate is terminals are respectively electrically connected to the output terminals of the first delay unit and the output terminal of the fourth delay unit, and are used to perform exclusive OR processing on the second reference differential signal to obtain a third exclusive OR result.

In the above scheme, the integrating circuit includes: a first integrating unit, a second integrating unit and a third integrating unit; the input end of the first integrating unit is electrically connected to the output end of the first NOR gate for The first XOR result is integrated to obtain a first integrated voltage; the input end of the second integrating unit is electrically connected to the output end of the second XOR gate, and is used to calculate the second XOR result. The result is integrated to obtain the second integrated voltage; the input terminal of the third integrating unit is electrically connected to the output terminal of the third XOR gate, and is used to perform integration processing on the third XOR result to obtain the third integrated voltage. Three integral voltage.

In the above scheme, the comparison circuit includes: a first comparator and a second comparator; the comparison result includes: a first comparison result and a second comparison result; the first comparator has a first input end electrically connected to The output terminal of the second integrating unit and its second input terminal are electrically connected to the output terminal of the first integrating unit for comparing the first integrated voltage and the second integrated voltage to obtain the third integrated voltage. A comparison result; the second comparator, whose first input terminal is electrically connected to the output terminal of the second integrating unit, and whose second input terminal is electrically connected to the output terminal of the third integrating unit, is used to compare the The second integrated voltage is compared with the third integrated voltage to obtain the second comparison result.

In the above solution, the phase adjustment control circuit is further configured to receive the first comparison result and the second comparison result, and determine the first comparison result based on the first comparison result and the second comparison result. The minimum value among the integrated voltage, the second integrated voltage and the third integrated voltage is determined to determine the i+1th differential signal corresponding to the minimum value.

In the above solution, the phase adjustment control circuit is further configured to send a first update instruction to the first delay unit if it is determined that the first reference differential signal is the i+1th differential signal. The i-th delay amount is updated to the i+1-th delay amount.

In the above solution, the phase adjustment control circuit is further configured to send a second update instruction to the second delay unit if it is determined that the second reference differential signal is the i+1th differential signal. The i-th delay amount is updated to the i+1-th delay amount.

An embodiment of the present disclosure also provides a memory, which includes the offset calibration circuit as described in the above solution.

In the above solution, the memory is a dynamic random access memory (DRAM).

It can be seen that the embodiment of the present disclosure provides an offset calibration circuit and a memory. The offset calibration circuit includes: an adjustable delay circuit, a phase detection circuit and a phase adjustment control circuit. Among them, the adjustable delay circuit is used to receive the initial differential signal and calibrate the initial differential signal to the i-th differential signal according to the i-th delay amount; i is greater than or equal to 1. A phase detection circuit, the input end of which is electrically connected to the output end of the adjustable delay circuit, is used to perform preset delay processing on the i-th differential signal to obtain a reference differential signal, and perform logical processing and summation on the i-th differential signal and the reference differential signal. Compare and get the comparison results. A phase adjustment control circuit, the input end of which is electrically connected to the output end of the phase detection circuit, and the first output end of which is electrically connected to the control end of the adjustable delay circuit, for determining the i-th differential signal and the reference differential signal based on the comparison result. The i+1th differential signal with the smallest offset is determined, and the i+1th delay corresponding to the i+1th differential signal is determined. The adjustable delay circuit is also used, controlled by the phase adjustment control circuit, to update the i-th delay amount to the i+1-th delay amount, so as to calibrate the initial differential signal to the i+1-th differential signal. It can be understood that the offset calibration circuit can update the calibration result from the i-th differential signal to the i+1-th differential signal with a smaller offset, thereby realizing automatic detection and detection of the phase offset of the input initial differential signal. Calibration, on the one hand, reduces the error of the differential signal and improves the quality of the differential signal. On the other hand, it reduces the design requirements for reducing the offset of the differential signal in the PCB board routing and reduces the cost of the differential signal in the PCB board. The difficulty of wiring reduces design costs.

Description of drawings

Figure 1A is an illustration of the offset of the differential signal;

Figure 1B is Figure 2 illustrating the offset of the differential signal;

Figure 2 is a schematic structural diagram of an offset calibration circuit provided by an embodiment of the present disclosure;

Figure 3 is a signal diagram 1 of the offset calibration circuit provided by an embodiment of the present disclosure;

Figure 4 is a schematic structural diagram 2 of an offset calibration circuit provided by an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram three of an offset calibration circuit provided by an embodiment of the present disclosure;

Figure 6 is a schematic structural diagram 4 of an offset calibration circuit provided by an embodiment of the present disclosure;

Figure 7 is a schematic structural diagram 5 of an offset calibration circuit provided by an embodiment of the present disclosure;

Figure 8 is a second signal diagram of the offset calibration circuit provided by an embodiment of the present disclosure;

Figure 9 is a signal diagram 3 of the offset calibration circuit provided by an embodiment of the present disclosure;

Figure 10 is a logic schematic diagram of an offset calibration circuit provided by an embodiment of the present disclosure;

Figure 11 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated below in conjunction with the accompanying drawings and examples. The described embodiments should not be regarded as limiting the present disclosure. Those of ordinary skill in the art will All other embodiments obtained without creative efforts belong to the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

If a similar description of "first/second" appears in the invention document, add the following description. In the following description, The terms "first\second\third" involved are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first\second\third" can be used interchangeably if permitted. The specific order or sequence may be changed so that the embodiments of the disclosure described herein can be implemented in an order other than that illustrated or described herein.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

In integrated circuits, some signals are transmitted in the form of differential signals, such as clock differential signals. Differential signals include two signals with the same amplitude but opposite phases. These two signals are transmitted simultaneously on two signal lines. The signal receiving end can determine the logical state of the differential signal by comparing the difference between the two signals. Compared with single-ended signals transmitted on a signal line, differential signals have the advantages of strong anti-interference ability and accurate timing positioning. However, since the differential signal includes two signals, the two signals may offset during transmission, thus affecting the accuracy of the differential signal.

The JEDEC (Joint Electron Device Engineering Council) standard defines the differential input cross point VIX of the clock differential signal, which is the difference between the clock signal (CK_t, true clock) and the complementary clock signal (CK_c, complement clock) The difference between the level of the actual cross point and the intermediate level between the ground voltage VSS and the supply voltage VDD. In order to ensure that the setup time (set-up time) and hold time (hold time) of the differential clock signal, as well as the output tilt parameters related to the clock, meet the requirements, the JEDEC standard limits the maximum value of the cross-point voltage VIX of the differential clock signal. and minimum value.

Referring to Figure 1A, the intermediate level between the ground voltage VSS and the power supply voltage VDD is VDD/2, then the difference between the level of the actual intersection point of the clock signal CK_t and the complementary clock signal CK_c to the intermediate level VDD/2 is expressed as a double The arrow indicates the differential input crossover point VIX. Referring to Figure 1B, the offset between the clock signal CK_t and the complementary clock signal CK_c is 0, that is, there is no offset, then the differential input cross point VIX is 0, that is, the actual cross point of the clock signal CK_t and the complementary clock signal CK_c. The level is the middle level VDD/2. It can be understood that when the absolute value of the differential input cross point VIX is smaller, the offset between the clock signal CK_t and the complementary clock signal CK_c is smaller, and the differential clock signal is closer to the ideal state.

In the related art, the phase of the differential clock signal is usually controlled through careful calculation of the traces on the PCB board to reduce the offset in the differential clock signal. However, with the continuous improvement of system integration and complexity, as well as the continuous improvement of clock frequency, the design cost of wiring line design and PCB wiring cost continue to increase, and the phase of the differential clock signal is increasingly difficult to effectively control. .

Figure 2 is an optional structural schematic diagram of an offset calibration circuit provided by an embodiment of the present disclosure. As shown in Figure 2, the offset calibration circuit 80 includes: an adjustable delay circuit 10, a phase detection circuit 20 and a phase adjustment control circuit 30 . The adjustable delay circuit 10 is used to receive the initial differential signal CK0, and calibrate the initial differential signal CK0 to the i-th differential signal CKi according to the i-th delay amount. The input terminal of the phase detection circuit 20 is electrically connected to the output terminal of the adjustable delay circuit 10 . The phase detection circuit 20 is used to perform preset delay processing on the i-th differential signal CKi to obtain a reference differential signal CKi/(not shown in Figure 2) corresponding to the i-th differential signal CKi, and to compare the i-th differential signal CKi and the reference The differential signal CKi/ is logically processed and compared, and a comparison result Fi corresponding to the i-th differential signal CKi is obtained. The input terminal of the phase adjustment control circuit 30 is electrically connected to the output terminal of the phase detection circuit 20 , and the first output terminal of the phase adjustment control circuit 30 is electrically connected to the control terminal of the adjustable delay circuit 10 . The phase adjustment control circuit 30 is used to determine, based on the comparison result Fi, the i+1th differential signal CK(i+1) with the smallest offset among the ith differential signal CKi and the reference differential signal CKi/, and determine the ith differential signal CK(i+1). The i+1th delay amount corresponding to the +1 differential signal CK2. The adjustable delay circuit 10 is also used to update the i-th delay amount to the i+1-th delay amount under the control of the phase adjustment control circuit, so as to calibrate the initial differential signal CK0 to the i+1-th differential signal CK(i+1). .

In the embodiment of the present disclosure, the adjustable delay circuit 10 can control the relative delay or relative advance of the two signals in the initial differential signal CK0 by applying a certain delay amount to the two signals in the initial differential signal CK0 to complete the adjustment. Calibration of initial differential signal CK0. Correspondingly, both the i-th delay amount and the i+1-th delay amount include the delay amounts applied to the two signals in the initial differential signal CK0 respectively. The adjustable delay circuit 10 can be configured according to the i-th delay amount or the i+1-th delay amount. The delay amount is used to calibrate the initial differential signal CK0 to the i-th differential signal CKi or the i+1-th differential signal CK(i+1) respectively.

For example, the initial differential signal CK0 includes an initial clock signal CK_t0 and an initial complementary clock signal CK_c0. If a delay of 8 ns is applied to the initial clock signal CK_t0, it means that the initial clock signal CK_t0 is delayed by 8 ns relative to the initial complementary clock signal CK_c0. If a delay of 4 ns is applied to the initial complementary clock signal CK_c0, it means that the initial complementary clock signal CK_c0 is delayed by 4 ns relative to the initial clock signal CK_t0, that is, the initial clock signal CK_t0 is advanced by 4 ns relative to the initial complementary clock signal CK_c0. Furthermore, if a delay of 8 ns is applied to the initial clock signal CK_t0 and a delay of 4 ns is applied to the initial complementary clock signal CK_c0, it means that the initial clock signal CK_t0 is delayed by 4 ns relative to the initial complementary clock signal CK_c0.

In the embodiment of the present disclosure, after the adjustable delay circuit 10 calibrates the initial differential signal CK0 to the i-th differential signal CKi according to the i-th delay amount, the phase detection circuit 20 can obtain the i-th differential signal from the output end of the adjustable delay circuit 10 CKi, and performs preset delay processing on the i-th differential signal CKi to obtain the reference differential signal CKi/ corresponding to the i-th differential signal CKi. Here, the preset delay processing is delayed according to the preset delay amount, and the size of the preset delay amount is set according to the calibration accuracy.

For example, referring to FIG. 3, the i-th differential signal CKi includes the i-th clock signal CK_ti and the i-th complementary clock signal CK_ci. The phase detection circuit 20 can apply a preset delay amount to the i-th clock signal CK_ti to obtain the corresponding clock reference signal CK_ti+, and apply a preset delay amount to the i-th complementary clock signal CK_ci to obtain the corresponding complementary clock reference signal CK_ci+, to Complete the preset delay processing of the i-th differential signal CKi.

In the embodiment of the present disclosure, the reference differential signal CKi/ corresponding to the i-th differential signal CKi may include a first reference differential signal CKi_T/ and a second reference differential signal CKi_C/. The first reference differential signal CKi_T/ includes the clock reference signal CK_ti+ and the i-th complementary clock signal CK_ci, and the second reference differential signal CK1_C/ includes the i-th clock signal CK_ti and the complementary clock reference signal CK_ci+. That is to say, the first reference differential signal CKi_T/ is obtained by delaying the i-th clock signal CK_ti with respect to the i-th complementary clock signal CK_ci by a preset delay amount; the second reference differential signal CKi_C/ is obtained by delaying the i-th complementary clock signal CK_ci. CK_ci is delayed by a preset delay amount relative to the i-th clock signal CK_ti. The first reference differential signal CKi_T/ can be regarded as the delay of the i-th clock signal CK_ti relative to the i-th complementary clock signal CK_ci, and the second reference differential signal CKi_C/ can be regarded as the delay of the i-th clock signal CK_ti relative to the i-th complementary clock signal CK_ci. Advance, relative delay and relative advance changes are all preset delay amounts.

In the embodiment of the present disclosure, the phase detection circuit 20 can perform logical processing and comparison on the i-th differential signal CKi and the reference differential signal CKi/ after generating the reference differential signal CKi/ corresponding to the i-th differential signal CKi, to obtain the i-th differential signal. The comparison result Fi corresponding to CKi. Furthermore, the phase adjustment control circuit 30 may determine the differential signal with the smallest offset among the i-th differential signal CKi and the reference differential signal CKi/ based on the comparison result Fi, and use the differential signal with the smallest offset as the i+th differential signal CKi/. 1 differential signal CK(i+1), and determine the i+1th delay amount corresponding to the i+1th differential signal CK(i+1). Here, the smallest offset means that the phase relationship of the corresponding differential signal is closest to the phase relationship of the differential signal under ideal conditions. In other words, the differential signal with the smallest offset has the smallest absolute value of the differential input cross point VIX. .

For example, referring to Figure 3, among the i-th differential signal CKi and the reference differential signal CKi/, the second reference differential signal CKi_C/ composed of the i-th clock signal CK_ti and the complementary clock reference signal CK_ci+ has the smallest offset (shown by the dotted line Shows). Therefore, the i-th clock signal CK_ti and the complementary clock reference signal CK_ci+ are determined as the i+1-th differential signal CK(i+1).

In the embodiment of the present disclosure, the adjustable delay circuit 10 will be controlled by the phase adjustment control circuit 30 to update the i-th delay amount to the i+1-th delay amount to calibrate the initial differential signal CK0 to the i+1-th differential signal CK. (i+1). That is to say, the output of the adjustable delay circuit 10 is updated from the i-th differential signal CKi to the i+1-th differential signal CK(i+1) with a smaller offset, thereby achieving calibration of the initial differential signal CK0.

In the embodiment of the present disclosure, if the offset of the i-th differential signal CKi is the smallest among the i-th differential signal CKi and the reference differential signal CKi/, then the i-th differential signal CKi is determined to be the i+1-th differential signal CK(i +1), the i-th delay amount is regarded as the i+1-th delay amount. Correspondingly, the adjustable delay circuit 10 does not change its setting, and still calibrates the initial differential signal to the i-th differential signal CKi according to the i-th delay amount.

It should be noted that in the embodiment of the present disclosure, only the initial differential signal is used as the clock differential signal as an example, that is, the offset calibration circuit 80 is not limited to performing offset calibration on the clock differential signal. The initial differential signal can also be any differential signal, such as the differential data strobe signal DQS_t/DQS_c.

It can be understood that the offset calibration circuit 80 can update the calibration result from the i-th differential signal CKi to the i+1-th differential signal CK(i+1) with a smaller offset, thereby realizing the adjustment of the input initial differential signal. The automatic detection and calibration of the phase offset of CK0, on the one hand, reduces the error of the differential signal and improves the quality of the differential signal. On the other hand, it reduces the problem of reducing the offset of the differential signal in the PCB board routing. The design requirements reduce the difficulty of wiring in the PCB board and reduce the design cost.

In some embodiments of the present disclosure, referring to FIG. 2 , if the i-th differential signal CKi is not determined to be the i+1-th differential signal CK(i+1), the offset calibration circuit 80 is also used to continue the offset calibration. , until the N-1th differential signal CK(N-1) is determined to be the Nth differential signal CKN.

It should be noted that CKi in Figure 2 can represent the first differential signal CK1 to the Nth differential signal CKN, and Fi in Figure 2 can represent the comparison results F1 to F corresponding to the first differential signal CK1 to the Nth differential signal CKN respectively. FN. In the embodiments of the present disclosure and related drawings, the label i in all the marks refers to any one of the labels 1 to N, corresponding to each signal generated in any offset calibration, which will not be described again later.

In the embodiment of the present disclosure, the i-th differential signal CKi is not determined to be the i+1-th differential signal CK(i+1), that is, the i-th differential signal CKi does not have the smallest offset when compared with the reference differential signal CKi/ , which means that further calibration is still possible under the current calibration accuracy.

Correspondingly, when the i-th differential signal CKi is not determined to be the i+1-th differential signal CK(i+1), the phase detection circuit 20 can continue to obtain the i+1-th differential signal output by the adjustable delay circuit 10 CK(i+1), perform preset delay processing on the i+1th differential signal CK(i+1) to obtain the reference differential signal CK(i+1) corresponding to the i+1th differential signal CK(i+1) / (not shown in Figure 2), and perform logical processing and comparison on the i+1th differential signal CK(i+1) and the reference differential signal CK(i+1)/ to obtain the i+1th differential signal CK (i+1) corresponds to the comparison result F(i+1). The phase adjustment control circuit 30 may determine the i-th differential signal CK(i+1)/ with the smallest offset among the i+1-th differential signal CK(i+1) and the reference differential signal CK(i+1)/ based on the comparison result F(i+1). +2 differential signal CK(i+2), and determine the third delay amount corresponding to the i+2nd differential signal CK(i+2). The adjustable delay circuit 10 is controlled by the phase adjustment control circuit to update the i+1th delay amount to the third delay amount to calibrate the initial differential signal CK0 to the i+2nd differential signal CK(i+2). By analogy, the offset calibration circuit 80 can continue to perform offset calibration until the N-1th differential signal CK(N-1) is determined to be the Nth differential signal CKN. That is to say, the offset calibration circuit 80 can continue to perform the offset calibration. Offset calibration until no further calibration is possible at the current calibration accuracy.

It can be understood that the offset calibration circuit 80 performs offset calibration multiple times in an iterative manner until no further calibration is possible. In this way, automatic detection and calibration of the phase offset of the input initial differential signal CK0 is achieved, further reducing the The error of the differential signal is reduced and the quality of the differential signal is improved.

In some embodiments of the present disclosure, referring to FIG. 4 , the phase detection circuit 20 includes: a precision configuration register 201 , a preset delay circuit 202 , an exclusive OR circuit 203 , an integration circuit 204 and a comparison circuit 205 . The output terminal of the precision configuration register 201 is electrically connected to the configuration terminal of the preset delay circuit 202 . The precision configuration register 201 is used to store the preset delay amount and send the preset delay amount to the preset delay circuit 202 . The input terminal of the preset delay circuit 202 is electrically connected to the output terminal of the adjustable delay circuit 10 . The preset delay circuit 202 is used to delay the i-th differential signal CKi according to a preset delay amount to obtain the reference differential signal CKi/. The input terminals of the NOR circuit 203 are electrically connected to the output terminals of the preset delay circuit 202 and the output terminals of the adjustable delay circuit 10 respectively. The exclusive OR circuit 203 is used to perform exclusive OR processing on the i-th differential signal CKi and the reference differential signal CKi/, respectively, to obtain multiple exclusive OR results Xi. The input terminal of the integrating circuit 204 is electrically connected to the output terminal of the OR circuit 203 . The integrating circuit 204 is used to integrate multiple XOR results Xi to obtain corresponding multiple integrated voltages Vi. The input terminal of the comparison circuit 205 is electrically connected to the output terminal of the integrating circuit 204 . The comparison circuit 205 is used to compare two of the plurality of integrated voltages Vi to obtain a comparison result Fi.

In some embodiments of the present disclosure, referring to FIG. 5 , the second output terminal of the phase adjustment control circuit 30 is electrically connected to the control terminal of the OR circuit 203 , the control terminal of the integrating circuit 204 and the control terminal of the comparison circuit 205 respectively. Phase adjustment control The circuit 30 is also used to send the enable signal En to the exclusive OR circuit 203, the integrating circuit 204 and the comparison circuit 205 to control the operation or stopping of the exclusive OR circuit 203, the integrating circuit 204 and the comparison circuit 205.

In the embodiment of the present disclosure, the phase adjustment control circuit 30 can control the exclusive OR circuit 203, the integration circuit 204 and the comparison circuit 205 to run or stop. For example, when the phase adjustment control circuit 30 sends a high-level enable signal En to the exclusive OR circuit 203, the integrating circuit 204, and the comparing circuit 205, the exclusive OR circuit 203, the integrating circuit 204, and the comparing circuit 205 remain in a running state; when The phase adjustment control circuit 30 sends the low-level enable signal En to the exclusive OR circuit 203, the integrating circuit 204, and the comparing circuit 205, and then the exclusive OR circuit 203, the integrating circuit 204, and the comparing circuit 205 remain stopped.

In some embodiments of the present disclosure, when the i-th differential signal CKi is not determined to be the i+1-th differential signal CK(i+1), that is, when further calibration can still be performed under the current calibration accuracy, the offset The shift calibration circuit 80 controls the exclusive OR circuit 203, the integrating circuit 204 and the comparing circuit 205 to keep running. When the i-th differential signal CKi is determined to be the i+1-th differential signal CK(i+1), that is, when further calibration cannot be performed under the current calibration accuracy, the offset calibration circuit 80 will control the exclusive OR circuit 203. , the integrating circuit 204 and the comparing circuit 205 are converted to a stopped state.

It can be understood that the phase adjustment control circuit 30 controls the exclusive OR circuit 203, the integrating circuit 204 and the comparison circuit 205 to keep running when further calibration is possible, and controls the exclusive OR circuit 203, 203, and the integrating circuit 204 when further calibration is impossible. The integrating circuit 204 and the comparing circuit 205 remain in a stopped state, thus avoiding invalid operation of the circuit and saving power consumption.

In some embodiments of the present disclosure, referring to FIG. 6 , the third output terminal of the phase adjustment control circuit 30 is electrically connected to the control terminal of the accuracy configuration register 201 . The phase adjustment control circuit 30 is also used to control the accuracy configuration register 201 to reduce the preset delay amount when the i-th differential signal CKi is determined to be the i+1-th differential signal CK(i+1).

In the embodiment of the present disclosure, the preset delay amount represents the accuracy of offset calibration. The smaller the preset delay amount, the smaller the change in each calibration result compared to the previous calibration result, and further, the higher the accuracy of the final calibration result. When the i-th differential signal CKi is determined to be the i+1-th differential signal CK(i+1), that is, when further calibration cannot be performed under the current calibration accuracy, the phase adjustment control circuit 30 may control the accuracy configuration register 201 to decrease The preset delay amount is small, and the NOR circuit 203, the integration circuit 204 and the comparison circuit 205 are controlled to keep running. In this way, the offset calibration circuit 80 can perform further calibration according to the reduced preset delay amount to obtain a better for accurate calibration results. For example, when the preset delay amount is 8 ns, the offset calibration circuit 80 performs offset calibration on the initial differential signal CK0 until the i-th differential signal CKi is determined to be the i+1-th differential signal CK(i+1), That means further calibration is not possible. At this time, the offset calibration circuit 80 can control the accuracy configuration register 201 to reduce the preset delay amount to 4 ns, and continue to perform offset calibration according to the reduced preset delay amount until no further calibration is possible.

In the embodiment of the present disclosure, the reduction of the preset delay amount can be performed multiple times. For example, the number of times of reduction of the preset delay amount can be set to 3. Correspondingly, if the initial differential signal CK0 reaches a situation where it cannot be further calibrated according to the preset delay amount after being reduced three times, the phase adjustment control circuit 30 can control the exclusive OR circuit 203, the integration circuit 204 and the comparison through the enable signal En. The circuit 205 switches to a stopped state, that is, ends the offset calibration of the initial differential signal CK0, and outputs the final calibration result.

It is understandable that when further calibration cannot be performed according to the accuracy of the current offset calibration, the preset delay amount is reduced, the accuracy of the offset calibration is improved, and offset calibration with higher accuracy is continued. In this way, lower-precision calibration is performed first to ensure the efficiency of the calibration, making the current calibration result closer to the final calibration result faster; and then higher-precision calibration is performed to ensure that the final calibration result is higher-precision.

FIG. 7 is an optional structural schematic diagram of an offset calibration circuit provided by an embodiment of the present disclosure. FIG. 8 and FIG. 9 are waveform diagrams of two examples of each signal in FIG. 7 .

In some embodiments of the present disclosure, in conjunction with FIGS. 6 and 7 , the initial differential signal CK0 includes an initial clock signal CK_t0 and an initial complementary clock signal CK_c0. The i-th differential signal CKi includes the i-th clock signal CK_ti and the i-th complementary clock signal CK_ci. The adjustable delay circuit 10 includes: a first delay unit D1 and a second delay unit D2.

Among them, the first delay unit D1 is used to receive the initial clock signal CK_t0 and delay the initial clock signal CK_t0. The delay is the i-th clock signal CK_ti; and the initial clock signal CK_t0 is delayed to the i+1-th clock signal CK_t(i+1). The second delay unit D2 is used to receive the initial complementary clock signal CK_c0, delay the initial complementary clock signal CK_c0 to the i-th complementary clock signal CK_ci; and, delay the initial complementary clock signal CK_c0 to the i+1 complementary clock signal CK_c(i +1).

In the embodiment of the present disclosure, the first delay unit D1 can apply a delay to the initial clock signal CK_t0, and the second delay unit D2 can apply a delay to the initial complementary clock signal CK_c0 to achieve calibration of the initial differential signal. In the i-th offset calibration, the first delay unit D1 and the second delay unit D2 first calibrate the initial differential signal CK0 according to the i-th delay amount. The i-th delay amount includes the delay corresponding to the initial clock signal CK_t0. quantity and the delay quantity corresponding to the initial complementary clock signal CK_c0. For example, the first delay unit D1 delays the initial clock signal CK_t0 by 4 ns according to the i-th delay amount to obtain the i-th clock signal CK_ti. At the same time, the second delay unit D2 delays the initial complementary clock signal CK_c0 by 6 ns according to the i-th delay amount to obtain the i-th clock signal CK_ti. i complements the clock signal CK_ci, thereby obtaining the i-th differential signal CKi.

Correspondingly, after the phase adjustment control circuit 30 determines the i+1th differential signal CK(i+1) and the corresponding i+1th delay amount, the first delay unit D1 and the second delay unit D2 first determine the i+1th differential signal CK(i+1) and the corresponding i+1th delay amount. The i+1 delay calibrates the initial differential signal CK0 to obtain the i+1th differential signal CK(i+1). Since the i+1 differential signal CK(i+1) is obtained based on the i-th differential signal CKi, therefore, based on the i-th delay amount stored in the first delay unit D1 and the second delay unit D2 By superimposing the change values, the i-th delay amount is updated to the i+1-th delay amount. For example, comparing the i+1 differential signal CK(i+1) with the i differential signal CKi, the i+1 clock signal CK_t(i+1) is delayed by 2ns from the i clock signal CK_ti. There is no delay between the complementary clock signal CK_c(i+1) and the i-th complementary clock signal CK_ci, so you only need to add another 2ns to the delay setting of the first delay unit D1, while the delay setting of the second delay unit D2 remains unchanged. In this way, Then, the i-th delay amount stored in the first delay unit D1 and the second delay unit D2 can be updated to the i+1-th delay amount.

In some embodiments of the present disclosure, with reference to FIGS. 6 and 7 , the reference differential signal CKi/ includes: a first reference differential signal CKi_T/ and a second reference differential signal CKi_C/. The preset delay circuit 202 includes: a third delay unit D3 and a fourth delay unit D4.

The input terminal of the third delay unit D3 is electrically connected to the output terminal of the first delay unit D1. The third delay unit D3 is used to delay the i-th clock signal CK_ti into a clock reference signal CK_ti+ according to a preset delay amount; the clock reference signal CK_ti+ and the i-th complementary clock signal CK_ci constitute the first reference differential signal CKi_T/. The input terminal of the fourth delay unit D4 is electrically connected to the output terminal of the second delay unit D2. The fourth delay unit D4 is used to delay the i-th complementary clock signal CK_ci into a complementary clock reference signal CK_ci+ according to a preset delay amount; the i-th clock signal CK_ti and the complementary clock reference signal CK_ci+ form the second reference differential signal CKi_C/.

In the embodiment of the present disclosure, referring to FIG. 8 or FIG. 9 , the i-th clock signal CK_ti is delayed to be the clock reference signal CK_ti+, and the i-th complementary clock signal CK_ci is delayed to be the complementary clock reference signal CK_ci+. Compared with the i-th differential signal CKi, the first reference differential signal CKi_T/ composed of the clock reference signal CK_ti+ and the i-th complementary clock signal CK_ci only delays the i-th clock signal CK_ti in the i-th differential signal CKi, and is composed of the i-th complementary clock signal CK_ci. The second reference differential signal CKi_C/ composed of the clock signal CK_ti and the complementary clock reference signal CK_ci+ only delays the i-th complementary clock signal CK_ci in the i-th differential signal CKi. In this way, the i-th differential signal CKi can be compared with the two differential signals (the first reference differential signal CKi_T/ and the second reference differential signal CKi_C/) that are offset in different directions, so as to determine in this offset calibration produce appropriate calibration results.

In some embodiments of the present disclosure, in conjunction with FIG. 6 and FIG. 7 , the XOR circuit 203 includes: a first XOR gate Xnor1, a second XOR gate Xnor2, and a third XOR gate Xnor3.

The input terminal of the first NOR gate Xnor1 is electrically connected to the output terminal of the second delay unit D2 and the output terminal of the third delay unit D3 respectively. The first XOR gate Xnor1 is used to perform XOR processing on the first reference differential signal CKi_T/ (that is, the clock reference signal CK_ti+ and the i-th complementary clock signal CK_ci) to obtain the first XOR result Xi_1. The input terminals of the second NOR gate Xnor2 are electrically connected to the output terminals of the first delay unit D1 and the output terminals of the second delay unit D2 respectively. The second NOR gate Perform identical-OR processing to obtain the second identical-OR result Xi_2. The input terminals of the third NOR gate Xnor3 are electrically connected to the output terminals of the first delay unit D1 and the output terminals of the fourth delay unit D4 respectively. The third XOR gate Xnor3 is used to perform XOR processing on the second reference differential signal CKi_C/ (that is, the i-th clock signal CK_ti and the complementary clock reference signal CK_ci+) to obtain the third XOR result Xi_3.

In the embodiment of the present disclosure, refer to FIG. 8 or FIG. 9 , which illustrates the waveforms of the first TIN-OR result Xi_1, the second TIN-OR result Xi_2, and the third TIN-OR result Xi_3. It should be noted that the exclusive OR logic operation is "1" (that is, high level) when the levels of the two input signals are the same, and is "0" (that is, low level) when the levels of the two input signals are different. level).

Since under ideal conditions, the two signals in the differential signal are mutually inverted, if the two mutually inverted signals are XORed, the output result will always be "0" (that is, it will always be low level) . It can be understood that among the first XOR result Xi_1, the second XOR result Xi_2 and the third XOR result Xi_3, the signal with the smallest proportion of high levels is closest to the XOR result obtained by the ideal differential signal.

It can be understood that the characteristics of the exclusive OR logic operation are used to determine the area where the levels of the two signals of the differential signal are equal. At the same time, due to the ideal differential signal, there is no area of equal levels between the two signals. Therefore, the differential signal closest to the ideal state can be determined by the XOR result.

In some embodiments of the present disclosure, with reference to FIGS. 6 and 7 , the integration circuit 204 includes: a first integration unit In1 , a second integration unit In2 , and a third integration unit In3 . The input terminal of the first integrating unit In1 is electrically connected to the output terminal of the first XOR gate Xnor1. The first integrating unit In1 is used to integrate the first XOR result Xi_1 to obtain the first integrated voltage Vi_1. The input terminal of the second integrating unit In2 is electrically connected to the output terminal of the second XOR gate Xnor2. The second integrating unit In2 is used to integrate the second XOR result Xi_2 to obtain the second integrated voltage Vi_2. The input terminal of the third integrating unit In3 is electrically connected to the output terminal of the third XOR gate Xnor3. The third integrating unit In3 is used to integrate the third XOR result Xi_3 to obtain the third integrated voltage Vi_3.

In the embodiment of the present disclosure, referring to Figure 8 or Figure 9, the magnitude of the integrated voltage is equal to the definite integral of the same-OR result within one cycle. For example, the first TIN-OR result Xi_1 shown in Figure 8 has 0.3 cycles of high-level VDD and 0.6 cycles of low-level VSS in one cycle, then the first T-OR result Xi_1 is within one cycle. The definite integral is 0.3VDD+0.6VSS. Since the low level VSS can be considered as 0, the first integral voltage Vi_1 is 0.3VDD. It can be seen that the size of the integrated voltage reflects the proportion of high levels in its corresponding same-OR result. For example, the first integrated voltage Vi_1 in Figure 8 is 0.3VDD, indicating that there are 0.3 cycles are high level.

Similarly, in Figure 8, the second integrated voltage Vi_2 is 0.2VDD, indicating that the second T-OR result Xi_2 has 0.2 periods of high level in one cycle; the third integrated voltage Vi_3 is 0.1VDD, indicating that the third T-OR result Xi_2 is high level. Or the result is that Xi_3 is high level for 0.1 cycles in one cycle. In Figure 9, the first integrated voltage Vi_1 is 0.1VDD, indicating that the first TIN-OR result Xi_1 has 0.1 periods of high level in one cycle; the second integrated voltage Vi_2 is 0.2VDD, indicating that the second TIN-OR result Xi_2 has a high level for 0.2 cycles in one cycle; the third integrated voltage Vi_3 is 0.3VDD, which means that the third TOR result Xi_3 has a high level for 0.3 cycles in a cycle.

It can be understood that processing the AND result as an integrated voltage makes it easier to process and compare later. Since the size of the integrated voltage reflects the proportion of high levels, that is, the proportion of areas with equal levels in the corresponding differential signal, the proportion of areas with equal levels can be determined by processing the integrated voltage. The smallest differential signal is the differential signal closest to the ideal state.

In some embodiments of the present disclosure, in conjunction with FIGS. 6 and 7 , the comparison circuit 205 includes: a first comparator A1 and a second comparator A2. The comparison result Fi includes: a first comparison result Fi_1 and a second comparison result Fi_2. The first input terminal of the first comparator A1 is electrically connected to the output terminal of the second integrating unit In2, and the second input terminal of the first comparator A1 is electrically connected to the output terminal of the first integrating unit In1. The first comparator A1 is used to compare the first integrated voltage Vi_1 and the second integrated voltage Vi_2 to obtain the first comparison result Fi_1. The first input terminal of the second comparator A2 is electrically connected to the output terminal of the second integrating unit In2, and the second input terminal of the second comparator A2 is electrically connected to the output terminal of the third integrating unit In3. The second comparator A2 is used to compare the second integrated voltage Vi_2 and the third integrated voltage Vi_3 to obtain a second comparison result Fi_2.

In the embodiment of the present disclosure, since the magnitude of the integrated voltage reflects the proportion of high levels in its corresponding identical-OR results, the magnitude of each integrated voltage is compared, that is, the proportion of high levels in each identical-OR result is compared. Than compare. Since the EXOR result obtained from the differential signal has a smaller proportion of high levels, the closer it is to the ideal EXOR result obtained from the differential signal. Therefore, by comparing the proportion of high levels in each EXOR result, we can Determine the differential signal that is closest to the ideal.

In the embodiment of the present disclosure, referring to Figure 7, the second integrated voltage Vi_2 is transmitted to the first input terminal of the first comparator A1 and the first input terminal of the second comparator, and the first integrated voltage Vi_1 is transmitted to the first comparator A1. The third integrated voltage Vi_3 is transmitted to the second input terminal of the second comparator A2 through the second input terminal of the comparator A1.

Combining Figures 7 and 8, in Figure 8, since the second integrated voltage Vi_2 is less than the first integrated voltage Vi_1, the first comparator A1 outputs the first comparison result Fi_1 as "0"; accordingly, since the second integrated voltage Vi_2 is greater than the third integrated voltage Vi_3, so the second comparator A2 outputs the second comparison result Fi_2 as “1”.

Combining Figures 7 and 9, in Figure 9, since the second integrated voltage Vi_2 is greater than the first integrated voltage Vi_1, the first comparator A1 outputs the first comparison result Fi_1 as "1"; accordingly, since the second integrated voltage Vi_2 is smaller than the third integrated voltage Vi_3, so the second comparator A2 outputs the second comparison result Fi_2 as “0”.

It can be understood that since the magnitude of the integrated voltage reflects the proportion of high levels, that is, the proportion of equal level areas in the corresponding differential signal, therefore, by comparing the integrated voltages, the value of each integrated voltage is determined. In this way, the differential signal with the smallest proportion of the area with equal levels can be determined, that is, the differential signal closest to the ideal state can be determined.

In some embodiments of the present disclosure, in conjunction with FIG. 6 and FIG. 7 , the phase adjustment control circuit 30 is also used to receive the first comparison result Fi_1 and the second comparison result Fi_2. Based on the first comparison result Fi_1 and the second comparison result Fi_2, The minimum value among the first integrated voltage Vi_1, the second integrated voltage Vi_2 and the third integrated voltage Vi_3 is determined, thereby determining the i+1th differential signal corresponding to the minimum value.

In the embodiment of the present disclosure, combined with FIG. 7 and FIG. 8 , if the first comparison result Fi_1 is “0” and the second comparison result Fi_2 is “1”, the phase adjustment control circuit 30 can determine that the second integrated voltage Vi_2 is less than The first integrated voltage Vi_1, and the second integrated voltage Vi_2 is greater than the third integrated voltage Vi_3, that is, the third integrated voltage Vi_3 is the minimum integrated voltage. Therefore, the phase adjustment control circuit 30 can determine the second integrated voltage corresponding to the third integrated voltage Vi_3. The reference differential signal CKi_C/ is the i+1th differential signal CK(i+1).

7 and 9 , if the first comparison result Fi_1 is “1” and the second comparison result Fi_2 is “0”, the phase adjustment control circuit 30 can determine that the second integrated voltage Vi_2 is greater than the first integrated voltage Vi_1, And the second integrated voltage Vi_2 is smaller than the third integrated voltage Vi_3, that is, the first integrated voltage Vi_1 is the minimum integrated voltage. Therefore, the phase adjustment control circuit 30 can determine that the first reference differential signal CKi_T/ corresponding to the first integrated voltage Vi_1 is The i+1th differential signal CK(i+1).

Correspondingly, if the first comparison result Fi_1 is “0” and the second comparison result Fi_2 is also “0”, the phase adjustment control circuit 30 can determine that the second integrated voltage Vi_2 is less than the first integrated voltage Vi_1, and the second integrated voltage Vi_2 is smaller than the first integrated voltage Vi_1. The integrated voltage Vi_2 is smaller than the third integrated voltage Vi_3, that is, the second integrated voltage Vi_2 is the minimum integrated voltage. Therefore, the phase adjustment control circuit 30 can determine that the i-th differential signal CKi corresponding to the second integrated voltage Vi_1 is the i+1-th differential signal. Signal CK(i+1).

It should be noted that in actual use, the two signals in the i-th differential signal Cki will not be almost in phase. Therefore, the second integrated voltage Vi_2 corresponding to the i-th differential signal Cki will not be the first integrated voltage. In the case of the maximum value among Vi_1, the second integrated voltage Vi_2 and the third integrated voltage Vi_3, that is, the first comparison result Fi_1 is “1” and the second comparison result Fi_2 is also “1”.

It can be understood that since the size of the integrated voltage reflects the proportion of high levels, that is, the proportion of areas with equal levels in the corresponding differential signal, therefore, determining the minimum integrated voltage determines the level. The differential signal with the smallest proportion of equal areas determines the differential signal closest to the ideal state.

In some embodiments of the present disclosure, referring to FIG. 7 , the phase adjustment control circuit 30 is also used to determine that the first reference differential signal CKi_T/ (ie, the clock reference signal CK_ti+ and the i-th complementary clock signal CK_ci) is the i+1 Differential signaling CK(i+1), then send the first update instruction to the first delay unit D1 to update the i-th delay amount to the i+1-th delay amount.

In the embodiment of the present disclosure, if it is determined that the first reference differential signal CKi_T/ is the i+1th differential signal CK(i+1), the phase adjustment control circuit 30 will control the first delay unit D1 through the first update command so that the A delay unit D1 adds the delay amount configured on the third delay unit D3 to its current delay amount. In this way, the i-th delay amount in the adjustable delay circuit 10 is updated to the i+1-th delay amount, the first delay unit D1 can delay the initial clock signal CK_t0 to the clock reference signal CK_ti+, and the second delay unit D2 will still be the initial complementary signal. The clock signal CK_c0 is delayed to the i-th complementary clock signal CK_ci, that is, the i-th delay amount in the adjustable delay circuit 10 is updated to the i+1-th delay amount, and the adjustable delay circuit 10 outputs the i+1-th differential signal CK(i +1).

In some embodiments of the present disclosure, referring to FIG. 7 , the phase adjustment control circuit 30 is also used to determine that the second reference differential signal Cki_C/ (ie, the i-th clock signal CK_ti and the complementary clock reference signal CK_ci+) is the i+1-th differential signal, then send a second update instruction to the second delay unit D2 to update the i-th delay amount to the i+1-th delay amount.

In the embodiment of the present disclosure, if it is determined that the second reference differential signal Cki_C/ is the i+1th differential signal, the phase adjustment control circuit 30 will control the second delay unit D2 through the second update command, so that the second delay unit D2 is in its The delay amount configured on the fourth delay unit D4 is added to the current delay amount. In this way, the i-th delay amount in the adjustable delay circuit 10 is updated to the i+1-th delay amount, the second delay unit D2 can delay the initial complementary clock signal CK_c0 to the complementary clock reference signal CK_ci+, while the first delay unit D1 will still The initial complementary clock signal CK_t0 is delayed to the i-th clock signal CK_ti, that is, the i-th delay amount in the adjustable delay circuit 10 is updated to the i+1-th delay amount, and the adjustable delay circuit 10 outputs the i+1-th differential signal CK ( i+1).

In some embodiments of the present disclosure, the phase adjustment control circuit 30 in FIG. 7 may perform the process shown in FIG. 10 .

7 and 10 , after receiving the first comparison result Fi_1 and the second comparison result Fi_2, the phase adjustment control circuit 30 may first determine whether the first comparison result Fi_1 and the second comparison result Fi_2 are equal. If the first comparison result Fi_1 and the second comparison result Fi_2 are equal, the first comparison result Fi_1 is "0", and the second comparison result Fi_2 is also "0", that is, the second integrated voltage Vi_2 is the minimum integrated voltage, and the The i-th differential signal CKi corresponding to the two integrated voltages Vi_1 is the i+1-th differential signal CK(i+1). In this way, the phase adjustment control circuit 30 will control the first delay unit D1 and the second delay unit D2 not to adjust. The delay circuit 10 still outputs the i-th differential signal CKi.

If the first comparison result Fi_1 and the second comparison result Fi_2 are not equal, the phase adjustment control circuit 30 will determine whether the first comparison result Fi_1 is “1”. If the first comparison result Fi_1 is "1", then the second comparison result Fi_2 is "0", then the first integrated voltage Vi_1 is the minimum integrated voltage, and the first reference differential signal CKi_T/ corresponding to the first integrated voltage Vi_1 is The i+1 differential signal CK(i+1), in this way, the phase adjustment control circuit 30 will control the first delay unit D1 to adjust, so that the first delay unit D1 increases its current delay amount by the amount of the third delay unit D3. According to the configured delay amount, the adjustable delay circuit 10 outputs the first reference differential signal CKi_T/. If the first comparison result Fi_1 is "0", then the second comparison result Fi_2 is "1", then the third integrated voltage Vi_3 is the minimum integrated voltage, and the second reference differential signal CKi_C/ corresponding to the third integrated voltage Vi_3 is The i+1 differential signal CK(i+1), in this way, the phase adjustment control circuit 30 will control the second delay unit D2 to adjust, so that the second delay unit D2 increases its current delay amount by the amount of the fourth delay unit D4. According to the configured delay amount, the adjustable delay circuit 10 outputs the second reference differential signal CKi_C/.

It can be understood that the phase adjustment control circuit 30 sends instructions to the first delay unit D1 or the second delay unit D2 in a targeted manner according to the comparison result of the integrated voltage, and controls the first delay unit D1 or the second delay unit D2 to perform the corresponding operation. In this way, the delay amount of the adjustable delay circuit 10 is updated with fewer instructions and adjustment amounts, which saves power consumption and improves efficiency.

FIG. 11 is an optional structural schematic diagram of a memory provided by an embodiment of the present disclosure. As shown in FIG. 11 , the memory 90 includes the offset calibration circuit 80 provided by the above embodiment.

In some embodiments of the present disclosure, referring to Figure 11, memory 90 is dynamic random access memory DRAM.

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, and also includes other elements not expressly listed or included for such process, method, article or apparatus. inherent elements. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide an offset calibration circuit and a memory. The offset calibration circuit includes: an adjustable delay circuit, a phase detection circuit and a phase adjustment control circuit. Among them, the adjustable delay circuit is used to receive the initial differential signal and calibrate the initial differential signal to the i-th differential signal according to the i-th delay amount; i is greater than or equal to 1. A phase detection circuit, the input end of which is electrically connected to the output end of the adjustable delay circuit, is used to perform preset delay processing on the i-th differential signal to obtain a reference differential signal, and perform logical processing and summation on the i-th differential signal and the reference differential signal. Compare and get the comparison results. A phase adjustment control circuit, the input end of which is electrically connected to the output end of the phase detection circuit, and the first output end of which is electrically connected to the control end of the adjustable delay circuit, for determining the i-th differential signal and the reference differential signal based on the comparison result. The i+1th differential signal with the smallest offset is determined, and the i+1th delay corresponding to the i+1th differential signal is determined. The adjustable delay circuit is also used, controlled by the phase adjustment control circuit, to update the i-th delay amount to the i+1-th delay amount, so as to calibrate the initial differential signal to the i+1-th differential signal. It can be understood that the offset calibration circuit can update the calibration result from the i-th differential signal to the i+1-th differential signal with a smaller offset, thereby realizing automatic detection of the phase offset of the input initial differential signal CK0. and calibration, in this way, on the one hand, it reduces the error of the differential signal and improves the quality of the differential signal. On the other hand, it reduces the design requirements for reducing the offset of the differential signal in the PCB board routing, reducing the PCB board The difficulty of routing traces reduces design costs.

Claims (15)

1. An offset calibration circuit (80), the offset calibration circuit (80) includes: an adjustable delay circuit (10), a phase detection circuit (20) and a phase adjustment control circuit (30);

   The adjustable delay circuit (10) is used to receive an initial differential signal and calibrate the initial differential signal to the i-th differential signal according to the i-th delay amount; i is greater than or equal to 1;

   The input end of the phase detection circuit (20) is electrically connected to the output end of the adjustable delay circuit (10), and is used to perform preset delay processing on the i-th differential signal to obtain a reference differential signal, and to The i-th differential signal and the reference differential signal are logically processed and compared to obtain a comparison result;

   The input terminal of the phase adjustment control circuit (30) is electrically connected to the output terminal of the phase detection circuit (20), and its first output terminal is electrically connected to the control terminal of the adjustable delay circuit (10). As a result of the comparison, the i+1th differential signal with the smallest offset is determined among the ith differential signal and the reference differential signal, and the i+1th differential signal corresponding to the i+1th differential signal is determined. amount of delay;

   The adjustable delay circuit (10) is also used to update the i-th delay amount to the i+1-th delay amount, controlled by the phase adjustment control circuit (30), so as to change the initial difference The signal is calibrated to the i+1th differential signal.
2. The offset calibration circuit (80) of claim 1, wherein:

   If the i-th differential signal is not determined to be the i+1-th differential signal, the offset calibration circuit (80) is also used to continue offset calibration until the N-1-th differential signal is determined to be the i-th differential signal. N differential signal.
3. The offset calibration circuit (80) according to claim 1 or 2, wherein the phase detection circuit (20) includes: a precision configuration register (201), a preset delay circuit (202), and an exclusive OR circuit (203) , integrating circuit (204) and comparison circuit (205);

   The output terminal of the precision configuration register (201) is electrically connected to the configuration terminal of the preset delay circuit (202), and is used to store the preset delay amount and send the preset delay amount to the preset delay amount. circuit(202);

   The input terminal of the preset delay circuit (202) is electrically connected to the output terminal of the adjustable delay circuit (10), and is used to delay the i-th differential signal according to the preset delay amount to obtain the desired Described with reference to differential signals;

   The input terminals of the XOR circuit (203) are electrically connected to the output terminals of the preset delay circuit (202) and the output terminals of the adjustable delay circuit (10) respectively, for processing the i-th differential signal. Perform exclusive OR processing with the reference differential signal respectively to obtain multiple exclusive OR results;

   The input terminal of the integrating circuit (204) is electrically connected to the output terminal of the XOR circuit (203), and is used for integrating multiple XOR results to obtain corresponding multiple integrated voltages;

   The input terminal of the comparison circuit (205) is electrically connected to the output terminal of the integrating circuit (204), and is used to compare two of the plurality of integrated voltages to obtain the comparison result.
4. The offset calibration circuit (80) of claim 3, wherein:

   The second output terminal of the phase adjustment control circuit (30) is electrically connected to the control terminal of the XOR circuit (203), the control terminal of the integrating circuit (204) and the control terminal of the comparison circuit (205) respectively. ;

   The phase adjustment control circuit (30) is also used to send an enable signal to the exclusive OR circuit (203), the integrating circuit (204) and the comparison circuit (205) to control the exclusive OR circuit. (203), the integrating circuit (204) and the comparing circuit (205) run or stop.
5. The offset calibration circuit (80) according to claim 3 or 4, wherein the third output terminal of the phase adjustment control circuit (30) is electrically connected to the control terminal of the precision configuration register (201);

   The phase adjustment control circuit (30) is also used to control the accuracy configuration register (201) to reduce the preset value when the i-th differential signal is determined to be the i+1-th differential signal. Amount of delay.
6. The offset calibration circuit (80) according to any one of claims 3 to 5, wherein the initial differential signal includes an initial clock signal and an initial complementary clock signal; the i-th differential signal includes an i-th clock signal and an i-th clock signal. i complementary clock signal; the adjustable delay circuit (10) includes: a first delay unit (D1) and a second delay unit (D2);

   The first delay unit (D1) is used to receive the initial clock signal, delay the initial clock signal to the i-th clock signal; and delay the initial clock signal to the i+1-th clock signal;

   The second delay unit (D2) is used to receive the initial complementary clock signal, delay the initial complementary clock signal to the i-th complementary clock signal; and delay the initial complementary clock signal to the i+1-th complementary clock signal. Complementary clock signals.
7. The offset calibration circuit (80) according to claim 6, wherein the reference differential signal includes: a first reference differential signal and a second reference differential signal; the preset delay circuit (202) includes: a third delay unit (D3) and the fourth delay unit (D4);

   The input terminal of the third delay unit (D3) is electrically connected to the output terminal of the first delay unit (D1), and is used to delay the i-th clock signal into a clock reference signal according to the preset delay amount; The clock reference signal and the i-th complementary clock signal constitute the first reference differential signal;

   The input terminal of the fourth delay unit (D4) is electrically connected to the output terminal of the second delay unit (D2), and is used to delay the i-th complementary clock signal into a complementary clock reference according to the preset delay amount. signal; the i-th clock signal and the complementary clock reference signal constitute the second reference differential signal.
8. The offset calibration circuit (80) according to claim 7, wherein the XOR circuit (203) includes: a first XOR gate (Xnor1), a second XOR gate (Xnor2) and a third XOR gate (Xnor3);

   The input terminals of the first NOR gate (Xnor1) are electrically connected to the output terminals of the second delay unit (D2) and the output terminal of the third delay unit (D3) respectively, and are used to control the first Perform exclusive OR processing with reference to the differential signal to obtain the first exclusive OR result;

   The input terminal of the second NOR gate (Xnor2) is electrically connected to the output terminal of the first delay unit (D1) and the output terminal of the second delay unit (D2) respectively, and is used to control the i-th The differential signals are subjected to XOR processing to obtain the second XOR result;

   The input terminals of the third NOR gate (Xnor3) are electrically connected to the output terminals of the first delay unit (D1) and the output terminals of the fourth delay unit (D4) respectively, and are used to control the second Perform XOR processing with reference to the differential signal to obtain the third XOR result.
9. The offset calibration circuit (80) according to claim 8, wherein the integrating circuit (204) includes: a first integrating unit (In1), a second integrating unit (In2) and a third integrating unit (In3);

   The input terminal of the first integrating unit (In1) is electrically connected to the output terminal of the first XOR gate (Xnor1), and is used for integrating the first XOR result to obtain a first integrated voltage;

   The input terminal of the second integrating unit (In2) is electrically connected to the output terminal of the second exclusive OR gate (Xnor2), and is used for integrating the second exclusive OR result to obtain a second integrated voltage;

   The input terminal of the third integrating unit (In3) is electrically connected to the output terminal of the third XOR gate (Xnor3), and is used for integrating the third XOR result to obtain a third integrated voltage.
10. The offset calibration circuit (80) according to claim 9, wherein the comparison circuit (205) includes: a first comparator (A1) and a second comparator (A2); the comparison result includes: a first comparator (A1) and a second comparator (A2); The comparison result and the second comparison result;

    The first comparator (A1) has a first input terminal electrically connected to the output terminal of the second integrating unit (In2), and a second input terminal electrically connected to the output terminal of the first integrating unit (In1), Used to compare the first integrated voltage and the second integrated voltage to obtain the first comparison result;

    The second comparator (A2) has a first input terminal electrically connected to the output terminal of the second integrating unit (In2), and a second input terminal electrically connected to the output terminal of the third integrating unit (In3), Used to compare the second integrated voltage and the third integrated voltage to obtain the second comparison result.
11. The offset calibration circuit (80) according to claim 10, wherein the phase adjustment control circuit (30) is further configured to receive the first comparison result and the second comparison result, based on the first comparison result. Compare the result and the second comparison result to determine the minimum value among the first integrated voltage, the second integrated voltage and the third integrated voltage, thereby determining the i-th value corresponding to the minimum value. +1 for differential signaling.
12. The offset calibration circuit (80) according to claim 10 or 11, wherein the phase adjustment control circuit (30) is further configured to: if it is determined that the first reference differential signal is the i+1th differential signal signal, a first update instruction is sent to the first delay unit (D1) to update the i-th delay amount to the i+1-th delay amount.
13. The offset calibration circuit (80) according to any one of claims 10 to 12, wherein the phase adjustment control circuit (30) is further configured to: if it is determined that the second reference differential signal is the i-th +1 differential signal, then send a second update instruction to the second delay unit (D2) to update the i-th delay amount to the i+1-th delay amount.
14. A memory (90) comprising the offset calibration circuit (80) according to any one of claims 1 to 13.
15. The memory (90) of claim 14, wherein the memory (90) is a dynamic random access memory (DRAM).