WO2024031769A9

WO2024031769A9 - Semiconductor structure and manufacturing method for semiconductor structure

Info

Publication number: WO2024031769A9
Application number: PCT/CN2022/117386
Authority: WO
Inventors: 庄凌艺; 吕开敏
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-10
Filing date: 2022-09-06
Publication date: 2024-04-04
Also published as: WO2024031769A1; CN117673013A

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method for the semiconductor structure. The semiconductor structure comprises: a substrate; an interposer soldered on the upper surface of the substrate; a power management chip soldered on the upper surface of the interposer; and a storage module located on the upper surface of the interposer, wherein the storage module comprises a plurality of storage chips stacked in a first direction, and the first direction is parallel to the upper surface of the interposer; each storage chip is internally provided with a power supply signal line, one of the plurality of storage chips is provided with at least a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; and the power management chip is further electrically connected to the power supply wiring layer. According to the embodiments of the present disclosure, at least the power consumption of the semiconductor structure can be reduced, and the integration level of the semiconductor structure can be improved.

Description

Semiconductor structure and method for manufacturing semiconductor structure

cross reference

This application refers to Chinese Patent Application No. 202210956447.0, filed on August 10, 2022, entitled “Semiconductor Structure and Method for Manufacturing Semiconductor Structure,” which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure belongs to the field of semiconductors, and in particular relates to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background technique

HBM (High Bandwidth Memory) is a new type of memory. The memory chip stacking technology represented by HBM expands the original one-dimensional memory layout to three dimensions, that is, stacking and packaging many memory chips together, thereby greatly improving the density of memory chips and achieving large capacity and high bandwidth.

However, HBM system power consumption is high and its integration level needs to be improved.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure, which are at least beneficial to reducing the power consumption of the semiconductor structure and improving the integration of the semiconductor structure.

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate; an interposer, welded on the upper surface of the substrate; a power management chip, welded on the upper surface of the interposer; a storage module, located on the upper surface of the interposer; the storage module includes a plurality of storage chips stacked along a first direction, and the first direction is parallel to the upper surface of the interposer; each of the storage chips has a power supply signal line, and one of the plurality of storage chips has at least a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; the power management chip is also electrically connected to the power supply wiring layer.

According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, the manufacturing method comprising: providing a storage module, the storage module comprising a plurality of storage chips stacked along a first direction, each of the storage chips having a power supply signal line, one of the plurality of storage chips having at least a power supply wiring layer, the power supply wiring layer being electrically connected to the power supply signal line; providing an interposer and a power management chip; welding the storage module and the power management chip on the interposer, and making the first direction parallel to the upper surface of the interposer; electrically connecting the power supply wiring layer to the power management chip; providing a substrate, and welding the interposer on the substrate.

The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the power management chip and the storage module are packaged in a system-level manner, thereby increasing the integration level, facilitating power management, and reducing system power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

FIG1 shows a schematic diagram of a semiconductor structure;

2-3, 5 and 7 respectively show cross-sectional views of different semiconductor structures provided in an embodiment of the present disclosure;

FIG4 , FIG6 , and FIG8 respectively show partial top views of different semiconductor structures provided by an embodiment of the present disclosure;

FIG9 is a schematic diagram showing an active surface of a memory chip provided by an embodiment of the present disclosure;

10 to 12 respectively show schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

Detailed ways

Referring to FIG1 , the arrangement direction of the multiple memory chips 200 in the HBM is perpendicular to the upper surface of the substrate 300, that is, the front or back of the memory chip 200 faces the logic chip 400. A power supply signal line (not shown in the figure) is led out from the front or back of the memory chip 200, and the power supply signal line establishes an electrical connection with the logic chip 400 through conductive structures such as conductive through holes and bonding parts; the logic chip 400 is electrically connected to the substrate 300, and the substrate 300 is electrically connected to the power management chip (not shown in the figure), thereby realizing the electrical connection between the memory chip 200 and the power management chip. However, the memory chip 200 and the power management chip are located in different packaging structures, and the distance between the two is relatively far, so the system power consumption is relatively large, and the integration of the semiconductor structure is relatively low.

The disclosed embodiment provides a semiconductor structure, in which a power management chip and a storage module are simultaneously welded on an interposer, and the interposer is welded on a substrate, that is, the power management chip and the storage module are located in the same packaging structure, and the integration is high. In addition, the power supply wiring layer of the storage chip does not need to be electrically connected to the power management chip through the substrate, which is conducive to shortening the wired power supply path to reduce power consumption.

The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

As shown in Figures 2 to 9, an embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate 92; an interposer 91, welded on the upper surface of the substrate 92; a power management chip 6, welded on the upper surface of the interposer 91; a storage module 100, located on the upper surface of the interposer 91; the storage module 100 includes a plurality of storage chips 1 stacked along a first direction X, and the first direction X is parallel to the upper surface of the interposer 91; each storage chip 1 has a power supply signal line 12, and one of the plurality of storage chips 1 has at least a power supply wiring layer 2, which is electrically connected to the power supply signal line 12; the power management chip 6 is also electrically connected to the power supply wiring layer 2.

That is, the power management chip 6 and the storage module 100 can be integrated into the same packaging structure to achieve system-level packaging, thereby increasing the integration. In addition, since the power management chip 6 and the storage module 100 are closer, it is beneficial to power management and reduce system power consumption.

It is worth noting that the multiple memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the multiple memory chips 1 is parallel to the substrate 92. Therefore, the side surface of the memory chip 1 faces the substrate 92. Since the area of the side surface of the memory chip 1 is small, the area of the upper surface of the substrate 92 occupied by the memory chip 1 is small, so more sufficient space can be provided for the power management chip 6 and the connection structure between the power management chip 6 and the memory chip 1, which is conducive to the realization of system-level packaging.

The semiconductor structure will be described in detail below with reference to the accompanying drawings.

First, it should be noted that the semiconductor structure has a first direction X, a second direction Y and a third direction Z. The first direction X is the stacking direction of the memory chip 1; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the substrate 92; and the third direction Z is perpendicular to the upper surface of the substrate 92.

Referring to Figures 2-3, 5 and 7, multiple memory chips 1 can be stacked in a hybrid bonding manner. For example, the surface of the memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together by molecular forces and other forces. In addition, the surface of the memory chip 1 can also have a bonding portion 42, and under elevated temperature conditions, adjacent bonding portions 42 are bonded together. In other words, the dielectric layer 43 is an insulating material that can play an isolation role; the bonding portion 42 is a conductive material that can play an electrical connection role. In addition, the dielectric layer 43 also exposes the end face 14 of the power supply wiring layer 2 facing away from the substrate 92, and covers the surface of the power supply wiring layer 2 except the end face 14.

The memory chip 1 may be a chip such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random-Access Memory). In some embodiments, adjacent memory chips 1 may be stacked front to back, which is beneficial to unify the bonding steps of the memory chip 1 and simplify the production process. In some embodiments, the stacking of adjacent memory chips 1 may also include front to front, or back to back. In some embodiments, the front of the memory chip 1 may also be understood as the active surface 13, and the back of the memory chip 1 may be understood as the non-active surface opposite to the active surface 13.

In some embodiments, there are two storage modules 100, so the storage capacity is larger and the integration is higher. The two storage modules 100 are respectively located on opposite sides of the power management chip 6, and the storage modules 100 and the power management chip 6 are arranged in the first direction X. That is, the opposite sides of the power management chip 6 can provide sufficient connection positions for the storage module 100, making the connection process simpler. In other embodiments, there can also be only one storage module 100.

2 to 8 , the semiconductor structure further includes: a lead frame 7, which is electrically connected between the power supply wiring layer 2 and the power management chip 6, and the power management chip 6 performs power management on the storage module 100 through the lead frame 7. The lead frame 7 has high strength and is not easily deformed, so that the direction of the wired power supply path can be standardized.

The lead frame 7 will be described in detail below.

Referring to FIGS. 2-3, 5 and 7, the lead frame 7 includes: a first frame 71, a second frame 72 and a third frame 73 connected in sequence; the first frame 71 and the third frame 73 both extend in the first direction X, the first frame 71 extends toward the storage module 100 relative to the second frame 72; the third frame 73 extends toward the power management chip 6 relative to the second frame 72. That is, the cross-sectional areas of the first frame 71 and the third frame 73 are greater than the cross-sectional area of the second frame 72, and the aforementioned cross-sections are parallel to the upper surface of the interposer 91.

The first frame 71 can reduce the distance between the storage module 100 and the lead frame 7, and the third frame 73 can reduce the distance between the power management chip 6 and the lead frame 7. In addition, the first frame 71 can provide more sufficient connection positions for the power supply wiring layer 2, and the third frame 73 can provide more sufficient connection positions for the power management chip 6, thereby reducing the difficulty of connection and improving the flexibility of connection.

FIG4, FIG6 and FIG8 are partial top views of different semiconductor structures, respectively, and FIG4 corresponds to the semiconductor structure shown in FIG2 and FIG3, FIG6 corresponds to the semiconductor structure shown in FIG5, and FIG8 corresponds to the semiconductor structure shown in FIG7. Referring to FIG4, FIG6 and FIG8, there are multiple lead frames 7, and the multiple lead frames 7 are arranged in the second direction Y; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the interposer 91; each power supply wiring layer 2 includes multiple power supply wirings 20 with different voltages; different lead frames 7 are electrically connected to the power supply wirings 20 with different voltages. That is, the power management chip 6 can provide different voltage signals to the storage module 100 through different lead frames 7.

For example, the lead frame 7 includes a ground lead frame 7G and a power lead frame 7P; the ground lead frame 7G and the power lead frame 7P are alternately arranged in the second direction Y. In this way, electromagnetic interference between adjacent lead frames 7 is reduced.

In some embodiments, the plurality of lead frames 7 are arranged at equal intervals in the second direction Y, thereby facilitating improvement of structural uniformity and preventing erroneous electrical connection caused by adjacent lead frames 7 being too close.

9, which is a schematic diagram of the active surface 13 of the memory chip 1, each power supply wiring layer 2 includes a plurality of power supply wirings 20 arranged at intervals, and different power supply signal lines 12 have different voltage signals. For example, the power supply wiring 20 is a ground wiring 20G or a power supply wiring 20P, that is, each power supply wiring layer 2 may include a plurality of ground wirings 20G and a plurality of power supply wirings 20P.

Continuing to refer to FIG9 , each memory chip 1 has a plurality of power supply signal lines 12, which extend from the memory chip 1 to the active surface 13 to connect to the power supply wiring layer 2. Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to the components in the memory chip 1. The power supply signal line 12 can be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.

It is not difficult to understand that the ground wiring 20G is electrically connected to the ground signal line 12G and the ground lead frame 7G, and the power wiring 20P is electrically connected to the power signal line 12P and the power lead frame 7P, thereby forming multiple wired power supply paths to provide different voltages for the memory chip 1.

Based on the above corresponding connection relationship, it can be known that the ground wiring 20G and the power wiring 20P can also be arranged alternately in the second direction Y, so as to reduce the electromagnetic interference between adjacent power supply wirings 20 .

The following will illustrate the arrangement of the power supply wiring layer 2 and the connection between the lead frame 7 and the power supply wiring layer 2 by way of examples.

Example 1, referring to Figures 2 to 4, each memory chip 1 has a power supply wiring layer 2, and the power supply wiring layer 2 in each memory chip 1 is connected to the power supply signal line 12 accordingly. That is, the power supply signal lines 12 of different memory chips 1 are independent of each other, and do not need to be electrically connected together through the conductive through-holes 41 and the bonding parts 42; the power supply signal lines 12 in each memory chip 1 can be led out through the power supply wiring layer 2 of the memory chip 1 itself, without borrowing the power supply wiring layer 2 of other memory chips 1. Since the power supply signal line 12 of each memory chip 1 can be led out separately, it is beneficial to improve the stability of power supply. In addition, the preparation step of the conductive through-hole 41 (refer to Figure 7) can be omitted, thereby reducing the production cost. In addition, since the multiple memory chips 1 are independent of each other, the bonding part 42 may not be set between adjacent memory chips 1, and the production cost is lower.

2-3, the memory chip 1 also has a plurality of welding bumps 81, and the welding bumps 81 are connected to the end surface 14 of the power supply wiring 20 away from the interposer 91; the lead frame 7 is electrically connected to the welding bumps 81 of the plurality of memory chips 1. That is, the welding bumps 81 can not only play the role of electrically connecting the lead frame 7 to the power supply wiring layer 2, but also play the role of fixing the lead frame 7, so that the memory module 100 can support the lead frame 7 to improve the stability of the structure.

For example, the soldering bump 81 includes a first bump and a second bump which are stacked; the cross-sectional area of the first bump is larger than the cross-sectional area of the second bump. That is, the larger cross-sectional area of the first bump is conducive to increasing the contact area between the soldering bump 81 and the power supply wiring layer 2 to reduce the contact resistance. The smaller cross-sectional area of the second bump is conducive to increasing the distance between adjacent soldering bumps 81 to avoid erroneous electrical connection between adjacent soldering bumps 81.

4 , the power supply wirings 20 with the same voltage in the plurality of power supply wiring layers 2 are aligned in the first direction X and are electrically connected to the same lead frame 7. Thus, the orthographic projection of the lead frame 7 on the substrate 92 can be a straight line, thereby facilitating the alignment of the lead frame 7 with the welding bump 81, simplifying the welding process, and saving the material of the lead frame 7.

Continuing to refer to FIG. 3 , the lead frame 7 may further include a groove 7a, and the welding bump 81 is directly opposite to and welded to the groove 7a. That is, the groove 7a is located in the first frame 71. It should be noted that the top surface of the welding bump 81 also includes a solder layer 82 to connect the welding bump 81 and the lead frame 7. The groove 7a can accommodate more solder to improve the welding strength and reduce the contact resistance between the welding bump 81 and the lead frame 7.

In some embodiments, the width of the first frame 71 in the second direction Y may be greater than the width of the welding bump 81 in the second direction Y, and the opening area of the groove 7a is greater than the top surface area of the welding bump 81. In this way, the capacity of the solder is larger and the firmness of the welding is higher; in addition, the larger opening facilitates the alignment of the welding bump 81 with the groove 7a. In other embodiments, the width of the first frame 71 in the second direction Y may also be less than or equal to the width of the welding bump 81.

In some embodiments, each lead frame 7 has a plurality of grooves 7a, and the plurality of grooves 7a correspond one-to-one to the plurality of welding bumps 81. Thus, the grooves 7a can guide the flow direction of the solder during the welding process, that is, guide the solder to flow into the grooves 7a to avoid electrical connection between adjacent welding bumps 81.

In other embodiments, each lead frame 7 has a groove 7 a, and one groove 7 a is welded to the welding bumps 81 of the plurality of memory chips 1 , that is, the groove 7 a extends in the first direction X. In this way, the production process is simpler.

Example 2, referring to Figures 5-6, the number of power supply wiring layers 2 can also be less than the number of memory chips 1. Specifically, a conductive through hole 41 is provided in the memory chip 1, and the conductive through hole 41 is connected to the power supply signal line 12; a bonding portion 42 is provided between adjacent memory chips 1, and the bonding portion 42 is connected to the conductive through hole 41 in the adjacent memory chip 1. In other words, the power supply signal lines 12 with the same voltage signal in different memory chips 1 can be connected together through the conductive through hole 41 and the bonding portion 42. By way of example, the power supply signal lines 12 with the same voltage signal in two adjacent memory chips 1 are electrically connected, so that one of the two memory chips 1 only needs to have a power supply wiring layer 2.

In other words, multiple memory chips 1 can share one power supply wiring layer 2. If a memory chip 1 has its own power supply wiring layer 2, the power supply signal line 12 of this memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have its own power supply wiring layer 2, this memory chip 1 can establish an electrical connection relationship with other memory chips 1 through the conductive through hole 41 and the bonding part 42, so as to lead out the power supply signal line 12 through the power supply wiring layer 2 of other memory chips 1.

Since multiple memory chips 1 can share one power supply wiring layer 2, the number of power supply wiring layers 2 is relatively small, and accordingly, the number of welding bumps 8 is relatively small, thereby increasing the spacing between adjacent welding bumps 8 to avoid erroneous electrical connection between adjacent welding bumps 8.

Example 3, referring to FIG. 7-FIG. 8, a memory chip 1 in the memory module 100 has a power supply wiring layer 2; a conductive through hole 41 is provided in the memory chip 1, and the conductive through hole 41 is connected to the power supply signal line 12; a bonding portion 42 is provided between adjacent memory chips 1, and the bonding portion 42 is connected to the conductive through hole in the adjacent memory chip 1, so that the power supply signal lines 12 of all memory chips 1 are electrically connected to the power supply wiring layer 2. In other words, the power supply signal lines 12 with the same voltage signal in different memory chips 1 can be connected together through the conductive through hole 41 and the bonding portion 42.

7-8, the semiconductor structure further includes: a first lead 75, which is connected between the power supply wiring layer 2 and the lead frame 7. Since the number of power supply wiring layers 2 is small, the lead connection method can be directly adopted, thereby making the process simpler and saving costs.

In addition, the bottom of the lead frame 7 can be welded to the interposer 91 through the welding pad 86, thereby improving the stability of the lead frame 7. That is, the first lead 75 cooperates with the welding pad 86 to increase the connection flexibility and the structural strength.

In some embodiments, the memory chip 1 closest to the power management chip 6 in the memory module 100 has a power supply wiring layer 2. Thus, the length of the first lead 75 can be shortened and power consumption can be reduced.

It is worth noting that the power supply wiring layer 2 may include a first wiring layer 21 and a second wiring layer 22, wherein the first wiring layer 21 extends in the third direction Z, and the second wiring layer 22 is located on the surface of the memory chip 1 away from the interposer 91. The second wiring layer 22 may increase the exposed area of the power supply wiring layer 2 to reduce the difficulty of connecting the first lead 75 to the power supply wiring layer 2.

By comparing the above three examples, it is not difficult to find that in Example 1 and Example 2, the number of power supply wiring layers 2 is relatively large, and the power supply wiring layer 2 can be connected to the lead frame 7 by using welding bumps 81. The main reason is that compared with the lead, the position of the welding bump 81 is fixed, so that the wrong electrical connection can be avoided; in addition, the second frame can extend on the top surface of the storage module 100, so as to provide sufficient connection positions for multiple welding bumps 81; in addition, the number of welding bumps 81 is large, which can strengthen the support and fixation of the lead frame 7. In Example 3, each storage module 100 has only one power supply wiring layer 2, and the first lead 75 can be used to connect to the lead frame 7. The main reason is that the lead is easy to bend, and the connection method is more flexible and simple; in addition, since the number of power supply wiring layers 2 is small, the number of first leads 75 is also small, and the distance between adjacent first leads 75 is large, which can avoid the wrong electrical connection of adjacent first leads 75.

2-3, 5 and 7, the semiconductor structure further includes a second lead 74 connected between the lead frame 7 and the power management chip 6. The second lead 74 can improve the flexibility of connecting the lead frame 7 and the power management chip 6.

2-3, 5 and 7, the semiconductor structure further includes: a first sealing layer 51, which surrounds the storage module 100 and exposes the surface of the storage module 100 away from the substrate 9. The first sealing layer 51 can protect the storage module 100 from the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration when the semiconductor structure is installed.

The semiconductor structure further includes a second sealing layer 52, which can cover the storage module 100, the lead frame 7, the intermediate layer 91, and the first sealing layer 51. The second sealing layer 52 can improve the protection and isolation effect to ensure the performance of the semiconductor structure.

In one embodiment, the first sealing layer 51 and the second sealing layer 52 may be made of the same material. For example, the first sealing layer 51 and the second sealing layer 52 may be made of epoxy resin.

In one embodiment, the materials of the first sealing layer 51 and the second sealing layer 52 may be different. For example, the thermal conductivity of the second sealing layer 52 is higher than that of the first sealing layer 51. Through such a setting, the heat introduced into the second sealing layer 52 through the lead frame 7 can be transferred to the external environment more quickly, thereby reducing the adverse effects of the high temperature environment on the storage module 100.

Referring to Figures 2-3, 5 and 7, the semiconductor structure also includes: a logic chip 3, located between the intermediate layer 91 and the storage module 100, the logic chip 3 has a first wireless communication unit 31; the storage chip 1 has a second wireless communication unit 11, and the second wireless communication unit 11 communicates wirelessly with the first wireless communication unit 31.

Since the distances between the multiple memory chips 1 and the logic chip 3 are the same, the delays of the wireless communications between the multiple memory chips 1 and the logic chip 3 remain consistent. In some embodiments, the second wireless communication unit 11 is located on the side of the memory chip 1 facing the logic chip 3. Thus, the distance between the first wireless communication unit 31 and the second wireless communication unit 11 can be reduced, thereby improving the quality of wireless communication.

It should be noted that if the arrangement direction of multiple memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delay between memory chips 1 and logic chip 3 in different layers will differ greatly; in addition, as the number of layers increases, the number of through-silicon vias (TSV) used for communication will increase proportionally, thereby sacrificing the wafer area. In the disclosed embodiment, the stacking direction and communication mode of the memory chips 1 are changed, which is beneficial to improving the communication quality and saving the wafer area.

Referring to Figures 2-3, 5 and 7, the side of the memory chip 1 is arranged toward the logic chip 3, and the area of the side is relatively small; however, the wireless communication method does not require a wired communication unit to be arranged between the memory chip 1 and the logic chip 3, thereby reducing the process difficulty and providing sufficient space for the connection structure between the memory chip 1 and the logic chip 3 to improve the structural strength of the two. In addition, the lower side of the memory module 100 is used for wireless communication, and the upper side of the memory module 100 is used for laying out a wired power supply path, thereby reducing the electromagnetic interference generated by the current in the wired power supply path to the coil in the wireless communication unit and avoiding signal loss.

In some embodiments, there is also an adhesive layer 32 between the storage module 100 and the logic chip 3. That is, the storage module 100 and the logic chip 3 are connected together by gluing to form a memory core. For example, the adhesive layer 32 can be a die attach film (DAF). The bonding process is relatively simple and can save costs. In addition, the adhesive layer 32 can also be doped with metal ions to improve the heat dissipation effect of the storage module 100 and the logic chip 3. In other embodiments, there can be a welding layer (not shown in the figure) between the storage module 100 and the logic chip 3, that is, the storage module 100 and the logic chip 3 are connected together by welding.

That is to say, by leading the power supply signal line 12 from the top of the storage module 100 , sufficient space can be left under the storage module 100 to connect the logic chip 3 , thereby improving the structural strength.

Referring to Figures 2-3, 5 and 7, there are pads 84 and solder paste layers 85 between the logic chip 3 and the interposer 91, that is, the logic chip 3 is soldered on the interposer 91 by flip-chip soldering. In this way, the logic chip 3 can be powered and signal exchanged by wire, and the wired method has high reliability. In addition, the bottom of the interposer 91 also has solder balls 93 to connect the interposer 91 and the substrate 92.

That is to say, the interposer 91 has wiring, which serves to expand the connection surface, thereby making it easier to realize the electrical connection between the substrate 92 and the power management chip 6 and the memory core. The substrate 92 can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the power management chip 6 and the memory core.

In summary, the arrangement direction of the multi-layer memory chip 1 is parallel to the upper surface of the logic chip 3, and the two form a memory core. The memory core and the power management chip 6 are packaged in a high-density system-level package on the interposer 91. In this packaging structure, the signal communication between the memory chip 1 and the logic chip 3 is achieved wirelessly, which can reduce the difficulty of communication caused by the increase in the number of stacked layers of the memory chip 1. In addition, the power management chip 6 and the memory chip 1 are wired to achieve wired power supply, thereby ensuring reliability. At the same time, the system-level packaging is conducive to the power management chip 6 to the memory chip 1 nearby power management, which can increase the integration and reduce the system power consumption.

As shown in Figures 10 to 12 and Figure 2, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can manufacture the semiconductor structure provided by the above embodiment. For detailed description of this semiconductor structure, reference can be made to the above embodiment.

Referring to Figure 10, a storage module 100 is provided, which includes a plurality of storage chips 1 stacked along a first direction X, each storage chip 1 having a power supply signal line 12, and one of the plurality of storage chips 1 having at least a power supply wiring layer 2, which is electrically connected to the power supply signal line 12.

Specifically, a plurality of memory chips 1 are provided; a power supply wiring layer 2 is formed on at least one of the plurality of memory chips 1, and after the power supply wiring layer 2 is formed, the plurality of memory chips 1 are stacked. For example, the power supply signal lines 12 of each layer of memory chips 1 are led out to the edge of the memory chip 1 through the power supply wiring layer 2, and the multi-layer memory chips 1 are stacked by hybrid bonding. It should be noted that during the bonding process, the memory chip 1 is placed horizontally.

Referring to FIG. 11 , the memory module 100 is rotated 90° so that each memory chip 1 is perpendicular to the logic chip 3, and the memory chip 1 and the logic chip 3 are fixed by the DAF film; a plurality of memory modules 100 are reconstructed by the first molding process to form a reconstructed wafer; solder bumps 81 are processed on the top surface of the reconstructed wafer by the rewiring process, and balls are planted on the solder bumps 81 to form a solder layer 82. Thereafter, the reconstructed wafer is diced to form memory cores, each of which includes a memory module 100 and a logic chip 3.

12, an interposer 91 and a power management chip 6 are provided; the memory module 100 and the power management chip 6 are welded on the interposer 91, and the first direction X is parallel to the upper surface of the interposer 91. For example, the memory core and the power management chip 6 are welded on the interposer 91 by flip-chip welding.

12 , the power supply wiring layer 2 is electrically connected to the power management chip 6. By way of example, the memory chip 1 and the power management chip 6 are electrically connected by welding the bumps 81, the lead frame 7 and the second lead 74, so that the power management chip 6 supplies power to the memory chip 1.

Referring to FIG. 2 , a substrate 92 is provided, and an interposer 91 is welded on the substrate 92. Thereafter, a second molding process may be performed to form a second molding layer 52 covering structures such as the interposer 91, the memory core, the power management chip 6, and the lead frame 7. Thus, the system-level packaging of the memory core and the power management chip 6 may be completed, thereby improving the integration and reducing the power consumption. Thereafter, a second molding process is performed to form a second sealing layer 82.

It is worth noting that the reason for using two molding processes in succession is that the first molding process can connect multiple storage modules 100 together, so the second wiring layer 22 can be formed on multiple storage modules 100 at the same time later, which is conducive to reducing the process steps. In addition, the volume of a single storage module 100 is small, and the total volume of multiple storage modules 100 connected together becomes larger, the stability is higher, and it is not easy to tip over. In addition, the first sealing layer 51 formed by the first molding process can protect and fix the storage module 100 in the subsequent steps of forming the welding bump 81 and flip-chip welding, so as to prevent the storage module 100 from collapsing or being damaged, which is conducive to ensuring the performance of the storage module 100. In addition, the two molding processes in succession can improve the sealing effect.

In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope of the patent of the present disclosure.

Claims

A semiconductor structure comprising:

Substrate;

An interposer, welded on the upper surface of the substrate;

A power management chip, soldered on the upper surface of the interposer;

A storage module is located on the upper surface of the interposer; the storage module comprises a plurality of storage chips stacked along a first direction, the first direction being parallel to the upper surface of the interposer; each of the storage chips has a power supply signal line, one of the plurality of storage chips has at least a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line;

The power management chip is also electrically connected to the power supply wiring layer.
The semiconductor structure according to claim 1, further comprising: a lead frame electrically connected between the power supply wiring layer and the power management chip.
The semiconductor structure according to claim 2, wherein the lead frames are multiple, and the multiple lead frames are arranged in a second direction; the second direction is perpendicular to the first direction and parallel to the upper surface of the interposer;

Each of the power supply wiring layers includes a plurality of power supply wirings having different voltages;

Different of the lead frames are electrically connected to the power supply wirings having different voltages.
The semiconductor structure according to claim 3, wherein each of the memory chips has a power supply wiring layer, and the power supply wiring layer in each of the memory chips is connected to the power supply signal line correspondingly;

The power supply wirings having the same voltage in the plurality of power supply wiring layers are aligned in the first direction and are electrically connected to the same lead frame.
The semiconductor structure according to claim 4, wherein

The memory chip also has a plurality of welding bumps, and the welding bumps are connected to the end surface of the power supply wiring away from the interposer;

The lead frame is electrically connected to the solder bumps of the plurality of memory chips.
The semiconductor structure according to claim 5, wherein

Each of the lead frames has a plurality of grooves, and the plurality of grooves are welded to the plurality of welding bumps in a one-to-one correspondence;

Alternatively, each of the lead frames has a groove, and one of the grooves is welded to the welding bumps of a plurality of the memory chips.
The semiconductor structure according to claim 2, wherein:

One of the memory chips in the memory module has the power supply wiring layer;

The memory chip has a conductive through hole in it, and the conductive through hole is connected to the power supply signal line;

There is a bonding portion between adjacent memory chips, and the bonding portion is connected to the conductive through-holes in the adjacent memory chips, so that the power supply signal lines of all the memory chips are electrically connected to the power supply wiring layer.
The semiconductor structure according to claim 7, wherein

The invention also includes a first lead connected between the power supply wiring layer and the lead frame.
The semiconductor structure according to claim 7, wherein the memory chip closest to the power management chip in the memory module has the power supply wiring layer.
The semiconductor structure according to claim 2, further comprising: a second lead connected between the lead frame and the power management chip.
The semiconductor structure according to claim 2, wherein the lead frame comprises: a first frame, a second frame and a third frame connected in sequence;

The first frame and the third frame both extend in the first direction. The first frame extends toward the storage module relative to the second frame. The third frame extends toward the power management chip relative to the second frame.
According to the semiconductor structure of claim 1, each of the power supply wiring layers includes ground wiring and power wiring, and the ground wiring and the power wiring are alternately arranged in a second direction; the second direction is perpendicular to the first direction and parallel to the upper surface of the interposer.
The semiconductor structure according to claim 1, wherein

There are two storage modules, which are respectively located at two opposite sides of the power management chip, and the storage modules and the power management chip are arranged in the first direction.
The semiconductor structure according to claim 1, further comprising:

a logic chip, located between the intermediary layer and the storage module, wherein the logic chip has a first wireless communication unit;

The memory chip includes a second wireless communication unit that performs wireless communication with the first wireless communication unit.
A method for manufacturing a semiconductor structure, comprising:

A storage module is provided, the storage module comprising a plurality of storage chips stacked along a first direction, each of the storage chips having a power supply signal line therein, one of the plurality of storage chips having at least a power supply wiring layer, the power supply wiring layer being electrically connected to the power supply signal line;

Provide interposer and power management chip;

Soldering the storage module and the power management chip on the interposer, and making the first direction parallel to the upper surface of the interposer;

Electrically connecting the power supply wiring layer to the power management chip;

A substrate is provided, and the intermediate layer is soldered on the substrate.