CN117673013A - Semiconductor structure and method for manufacturing semiconductor structure - Google Patents
Semiconductor structure and method for manufacturing semiconductor structure Download PDFInfo
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- CN117673013A CN117673013A CN202210956447.0A CN202210956447A CN117673013A CN 117673013 A CN117673013 A CN 117673013A CN 202210956447 A CN202210956447 A CN 202210956447A CN 117673013 A CN117673013 A CN 117673013A
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- 229910000679 solder Inorganic materials 0.000 claims description 42
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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Abstract
The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method of the semiconductor structure, wherein the semiconductor structure comprises: a substrate; an interposer soldered to an upper surface of the substrate; the power management chip is welded on the upper surface of the medium layer; the storage module is positioned on the upper surface of the medium layer; the memory module includes a plurality of memory chips stacked along a first direction, the first direction being parallel to an upper surface of the interposer; each memory chip is internally provided with a power supply signal wire, one of the memory chips is at least provided with a power supply wiring layer, and the power supply wiring layer is electrically connected with the power supply signal wire; the power management chip is also electrically connected with the power supply wiring layer. The embodiment of the disclosure can at least reduce the power consumption of the semiconductor structure and improve the integration level of the semiconductor structure.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method of manufacturing the semiconductor structure.
Background
HBM (High Bandwidth Memory ) is a new type of memory. The memory chip stacking technology represented by HBM expands the original one-dimensional memory layout to three dimensions, namely, a plurality of memory chips are stacked together and packaged, so that the density of the memory chips is greatly improved, and high capacity and high bandwidth are realized.
However, the system power consumption of HBM is high, and the integration level is to be promoted.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least beneficial to reducing the power consumption of the semiconductor structure and improving the integration level of the semiconductor structure.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate; an interposer soldered to an upper surface of the substrate; the power management chip is welded on the upper surface of the medium layer; the storage module is positioned on the upper surface of the medium layer; the memory module includes a plurality of memory chips stacked along a first direction, the first direction being parallel to an upper surface of the interposer; each memory chip is internally provided with a power supply signal wire, one of the memory chips is at least provided with a power supply wiring layer, and the power supply wiring layer is electrically connected with the power supply signal wire; the power management chip is also electrically connected with the power supply wiring layer.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a memory module comprising a plurality of memory chips stacked in a first direction, each memory chip having a power supply signal line therein, one of the plurality of memory chips having at least a power supply wiring layer electrically connected to the power supply signal line; providing an interposer and a power management chip; soldering the memory module and the power management chip on the interposer with the first direction parallel to an upper surface of the interposer; electrically connecting the power supply wiring layer with the power management chip; providing a substrate, and welding the intermediate layer on the substrate.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: and the power management chip and the storage module are subjected to system-level packaging, so that the integration level is increased, the power management is facilitated, and the system power consumption is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
FIG. 1 shows a schematic diagram of a semiconductor structure;
FIGS. 2-3, 5, and 7 illustrate cross-sectional views of different semiconductor structures provided by an embodiment of the present disclosure;
FIGS. 4, 6, 8 illustrate partial top views of different semiconductor structures provided by an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an active surface of a memory chip according to an embodiment of the disclosure;
fig. 10 to 12 are schematic structural diagrams respectively showing steps in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
Referring to fig. 1, as known from the background art, the HBM system consumes a relatively high amount of power, and the integration level is to be improved. The main reason is found by analysis: the plurality of memory chips 200 in the HBM are arranged in a direction perpendicular to the upper surface of the substrate 300, i.e., the front or back of the memory chips 200 are directed toward the logic chip 400. A power supply signal line (not shown) is led out from the front or back of the memory chip 200, and the power supply signal line establishes an electrical connection relationship with the logic chip 400 through conductive structures such as conductive vias and bonding portions; the logic chip 400 is electrically connected to the substrate 300, and the substrate 300 is electrically connected to a power management chip (not shown), thereby electrically connecting the memory chip 200 to the power management chip. However, the memory chip 200 and the power management chip are located in different package structures, and the distance between the two is long, so that the system power consumption is large and the integration level of the semiconductor structure is low.
The embodiment of the disclosure provides a semiconductor structure, wherein a power management chip and a memory module are welded on an interposer at the same time, and the interposer is welded on a substrate, namely the power management chip and the memory module are positioned in the same packaging structure, so that the integration level is higher. In addition, the power supply wiring layer of the memory chip is not required to be electrically connected with the power management chip through the substrate, so that the wired power supply path is shortened, and power consumption is reduced.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the embodiments of the present disclosure. However, the technical solutions claimed in the embodiments of the present disclosure can be implemented without these technical details and based on various changes and modifications of the following embodiments.
As shown in fig. 2-9, an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate 92; an interposer 91 soldered to the upper surface of the substrate 92; a power management chip 6 soldered to the upper surface of the interposer 91; a memory module 100 located on the upper surface of the interposer 91; the memory module 100 includes a plurality of memory chips 1 stacked in a first direction X parallel to an upper surface of the interposer 91; each memory chip 1 has a power supply signal line 12 therein, and one of the plurality of memory chips 1 has at least a power supply wiring layer 2, the power supply wiring layer 2 being electrically connected to the power supply signal line 12; the power management chip 6 is also electrically connected to the power supply wiring layer 2.
That is, the power management chip 6 and the memory module 100 may be integrated inside the same package structure to implement a system-in-package, thereby increasing the degree of integration. In addition, since the power management chip 6 is closer to the memory module 100, power management is facilitated and system power consumption is reduced.
It should be noted that the plurality of memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the plurality of memory chips 1 is parallel to the substrate 92. Therefore, the side surface of the memory chip 1 faces the substrate 92, and the area of the side surface of the memory chip 1 is smaller, so that more sufficient space can be provided for the power management chip 6 and the connection structure between the power management chip 6 and the memory chip 1, thereby being beneficial to realizing system-in-package.
The semiconductor structure will be described in detail below with reference to the accompanying drawings.
First, the semiconductor structure has a first direction X, a second direction Y, and a third direction Z. Wherein the first direction X is the stacking direction of the memory chip 1; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the substrate 92, and the third direction Z is perpendicular to the upper surface of the substrate 92.
Referring to fig. 2 to 3, 5 and 7, a plurality of memory chips 1 may be stacked in a hybrid bonding manner. For example, the surface of the memory chip 1 further has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 may be connected together by a molecular force or the like. In addition, the surface of the memory chip 1 may further have bonding portions 42, and adjacent bonding portions 42 are bonded together under the temperature-increasing condition. That is, the dielectric layer 43 is an insulating material, and can play a role in isolation; the bonding portion 42 is made of a conductive material and can function as an electrical connection. The dielectric layer 43 also exposes the end face 14 of the power supply wiring layer 2 facing away from the substrate 92, and covers the surface of the power supply wiring layer 2 except for the end face 14.
The Memory chip 1 may be a chip such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random-Access Memory). In some embodiments, the stacking manner of the adjacent memory chips 1 may be front-to-back, so as to facilitate unifying the bonding steps of the memory chips 1, and the production process is simpler. In some embodiments, the stacking of adjacent memory chips 1 may also include front-to-front, or back-to-back. In some embodiments, the front side of the memory chip 1 may also be understood as the active side 13, and the back side of the memory chip 1 may be understood as the inactive side opposite the active side 13.
In some embodiments, the memory modules 100 are two, so the memory capacity is larger and the integration level is higher. The two memory modules 100 are located on opposite sides of the power management chip 6, respectively, and the memory modules 100 and the power management chip 6 are arranged in the first direction X. That is, the opposite sides of the power management chip 6 can provide sufficient connection positions for the memory module 100, so that the connection process is simpler. In other embodiments, there may be only one memory module 100.
Referring to fig. 2-8, the semiconductor structure further includes: the lead frame 7 is electrically connected between the power supply wiring layer 2 and the power management chip 6, and the power management chip 6 performs power management on the memory module 100 through the lead frame 7. The lead frame 7 has high strength and is not easy to deform, so that the trend of the wired power supply path can be standardized.
The lead frame 7 will be described in detail below.
Referring to fig. 2-3, 5, 7, the lead frame 7 includes: a first frame 71, a second frame 72, and a third frame 73 connected in this order; the first frame 71 and the third frame 73 each extend in a first direction X, the first frame 71 extending toward the storage module 100 relative to the second frame 72; the third frame 73 extends toward the power management chip 6 with respect to the second frame 72. I.e. the cross-sectional area of the first frame 71 and the third frame 73 is larger than the cross-sectional area of the second frame 72, and the aforementioned cross-sections are all parallel to the upper surface of the interposer 91.
The first frame 71 may reduce the distance between the memory module 100 and the lead frame 7, the third frame 73 may reduce the distance between the power management chip 6 and the lead frame 7, and in addition, the first frame 71 may provide a more sufficient connection position for the power supply wiring layer 2, and the third frame 73 may provide a more sufficient connection position for the power management chip 6, thereby reducing the difficulty of connection and improving the flexibility of connection.
Fig. 4, 6 and 8 are partial top views of different semiconductor structures, respectively, and fig. 4 corresponds to the semiconductor structure shown in fig. 2 and 3, fig. 6 corresponds to the semiconductor structure shown in fig. 5, and fig. 8 corresponds to the semiconductor structure shown in fig. 7. Referring to fig. 4, 6 and 8, the lead frames 7 are plural, and the plural lead frames 7 are arranged in the second direction Y; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the interposer 91; each power supply wiring layer 2 includes a plurality of power supply wirings 20 having different voltages; the different lead frames 7 are electrically connected to the power supply wiring 20 having different voltages. That is, the power management chip 6 may provide different voltage signals to the memory module 100 through different lead frames 7.
Illustratively, the lead frame 7 includes a ground lead frame 7G and a power supply lead frame 7P; the ground lead frames 7G and the power lead frames 7P are alternately arranged in the second direction Y. In this way, it is advantageous to reduce electromagnetic interference between adjacent lead frames 7.
In some embodiments, the plurality of lead frames 7 are arranged at equal intervals in the second direction Y, thereby facilitating improvement of structural uniformity and avoiding erroneous electrical connection of adjacent lead frames 7 due to too close distance.
Referring to fig. 9, fig. 9 is a schematic diagram of an active surface 13 of a memory chip 1, each power supply wiring layer 2 includes a plurality of power supply wirings 20 arranged at intervals, and different power supply signal lines 12 have different voltage signals. Illustratively, the power supply wiring 20 is a ground wiring 20G or a power supply wiring 20P, i.e., each power supply wiring layer 2 may include a plurality of ground wirings 20G and a plurality of power supply wirings 20P.
With continued reference to fig. 9, each memory chip 1 has a plurality of power supply signal lines 12 therein, the power supply signal lines 12 extending from within the memory chip 1 to the active face 13 for connection to the power supply wiring layer 2. Different power supply signal lines 12 may provide different voltage signals, such as digital signals or analog signals, to the elements within the memory chip 1. The power supply signal line 12 may be a ground signal line 12G or a power supply signal line 12P. The different ground signal lines 12G have different voltage signals, and the different power signal lines 12P have different voltage signals.
It is to be understood that the ground wiring 20G is electrically connected to the ground signal line 12G and the ground lead frame 7G, and the power wiring 20P is electrically connected to the power signal line 12P and the power lead frame 7P, whereby a plurality of wired power supply paths can be constituted to supply different voltages to the memory chip 1.
Based on the above correspondence relationship, the ground wirings 20G and the power supply wirings 20P may be alternately arranged in the second direction Y, thereby reducing electromagnetic interference between adjacent power supply wirings 20.
The arrangement of the power supply wiring layer 2 and the connection of the lead frame 7 to the power supply wiring layer 2 will be exemplified below.
For example, referring to fig. 2 to 4, each memory chip 1 has one power supply wiring layer 2, and the power supply wiring layer 2 in each memory chip 1 is connected to a power supply signal line 12. That is, the power supply signal lines 12 of different memory chips 1 are independent of each other without being electrically connected together through the conductive via 41 and the bonding portion 42; the power supply signal line 12 in each memory chip 1 can be led out through the power supply wiring layer 2 of the memory chip 1 itself without resorting to the power supply wiring layer 2 of the other memory chip 1. Since the power supply signal line 12 of each memory chip 1 can be individually led out, it is advantageous to improve the stability of power supply. In addition, the step of preparing the conductive via 41 (refer to fig. 7) can be omitted, thereby reducing the production cost. In addition, since the plurality of memory chips 1 are independent of each other, the bonding portion 42 is not required to be provided between the adjacent memory chips 1, and the production cost is low.
Referring to fig. 2 to 3, the memory chip 1 further has a plurality of solder bumps 81, the solder bumps 81 being connected to the end face 14 of the power supply wiring 20 remote from the interposer 91; the lead frame 7 is electrically connected to the solder bumps 81 of the plurality of memory chips 1. That is, the solder bumps 81 may not only function to electrically connect the lead frame 7 with the power supply wiring layer 2, but also function to fix the lead frame 7, thereby enabling the memory module 100 to support the lead frame 7 to improve structural stability.
Illustratively, the solder bump 81 includes a first bump and a second bump that are stacked; the cross-sectional area of the first bump is larger than the cross-sectional area of the second bump. I.e., the larger cross-sectional area of the first bump, is advantageous in increasing the contact area between the solder bump 81 and the power supply wiring layer 2 to reduce the contact resistance. The smaller cross-sectional area of the second bump is advantageous in increasing the distance between adjacent solder bumps 81 to avoid erroneous electrical connection of adjacent solder bumps 81.
Referring to fig. 4, the power supply wirings 20 having the same voltage among the plurality of power supply wiring layers 2 are aligned in the first direction X and electrically connected to the same lead frame 7. Thus, the orthographic projection of the lead frame 7 on the substrate 92 may be linear, thereby facilitating alignment of the lead frame 7 with the solder bumps 81, simplifying the soldering process, and saving the material of the lead frame 7.
With continued reference to fig. 3, the lead frame 7 may also have a groove 7a therein, and the solder bump 81 is directly opposite to and soldered to the groove 7 a. That is, the groove 7a is located in the first frame 71. It should be noted that the top surface of the solder bump 81 also has a solder layer 82 to connect the solder bump 81 and the lead frame 7. The recess 7a can accommodate more solder to improve the soldering strength and reduce the contact resistance of the solder bump 81 with the lead frame 7.
In some embodiments, the width of the first frame 71 in the second direction Y may be greater than the width of the solder bump 81 in the second direction Y, and the opening area of the groove 7a is greater than the top surface area of the solder bump 81. Thus, the capacity of the solder is larger, and the welding firmness is higher; in addition, the larger opening facilitates alignment of the solder bump 81 with the recess 7 a. In other embodiments, the width of the first frame 71 in the second direction Y may also be less than or equal to the width of the solder bump 81.
In some embodiments, each lead frame 7 has a plurality of grooves 7a, and the plurality of grooves 7a are in one-to-one correspondence with the plurality of solder bumps 81. Thus, the grooves 7a can guide the flow direction of the solder during the soldering process, that is, guide the solder to flow toward the inside of the grooves 7a, thereby avoiding the electrical connection between the adjacent solder bumps 81.
In other embodiments, each lead frame 7 has one groove 7a, one groove 7a being soldered with the solder bumps 81 of the plurality of memory chips 1, i.e., the groove 7a extends in the first direction X. Thus, the production process is simpler.
For example, referring to fig. 5 to 6, the number of power supply wiring layers 2 may be smaller than the number of memory chips 1. Specifically, the memory chip 1 has therein a conductive via 41, the conductive via 41 being connected to the power supply signal line 12; the adjacent memory chips 1 have bonding portions 42 therebetween, and the bonding portions 42 are connected to the conductive vias 41 in the adjacent memory chips 1. That is, the power supply signal lines 12 having the same voltage signal in different memory chips 1 may be connected together through the conductive via 41 and the bonding portion 42. For example, the power supply signal lines 12 having the same voltage signal in two adjacent memory chips 1 are electrically connected, so that one of the two memory chips 1 may have the power supply wiring layer 2.
In other words, a plurality of memory chips 1 may share one power supply wiring layer 2. If one memory chip 1 itself has the power supply wiring layer 2, the power supply signal line 12 of this memory chip 1 may be directly connected to the power supply wiring layer 2 itself, that is, may be led out through the power supply wiring layer 2 itself. If one memory chip 1 does not have the power supply wiring layer 2, the memory chip 1 may be electrically connected to the other memory chip 1 through the conductive via 41 and the bonding portion 42, so that the power supply signal line 12 is led out through the power supply wiring layer 2 of the other memory chip 1.
Since the plurality of memory chips 1 can share one power supply wiring layer 2, the number of power supply wiring layers 2 is small, and accordingly, the number of solder bumps 8 is small, thereby increasing the pitch of adjacent solder bumps 8 to avoid erroneous electrical connection of adjacent solder bumps 8.
Example three, referring to fig. 7 to 8, one memory chip 1 in the memory module 100 has a power supply wiring layer 2; the memory chip 1 is internally provided with a conductive through hole 41, and the conductive through hole 41 is connected with the power supply signal line 12; the adjacent memory chips 1 have bonding portions 42 therebetween, and the bonding portions 42 are connected to conductive vias in the adjacent memory chips 1 so that the power supply signal lines 12 of all the memory chips 1 are electrically connected to the power supply wiring layer 2. That is, the power supply signal lines 12 having the same voltage signal in different memory chips 1 may be connected together through the conductive via 41 and the bonding portion 42.
With continued reference to fig. 7-8, the semiconductor structure further includes: the first lead 75, the first lead 75 being connected between the power supply wiring layer 2 and the lead frame 7. Because the number of the power supply wiring layers 2 is small, a lead connection mode can be directly adopted, so that the process is simpler, and the cost is saved.
In addition, the bottom of the lead frame 7 may be soldered to the interposer 91 through the pads 86, thereby improving the stability of the lead frame 7. That is, the first lead 75 is mated with the pad 86, which can increase the structural strength while improving the connection flexibility.
In some embodiments, the memory chip 1 of the memory module 100 closest to the power management chip 6 has the power supply wiring layer 2. Thereby, the length of the first lead 75 can be shortened, and power consumption can be reduced.
It is noted that the power supply wiring layer 2 may include a first wiring layer 21 and a second wiring layer 22, the first wiring layer 21 extending in the third direction Z, the second wiring layer 22 being located on a surface of the memory chip 1 remote from the interposer 91. The second wiring layer 22 can increase the exposed area of the power supply wiring layer 2 to reduce the difficulty in connecting the first lead 75 with the power supply wiring layer 2.
In comparison with the above three examples, it is found that in the first and second examples, the number of the power supply wiring layers 2 is large, and the power supply wiring layers 2 can be connected to the lead frame 7 by using the solder bumps 81. The main reason is that: the position of the solder bump 81 is fixed compared to the lead wire, so that erroneous electrical connection can be prevented from occurring; in addition, the second frame may extend over the top surface of the memory module 100 to provide sufficient connection locations for the plurality of solder bumps 81; further, the number of the solder bumps 81 is large, and the supporting and fixing action on the lead frame 7 can be enhanced. In example three, each memory module 100 has only one power supply wiring layer 2, and the first lead 75 may be connected to the lead frame 7. The main reason is that: the lead is easy to bend, and the connection mode is more flexible and simple; further, since the number of power supply wiring layers 2 is small, the number of first leads 75 is small, and the distance between adjacent first leads 75 is large, so that erroneous electrical connection between adjacent first leads 75 can be avoided.
Referring to fig. 2-3, 5, and 7, the semiconductor structure further includes: and a second lead 74, the second lead 74 being connected between the lead frame 7 and the power management chip 6. The second leads 74 may improve the flexibility of connecting the lead frame 7 with the power management chip 6.
Referring to fig. 2-3, 5 and 7, the semiconductor structure further includes: the first sealing layer 51, the first sealing layer 51 surrounds the memory module 100 and exposes a surface of the memory module 100 remote from the substrate 9. The first sealing layer 51 can protect the memory module 100 from external environments, such as external moisture, solvents, and also can resist thermal shock and mechanical vibration when the semiconductor structure is mounted.
The semiconductor structure further includes: the second sealing layer 52, the second sealing layer 52 may cover the memory module 100, the lead frame 7, the interposer 91, the first sealing layer 51, and the like. The second sealing layer 52 can enhance the protection and isolation effects to ensure the performance of the semiconductor structure.
In one embodiment, the materials of the first sealing layer 51 and the second sealing layer 52 may be the same, for example, the first sealing layer 51 and the second sealing layer 52 may be epoxy-based resins.
In one embodiment, the materials of the first sealing layer 51 and the second sealing layer 52 may be different, for example, the second sealing layer 52 has higher thermal conductivity than the first sealing layer 51, and by such arrangement, the heat introduced into the second sealing layer 52 through the lead frame 7 may be transferred to the external environment more quickly, reducing the adverse effect of the high temperature environment on the memory module 100.
Referring to fig. 2-3, 5 and 7, the semiconductor structure further includes: a logic chip 3 located between the interposer 91 and the memory module 100, the logic chip 3 having a first wireless communication section 31; the memory chip 1 has a second wireless communication unit 11, and the second wireless communication unit 11 performs wireless communication with the first wireless communication unit 31.
Since the distances between the plurality of memory chips 1 and the logic chip 3 are the same, the delays of the wireless communication between the plurality of memory chips 1 and the logic chip 3 are kept uniform. In some embodiments, the second wireless communication section 11 is located on a side of the memory chip 1 facing the logic chip 3. Thereby, the distance between the first wireless communication section 31 and the second wireless communication section 11 can be reduced, thereby improving the quality of wireless communication.
It should be noted that, if the arrangement direction of the plurality of memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delays between the memory chips 1 and the logic chip 3 in different layers are greatly different; in addition, as the number of layers increases, the number of Through-Silicon Vias (TSVs) used for communication increases proportionally, thereby sacrificing wafer area. In the embodiment of the disclosure, the stacking direction and the communication mode of the memory chip 1 are changed, so that the communication quality is improved, and the wafer area can be saved.
Referring to fig. 2 to 3, 5 and 7, the side of the memory chip 1 is disposed toward the logic chip 3, and the area of the side is small; the wireless communication mode is adopted without arranging a wired communication part between the memory chip 1 and the logic chip 3, so that the process difficulty can be reduced, and sufficient space positions can be provided for the connection structure between the memory chip 1 and the logic chip 3, so that the structural strength of the memory chip 1 and the logic chip 3 is improved. In addition, the lower side of the memory module 100 is used for wireless communication, and the upper side of the memory module 100 is used for laying out a wired power supply path, so that electromagnetic interference generated by current in the wired power supply path to a coil in the wireless communication part can be reduced, and signal loss is avoided.
In some embodiments, there is also an adhesive layer 32 between the memory module 100 and the logic chip 3. That is, the memory module 100 and the logic chip 3 are connected together by means of gluing, thereby constituting one memory die. Illustratively, the bonding layer 32 may be Die Attach Film (DAF). The bonding process is simpler, and the cost can be saved. In addition, metal ions may be doped in the adhesive layer 32 to improve the heat dissipation effect of the memory module 100 and the logic chip 3. In other embodiments, a solder layer (not shown) may be provided between the memory module 100 and the logic chip 3, i.e., the memory module 100 and the logic chip 3 are connected together by soldering.
That is, the power supply signal line 12 is led out from above the memory module 100, and a sufficient space is left below the memory module 100 to connect the logic chip 3, thereby improving structural strength.
Referring to fig. 2 to 3, 5 and 7, there are also pads 84 and a solder paste layer 85 between the logic chip 3 and the interposer 91, i.e., the logic chip 3 is soldered to the interposer 91 by flip-chip bonding. Thus, the logic chip 3 can be powered and exchanged by a wired method, and the wired method has high reliability. In addition, the bottom of the interposer 91 has solder balls 93 to connect the interposer 91 with the substrate 92.
That is, the interposer 91 has traces therein, which function to enlarge the connection surface, thereby making it easier to electrically connect the substrate 92 with the power management chip 6 and the memory die. The substrate 92 may provide electrical connection, protection, support, heat dissipation, assembly, etc. for the power management chip 6 and the memory die.
In summary, the array direction of the multi-layered memory chip 1 is parallel to the upper surface of the logic chip 3, and the two form the memory chip. The memory die and power management chip 6 are high density system in package on interposer 91. In the packaging structure, signal communication between the memory chip 1 and the logic chip 3 is realized by wireless, so that the difficulty brought to communication along with the increase of the stacking layers of the memory chip 1 can be reduced. In addition, the power management chip 6 and the memory chip 1 are wired to realize wired power supply, thereby ensuring reliability. Meanwhile, the system-in-package is beneficial to the power management of the power management chip 6 on the memory chip 1 nearby, so that the integration level can be increased, and the system power consumption can be reduced.
As shown in fig. 10-12 and 2, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can manufacture the semiconductor structure provided in the foregoing embodiment. For a detailed description of this semiconductor structure reference is made to the previous embodiments.
Referring to fig. 10, there is provided a memory module 100, the memory module 100 including a plurality of memory chips 1 stacked in a first direction X, each memory chip 1 having a power supply signal line 12 therein, one of the plurality of memory chips 1 having at least a power supply wiring layer 2, the power supply wiring layer 2 being electrically connected to the power supply signal line 12.
Specifically, a plurality of memory chips 1 are provided; the power supply wiring layer 2 is formed on at least one of the plurality of memory chips 1, and the plurality of memory chips 1 are stacked after the power supply wiring layer 2 is formed. For example, the power supply signal lines 12 of the memory chips 1 of each layer are led out to the edges of the memory chips 1 through the power supply wiring layer 2, and the memory chips 1 of the layers are stacked by hybrid bonding. During the bonding process, the memory chip 1 is placed horizontally.
Referring to fig. 11, the memory module 100 is rotated by 90 ° so that each memory chip 1 is perpendicular to the logic chip 3, and the memory chip 1 and the logic chip 3 are fixed by the DAF film; reconstituting the plurality of memory modules 100 by a first molding process to form a reconstituted wafer; the solder bump 81 is processed on the top surface of the reconstituted wafer by a re-routing process, and balls are implanted on the solder bump 81 to form a solder layer 82. Thereafter, the reconstituted wafer is diced to form memory dice, each of which includes a memory module 100 and a logic chip 3.
Referring to fig. 12, an interposer 91 and a power management chip 6 are provided; the memory module 100 and the power management chip 6 are soldered on the interposer 91 with the first direction X parallel to the upper surface of the interposer 91. The memory die and the power management chip 6 are illustratively flip-chip bonded to the interposer 91.
With continued reference to fig. 12, the power supply wiring layer 2 is electrically connected with the power management chip 6. The electrical connection of the memory chip 1 and the power management chip 6 is, for example, realized by means of the solder bumps 81, the lead frame 7 and the second leads 74, so that the power management chip 6 supplies power to the memory chip 1.
Referring to fig. 2, a substrate 92 is provided, and an interposer 91 is soldered on the substrate 92. Thereafter, a second molding process may be further performed to form a second molding layer 52 covering the interposer 91, the memory core, the power management chip 6, the lead frame 7, and the like. Thus, the system-in-package of the memory die and the power management chip 6 can be completed, thereby improving the integration level and reducing the power consumption. Thereafter, a second molding process is used to form a second sealing layer 82.
Notably, the reason for using two molding processes in succession is that: the first molding process may connect the plurality of memory modules 100 together, and thus, the second wiring layer 22 may be formed on the plurality of memory modules 100 at the same time later, thereby advantageously reducing the number of process steps. In addition, the volume of a single memory module 100 is smaller, the total volume of a plurality of memory modules 100 connected together becomes larger, the stability is higher, and the toppling is not easy to occur. In addition, the first sealing layer 51 formed by the first molding process can protect and fix the memory module 100 in the subsequent steps of forming the solder bump 81, flip-chip bonding, and the like, so as to avoid collapse or damage to the memory module 100, thereby being beneficial to ensuring the performance of the memory module 100. In addition, the two molding processes in sequence can improve the sealing effect.
In the description of the present specification, a description of the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the present disclosure, and that variations, modifications, alternatives, and variations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, which is therefore intended to be within the scope of the present disclosure as defined by the claims and specification.
Claims (15)
1. A semiconductor structure, comprising:
a substrate;
an interposer soldered to an upper surface of the substrate;
the power management chip is welded on the upper surface of the medium layer;
the storage module is positioned on the upper surface of the medium layer; the memory module includes a plurality of memory chips stacked along a first direction, the first direction being parallel to an upper surface of the interposer; each memory chip is internally provided with a power supply signal wire, one of the memory chips is at least provided with a power supply wiring layer, and the power supply wiring layer is electrically connected with the power supply signal wire;
the power management chip is also electrically connected with the power supply wiring layer.
2. The semiconductor structure of claim 1, further comprising: and the lead frame is electrically connected between the power supply wiring layer and the power management chip.
3. The semiconductor structure of claim 2, wherein the plurality of lead frames are arranged in a second direction; the second direction is perpendicular to the first direction and parallel to the upper surface of the interposer;
each of the power supply wiring layers includes a plurality of the power supply wirings having different voltages;
different ones of the lead frames are electrically connected to the power supply wiring having different voltages.
4. The semiconductor structure according to claim 3, wherein each of the memory chips has one power supply wiring layer, and the power supply wiring layer in each of the memory chips is connected to the power supply signal line in correspondence;
the power supply wirings having the same voltage among the plurality of power supply wiring layers are aligned in the first direction and electrically connected to the same lead frame.
5. The semiconductor structure of claim 4, wherein,
the memory chip is also provided with a plurality of welding convex blocks, and the welding convex blocks are connected with the end face, far away from the medium layer, of the power supply wiring;
the lead frame is electrically connected with the solder bumps of the plurality of memory chips.
6. The semiconductor structure of claim 5, wherein,
each lead frame is provided with a plurality of grooves, and the grooves are welded with the welding lugs in a one-to-one correspondence manner;
alternatively, each of the lead frames has a recess, and one of the recesses is soldered with the solder bumps of a plurality of the memory chips.
7. The semiconductor structure of claim 2, wherein,
one of the memory chips in the memory module has the power supply wiring layer;
the memory chip is internally provided with a conductive through hole, and the conductive through hole is connected with the power supply signal line;
and bonding parts are arranged between the adjacent memory chips and connected with the conductive through holes in the adjacent memory chips so as to electrically connect the power supply signal lines of all the memory chips with the power supply wiring layer.
8. The semiconductor structure of claim 7, wherein,
further comprises: and a first lead connected between the power supply wiring layer and the lead frame.
9. The semiconductor structure of claim 7, wherein the memory chip of the memory module closest to the power management chip has the power supply wiring layer.
10. The semiconductor structure of claim 2, further comprising: and a second lead connected between the lead frame and the power management chip.
11. The semiconductor structure of claim 2, wherein the leadframe comprises: the first frame, the second frame and the third frame are sequentially connected;
the first frame and the third frame each extend in the first direction, the first frame extending toward the storage module relative to the second frame; the third frame extends toward the power management chip relative to the second frame.
12. The semiconductor structure according to claim 1, wherein each of the power supply wiring layers includes a ground wiring and a power supply wiring, and the ground wiring and the power supply wiring are alternately arranged in the second direction; the second direction is perpendicular to the first direction and parallel to an upper surface of the interposer.
13. The semiconductor structure of claim 1, wherein,
the number of the storage modules is two, the two storage modules are respectively positioned at two opposite sides of the power management chip, and the storage modules and the power management chip are arranged in the first direction.
14. The semiconductor structure of claim 1, further comprising:
a logic chip located between the interposer and the memory module, the logic chip having a first wireless communication section;
the memory chip has a second wireless communication section that performs wireless communication with the first wireless communication section.
15. A method of fabricating a semiconductor structure, comprising:
providing a memory module comprising a plurality of memory chips stacked in a first direction, each memory chip having a power supply signal line therein, one of the plurality of memory chips having at least a power supply wiring layer electrically connected to the power supply signal line;
providing an interposer and a power management chip;
soldering the memory module and the power management chip on the interposer with the first direction parallel to an upper surface of the interposer;
electrically connecting the power supply wiring layer with the power management chip;
providing a substrate, and welding the intermediate layer on the substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210956447.0A CN117673013A (en) | 2022-08-10 | 2022-08-10 | Semiconductor structure and method for manufacturing semiconductor structure |
| PCT/CN2022/117386 WO2024031769A1 (en) | 2022-08-10 | 2022-09-06 | Semiconductor structure and manufacturing method for semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210956447.0A CN117673013A (en) | 2022-08-10 | 2022-08-10 | Semiconductor structure and method for manufacturing semiconductor structure |
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| Publication Number | Publication Date |
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| CN117673013A true CN117673013A (en) | 2024-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202210956447.0A Pending CN117673013A (en) | 2022-08-10 | 2022-08-10 | Semiconductor structure and method for manufacturing semiconductor structure |
Country Status (2)
| Country | Link |
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| CN (1) | CN117673013A (en) |
| WO (1) | WO2024031769A1 (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014011169A (en) * | 2012-06-27 | 2014-01-20 | Ps4 Luxco S A R L | Silicon interposer and semiconductor device with the same |
| US9917041B1 (en) * | 2016-10-28 | 2018-03-13 | Intel Corporation | 3D chip assemblies using stacked leadframes |
| KR102663810B1 (en) * | 2016-12-30 | 2024-05-07 | 삼성전자주식회사 | electronic device package |
| US10545860B2 (en) * | 2017-08-10 | 2020-01-28 | Samsung Electronics Co., Ltd. | Intelligent high bandwidth memory appliance |
| KR102605616B1 (en) * | 2018-10-05 | 2023-11-24 | 에스케이하이닉스 주식회사 | Semiconductor Module Including a Memory Stack Having TSVs |
| KR20220041454A (en) * | 2020-09-25 | 2022-04-01 | 에스케이하이닉스 주식회사 | Semiconductor Memory Apparatus, Processing System Having the Same, and Power control Circuit Therefor |
| CN113690230A (en) * | 2021-07-07 | 2021-11-23 | 江苏盐芯微电子有限公司 | Multilayer chip stacking packaging structure and packaging method |
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2022
- 2022-08-10 CN CN202210956447.0A patent/CN117673013A/en active Pending
- 2022-09-06 WO PCT/CN2022/117386 patent/WO2024031769A1/en unknown
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| WO2024031769A9 (en) | 2024-04-04 |
| WO2024031769A1 (en) | 2024-02-15 |
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