WO2024031531A9 - Display panel and display apparatus - Google Patents

Abstract

A display panel and a display apparatus. A display area of the display panel comprises a secondary display area and a primary display area, the secondary display area comprising a light-transmitting area and a circuit area. A drive back plate comprises pixel circuits and first reset signal lines; the pixel circuits comprise first pixel circuits and second pixel circuits; some of the first pixel circuits are located in the primary display area and the circuit area, and the second pixel circuits are located in the circuit area; some of the first reset signal lines comprise first reset sections and second reset sections which are discontinuously arranged in a first direction; the first reset sections are located in the primary display area, and the second reset sections are located in the circuit area; light-emitting devices comprise first light-emitting devices located in the primary display area and the circuit area, and second light-emitting devices located in the light-transmitting area; the first light-emitting devices in the primary display area are connected, by means of the first pixel circuits in the primary display area, to the part of the first reset signal lines located in the primary display area; and the light-emitting devices in the secondary display area are connected to the second reset sections by means of the pixel circuits in the circuit area.

Description

Display panel and display device Technical Field

The present disclosure relates to the field of display technology, and in particular to a display panel and a display device.

Background technique

With the development of display technology, full display with camera (FDC) has been gradually applied to display products due to its advantage of large screen-to-body ratio. Full-screen display devices usually place optical components such as cameras under the display panel, greatly improving the screen-to-body ratio.

It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

Summary of the invention

The present disclosure provides a display panel and a display device.

According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a peripheral area at least partially surrounding the display area; the display area comprises a secondary display area and a main display area located at at least one side of the secondary display area, the secondary display area comprises a light-transmitting area and a circuit area located at at least one side of the light-transmitting area;

A driving backplane, comprising a plurality of pixel circuits distributed in an array and a plurality of first reset signal lines, wherein the pixel circuits include a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is located in the main display area and the circuit area, and the second pixel circuit is located in the circuit area; wherein the plurality of first reset signal lines extend along a first direction, and some of the plurality of first reset signal lines are first-type first reset signal lines, and some of the first reset signal lines are second-type first reset signal lines; wherein the second-type first reset signal lines include a first reset segment and a second reset segment intermittently arranged along the first direction; wherein the first reset segment is located in the main display area, and the second reset segment is located in the circuit area;

A plurality of light-emitting devices are located on one side of the driving backplane, and include a first light-emitting device located in the main display area and the circuit area and a second light-emitting device located in the light-transmitting area; the first light-emitting device is connected to the first pixel circuit, and the second light-emitting device is connected to the second pixel circuit via a transfer line;

The first reset segment is connected to a portion of the first pixel circuit in the main display area, and the first reset segment is configured to provide a first reset signal to the first pixel circuit in the main display area; the second reset segment is connected to the first pixel circuit and the second pixel circuit in the circuit area, and the second reset segment is configured to provide a second reset signal to the first pixel circuit and the second pixel circuit in the circuit area.

In an exemplary embodiment of the present disclosure, the driving backplane further includes:

A first reset bus located in the peripheral area;

a second reset bus located in the peripheral area and spaced apart from the first reset bus, the second reset bus being connected to the first reset segment of the main display area;

A first reset connection line extends from the peripheral area to the display area along a second direction, the first reset connection line connecting the first reset bus and the second reset segment;

The first direction and the second direction intersect.

In an exemplary embodiment of the present disclosure, in the first direction, there is a spacing area extending along the second direction between the main display area and the circuit area, and the first reset connection line is located in the spacing area.

In an exemplary embodiment of the present disclosure, the number of the circuit areas of the auxiliary display area is two, and they are respectively located on both sides of the light-transmitting area along the first direction; the spacing area is provided between the two circuit areas and the main display area;

The number of the first reset connection lines is two, and the first reset connection lines are arranged in the two interval areas, and the two first reset connection lines are connected to the first reset bus.

In an exemplary embodiment of the present disclosure, the number of the auxiliary display areas is two, and the number of the first reset connection lines is four; the first reset connection line is provided in each of the spacing areas, and the four first reset connection lines are all connected to the first reset bus.

In an exemplary embodiment of the present disclosure, among the two first reset connection lines located on both sides of the auxiliary display area, the first ends of the two first reset connection lines are connected to the first reset bus, and the second ends of the two first reset connection lines are connected through a connecting line extending along the first direction.

In an exemplary embodiment of the present disclosure, the peripheral area includes a fan-out area extending in a direction away from the display area;

The first reset bus includes a first bus segment, a second bus segment and a third bus segment, wherein the first bus segment and the second bus segment are located at both sides of the display area and extend to the fan-out area; the third bus segment is located at a side of the display area away from the fan-out area and connects the first bus segment and the second bus segment; the first reset connection line is connected to the third bus segment;

The second reset bus is located at both sides of the display area and extends to the fan-out area. The second reset bus is disconnected at a side of the display area away from the fan-out area. The first reset connection line passes through the position where the second reset bus is disconnected.

In an exemplary embodiment of the present disclosure, the number of the secondary display areas is plural and they are spaced apart and distributed along the first direction;

The main display area between two adjacent auxiliary display areas is provided with a second reset connection line extending along the second direction; at least one first-type first reset signal line is connected to the first reset segment between two adjacent auxiliary display areas through the second reset connection line.

In an exemplary embodiment of the present disclosure, the number of the second reset connection lines between the two auxiliary display areas is two and they are spaced apart along the first direction; the first reset segments between two adjacent auxiliary display areas are connected by two second reset connection lines.

In an exemplary embodiment of the present disclosure, two first reset segments of the same first reset signal line separated by the auxiliary display area in the first direction are connected by a lead; at least part of the lead is located on a side of the first reset segment to which it is connected close to the fan-out area, or at least part of the lead is located on a side of the first reset segment to which it is connected away from the fan-out area.

In an exemplary embodiment of the present disclosure, the first reset signal line includes a plurality of routing units distributed along the first direction and a connection unit connected to two adjacent routing units, and the connection unit and the routing unit are located in different layers;

The first reset section and the second reset section both include a plurality of routing units and a plurality of connecting units;

In a first reset signal line having the first reset segment and the second reset segment, a connection unit is intermittently arranged in the spacing area, and one end is connected to a routing unit of the first reset segment, and the other end is connected to a routing unit of the second reset segment;

The first reset connection line crosses the discontinuously arranged connection units.

In an exemplary embodiment of the present disclosure, the routing unit, the first reset connection line, and the second reset connection line are arranged in the same layer and are located on a side of the connection unit close to the light emitting device.

In an exemplary embodiment of the present disclosure, the first reset connection line and the second reset connection line are arranged in the same layer and are located at a side of the routing unit away from the connection unit.

In an exemplary embodiment of the present disclosure, the second reset connection line is arranged to cross and connect with a portion of the connection units.

In an exemplary embodiment of the present disclosure, each of the pixel circuits is divided into a plurality of circuit groups distributed in an array; one of the circuit groups includes a plurality of circuit units distributed along the first direction; one of the circuit units includes two of the pixel circuits distributed along the first direction;

In the first direction, the distance between two adjacent circuit groups is greater than the distance between two adjacent pixel circuits; the two pixel circuits of the same circuit unit are symmetrically arranged about a straight line extending along the second direction;

The spacing area is a partial area between two adjacent circuit groups.

In an exemplary embodiment of the present disclosure, the pixel circuit includes a first reset transistor;

In the circuit area, the second reset segment is connected to the light emitting device through the first reset transistor;

In the main display area, the first reset segment is connected to the light emitting device through the first reset transistor.

In an exemplary embodiment of the present disclosure, the display panel further includes:

The transfer layer is arranged between the driving backplane and the light-emitting device, and includes the transfer line, which extends from the circuit area to the light-transmitting area. At least one of the second light-emitting devices is connected to at least one of the second pixel circuits through at least one of the transfer lines.

According to one aspect of the present disclosure, there is provided a display device, comprising:

The display panel as described in any one of the above items;

A photosensitive element is located on a side of the driving backplane away from the plurality of light-emitting devices, and an orthographic projection of the photosensitive element on the driving backplane at least partially overlaps with an orthographic projection of the light-transmitting area on the driving backplane.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

FIG. 1 is a top view of an embodiment of a display panel of the present disclosure.

FIG. 2 is a schematic diagram of partial distribution of pixel circuits and light-emitting devices of an embodiment of a display panel disclosed herein.

FIG. 3 is a schematic diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

FIG. 4 is a schematic cross-sectional view of an embodiment of a display panel according to the present disclosure.

FIG. 5 is a partial view of section A in FIG. 1 .

FIG. 6 is a schematic diagram of the first semiconductor layer and the first gate layer in FIG. 5 .

FIG. 7 is a schematic diagram of the first semiconductor layer to the second gate layer in FIG. 5 .

FIG. 8 is a schematic diagram of the first semiconductor layer to the third gate layer in FIG. 5 .

FIG. 9 is a schematic diagram of the first semiconductor layer to the first source and drain layer in FIG. 5 .

10 to 16 are partial schematic diagrams of some film layers in FIG. 5 .

FIG. 17 is a partial view of portion B in FIG. 5 .

18-20 are partial schematic diagrams of some film layers in FIG. 17 .

FIG. 21 is a top view of another embodiment of the display panel disclosed herein.

FIG. 22 is a top view of another embodiment of the display panel disclosed herein.

FIG. 23 is a top view of another embodiment of the display panel disclosed herein.

FIG. 24 is a top view of an embodiment of a display device disclosed herein.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements/components/etc. may exist in addition to the listed elements/components/etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

Herein, the first direction may be represented by a row direction X, and the second direction may be represented by a column direction Y, and the row direction X and the column direction Y are only two mutually intersecting directions, for example, the two may be perpendicular to each other. In the drawings of the present disclosure, the row direction X may be horizontal, and the column direction Y may be vertical, but it is not limited thereto. If the display panel is rotated, the actual directions of the row direction X and the column direction Y may change.

In this document, "overlapping" of feature A and feature B means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.

In this article, feature A and feature B are "in the same layer" means that feature A and feature B can be formed at the same time, they are different discontinuous or continuous regions in the same film layer, and they are not separated by other film layers in the direction perpendicular to the substrate. "Different layers" means that feature A and feature B are spaced apart in the direction perpendicular to the substrate, and they are separated by other film layers.

An embodiment of the present disclosure provides a display panel, as shown in Figures 1 and 2, the display panel may have a display area AA and a peripheral area WA located outside the display area AA, the peripheral area WA may be a continuous or discontinuous annular area surrounding the display area AA, that is, the peripheral area WA is at least partially arranged around the display area AA, and the shape of the peripheral area WA is not particularly limited herein.

The peripheral area WA may include a fan-out area FA extending in a direction away from the display area AA, and the display area AA and the fan-out area FA may be distributed along the column direction Y. The fan-out area FA has a binding portion PA, and the binding portion PA may be provided with a plurality of pads, through which the flexible circuit board may be bound, so that the display area AA of the display panel may be controlled to emit light through the control circuit board bound to the flexible circuit board to display an image.

The display area AA may include a main display area MA and a sub-display area SA. The main display area MA is located outside the sub-display area SA. In the row direction X, the main display area MA may be located on at least one side of the sub-display area SA. For example, the main display area MA may be surrounded by the sub-display area SA, or a boundary of the main display area MA may partially overlap with a boundary of the sub-display area SA.

The auxiliary display area SA may include a light-transmitting area SA1 and a circuit area SA2 outside the light-transmitting area SA1. In the row direction X, the circuit area SA2 is located on at least one side of the light-transmitting area SA1. Both the light-transmitting area SA1 and the circuit area SA2 can emit light, but the transmittance of the light-transmitting area SA1 is greater than that of the circuit area SA2, so as to realize under-screen camera. The shape of the light-transmitting area SA1 can be circular, elliptical, or a polygon such as a rectangle, or other regular or irregular shapes, which are not specifically limited here. At least part of the circuit area SA2 and the light-transmitting area SA1 can be distributed along the row direction X. For example: there is one light-transmitting area SA1 and two circuit areas SA2 in the auxiliary display area SA, and the two circuit areas SA2 are respectively located on both sides of the light-transmitting area SA1 along the row direction X, and can be symmetrically arranged about a straight line passing through the center of the light-transmitting area SA1 along the column direction Y.

As shown in FIG. 2 and FIG. 4 , the display panel may include a driving backplane BP and a plurality of light emitting devices LD disposed on one side of the driving backplane BP, wherein the driving backplane BP has a driving circuit for driving the light emitting devices LD to emit light. The driving circuit may include a pixel circuit PC located in the display area AA and a peripheral circuit located in the peripheral area WA, wherein:

There are multiple pixel circuits PC, and they are arranged in multiple rows and columns along the row direction X and the column direction Y. One pixel circuit PC can be connected to one light emitting device LD. Of course, there can also be a situation where one pixel circuit PC is connected to multiple light emitting devices LD. This article only takes the one-to-one connection between the pixel circuit PC and the light emitting device LD as an example for explanation. Among them, the pixel circuit PC can be distributed in the circuit area SA2 of the main display area and the auxiliary display area SA, and the pixel circuit PC is not set in the light-transmitting area SA1 to improve the light transmittance of the light-transmitting area SA1. Specifically, each pixel circuit PC can be divided into a first pixel circuit PC1 and a second pixel circuit PC2. The first pixel circuit PC1 is distributed in the main display area MA and the circuit area SA2, and the second pixel circuit PC2 is located in the circuit area SA2. That is to say, the circuit area SA2 has both the first pixel circuit PC1 and the second pixel circuit PC2, while the main display area MA has only the first pixel circuit PC1.

The pixel circuit PC may include multiple transistors and capacitors, which may be 3T1C, 7T1C, 8T1C and other pixel circuits. nTmC means that a pixel circuit PC includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C").

The peripheral circuit may be connected to the pixel circuit PC and the light emitting device LD, and may control the current passing through the light emitting device LD through the pixel circuit PC, thereby controlling the brightness of the light emitting device LD. The peripheral circuit may include a gate drive circuit and a light emitting control circuit, and of course, may also include other circuits, and the specific structure of the peripheral circuit is not particularly limited here.

Each light emitting device LD may be arranged on one side of the driving backplane BP and located in the display area AA. The main display area MA and the light-transmitting area SA1 and the circuit area SA2 of the auxiliary display area SA are all provided with light emitting devices LD, so that the entire display area AA can emit light. At the same time, the light emitting device LD may include a first electrode ANO, a light emitting layer EL, and a second electrode CAT stacked in a direction away from the driving backplane BP. The light emitting device LD may be an OLED (organic light emitting diode), of course, it may also be a Micro LED (micrometer light emitting diode) and a Mini LED (sub-millimeter light emitting diode), or it may be a light emitting device such as a QLED (quantum dot diode).

As shown in FIG. 4 , the first electrode ANO may be arranged on one side of the driving backplane BP and distributed in an array. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the driving backplane BP. Each light-emitting device LD may share the second electrode CAT, that is, the second electrode CAT may be a continuous whole-layer structure, and the second electrode CAT may extend to the peripheral area and may receive the second power supply signal VSS, while the first electrode ANO is distributed in an array and connected to the pixel circuit PC to ensure that each light-emitting device LD can emit light independently. In addition, in order to limit the light-emitting range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL may be provided on the surface where the first electrode ANO is provided, and the pixel definition layer PDL may be provided with an opening exposing each first electrode ANO, and the light-emitting layer EL is stacked with the first electrode ANO in the opening.

Each light emitting device LD may at least share a light emitting material layer, so that the light emitting colors of each light emitting device LD are the same. At this time, in order to achieve color display, a color filter layer may be provided on the side of the light emitting device LD away from the driving backplane BP, and color display may be achieved through the filter portion corresponding to each light emitting device LD in the color filter layer. Of course, the light emitting material layer of each light emitting device LD may also be independent, so that the light emitting device LD may directly emit monochromatic light, and the light emitting colors of different light emitting devices LD may be different, thereby achieving color display.

As shown in FIG2 , based on the above division of the pixel circuit PC, the light-emitting device can be divided into the first light-emitting device LD1 and the second light-emitting device LD2. The first light-emitting device LD1 is distributed in the main display area MA and the circuit area SA2, and the second light-emitting device LD2 is distributed in the light-transmitting area SA1. At the same time, in order to drive each light-emitting device LD, in the main display area MA and the circuit area SA2, the first light-emitting device LD1 can be connected to the first pixel circuit PC1, so as to emit light under the drive of the first pixel circuit PC1, and the second light-emitting device LD2 can be connected to the second pixel circuit PC2 through the adapter CL, and the adapter CL can extend from the light-transmitting area SA1 to the circuit area SA2. For example:

As shown in FIG. 2 and FIG. 4 , in some embodiments of the present disclosure, the display panel may include a transfer layer BL, which may be disposed between the driving backplane BP and the light-emitting device LD, and includes a plurality of transfer lines CL extending from the circuit area SA2 to the light-transmitting area SA1, and at least one second light-emitting device LD2 is connected to at least one second pixel circuit PC2 through at least one transfer line CL. For example, a second light-emitting device LD2 is connected to a second pixel circuit PC2 through a transfer line CL, so that one second pixel circuit PC2 drives only one second light-emitting device LD2; or, a second light-emitting device LD2 is connected to a plurality of second pixel circuits PC2 through a plurality of transfer lines CL, so that a plurality of second pixel circuits PC2 can drive the same second light-emitting device LD2; or, a plurality of second light-emitting devices LD2 are connected to the same second pixel circuit PC2 through a plurality of transfer lines CL, so that one second pixel circuit PC2 can drive a plurality of second light-emitting devices LD2.

The adapter wire CL may be made of a transparent conductive material, which may include a transparent conductive material such as indium tin oxide (ITO) to reduce the effect on the transmittance of the light-transmitting area SA1. In addition, the adapter wires CL connected to each second light-emitting device LD2 may be located in the same layer or distributed in multiple layers. For example, the adapter layer BL may include multiple routing layers and planarization layers alternately distributed in a direction away from the driving backplane BP. The specific number is not specifically limited here, so that each routing layer is covered by a planarization layer. Each routing layer may be provided with a portion of the adapter wires CL to increase the wiring space.

In addition, the display panel may further include an encapsulation layer covering each light-emitting device LD, which may be encapsulated in a thin film manner, for example, the encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer, wherein: the first inorganic layer may cover each light-emitting device, that is, the first inorganic layer may cover the surface of the second electrode CAT away from the driving backplane BP. The material of the first inorganic layer may include inorganic insulating materials such as silicon nitride and silicon oxide. The organic layer may be provided on the surface of the first inorganic layer away from the driving backplane BP, and the boundary of the organic layer may be limited to the inner side of the boundary of the first inorganic layer by a blocking dam located in the peripheral area WA, and the material of the organic layer may be an organic material such as resin.

The second inorganic layer can cover the organic layer and the first inorganic layer not covered by the organic layer, and can block water and oxygen intrusion through the second inorganic layer, and achieve planarization through the organic layer with fluidity (during the manufacturing process). The material of the second inorganic layer can include inorganic insulating materials such as silicon nitride and silicon oxide.

In addition, the display panel may further include other film layers such as a touch layer and a transparent cover plate arranged on a side of the encapsulation layer away from the driving backplane BP. The transparent cover plate may be located on a side of the touch layer away from the driving backplane BP.

Taking the touch layer adopting the mutual capacitance touch structure as an example, the touch layer may include a plurality of first touch electrodes and a plurality of second touch electrodes, each first touch electrode may be spaced apart along the row direction X, a first touch electrode may include a plurality of first electrode blocks spaced apart along the column direction Y and a switching bridge connecting two adjacent first electrode blocks; each second touch electrode may be spaced apart along the column direction Y, a second touch electrode may include a plurality of second electrode blocks connected in series along the row direction X; a switching bridge crosses a second touch electrode and is insulated. One of the first touch electrode and the second touch electrode may be used as a transmitting electrode, and the other as a receiving electrode, and both are connected to the peripheral touch driving circuit.

The following is an explanation of a pixel circuit PC with a 7T1C structure as an example:

As shown in Figures 3 to 9, the transistors of the pixel circuit PC may include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7 and a storage capacitor Cst, each transistor includes a gate, a first electrode and a second electrode, and the first electrode and the second electrode can be turned on or off by applying a control signal to the gate. The storage capacitor Cst may include an overlapping first plate and a second plate.

As shown in FIG3 , the gate of the first light emitting control transistor T5 is used to input the light emitting control signal EM, the first electrode is used to input the first power supply signal VDD, and the second electrode is connected to the first electrode of the driving transistor T3. The gate of the driving transistor T3 is connected to the first node N1, the second electrode and the first electrode of the second light emitting control transistor T6 are connected to the second node N2, the second electrode of the second light emitting control transistor T6 is connected to the first electrode ANO of a light emitting device LD, and the gate of the second light emitting control transistor T6 is used to input the light emitting control signal EM.

The gate of the first reset transistor T1 is used to input the first reset control signal RE1, the first electrode is used to input the first reset signal VI1, that is, the first reset signal, and the second electrode and the first electrode ANO of the second light emitting control transistor T6 are connected to the fourth node N4.

The gate of the writing transistor T4 is used to input the first scanning signal Gate1 , the first electrode is used to input the data signal DA, and the second electrode and the first electrode of the driving transistor T3 and the second electrode of the first light emission control transistor T5 are connected to the third node N3 .

The gate of the compensation transistor T2 is used to input the second scanning signal Gate2, the first electrode and the driving transistor T3 are connected to the second node N2, and the second electrode is connected to the first node N1.

The gate of the second reset transistor T7 is used to input the second reset control signal RE2 , the first electrode is used to input the second reset signal VI2 , and the second electrode is connected to the first node N1 .

A first plate of the storage capacitor Cst is used to input a first power signal VDD, and a second plate is connected to a first node N1.

The working principle of the above pixel circuit PC is described below:

In the reset stage t1: the second reset transistor T7 is turned on by the second reset control signal RE2, and the first reset signal VI2 is written to the first node N1. At the same time, the first reset transistor T1 is turned on by the first reset control signal RE1, and the first reset signal VI1 is written to the fourth node N4. Thus, the gate of the driving transistor T3 and the light emitting device LD can be reset.

In the writing stage t2: the writing transistor T4 and the compensation transistor T2 are turned on by the first scanning signal Gate1 and the second scanning signal Gate2, and the data signal DA is written to the first node N1 through the third node N3 and the second node N2 until the potential reaches Vdata+vth, where Vdata is the voltage of the data signal DA and Vth is the threshold voltage of the driving transistor T3. The first scanning signal Gate1 and the second scanning signal Gate2 can be the same signal or two synchronized signals. In addition, the first scanning signal Gate1 and the second scanning signal Gate2 can be high-frequency signals, which is beneficial to reduce the load of the source signal of the driving transistor T3.

In the light-emitting stage t3: the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on by the light-emitting control signal EM, the driving transistor T3 is turned on under the action of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD, and the light-emitting device LD emits light under the action of the first power signal VDD and the second power signal VSS. In this process, the first electrode of the driving transistor T3 serves as the source electrode and the second electrode serves as the drain electrode.

The output current of the driving transistor T3 satisfies the following formula:

I＝(μWCox/2L)(Vgs-Vth) ²

Wherein, I is the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor T3, L is the channel length of the driving transistor T3, Vgs is the gate-source voltage difference (the voltage difference between the gate and the source) of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

According to the above formula for the output current of the driving transistor T3, the gate voltage Vdata+Vth and the source voltage VDD of the driving transistor T3 in the pixel circuit PC of the present disclosure are substituted into the above formula to obtain: the output current I of the driving transistor T3 = (μWCox/2L)(Vdata+Vth-VDD-Vth) ^2. It can be seen that the output current of the pixel circuit PC has nothing to do with the threshold voltage Vth of the driving transistor T3, but only with Vdata, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current, and the output current can be controlled only by the voltage Vdata of the data signal DA, so as to control the brightness of the light-emitting device LD.

Each transistor of the above-mentioned pixel circuit PC can adopt a polycrystalline silicon transistor, that is, the channel of the transistor is polycrystalline silicon, such as a P-type low-temperature polycrystalline silicon transistor or an N-type low-temperature polycrystalline silicon transistor. Of course, a metal oxide transistor can also be adopted, that is, the channel of the transistor is a metal oxide such as indium gallium zinc oxide. Among them, the P-type low-temperature polycrystalline silicon transistor can be turned off when a high level is input to its gate, and turned on when a low level signal is input; the N-type low-temperature polycrystalline silicon transistor can be turned off when a low level is input to its gate, and turned on when a high level signal is input. The metal oxide transistor can be an N-type metal oxide transistor, which can be turned on when a high level is input to the gate, and turned off when a low level is input.

In some embodiments of the present disclosure, the above-mentioned 7T1C pixel circuit may adopt LTPO (LTPS+Oxide) technology. Specifically, the driving transistor T3, the writing transistor T4, the first reset transistor T1, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 may adopt P-type low-temperature polysilicon transistors; the second reset transistor T7 and the compensation transistor T2 may adopt N-type metal oxide transistors. Since the P-type low-temperature polysilicon transistor has a higher carrier mobility, it is conducive to realizing a display panel with high resolution, high response speed, high pixel density and high aperture ratio, so as to obtain a higher carrier mobility and improve the response speed. At the same time, leakage can be reduced by using the N-type metal oxide transistor.

As shown in FIG6 , based on the pixel circuit PC using LTPO technology described above, in some embodiments of the present disclosure, each pixel circuit PC may be divided into a plurality of circuit groups CM distributed in an array, and a circuit group CM may include a plurality of circuit units CU distributed along the row direction X, and a circuit unit CU may include two pixel circuits PC distributed along the row direction X. At the same time, in the row direction X, the spacing between two adjacent circuit groups CM is greater than the spacing between two adjacent pixel circuits PC, and the two pixel circuits PC in the same circuit unit CU may be symmetrically arranged about a straight line extending along the column direction Y, and the symmetrical arrangement here means that the two pixel circuits PC are completely symmetrical or the transistors of the two pixel circuits PC are symmetrical.

The above-mentioned signals input to the pixel circuit PC can be transmitted through wiring. The wiring for transmitting the above-mentioned signals is described below:

As shown in FIGS. 5 to 9 , the driving backplane BP may include a plurality of running lines extending at least partially along the row direction X, any of which may be connected to a row of pixel circuits PC, and these running lines may include a first reset control line REL1, a first reset signal line VIL1, a second reset control line REL2, a second reset signal line VIL2, a first scan line GAL1, a second scan line GAL2 and a light emitting control line EML, wherein:

For a pixel circuit PC:

The first reset control line REL1 may be connected to the gate of the first reset transistor T1 for transmitting the first reset control signal RE1. The first reset signal line VIL1 may be connected to the first electrode of the first reset transistor T1 for transmitting the first reset signal VI1 to the first electrode ANO of the light emitting device LD.

In some embodiments of the present disclosure, the first reset signal line VIL1 may include a plurality of routing units VB distributed along the row direction X and a connection unit VL connected to two adjacent routing units VB, and the connection unit VL and the routing unit VB are located in different layers, so that other routing lines on the same layer as the routing unit VB can pass between the two adjacent routing units VB. Further, the routing unit VB may be located within the range of the above-mentioned circuit group CM, and the connection unit VL is located between the two adjacent circuit groups CM, that is, the two adjacent routing units VB cross the area between the two adjacent circuit groups CM through the connection unit VL.

The second reset control line REL2 may be connected to the gate of the second reset transistor T7 for transmitting the second reset control signal RE2. The second reset signal line VIL2 is connected to the first electrode of the second reset transistor T7 for transmitting the second reset signal VI2.

The first scan line GAL1 may be connected to the gate of the write transistor T4 for transmitting the first scan signal Gate1. The second scan line GAL2 may be connected to the gate of the compensation transistor T2 for transmitting the second scan signal Gate2.

The light emission control line EML may be connected to a gate of the first light emission control transistor T5 and a gate of the second light emission control transistor T6 for transmitting a light emission control signal.

In addition to the above-mentioned routing lines, the driving backplane BP also includes column routing lines extending along the column direction Y, including data lines DAL and power lines VDL. A data line DAL is connected to the first electrode of the write transistor T4 of each pixel circuit PC in a column of pixel circuits PC for transmitting a data signal DA. A power line VDL can be connected to the second electrode plate Cst2 of each pixel circuit PC in a column of pixel circuits PC and the first electrode of the first light-emitting control transistor T5 for transmitting a first power signal VDD.

Based on the above 7T1C pixel circuit, the following describes in detail the various film layers of the driving backplane BP:

As shown in FIG. 4 , in some embodiments of the present disclosure, the driving backplane BP may include a substrate SU, a first semiconductor layer POL, a first gate insulating layer GI1, a first gate layer GA1, a first insulating layer ILD0, a second gate layer GA2, a second insulating layer ILD1, a second semiconductor layer IGL, a second gate insulating layer GI2, a third gate layer GA3, a third insulating layer ILD2, a first source and drain layer SD1, a first planar layer PLN1, a second source and drain layer SD2, and a second planar layer PLN2, wherein:

The substrate SU may be made of a flexible transparent material such as polyimide (PI) or a hard transparent material such as glass, and the substrate SU may be a multi-layer or single-layer structure.

As shown in Fig. 10, the first semiconductor layer POL may be disposed on one side of the substrate SU and include channels of the driving transistor T3, the writing transistor T4, the first reset transistor T1, the first emission control transistor T5 and the second emission control transistor T6 in the pixel circuit PC. The material of the first semiconductor layer POL may be polycrystalline silicon.

The first gate insulating layer GI1 may cover the first semiconductor layer POL, and the material of the first gate insulating layer GI1 may be an insulating material such as silicon nitride and silicon oxide.

As shown in FIG. 11 , the first gate layer GA1 may be disposed on a surface of the first gate insulating layer GI1 away from the substrate SU, and includes a first reset control line REL1, an emission control line EML, a first scan line GAL1 and a first plate Cst1 of a storage capacitor Cst, wherein:

The first electrode Cst1 overlaps with a part of the first semiconductor layer POL, and the first semiconductor layer POL at the overlap is the channel of the driving transistor T3, and the first electrode Cst1 is multiplexed as the gate of the driving transistor T3. The first reset control line REL1 overlaps with a part of the first semiconductor layer POL, and the first semiconductor layer POL at the overlap is the channel of the first reset transistor T1, and the first reset control line REL1 at the overlap is the gate of the first reset transistor T1. The first scan line GAL1 overlaps with a part of the first semiconductor layer POL, and the first semiconductor layer POL at the overlap is the channel of the write transistor T4, and the first scan line GAL1 at the overlap is the gate of the write transistor T4. The light control line EML overlaps with a part of the first semiconductor layer POL, and the first semiconductor layer POL at the overlap is the channel of the first light control transistor T5 and the second light control transistor T6, and the light control line EML at the overlap is the gate of the first light control transistor T5 and the second light control transistor T6.

In addition, the connection unit VL of the first reset signal line VIL1 mentioned above may also be located in the first gate layer GA1.

The first insulating layer ILD0 may cover the first gate layer GA1 , and the material of the first insulating layer ILD0 may be insulating materials such as silicon nitride and silicon oxide.

As shown in FIG. 12 , the second gate layer GA2 may be disposed on a surface of the first insulating layer ILD0 away from the substrate SU and include a second reset signal line VIL2 and a second plate Cst2 . The second plate Cst2 overlaps the first plate Cst1 to form a storage capacitor Cst.

The second insulating layer ILD1 may cover the second gate layer GA2 and may be a single layer or a multi-layer structure, and the material may include insulating materials such as silicon nitride and silicon oxide. For example, the second insulating layer ILD1 may include a dielectric layer and a buffer layer stacked in sequence in a direction away from the substrate SU.

As shown in FIG. 13 , the second semiconductor layer IGL may be disposed on a surface of the second insulating layer ILD1 away from the substrate SU, and include channels of the second reset transistor T7 and the compensation transistor T2 .

The second gate insulating layer GI2 may cover the second semiconductor layer IGL, and the material of the second gate insulating layer GI2 may be insulating materials such as silicon nitride and silicon oxide.

As shown in FIG. 14 , the third gate layer GA3 may be disposed on a surface of the second gate insulating layer GI2 away from the substrate SU, and includes a second reset control line REL2 and a second scan line GAL2 , and overlaps at least a portion of the second semiconductor layer IGL.

The third insulating layer ILD2 may cover the third gate layer GA3 , and may be a single-layer or multi-layer structure, and the material may include inorganic insulating materials such as silicon nitride and silicon oxide, or may include organic insulating materials such as insulating resin.

As shown in FIG. 15 , the first source-drain layer SD1 may be disposed on a surface of the third insulating layer ILD2 away from the substrate SU, and include a wiring unit VB.

The first planar layer PLN1 may cover the first source-drain layer SD1, and its material may be an insulating material such as resin. In addition, a passivation layer may be included, which may cover the first source-drain layer SD1. The first planar layer PLN1 covers the first source-drain layer SD1.

As shown in FIG. 16 , the second source-drain layer SD2 may be disposed on a surface of the first planar layer PLN1 away from the substrate SU, and include a data line DAL and a power line VDL.

The second planar layer PLN2 may cover the second source-drain layer SD2, and its material may be an insulating material such as resin. The transfer layer BL may be disposed on the surface of the second planar layer PLN2 away from the substrate SU.

In addition, further, as shown in FIG. 5 and FIG. 12, the second gate layer GA2 may also include an auxiliary reset line REL2s and an auxiliary scanning line GAL2s extending along the row direction X, the auxiliary reset line REL2s may overlap with the second reset control line REL2, the auxiliary reset line REL2s also overlaps with the second semiconductor layer IGL, and the second semiconductor layer IGL corresponding to the overlap is still the channel of the second reset transistor T7, and the auxiliary reset line REL2s at the overlap is also the gate of the second reset transistor T7. At the same time, the auxiliary reset line REL2s may be connected to the second reset control line REL2 in the display area AA through a contact hole, or the two may be connected after being extended to the peripheral area WA, thereby increasing the area of the gate of the second reset transistor T7.

The auxiliary scanning line GAL2s can overlap with the second scanning line GAL2, and the auxiliary scanning line GAL2s also overlaps with the second semiconductor layer IGL, and the second semiconductor layer IGL corresponding to the overlap is still the channel of the compensation transistor T2, and the auxiliary scanning line GAL2s at the overlap is also the gate of the compensation transistor T2. At the same time, the auxiliary scanning line GAL2s can be connected to the second scanning line GAL2 in the display area AA through a contact hole, or they can be connected after being extended to the peripheral area WA, so that the area of the gate of the compensation transistor T2 can be increased.

In addition, as shown in FIG4 , a light shielding layer BSM may be provided between the substrate SU and the first semiconductor layer POL, which may be made of light shielding metal or other materials, and may be a single-layer or multi-layer structure. At least a portion of the light shielding layer BSM may overlap with the channel region of at least a portion of the transistors to shield the light irradiated to the transistors, so that the electrical characteristics of the transistors are stable. For example, the light shielding layer BSM may include a plurality of light shielding units distributed in an array, and a light shielding unit may shield a channel of a driving transistor T3. At the same time, the light shielding units may be connected by a light shielding line, so that the light shielding layer BSM is an integrated structure, and the second power supply signal VSS or the second power supply signal VDD is input to the light shielding layer BSM, so that the light shielding layer BSM plays the role of electrostatic shielding.

Further, as shown in Fig. 4, the light shielding layer BSM may be covered by an insulating buffer layer, and the first semiconductor layer may be arranged on the surface of the buffer layer away from the substrate SU. The buffer layer may be a single layer or multilayer structure, and its material may include insulating materials such as silicon nitride and silicon oxide.

In order to save space, as shown in FIG5 and FIG8, part of the wiring of two adjacent rows of pixel circuits PC can be reused. For example, the first reset control line REL1 connected to the nth row of pixel circuits PC can be reused as the first scan line GAL1 connected to the n+1th row of pixel circuits PC, where n is a positive integer. In other words, the first reset control line REL1 connected to the nth row of pixel circuits PC is also the first scan line GAL1 connected to the n+1th row of pixel circuits PC.

The inventors discovered that, as shown in FIG2 , since the second pixel circuit PC2 is connected to the second light-emitting device LD2 through the adapter line CL, compared to the first pixel circuit PC1 directly connected to the first light-emitting device LD1, the presence of the adapter line CL will increase the load between the second pixel circuit PC2 and the second light-emitting device LD2 connected thereto. If the same reset signal is used to reset the first light-emitting device LD1 and the second light-emitting device LD2, the reset of the second light-emitting device LD2 lags behind the reset of the first light-emitting device, causing the light-transmitting area SA1 to be asynchronous with the main display area MA and the circuit area SA2, and abnormal lighting occurs especially at low grayscales.

In order to solve the above-mentioned abnormal lighting problem, as shown in FIG3 , the inventor provides a new solution, by designing the first reset signal line, the first light emitting device LD1 and the second light emitting device LD2 are reset respectively, that is, the first reset signal VI1 is used to reset the first light emitting device LD1, and the third reset signal VI3 is used to reset the second light emitting device LD2. By controlling the timing of the third reset signal VI3 and the first reset signal VI1, the abnormal lighting can be compensated, and the difference between the lighting time of the light-transmitting area SA1 and the lighting time of the main display area MA and the circuit area SA2 can be reduced or eliminated. The third reset signal VI3 is the second reset signal. The solution is described in detail below:

As shown in Figures 1 and 2, for all pixel circuits PC in the display area AA, each row of pixel circuits PC can be connected to a reset signal line VIL1, which can be divided into two categories. The first category first reset signal line VIL1 is located outside the sub-display area SA in the column direction Y, that is, the first category first reset signal line VIL11 and the sub-display area SA are distributed along the column direction Y; the extension direction of the second category first reset signal line VIL12 intersects with the sub-display area SA, and a partial area of the second category first reset signal line VIL12 is located in the circuit area SA2 in the sub-display area SA.

The second type first reset signal line VIL12 can be divided into a first reset segment LV1 and a second reset segment LV2 which are intermittently arranged along the row direction X. The first reset segment LV1 is located in the main display area MA, and the second reset segment LV2 is located in the circuit area SA2. As shown in FIGS. 5, 6, 11 and 15, the first reset segment LV1 and the second reset segment LV2 both include a plurality of routing units VB and a connection unit VL; wherein:

For the first light emitting device LD1 in the main display area MA, the first pixel circuit PC1 connected thereto can be connected to the first reset segment LV1 of the first type first reset signal line VIL11 and the second type first reset signal line VIL12, that is, in the main display area MA, the first pixel circuit PC1 distributed along the row direction X with the pixel circuit PC in the auxiliary display area SA can be connected to the first reset segment LV1 of the second type first reset signal line VIL12, and other first pixel circuits PC1 are connected to the first type first reset signal line VIL11. Thus, the first reset signal VI1 can be transmitted through the first type first reset signal line VIL11 and the first reset segment LV1 to reset the first light emitting device LD1 in the main display area AA.

For the light-emitting device LD in the sub-display area SA (the second light-emitting device LD2 and part of the first light-emitting device LD1), the pixel circuit PC (the second pixel circuit PC2 and part of the first pixel circuit PC1) connected thereto can be connected to the second reset segment LV2 of the second type first reset signal line VIL12, so that the third reset signal VI3 can be transmitted through the second reset segment LV2, thereby resetting the first electrode ANO of the light-emitting device LD in the sub-display area SA through the third reset signal VI3.

As shown in FIG. 1 , in some embodiments of the present disclosure, the driving backplane may further include a first reset bus BV1, a second reset bus BV2 and a first reset connection line LV3, wherein:

The first reset bus BV1 may be disposed in the peripheral area WA, and connected to a portion of the first reset segments LV1 of the first type first reset signal line VIL11 and the second type first reset signal line VIL12, that is, connected to a portion of each first reset signal line VIL1 located in the main display area MA. At the same time, the first reset bus BV1 extends to the fan-out area FA and is connected to the binding portion PA to transmit the third reset signal VI3.

The second reset bus BV2 may be disposed in the peripheral area and may be disposed in the same layer as the first reset bus BV1 and spaced apart. The second reset bus BV2 extends to the fan-out area FA and is connected to the binding portion PA to transmit the first reset signal VI1.

The first reset connection line LV3 can extend from the peripheral area WA to the display area AA along the column direction Y, and connect the first reset bus BV1 and the second reset segment LV2, so as to transmit the third reset signal VI3 to the second reset segment LV2 and avoid short circuit with the first reset segment LV1.

As shown in FIG. 1 , in some embodiments of the present disclosure, the first reset bus BV1 may include a first bus segment BV11, a second bus segment BV12, and a third bus segment BV13, wherein the first bus segment BV11 and the second bus segment BV12 are located on both sides of the display area AA and extend to the fan-out area FA, and are connected to the binding portion PA. The third bus segment BV13 is located on the side of the display area AA away from the fan-out area FA, and connects the first bus segment BV11 and the second bus segment BV12, thereby forming a "U"-shaped structure surrounding the display area AA. The first reset connection line LV3 may extend along the column direction Y to the peripheral area WA, and be connected to the third bus segment BV13.

The second reset bus BV2 is located on both sides of the display area AA, and is disconnected on the side of the display area AA away from the fan-out area FA. The first reset connection line LV3 can pass through the position where the second reset bus BV2 is disconnected, so as not to overlap with the second reset bus BV2. If the first reset bus BV1 and the first reset connection line LV3 are arranged on the same layer and adopt an integrated structure, the position where the second reset bus BV2 is disconnected can avoid short circuit. Of course, if the second reset bus BV2 and the first reset connection line LV3 are located on different layers, the first reset connection line LV3 can cross the second reset bus BV2.

Further, as shown in FIG. 5 and FIG. 9 , in some embodiments of the present disclosure, in the row direction X, there may be a spacing area Gap extending along the column direction Y between the main display area MA and the circuit area SA2, and the spacing area Gap may be one of the regions between two adjacent circuit groups CM, only the region between a circuit group CM closest to the main display area MA in the circuit area SA2 and a circuit group CM closest to the circuit area SA2 in the main display area MA. The first reset connection line LV3 may be located in the spacing area Gap, so that the end of the second reset segment LV2 may be connected to the first reset connection line LV3. The first reset connection line LV3 may be arranged in the same layer as each routing unit VB, for example, the first reset connection line LV3 and the routing unit VB are both located in the first source and drain layer SD1, and are connected to the second reset segment LV2 by an integral molding method.

At the same time, as shown in FIG. 5 and FIG. 9 , the first reset connection line LV3 can be arranged to cross the connection unit VL in the gap area Gap, and the connection unit VL is arranged intermittently, that is, it is divided into at least two disconnected parts in the row direction X, so as to realize the disconnection of the first reset segment LV1 and the second reset segment LV2, and prevent the first reset connection line LV3 from connecting to the first reset segment LV1. Specifically, in a first reset signal line VIL1 having a first reset segment LV1 and a second reset segment LV2, a connection unit VL is arranged intermittently in the gap area, and one end is connected to a wiring unit VB of the first reset segment LV1 through a contact hole, and the other end is connected to a wiring unit VB of the second reset segment LV2 through a contact hole. The intermittent connection unit VL here can also be completely omitted, as long as the first reset connection line LV3 can be prevented from connecting to the first reset segment LV1. The reason for setting the intermittent connection unit VL and connecting to the first reset segment LV1 and the second reset segment LV2 through the contact hole is to make the contact holes in the display area AA evenly distributed and ensure the uniformity of the morphology.

Of course, the first reset connection line LV3 can also be located between two adjacent circuit groups CM in the circuit area SA2, or between two adjacent circuit units CU, and can be connected to the routing units VB of the second reset segment LV2 on both sides thereof by means of one-piece molding, etc., but there is no need to disconnect the connection unit VL connected to the two routing units VB connected by the first reset connection line LV3.

In some embodiments of the present disclosure, if, as described above, the number of the circuit areas SA2 of the auxiliary display area SA is two, and they are separated on both sides of the light-transmitting area SA1 along the row direction X; there is a gap area Gap between the two circuit areas SA2 and the main display area MA. Accordingly, the number of the first reset connection lines LV3 may also be two, and the first reset connection lines LV3 may be provided in both gap areas Gap, and the two first reset connection lines LV3 are connected to the first reset bus BV1.

In some embodiments of the present disclosure, as shown in FIG1 , the number of auxiliary display areas SA is two, and the number of circuit areas SA2 of the auxiliary display area SA is two; there is a gap area Gap between the circuit area SA2 and the main display area MA, so there are four circuit areas SA2 and four gap areas Gap. Correspondingly, the number of first reset connection lines LV3 is four; each gap area Gap is provided with a first reset connection line LV3, and the four first reset connection lines LV3 are electrically connected to the first reset bus BV1.

As shown in FIG23 , the first reset connection line LV3 has a first end and a second end distributed along the column direction Y. Among the two first reset connection lines LV3 located on both sides of the secondary display area SA, the first ends of the two first reset connection lines LV3 are connected to the first reset bus BV1, and the second ends of the two first reset connection lines LV3 are connected through a connection line LV6 extending along the row direction X.

As shown in FIG21 , for a display panel having only one auxiliary display area SA, the first reset segments LV1 on both sides of the auxiliary display area SA are disconnected at the auxiliary display area SA, but can be extended in the reverse direction to the peripheral area WA and connected to the second reset bus BV2 to receive the first reset signal VI1. However, if there are multiple auxiliary display areas SA linearly distributed along the row direction X, the first reset segment LV1 between two adjacent auxiliary display areas SA can receive the first reset signal VI1 in the following manner:

As shown in Figures 1, 17 to 20 and 22, in some embodiments of the present disclosure, a second reset connection line LV4 extending along the column direction Y may be set in the main display area MA between two adjacent sub-display areas SA, and the second reset connection line LV4 is connected to at least one first reset signal line VIL1 (first-type first reset signal line VIL11) located outside the sub-display area SA in the column direction Y. At the same time, the second reset connection line LV4 is connected to the first reset segment LV1 between the two adjacent sub-display areas SA, so that the second reset connection line LV4 can be used to bypass the sub-display area SA and transmit the first reset signal VI1 to a reset segment LV1 between the two adjacent sub-display areas SA.

As shown in FIGS. 17 to 20, the second reset connection line LV4 can be located in the same spacing area Gap as the first reset connection line LV3, but the spacing is set on the side of the first reset connection line LV3 away from the light-transmitting area SA1. At this time, the first reset segment LV1 between the two adjacent sub-display areas SA is located on the same side of the second reset connection line LV4. Of course, at least one circuit group CM can be spaced between the second reset connection line LV4 and the first reset connection line LV3, and both sides of the second reset connection line LV4 have the first reset segment LV1. At this time, the second reset connection line LV4 crosses the connection unit VL of the first reset segment LV1, and the cross-connection unit VL with the second reset connection line LV4 is continuous in the row direction X without being disconnected, so as to ensure that the second reset connection line LV4 can transmit the first reset signal VI1 to both sides.

Further, the second reset connection line LV4 can be arranged in the same layer as the first reset connection line LV2, for example, both are arranged in the first source and drain layer SD1, and can be arranged in the same layer as the wiring unit VB. The second reset connection line LV4 can be located between two adjacent circuit groups CM in the main display area MA, or between two adjacent circuit units CU.

As shown in FIG1 , the number of the second reset connection lines LV4 can be multiple and distributed along the row direction X. For example, the number of the second reset connection lines LV4 is two and both are connected to the first reset segment LV1 between two adjacent sub-display areas SA. Meanwhile, the two second reset connection lines LV4 can be symmetrically arranged about the central axis of the area along the column direction Y between the two adjacent sub-display areas SA.

In some other embodiments of the present disclosure, the second reset connection line LV4 may also be located on the side of the wiring unit VB away from the connection unit VL. In this case, the second reset connection line LV4 may overlap with the pixel circuit PC, as long as the first reset signal VI1 can be transmitted to the first reset segment LV1 in the main display area MA between two adjacent sub-display areas SA.

As shown in FIG. 22 , in other embodiments of the present disclosure, for the first reset segments LV1 separated by the auxiliary display area SA on the same first reset signal line VIL1, the first reset segments LV1 on both sides of the auxiliary display area SA can be connected by a lead LV5 bypassing the auxiliary display area SA, and the lead LV5 can be located at any film layer of the driving backplane BP, or at any film layer between the driving backplane BP and the light-emitting device LD. At the same time, the lead LV5 can be located in the same film layer, or can include different line segments located in multiple film layers, as long as it can play the aforementioned connection role.

Further, as shown in FIG22 , two first reset segments LV1 of the same first reset signal line VIL1 separated by a secondary display area SA in the row direction X are connected via a lead LV5; at least part of the lead LV5 is located on a side of the first reset segment LV1 connected thereto close to the fan-out area FA, or at least part of the lead LV5 is located on a side of the first reset segment LV1 connected thereto far from the fan-out area FA. For example:

In some embodiments of the present disclosure, each lead LV5 can be divided into two parts, and the number of leads LV5 in the two parts can be the same or different; wherein, one part of the lead LV5 is located on the side of the first reset segment LV1 to which it is connected close to the fan-out area FA, and the other part of the lead LV5 is located on the side of the first reset segment LV1 to which it is connected away from the fan-out area FA, which can avoid excessive concentration of the leads LV5 and facilitate full utilization of the space for routing.

In some embodiments of the present disclosure, each lead LV5 is located at a side of the first reset segment LV1 to which it is connected that is close to the fan-out area FA.

In some embodiments of the present disclosure, each lead LV5 is located at a side of the first reset segment LV1 to which it is connected, away from the fan-out area FA.

The embodiment of the present disclosure also provides a display device, which can be a mobile phone, a tablet computer, a television or other electronic device with an under-screen camera function, which will not be listed here one by one. As shown in FIG. 23, the display device of the present disclosure may include a display panel PNL and a photosensitive element CAU, wherein:

The display panel PNL may be any of the display panel PNL in the above embodiments, and its structure may refer to the embodiments of the display panel PNL in the above text, which will not be described in detail here.

The photosensitive element CAU may be disposed on a side of the driving back plate BP away from the light emitting device LD, and the orthographic projection of the photosensitive element CAU on the driving back plate BP at least partially overlaps with the orthographic projection of the light-transmitting area SA1 on the driving back plate BP.

In some embodiments of the present disclosure, there are multiple auxiliary display areas SA, the number of photosensitive elements CAU is the same as the number of auxiliary display areas SA, and each photosensitive element CAU is overlapped with the light-transmitting area SA1 of each auxiliary display area SA in a one-to-one correspondence.

External light can pass through the light-transmitting area SA1 to illuminate the corresponding photosensitive element CAU, and the photosensitive element CAU can generate an electrical signal according to the light passing through the corresponding light-transmitting area SA1 to generate an image. The photosensitive element CAU may include an image sensor, such as a CCD image sensor or a CMOS image sensor.

The photosensitive element CAU may generate an image based on visible light, and may also generate an image based on infrared or other light. For example, the photosensitive element CAU may include an infrared sensor, which forms an infrared image by receiving infrared light from the outside world, so as to recognize fingerprint patterns, iris patterns, facial patterns, etc. according to the infrared image. Alternatively, the photosensitive element CAU may also include an illumination sensor, which may measure the illumination around the display device, and the display panel PNL may adjust the brightness of the display panel based on the measured illumination. In addition, the photosensitive element CAU may also use a laser radar (Light Detection and Ranging, LIDAR) sensor, etc.

The photosensitive element CAU can be used not only in cameras that capture images, but also in small lamps that output light to measure distance by outputting and detecting light.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims (18)

1. A display panel comprises a display area and a peripheral area at least partially surrounding the display area; the display area comprises a secondary display area and a main display area located at at least one side of the secondary display area, the secondary display area comprises a light-transmitting area and a circuit area located at at least one side of the light-transmitting area;

   A driving backplane, comprising a plurality of pixel circuits distributed in an array and a plurality of first reset signal lines, wherein the pixel circuits include a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is located in the main display area and the circuit area, and the second pixel circuit is located in the circuit area; wherein the plurality of first reset signal lines extend along a first direction, and some of the plurality of first reset signal lines are first-type first reset signal lines, and some of the first reset signal lines are second-type first reset signal lines; wherein the second-type first reset signal lines include a first reset segment and a second reset segment intermittently arranged along the first direction; wherein the first reset segment is located in the main display area, and the second reset segment is located in the circuit area;

   A plurality of light-emitting devices are located on one side of the driving backplane, and include a first light-emitting device located in the main display area and the circuit area and a second light-emitting device located in the light-transmitting area; the first light-emitting device is connected to the first pixel circuit, and the second light-emitting device is connected to the second pixel circuit via a transfer line;

   The first reset segment is connected to part of the first pixel circuit in the main display area, and the first reset segment is configured to provide a first reset signal to the first pixel circuit in the main display area; the second reset segment is connected to the first pixel circuit and the second pixel circuit in the circuit area, and the second reset segment is configured to provide a second reset signal to the first pixel circuit and the second pixel circuit in the circuit area.
2. The display panel according to claim 1, wherein the driving backplane further comprises:

   A first reset bus located in the peripheral area;

   a second reset bus located in the peripheral area and spaced apart from the first reset bus, the second reset bus being connected to the first reset segment of the main display area;

   A first reset connection line extends from the peripheral area to the display area along a second direction, the first reset connection line connecting the first reset bus and the second reset segment;

   The first direction and the second direction intersect.
3. The display panel according to claim 2, wherein in the first direction, there is a spacing area extending along the second direction between the main display area and the circuit area, and the first reset connection line is located in the spacing area.
4. The display panel according to claim 3, wherein the number of the circuit areas of the auxiliary display area is two, and they are respectively located on both sides of the light-transmitting area along the first direction; and the spacing area is provided between the two circuit areas and the main display area;

   The number of the first reset connection lines is two, and the first reset connection lines are arranged in the two interval areas, and the two first reset connection lines are connected to the first reset bus.
5. The display panel according to claim 4, wherein the number of the auxiliary display areas is two, and the number of the first reset connection lines is four; the first reset connection line is provided in each of the spacing areas, and the four first reset connection lines are all connected to the first reset bus.
6. The display panel according to claim 5, wherein, among the two first reset connection lines located on both sides of the auxiliary display area, the first ends of the two first reset connection lines are connected to the first reset bus, and the second ends of the two first reset connection lines are connected through a connecting line extending along the first direction.
7. The display panel according to claim 4, wherein the peripheral area includes a fan-out area extending in a direction away from the display area;

   The first reset bus includes a first bus segment, a second bus segment and a third bus segment, wherein the first bus segment and the second bus segment are located at both sides of the display area and extend to the fan-out area; the third bus segment is located at a side of the display area away from the fan-out area and connects the first bus segment and the second bus segment; the first reset connection line is connected to the third bus segment;

   The second reset bus is located at both sides of the display area and extends to the fan-out area. The second reset bus is disconnected at a side of the display area away from the fan-out area. The first reset connection line passes through the position where the second reset bus is disconnected.
8. The display panel according to claim 7, wherein the number of the auxiliary display areas is plural and they are spaced apart along the first direction;

   The main display area between two adjacent auxiliary display areas is provided with a second reset connection line extending along the second direction; at least one first-type first reset signal line is connected to the first reset segment between two adjacent auxiliary display areas through the second reset connection line.
9. The display panel according to claim 8, wherein the number of the second reset connection lines between the two auxiliary display areas is two, and they are spaced apart along the first direction; and the first reset segments between two adjacent auxiliary display areas are connected by two second reset connection lines.
10. The display panel according to claim 7, wherein two first reset segments of the same first reset signal line separated by the auxiliary display area in the first direction are connected by a lead; at least part of the lead is located on a side of the first reset segment to which it is connected close to the fan-out area, or at least part of the lead is located on a side of the first reset segment to which it is connected away from the fan-out area.
11. The display panel according to claim 8, wherein the first reset signal line comprises a plurality of routing units distributed along the first direction and a connecting unit connected to two adjacent routing units, and the connecting unit and the routing unit are located in different layers;

    The first reset section and the second reset section both include a plurality of routing units and a plurality of connecting units;

    In a first reset signal line having the first reset section and the second reset section, a connection unit is intermittently arranged in the spacing area, and one end is connected to a routing unit of the first reset section, and the other end is connected to a routing unit of the second reset section;

    The first reset connection line crosses the discontinuously arranged connection units.
12. The display panel according to claim 11, wherein the routing unit, the first reset connection line and the second reset connection line are arranged in the same layer and are located on a side of the connection unit close to the light-emitting device.
13. The display panel according to claim 11, wherein the first reset connection line and the second reset connection line are arranged in the same layer and are located on a side of the routing unit away from the connection unit.
14. The display panel according to claim 11, wherein the second reset connection line crosses and is connected to a portion of the connection units.
15. The display panel according to claim 3, wherein each of the pixel circuits is divided into a plurality of circuit groups distributed in an array; one of the circuit groups includes a plurality of circuit units distributed along the first direction; one of the circuit units includes two of the pixel circuits distributed along the first direction;

    In the first direction, the distance between two adjacent circuit groups is greater than the distance between two adjacent pixel circuits; the two pixel circuits of the same circuit unit are symmetrically arranged about a straight line extending along the second direction;

    The spacing area is a partial area between two adjacent circuit groups.
16. The display panel according to claim 12, wherein the pixel circuit comprises a first reset transistor;

    In the circuit area, the second reset segment is connected to the light emitting device through the first reset transistor;

    In the main display area, the first reset segment is connected to the light emitting device through the first reset transistor.
17. The display panel according to any one of claims 1 to 16, wherein the display panel further comprises:

    The transfer layer is arranged between the driving backplane and the light-emitting device, and includes the transfer line, which extends from the circuit area to the light-transmitting area. At least one of the second light-emitting devices is connected to at least one of the second pixel circuits through at least one of the transfer lines.
18. A display device, comprising:

    The display panel according to any one of claims 1 to 17;

    The photosensitive element is located on a side of the driving backplane away from the plurality of light-emitting devices, and the orthographic projection of the photosensitive element on the driving backplane at least partially overlaps with the orthographic projection of the light-transmitting area on the driving backplane.

Images