WO2024031531A1 - Display panel and display apparatus - Google Patents

Abstract

A display panel and a display apparatus. A display area of the display panel comprises a secondary display area and a primary display area, the secondary display area comprising a light-transmitting area and a circuit area. A drive back plate comprises pixel circuits and first reset signal lines; the pixel circuits comprise first pixel circuits and second pixel circuits; some of the first pixel circuits are located in the primary display area and the circuit area, and the second pixel circuits are located in the circuit area; some of the first reset signal lines comprise first reset sections and second reset sections which are discontinuously arranged in a first direction; the first reset sections are located in the primary display area, and the second reset sections are located in the circuit area; light-emitting devices comprise first light-emitting devices located in the primary display area and the circuit area, and second light-emitting devices located in the light-transmitting area; the first light-emitting devices in the primary display area are connected, by means of the first pixel circuits in the primary display area, to the part of the first reset signal lines located in the primary display area; and the light-emitting devices in the secondary display area are connected to the second reset sections by means of the pixel circuits in the circuit area.

Description

Display panels and display devices Technical field

The present disclosure relates to the field of display technology, and specifically, to a display panel and a display device.

Background technique

With the development of display technology, Full Display with Camera (FDC) with a camera has been gradually used in display products due to its large screen-to-body ratio. Full-screen display devices usually place optical components such as cameras in the under-screen area of the display panel, greatly increasing the screen-to-body ratio.

It should be noted that the information disclosed in the above background section is only used to enhance understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.

Contents of the invention

The present disclosure provides a display panel and a display device.

According to an aspect of the present disclosure, a display panel is provided, having a display area and a peripheral area at least partially surrounding the display area; the display area includes a secondary display area and a main display area located on at least one side of the secondary display area , the secondary display area includes a light-transmitting area and a circuit area located on at least one side of the light-transmitting area;

The driving backplane includes a plurality of pixel circuits distributed in an array and a plurality of first reset signal lines. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit is located in the main display area and the main display area. The circuit area, the second pixel circuit is located in the circuit area; the plurality of first reset signal lines extend along the first direction, and part of the first reset signal in the plurality of first reset signal lines The lines are first type first reset signal lines, and part of the first reset signal lines are second type first reset signal lines; the second type first reset signal lines include a third type intermittently arranged along the first direction. A reset section and a second reset section; the first reset section is located in the main display area, and the second reset section is located in the circuit area;

A plurality of light-emitting devices located on one side of the driving backplane, and including a first light-emitting device located in the main display area and the circuit area and a second light-emitting device located in the light-transmitting area; the first light-emitting device The device is connected to the first pixel circuit, and the second light-emitting device is connected to the second pixel circuit through a transfer line;

The first reset section is connected to part of the first pixel circuit in the main display area, and the first reset section is configured to provide a first reset signal to the first pixel circuit in the main display area. ; The second reset section is connected to the first pixel circuit and the second pixel circuit of the circuit area, and the second reset section is configured to provide a signal to the first pixel circuit and the second pixel circuit of the circuit area. The second pixel circuit provides a second reset signal.

In an exemplary implementation of the present disclosure, the driving backplane further includes:

A first reset bus located in the peripheral area;

A second reset bus is located in the peripheral area and is spaced apart from the first reset bus. The second reset bus is connected to the first reset segment of the main display area;

A first reset connection line extends from the peripheral area to the display area along the second direction, and the first reset connection line connects the first reset bus and the second reset segment;

The first direction and the second direction intersect.

In an exemplary embodiment of the present disclosure, in the first direction, there is a spacing area extending along the second direction between the main display area and the circuit area, and the first reset connection The line is located within the spacer area.

In an exemplary embodiment of the present disclosure, the number of circuit areas in the secondary display area is two, and they are located on both sides of the light-transmitting area along the first direction; two circuit areas The spacer area is provided between the main display area and the main display area;

The number of the first reset connection lines is two, and the first reset connection lines are provided in the two separation areas, and the two first reset connection lines are connected to the first reset bus. .

In an exemplary embodiment of the present disclosure, the number of the secondary display areas is two, and the number of the first reset connection lines is four; the first reset connection is provided in each of the separation areas. lines, and the four first reset connection lines are all connected to the first reset bus.

In an exemplary embodiment of the present disclosure, among the two first reset connection lines located on both sides of a secondary display area, the first ends of the two first reset connection lines are connected to the first reset connection lines. The first reset bus is connected, and the second ends of the two first reset connection lines are connected through connecting wires extending along the first direction.

In an exemplary embodiment of the present disclosure, the peripheral area includes a fan-out area extending in a direction away from the display area;

The first reset bus includes a first bus segment, a second bus segment and a third bus segment, the first bus segment and the second bus segment are located on both sides of the display area and extend to the fan-out area; The third bus segment is located on a side of the display area away from the fan-out area and connects the first bus segment and the second bus segment; the first reset connection line and the third bus segment connect;

The second reset bus is located on both sides of the display area and extends to the fan-out area. The second reset bus is disconnected on a side of the display area away from the fan-out area. A reset connection line passes through the disconnected position of the second reset bus.

In an exemplary embodiment of the present disclosure, the number of the secondary display areas is multiple, and they are spaced apart along the first direction;

The main display area between two adjacent secondary display areas is provided with a second reset connection line extending along the second direction; at least one of the first type first reset signal lines is connected to two adjacent secondary display areas. The first reset sections between regions are connected by the second reset connection line.

In an exemplary embodiment of the present disclosure, the number of second reset connection lines between two secondary display areas is two, and they are spaced apart along the first direction; two adjacent secondary display areas The first reset sections between zones are connected by two second reset connection lines.

In an exemplary embodiment of the present disclosure, two first reset sections of the same first reset signal line that are separated by one of the secondary display areas in the first direction are connected by wires; at least Part of the lead wire is located on the side of the first reset section to which it is connected, close to the fan-out area, or at least part of the lead wire is located on the side of the first reset section to which it is connected, away from the fan-out area.

In an exemplary embodiment of the present disclosure, the first reset signal line includes a plurality of wiring units distributed along the first direction and a connection unit connected to two adjacent wiring units, and the The connection unit and the wiring unit are located on different layers;

Both the first reset section and the second reset section include a plurality of wiring units and connection units;

In a first reset signal line having the first reset section and the second reset section, a connection unit is intermittently provided in the spacing area, and one end is connected to an end of the first reset section. The wiring unit is connected, and the other end is connected to a wiring unit of the second reset section;

The first reset connection line crosses the intermittently arranged connection units.

In an exemplary embodiment of the present disclosure, the wiring unit, the first reset connection line and the second reset connection line are arranged on the same layer, and are located on a side of the connection unit close to the light-emitting device. side.

In an exemplary embodiment of the present disclosure, the first reset connection line and the second reset connection line are arranged on the same layer and are located on a side of the wiring unit away from the connection unit.

In an exemplary embodiment of the present disclosure, the second reset connection line is disposed across and connected to part of the connection unit.

In an exemplary implementation of the present disclosure, each of the pixel circuits is divided into a plurality of circuit groups distributed in an array; one of the circuit groups includes a plurality of circuit units distributed along the first direction; one of the circuits The unit includes two of the pixel circuits distributed along the first direction;

In the first direction, the distance between two adjacent circuit groups is greater than the distance between two adjacent pixel circuits; two pixel circuits of the same circuit unit are aligned with a straight line extending along the second direction. Symmetrical settings;

The spacing area is a partial area between two adjacent circuit groups.

In an exemplary embodiment of the present disclosure, the pixel circuit includes a first reset transistor;

In the circuit area, the second reset section is connected to the light-emitting device through the first reset transistor;

In the main display area, the first reset segment is connected to the light-emitting device through the first reset transistor.

In an exemplary implementation of the present disclosure, the display panel further includes:

A transfer layer is provided between the driving backplane and the light-emitting device, and includes the transfer line, which extends from the circuit area to the light-transmitting area, and at least one of the second light-emitting devices The device is connected to at least one of the second pixel circuits through at least one of the transfer lines.

According to an aspect of the present disclosure, a display device is provided, including:

The display panel described in any of the above;

The photosensitive element is located on the side of the driving backplane away from the plurality of light-emitting devices. The orthographic projection of the photosensitive element on the driving backplane and the orthographic projection of the light-transmitting area on the driving backplane are at least partially overlap.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a top view of a display panel according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram showing the partial distribution of pixel circuits and light-emitting devices of a display panel according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a pixel circuit in an embodiment of the display panel of the present disclosure.

FIG. 4 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

Figure 5 is a partial view of part A in Figure 1 .

FIG. 6 is a schematic diagram of the first semiconductor layer and the first gate layer in FIG. 5 .

FIG. 7 is a schematic diagram of the first semiconductor layer to the second gate electrode layer in FIG. 5 .

FIG. 8 is a schematic diagram of the first semiconductor layer to the third gate layer in FIG. 5 .

FIG. 9 is a schematic diagram of the first semiconductor layer to the first source and drain layer in FIG. 5 .

Figures 10 to 16 are partial schematic views of some of the film layers in Figure 5 respectively.

Figure 17 is a partial view of part B in Figure 5.

Figures 18-20 are partial schematic views of some of the film layers in Figure 17.

FIG. 21 is a top view of another embodiment of the display panel of the present disclosure.

FIG. 22 is a top view of another embodiment of the display panel of the present disclosure.

FIG. 23 is a top view of another embodiment of the display panel of the present disclosure.

FIG. 24 is a top view of a display device according to an embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art. The same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "include" and "have" are used to indicate an open-ended are inclusive and mean that there may be additional elements/components/etc. in addition to those listed; the terms "first", "second", "third" etc. are only Used as a marker, not a limit on the number of its objects.

In this article, the first direction can be represented by the row direction X, and the second direction can be represented by the column direction Y. The row direction In the drawings of the present disclosure, the row direction

The "overlap" of feature A and feature B in this article means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.

In this article, the A feature and the B feature "same layer" means that the A feature and the B feature can be formed at the same time. They are discontinuous or continuous different areas in the same film layer, and in the direction perpendicular to the substrate, both Not separated by other membrane layers. "Different layers" means that the A feature and the B feature are spaced apart in a direction perpendicular to the substrate, and they are separated by other film layers.

Embodiments of the present disclosure provide a display panel. As shown in FIGS. 1 and 2 , the display panel may have a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous area surrounding the display area AA. Or an intermittent annular area, that is, the peripheral area WA is at least partially set around the display area AA. The shape of the peripheral area WA is not specifically limited here.

The peripheral area WA may include a fan-out area FA extending in a direction away from the display area AA, and the display area AA and the fan-out area FA may be distributed along the column direction Y. The fan-out area FA has a binding part PA. The binding part PA can be provided with a plurality of pads. Each pad can be bound to the flexible circuit board, so that the display panel can be controlled through the control circuit board bound to the flexible circuit board. The display area AA emits light to display images.

The display area AA may include a main display area MA and a sub-display area SA. The main display area MA is located outside the sub-display area SA. In the row direction The display area MA may surround the sub-display area SA, or the boundary of the main display area MA may partially coincide with the boundary of the sub-display area SA.

The sub-display area SA may include a light-transmitting area SA1 and a circuit area SA2 outside the light-transmitting area SA1. In the row direction X, the circuit area SA2 is located on at least one side of the light-transmitting area SA1. Both the light-transmitting area SA1 and the circuit area SA2 can emit light, but the light transmittance of the light-transmitting area SA1 is greater than that of the circuit area SA2 in order to achieve under-screen imaging. The shape of the light-transmitting area SA1 may be a circle, an ellipse, a polygon such as a rectangle, or other regular or irregular shapes, which are not particularly limited here. At least part of the circuit area SA2 and the light-transmitting area SA1 can be distributed along the row direction X. For example: a display area SA has one light-transmitting area SA1 and two circuit areas SA2, and the two circuit areas SA2 are along the row Directions

As shown in FIGS. 2 and 4 , the display panel may include a driving backplane BP and a plurality of light-emitting devices LD disposed on one side of the driving backplane BP. The driving backplane BP has a driving circuit for driving the light-emitting devices LD to emit light. The driving circuit may include a pixel circuit PC located in the display area AA and a peripheral circuit located in the peripheral area WA, where:

There are multiple pixel circuits PC, and the arrays are distributed in multiple rows and columns along the row direction X and column direction Y. One pixel circuit PC can be connected to one light-emitting device LD. Of course, there can also be one pixel circuit PC connected to multiple In the case of the light-emitting device LD, this article only takes the one-to-one connection between the pixel circuit PC and the light-emitting device LD as an example. Among them, the pixel circuit PC can be distributed in the circuit area SA2 of the main display area and the sub-display area SA, and the pixel circuit PC is not provided in the light-transmitting area SA1 to improve the light transmittance of the light-transmitting area SA1. Specifically, each pixel circuit PC can be divided into a first pixel circuit PC1 and a second pixel circuit PC2. The first pixel circuit PC1 is distributed in the main display area MA and the circuit area SA2, and the second pixel circuit PC2 is located in the circuit area SA2. That is to say, the circuit area SA2 has both the first pixel circuit PC1 and the second pixel circuit PC2, while the main display area MA only has the first pixel circuit PC1.

The pixel circuit PC can include multiple transistors and capacitors, which can be 3T1C, 7T1C, 8T1C and other pixel circuits. nTmC means that a pixel circuit PC includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C"). "express).

The peripheral circuit can be connected to the pixel circuit PC and the light-emitting device LD, and can control the current passing through the light-emitting device LD through the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD. The peripheral circuit may include a gate drive circuit, a light-emitting control circuit, etc., and of course may also include other circuits. The specific structure of the peripheral circuit is not particularly limited here.

Each light-emitting device LD can be disposed on one side of the driving backplane BP and located in the display area AA. The light-emitting device LD is provided in the light-transmitting area SA1 and the circuit area SA2 of the main display area MA and the sub-display area SA, so that the entire display area AA All can shine. Meanwhile, the light emitting device LD may include the first electrode ANO, the light emitting layer EL and the second electrode CAT stacked in a direction away from the driving backplane BP. The light-emitting device LD can be an OLED (organic light-emitting diode), of course, it can also be a Micro LED (micron light-emitting diode) and Mini LED (sub-millimeter light-emitting diode), or it can also be a light-emitting device such as QLED (quantum dot diode).

As shown in FIG. 4 , the first electrode ANO can be disposed on one side of the driving backplane BP and distributed in an array. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the driving backplane BP. Each light-emitting device LD can share the second electrode CAT. That is to say, the second electrode CAT can be a continuous whole-layer structure, and the second electrode CAT can extend to the peripheral area and can receive the second power signal VSS. The first electrode ANO is distributed in an array and connected to the pixel circuit PC to ensure that each light-emitting device LD can emit light independently. In addition, in order to limit the light-emitting range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL can be provided on the surface where the first electrode ANO is provided, which can have openings exposing each first electrode ANO, and the light-emitting layer EL is connected to the first electrode ANO in the opening. One electrode ANO is stacked.

Each light-emitting device LD can at least share a light-emitting material layer, so that the light-emitting color of each light-emitting device LD is the same. At this time, in order to achieve color display, a color film layer can be provided on the side of the light-emitting device LD away from the driving backplane BP. Through the color film The filter portion corresponding to each light-emitting device LD in the layer realizes color display. Of course, the light-emitting material layers of each light-emitting device LD can also be independent, so that the light-emitting device LD can directly emit monochromatic light, and the light-emitting colors of different light-emitting devices LD can be different, thereby achieving color display.

As shown in Figure 2, based on the above division of the pixel circuit PC, the light-emitting device can be divided into a first light-emitting device LD1 and a second light-emitting device LD2. The first light-emitting device LD1 is distributed in the main display area MA and the circuit area. SA2, the second light-emitting device LD2 is distributed in the light-transmitting area SA1. At the same time, in order to drive each light-emitting device LD, in the main display area MA and the circuit area SA2, the first light-emitting device LD1 can be connected to the first pixel circuit PC1 , thereby emitting light under the driving of the first pixel circuit PC1, and the second light-emitting device LD2 can be connected to the second pixel circuit PC2 through the adapter line CL, and the adapter line CL can extend from the light-transmitting area SA1 to the circuit area SA2. For example:

As shown in FIGS. 2 and 4 , in some embodiments of the present disclosure, the display panel may include a transfer layer BL, which may be provided between the driving backplane BP and the light emitting device LD, and may extend from the circuit area SA2 to At least one second light-emitting device LD2 is connected to at least one second pixel circuit PC2 through a plurality of transfer lines CL in the light-transmitting area SA1. For example, a second light-emitting device LD2 is connected to a second pixel circuit PC2 through a transfer line CL, so that a second pixel circuit PC2 only drives one second light-emitting device LD2; or, a second light-emitting device LD2 passes through multiple Each transfer line CL is connected to a plurality of second pixel circuits PC2 respectively, so that the plurality of second pixel circuits PC2 can all drive the same second light-emitting device LD2; or, the plurality of second light-emitting devices LD2 are respectively connected to a plurality of second pixel circuits PC2 through a plurality of transfer lines CL. The same second pixel circuit PC2 is connected, so that one second pixel circuit PC2 can drive multiple second light-emitting devices LD2.

The adapter line CL can be made of a transparent conductive material, and its material can include indium tin oxide (ITO) and other transparent conductive materials to reduce the impact on the light transmittance of the light transmitting area SA1. In addition, the transfer lines CL connected to each second light-emitting device LD2 may be located on the same layer, or may be distributed on multiple layers. For example, the transfer layer BL may include multiple wiring layers alternately distributed in a direction away from the driving backplane BP. and planarization layers, the specific number is not specifically limited here, so that each wiring layer is covered by a planarization layer, and each wiring layer can be provided with a partial transfer line CL to increase the wiring space.

In addition, the display panel may also include an encapsulation layer covering each light-emitting device LD, which may adopt a thin film encapsulation method. For example, the encapsulation layer includes a first inorganic layer, an organic layer and a second inorganic layer, wherein: the first inorganic layer may cover Each light-emitting device, that is, the first inorganic layer can cover the surface of the second electrode CAT away from the driving backplane BP. The material of the first inorganic layer may include inorganic insulating materials such as silicon nitride and silicon oxide. The organic layer can be disposed on the surface of the first inorganic layer away from the driving backplane BP, and the boundary of the organic layer can be limited to the inside of the boundary of the first inorganic layer by a barrier dam located in the peripheral area WA. The material of the organic layer can be resin. and other organic materials.

The second inorganic layer can cover the organic layer and the first inorganic layer that is not covered by the organic layer, can block the intrusion of water and oxygen through the second inorganic layer, and achieve planarization through the organic layer with fluidity (during the manufacturing process). The material of the second inorganic layer may include inorganic insulating materials such as silicon nitride and silicon oxide.

In addition, the display panel may also include other film layers such as a touch layer and a transparent cover disposed on a side of the encapsulation layer away from the driving backplane BP. The transparent cover may be disposed on a side of the touch layer away from the driving backplane BP.

Taking the touch layer adopting a mutual capacitance touch structure as an example, the touch layer may include a plurality of first touch electrodes and a plurality of second touch electrodes, and each first touch electrode may be distributed at intervals along the row direction X. The first touch electrodes may include a plurality of first electrode blocks spaced apart along the column direction Y and a transfer bridge connecting two adjacent first electrode blocks; each second touch electrode may be spaced apart along the column direction Y. The two touch electrodes include a plurality of second electrode blocks connected in series along the row direction X; a transfer bridge crosses and is insulated from a second touch electrode. One of the first touch electrode and the second touch electrode can be used as a transmitting electrode, and the other can be used as a receiving electrode, and both are connected to a peripheral touch driving circuit.

The following is an example of a pixel circuit PC with a 7T1C structure:

As shown in Figures 3-9, the transistors of the pixel circuit PC may include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, Two reset transistors T7 and storage capacitor Cst. Each transistor includes a gate electrode, a first electrode and a second electrode. The first electrode and the second electrode can be turned on or off by applying a control signal to the gate electrode. The storage capacitor Cst may include overlapping first and second plates.

As shown in FIG. 3 , the gate electrode of the first light-emitting control transistor T5 is used to input the light-emitting control signal EM, the first electrode is used to input the first power signal VDD, and the second electrode is connected to the first electrode of the driving transistor T3. The gate electrode of the driving transistor T3 is connected to the first node N1, the second electrode and the first electrode of the second light emitting control transistor T6 are connected to the second node N2, and the second electrode of the second light emitting control transistor T6 is connected to the second electrode of a light emitting device LD. The first electrode ANO is connected, and the gate of the second light emission control transistor T6 is used to input the light emission control signal EM.

The gate of the first reset transistor T1 is used to input the first reset control signal RE1, the first electrode is used to input the first reset signal VI1, that is, the first reset signal, and the second electrode of the second light emitting control transistor T6 is used to input the first reset signal RE1. The electrode ANO is connected to the fourth node N4.

The gate electrode of the writing transistor T4 is used to input the first scanning signal Gate1, the first electrode is used to input the data signal DA, and the second electrode is connected to the first electrode of the driving transistor T3 and the second electrode of the first light-emitting control transistor T5. The third node N3.

The gate electrode of the compensation transistor T2 is used to input the second scanning signal Gate2, the first electrode and the driving transistor T3 are connected to the second node N2, and the second electrode is connected to the first node N1.

The gate electrode of the second reset transistor T7 is used to input the second reset control signal RE2, the first electrode is used to input the second reset signal VI2, and the second electrode is connected to the first node N1.

The first plate of the storage capacitor Cst is used to input the first power signal VDD, and the second plate is connected to the first node N1.

The following explains the working principle of the above pixel circuit PC:

In the reset phase t1: the second reset transistor T7 can be turned on through the second reset control signal RE2, and the first reset signal VI2 can be written to the first node N1. At the same time, the first reset transistor T1 is turned on through the first reset control signal RE1, and the first reset signal VI1 is written to the fourth node N4. Thereby, the gate of the driving transistor T3 and the light emitting device LD can be reset.

In the writing phase t2: the writing transistor T4 and the compensation transistor T2 are turned on through the first scanning signal Gate1 and the second scanning signal Gate2, and the data signal DA is written to the first node N1 through the third node N3 and the second node N2. , until the potential reaches Vdata+vth, where Vdata is the voltage of the data signal DA, and Vth is the threshold voltage of the driving transistor T3. The first scanning signal Gate1 and the second scanning signal Gate2 may be the same signal, or they may be two synchronized signals. In addition, the first scanning signal Gate1 and the second scanning signal Gate2 may be high-frequency signals, which is beneficial to reducing the load of the source signal of the driving transistor T3.

In the light-emitting stage t3: the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on through the light-emitting control signal EM, and the driving transistor T3 is turned on under the action of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD. On, under the action of the first power signal VDD and the second power signal VSS, the light-emitting device LD emits light. During this process, the first electrode of the driving transistor T3 serves as the source electrode, and the second electrode serves as the drain electrode.

The output current of drive transistor T3 satisfies the following formula:

I＝(μWCox/2L)(Vgs-Vth) ²

Among them, I is the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, L is the channel length of the driving transistor T3, Vgs is the gate-source voltage difference (the voltage difference between the gate and the source) of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

According to the above formula for the output current of the driving transistor T3, by adding the gate voltage Vdata+Vth and the source voltage VDD of the driving transistor T3 in the pixel circuit PC of the present disclosure into the above formula, we can obtain: the output current I of the driving transistor T3 = (μWCox/ 2L)(Vdata+Vth-VDD-Vth) ² . It can be seen that the output current of the pixel circuit PC has nothing to do with the threshold voltage Vth of the driving transistor T3, but is only related to Vdata, thereby eliminating the impact of the threshold voltage of the driving transistor T3 on its output current, and only passing through the voltage of the data signal DA Vdata can control the output current to control the brightness of the light-emitting device LD.

Each transistor of the above-mentioned pixel circuit PC can be a polycrystalline silicon transistor, that is, the channel of the transistor is polycrystalline silicon, such as a P-type low-temperature polysilicon transistor or an N-type low-temperature polysilicon transistor. Of course, metal oxide transistors can also be used, that is, the channels of the transistors are metal oxides such as indium gallium zinc oxide. Among them, the P-type low-temperature polysilicon transistor can be turned off when a high level is input to its gate and turned on when a low-level signal is input; the N-type low-temperature polysilicon transistor can be turned off when a low level is input to its gate and turned on when a low-level signal is input. Turns on when the signal is high. The metal oxide transistor can be an N-type metal oxide transistor, which can be turned on when the gate input is high level and turned off when the gate input is low level.

In some embodiments of the present disclosure, the above-mentioned 7T1C pixel circuit may adopt LTPO (LTPS+Oxide) technology. Specifically, the driving transistor T3, the writing transistor T4, the first reset transistor T1, the first light-emitting control transistor T5 and The second light emission control transistor T6 can be a P-type low-temperature polysilicon transistor; the second reset transistor T7 and the compensation transistor T2 can be an N-type metal oxide transistor. Since P-type low-temperature polysilicon transistors have higher carrier mobility, they are conducive to realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio in order to obtain higher carrier mobility. Improve response speed. At the same time, leakage can be reduced through N-type metal oxide transistors.

As shown in Figure 6, based on the above pixel circuit PC using LTPO technology, in some embodiments of the present disclosure, each pixel circuit PC can be divided into multiple array-distributed circuit groups CM. One circuit group CM can include A plurality of circuit units CU are distributed along the row direction X. One circuit unit CU may include two pixel circuits PC distributed along the row direction X. At the same time, in the row direction Symmetrical setting. The symmetrical setting here refers to: the two pixel circuits PC are completely symmetrical or the transistors of the two pixel circuits PC are symmetrical.

The above-mentioned signals input to the pixel circuit PC can all be transmitted through wiring. The wiring for transmitting each of the above signals is explained below:

As shown in Figures 5-9, the driving backplane BP may include a plurality of walking lines extending at least partially along the row direction REL1, the first reset signal line VIL1, the second reset control line REL2, the second reset signal line VIL2, the first scanning line GAL1, the second scanning line GAL2 and the emission control line EML, where:

For a pixel circuit PC:

The first reset control line REL1 may be connected to the gate of the first reset transistor T1 for transmitting the first reset control signal RE1. The first reset signal line VIL1 may be connected to the first pole of the first reset transistor T1 for transmitting the first reset signal VI1 to the first electrode ANO of the light emitting device LD.

In some embodiments of the present disclosure, the first reset signal line VIL1 may include a plurality of wiring units VB distributed along the row direction X and a connection unit VL connected to two adjacent wiring units VB, and the connection unit VL and the wiring unit VL The line units VB are located on different layers, so that other lines on the same layer as the line units VB can pass through between two adjacent line units VB. Further, the wiring unit VB can be located within the range of the above-mentioned circuit group CM, and the connection unit VL is located between two adjacent circuit groups CM. That is to say, two adjacent wiring units VB are spanned by the connection unit VL. The area between two adjacent circuit groups CM.

The second reset control line REL2 may be connected to the gate of the second reset transistor T7 for transmitting the second reset control signal RE2. The second reset signal line VIL2 is connected to the first pole of the second reset transistor T7 for transmitting the second reset signal VI2.

The first scan line GAL1 may be connected to the gate of the writing transistor T4 for transmitting the first scan signal Gate1. The second scan line GAL2 may be connected to the gate of the compensation transistor T2 for transmitting the second scan signal Gate2.

The emission control line EML may be connected to the gate of the first emission control transistor T5 and the gate of the second emission control transistor T6 for transmitting the emission control signal.

In addition to the above-mentioned walking lines, the driving backplane BP also includes column lines extending along the column direction Y, including a data line DAL and a power line VDL. A data line DAL and a write transistor T4 of each pixel circuit PC in a column of pixel circuits PC The first pole connection is used to transmit the data signal DA. A power line VDL may be connected to the second plate Cst2 of each pixel circuit PC in a column of pixel circuits PC and the first pole of the first light-emitting control transistor T5 for transmitting the first power signal VDD.

Based on the above-mentioned 7T1C pixel circuit, the following is a detailed description of each film layer of the driving backplane BP:

As shown in FIG. 4 , in some embodiments of the present disclosure, the driving backplane BP may include a substrate SU, a first semiconductor layer POL, a first gate insulating layer GI1 , a first gate layer GA1 , and a first insulating layer ILD0 , the second gate layer GA2, the second insulating layer ILD1, the second semiconductor layer IGL, the second gate insulating layer GI2, the third gate layer GA3, the third insulating layer ILD2, the first source and drain layer SD1, the first flat layer PLN1, the second source and drain layer SD2, and the second flat layer PLN2, where:

The substrate SU can be a flexible transparent material such as polyimide (PI), or a hard transparent material such as glass, and the substrate SU can be a multi-layer or single-layer structure.

As shown in FIG. 10 , the first semiconductor layer POL may be provided on one side of the substrate SU, and includes a driving transistor T3, a writing transistor T4, a first reset transistor T1, a first light emission control transistor T5 and a third transistor in the pixel circuit PC. 2. The channel of the luminescence control transistor T6. The material of the first semiconductor layer POL may be polysilicon.

The first gate insulating layer GI1 may cover the first semiconductor layer POL, and the material of the first gate insulating layer GI1 may be an insulating material such as silicon nitride or silicon oxide.

As shown in FIG. 11 , the first gate layer GA1 can be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU, and includes a first reset control line REL1, an emission control line EML, a first scan line GAL1 and a storage capacitor. The first plate of Cst Cst1, where:

The first plate Cst1 overlaps with a partial region of the first semiconductor layer POL. The first semiconductor layer POL at the overlap is the channel of the driving transistor T3, and the first plate Cst1 is multiplexed as the gate of the driving transistor T3. The first reset control line REL1 overlaps with a part of the first semiconductor layer POL. The first semiconductor layer POL at the overlap is the channel of the first reset transistor T1. The first reset control line REL1 at the overlap is the first reset transistor T1. Reset the gate of transistor T1. The first scanning line GAL1 overlaps a part of the first semiconductor layer POL. The first semiconductor layer POL at the overlap is the channel of the writing transistor T4. The first scanning line GAL1 at the overlap is the channel of the writing transistor T4. gate. The emission control line EML overlaps with a partial area of the first semiconductor layer POL. The first semiconductor layer POL at the overlap is the channel of the first emission control transistor T5 and the second emission control transistor T6, and the emission control line at the overlap is The line EML is the gate electrode of the first light emission control transistor T5 and the second light emission control transistor T6.

In addition, the connection unit VL of the first reset signal line VIL1 mentioned above may also be located on the first gate layer GA1.

The first insulating layer ILD0 may cover the first gate layer GA1, and its material may be an insulating material such as silicon nitride or silicon oxide.

As shown in FIG. 12 , the second gate layer GA2 can be disposed on the surface of the first insulating layer ILD0 away from the substrate SU, and includes a second reset signal line VIL2 and a second plate Cst2. The second plate Cst2 and the first The plates Cst1 overlap to form a storage capacitor Cst.

The second insulating layer ILD1 may cover the second gate layer GA2, which may be a single-layer or multi-layer structure, and the material may include insulating materials such as silicon nitride and silicon oxide. For example, the second insulating layer ILD1 may include a dielectric layer and a buffer layer sequentially stacked in a direction away from the substrate SU.

As shown in FIG. 13 , the second semiconductor layer IGL may be disposed on a surface of the second insulating layer ILD1 away from the substrate SU, and includes channels of the second reset transistor T7 and the compensation transistor T2 .

The second gate insulating layer GI2 may cover the second semiconductor layer IGL, and its material may be an insulating material such as silicon nitride or silicon oxide.

As shown in FIG. 14 , the third gate layer GA3 may be disposed on a surface of the second gate insulating layer GI2 away from the substrate SU, and includes a second reset control line REL2 and a second scan line GAL2, and is connected to the second semiconductor layer IGL. overlap at least partially.

The third insulating layer ILD2 may cover the third gate layer GA3. It may have a single-layer or multi-layer structure, and the material may include inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials such as insulating resin.

As shown in FIG. 15 , the first source and drain layer SD1 may be disposed on a surface of the third insulating layer ILD2 away from the substrate SU, and includes a wiring unit VB.

The first planar layer PLN1 may cover the first source and drain layer SD1, and its material may be an insulating material such as resin. In addition, a passivation layer may also be included, which may cover the first source and drain layer SD1, and the first planar layer PLN1 covers the first source and drain layer SD1.

As shown in FIG. 16 , the second source and drain layer SD2 may be disposed on the surface of the first planar layer PLN1 away from the substrate SU, and includes the data line DAL and the power line VDL.

The second flat layer PLN2 may cover the second source and drain layer SD2, and its material may be an insulating material such as resin. The transfer layer BL may be disposed on a surface of the second flat layer PLN2 away from the substrate SU.

In addition, further, as shown in FIGS. 5 and 12 , the second gate layer GA2 may also include an auxiliary reset line REL2s and an auxiliary scan line GAL2s extending along the row direction X. The auxiliary reset line REL2s may be connected to the second reset control line REL2 overlaps, the auxiliary reset line REL2s also overlaps with the second semiconductor layer IGL, and the corresponding second semiconductor layer IGL at the overlap is still the channel of the second reset transistor T7, and the auxiliary reset line REL2s at the overlap is also The gate of the second reset transistor T7. At the same time, the auxiliary reset line REL2s can be connected to the second reset control line REL2 through a contact hole in the display area AA, or they can be connected after extending to the peripheral area WA, thereby increasing the gate size of the second reset transistor T7. Extreme area.

The auxiliary scanning line GAL2s may overlap with the second scanning line GAL2. The auxiliary scanning line GAL2s also overlaps with the second semiconductor layer IGL, and the corresponding second semiconductor layer IGL at the overlap is still the channel of the compensation transistor T2, and the overlap The auxiliary scanning line GAL2s at is also the gate of the compensation transistor T2. At the same time, the auxiliary scan line GAL2s can be connected to the second scan line GAL2 through a contact hole in the display area AA, or they can be extended to the peripheral area WA before being connected, thereby increasing the area of the gate of the compensation transistor T2 .

In addition, as shown in FIG. 4 , a light-shielding layer BSM can also be provided between the substrate SU and the first semiconductor layer POL, which can be made of light-shielding metal or other materials, and can be a single-layer or multi-layer structure. At least part of the area of the light-shielding layer BSM can overlap with at least part of the channel region of the transistor to block the light irradiating the transistor to stabilize the electrical characteristics of the transistor. For example, the light-shielding layer BSM can include a plurality of light-shielding units distributed in an array. The light shielding unit can shield a channel of a driving transistor T3. At the same time, each light-shielding unit can be connected through a shading line, so that the light-shielding layer BSM has an integrated structure, and the second power signal VSS or the second power signal VDD is input to the light-shielding layer BSM, so that the light-shielding layer BSM can play an electrostatic shielding role. .

Further, as shown in FIG. 4 , the light-shielding layer BSM can be covered by an insulating buffer layer, and the first semiconductor layer can be provided on the surface of the buffer layer facing away from the substrate SU. The buffer layer can be a single-layer or multi-layer structure, and its materials can include insulating materials such as silicon nitride and silicon oxide.

In order to save space, as shown in Figure 5 and Figure 8, part of the wiring of two adjacent rows of pixel circuits PC can be reused. For example, the first reset control line REL1 connected to the nth row of pixel circuits PC can be reused. It is used to connect the first scanning line GAL1 of the n+1th row pixel circuit PC, n is a positive integer. That is to say, the first reset control line REL1 connected to the n-th row pixel circuit PC is also the first scanning line GAL1 connected to the n+1-th row pixel circuit PC.

The inventor found that, as shown in FIG. 2 , since the second pixel circuit PC2 is connected to the second light-emitting device LD2 through the adapter line CL, compared with the first pixel circuit PC1 that is directly connected to the first light-emitting device LD1, the adapter line The presence of CL will increase the load between the second pixel circuit PC2 and the connected second light-emitting device LD2. If the same reset signal is used to reset the first light-emitting device LD1 and the second light-emitting device LD2, the second light-emitting device will emit light. The reset of the device LD2 lags behind the reset of the first light-emitting device, causing the lighting of the light-transmitting area SA1 to be out of synchronization with the main display area MA and the circuit area SA2. Especially at low gray levels, the lighting is abnormal.

In order to solve the above problem of abnormal lighting, as shown in Figure 3, the inventor provides a new solution. By designing the first reset signal line, the first light-emitting device LD1 and the second light-emitting device LD2 are reset respectively, that is, The first reset signal VI1 is used to reset the first light-emitting device LD1, and the third reset signal VI3 is used to reset the second light-emitting device LD2. By controlling the timing of the third reset signal VI3 and the first reset signal VI1, it is possible to To compensate for abnormal lighting and reduce or eliminate the difference between the lighting time of the light-transmitting area SA1 and the lighting time of the main display area MA and the circuit area SA2, the third reset signal VI3 is the second reset signal. The solution is explained in detail below:

As shown in Figures 1 and 2, for all pixel circuits PC in the display area AA, each row of pixel circuits PC can be connected to a reset signal line VIL1, which can be divided into two categories, the first category and the first reset signal line Line VIL1 is located outside the sub-display area SA in the column direction Y, that is, the first type of first reset signal line VIL11 and the sub-display area SA are distributed along the column direction Y; the extension direction of the second type of first reset signal line VIL12 is in line with the sub-display area The areas SA intersect, and a part of the second type first reset signal line VIL12 is located in the circuit area SA2 in the sub-display area SA.

The second type of first reset signal line VIL12 can be divided along the row direction In area SA2, as shown in Figures 5, 6, 11, and 15, both the first reset section LV1 and the second reset section LV2 include multiple wiring units VB and connection units VL; where:

For the first light-emitting device LD1 in the main display area MA, the first pixel circuit PC1 connected thereto can be connected to the first reset section LV1 of the first type first reset signal line VIL11 and the second type first reset signal line VIL12, That is, in the main display area MA, the first pixel circuit PC1 distributed along the row direction A pixel circuit PC1 is connected to the first reset signal line VIL11 of the first type. Therefore, the first reset signal VI1 can be transmitted through the first type first reset signal line VIL11 and the first reset segment LV1 to reset the first light-emitting device LD1 in the main display area AA.

For the light-emitting device LD (the second light-emitting device LD2 and part of the first light-emitting device LD1) in the sub-display area SA, the pixel circuit PC (the second pixel circuit PC2 and part of the first pixel circuit PC1) connected thereto can be connected with the second type The second reset section LV2 of the first reset signal line VIL12 is connected, so that the third reset signal VI3 can be transmitted through the second reset section LV2, so that the first electrode of the light-emitting device LD in the sub-display area SA can be transmitted through the third reset signal VI3. ANO performs reset.

As shown in Figure 1, in some embodiments of the present disclosure, the driving backplane may also include a first reset bus BV1, a second reset bus BV2, and a first reset connection line LV3, where:

The first reset bus BV1 may be disposed in the peripheral area WA and connected to part of the first reset section LV1 of the first type first reset signal line VIL11 and the second type first reset signal line VIL12, that is, with each first reset signal Line VIL1 is connected partially within the main display area MA. At the same time, the first reset bus BV1 extends to the fan-out area FA and is connected to the bonding part PA to transmit the third reset signal VI3.

The second reset bus BV2 can be provided in the peripheral area, and can be provided on the same layer as the first reset bus BV1 and distributed at intervals. The second reset bus BV2 extends to the fan-out area FA and is connected to the binding part PA to transmit the first reset signal VI1.

The first reset connection line LV3 can extend from the peripheral area WA to the display area AA along the column direction Y, and connect the first reset bus BV1 and the second reset segment LV2, thereby transmitting the third reset signal VI3 to the second reset segment LV2. , and avoid short circuit with the first reset segment LV1.

As shown in Figure 1, in some embodiments of the present disclosure, the first reset bus BV1 may include a first bus segment BV11, a second bus segment BV12, and a third bus segment BV13. The first bus segment BV11 and the second bus segment BV12 is located on both sides of the display area AA and extends to the fan-out area FA, and is connected to the binding part PA. The third bus segment BV13 is located on the side of the display area AA away from the fan-out area FA, and connects the first bus segment BV11 and the second bus segment BV12, thereby forming a “U”-shaped structure surrounding the display area AA. The first reset connection line LV3 may extend to the peripheral area WA along the column direction Y and be connected to the third bus segment BV13.

The second reset bus BV2 is located on both sides of the display area AA, and is disconnected on the side of the display area AA away from the fan-out area FA. The first reset connection line LV3 can pass through the disconnection position of the second reset bus BV2, thereby connecting with The second reset bus BV2 does not overlap. If the first reset bus BV1 and the first reset connection line LV3 are arranged on the same layer and adopt an integrated structure, the disconnection position of the second reset bus BV2 can avoid short circuit. Of course, if the second reset bus BV2 and the first reset connection line LV3 are located on different layers, the first reset connection line LV3 may cross the second reset bus BV2.

Further, as shown in FIGS. 5 and 9 , in some embodiments of the present disclosure, in the row direction X, there may be a gap Gap extending along the column direction Y between the main display area MA and the circuit area SA2. The area Gap may be one of the areas between two adjacent circuit groups CM, only the circuit group CM closest to the main display area MA in the circuit area SA2 and the circuit group closest to the circuit area SA2 in the main display area MA The area between CM. The first reset connection line LV3 can be located in the gap area Gap, so that the end of the second reset section LV2 can be connected to the first reset connection line LV3. The first reset connection line LV3 can be arranged on the same layer as each wiring unit VB. For example, the first reset connection line LV3 and the wiring unit VB are both located on the first source-drain layer SD1 and are integrally formed with the second reset section LV2. way to connect.

At the same time, as shown in Figures 5 and 9, the first reset connection line LV3 can be intersected with the connection unit VL in the gap area Gap, and the connection unit VL is set intermittently, that is, it is divided into at least two breaks in the row direction X. The open portion thereby realizes the disconnection of the first reset section LV1 and the second reset section LV2, and prevents the first reset connection line LV3 from being connected to the first reset section LV1. Specifically, in a first reset signal line VIL1 having a first reset section LV1 and a second reset section LV2, a connection unit VL is intermittently provided in the separation area, and one end is connected to a trace of the first reset section LV1 The unit VB is connected through the contact hole, and the other end is connected to a wiring unit VB of a second reset section LV2 through the contact hole. The intermittently provided connection unit VL here can also be completely omitted, as long as it can prevent the first reset connection line LV3 from being connected to the first reset section LV1. The reason why the intermittent connection unit VL is provided is to connect it to the first reset section LV1 through the contact hole. The reset segment LV1 is connected to the second reset segment LV2, which makes the contact holes in the display area AA evenly distributed to ensure the uniformity of the topography.

Of course, the first reset connection line LV3 can also be located between two adjacent circuit groups CM in the circuit area SA2, or between two adjacent circuit units CU, and can be connected to the wiring units of the second reset section LV2 on both sides. VB is connected through integrated molding, etc., but there is no need to disconnect the connection unit VL connected to the two wiring units VB connected by the first reset connection line LV3.

In some embodiments of the present disclosure, as mentioned above, the number of circuit areas SA2 in the sub-display area SA is two, and they are separated on both sides of the light-transmitting area SA1 along the row direction X; the two circuit areas SA2 and There is a gap area Gap between the main display areas MA. Correspondingly, the number of the first reset connection lines LV3 can also be two, and the first reset connection lines LV3 can be provided in the two intervals Gap, and the two first reset connection lines LV3 are both connected to the first reset bus. BV1 connection.

In some embodiments of the present disclosure, as shown in FIG. 1 , the number of sub-display areas SA is two, and the number of circuit areas SA2 of the sub-display area SA is two; there is an equal distance between the circuit area SA2 and the main display area MA. There is a gap area Gap, and thus there are four circuit areas SA2 and four gap areas Gap. Correspondingly, the number of first reset connection lines LV3 is four; first reset connection lines LV3 are provided in each gap area Gap, and the four first reset connection lines LV3 are all electrically connected to the first reset bus BV1.

As shown in FIG. 23 , the first reset connection line LV3 has a first end and a second end distributed along the column direction Y. Among the two first reset connection lines LV3 located on both sides of the secondary display area SA, the first ends of the two first reset connection lines LV3 are connected to the first reset bus BV1, and the second ends of the two first reset connection lines LV3 They are connected through the connection trace LV6 extending along the row direction X.

As shown in Figure 21, for a display panel with only one sub-display area SA, the first reset sections LV1 on both sides of the sub-display area SA are disconnected at the sub-display area SA, but can be extended in the opposite direction to the peripheral area WA. And connected to the second reset bus BV2 to receive the first reset signal VI1. However, if there are multiple sub-display areas SA distributed linearly along the row direction X, the first reset section LV1 between two adjacent sub-display areas SA can receive the first reset signal VI1 in the following way:

As shown in FIGS. 1 , 17 - 20 and 22 , in some embodiments of the present disclosure, a second second display area extending along the column direction Y may be provided in the main display area MA between two adjacent secondary display areas SA. Reset the connection line LV4, and connect the second reset connection line LV4 to at least one first reset signal line VIL1 (the first type of first reset signal line VIL11) located outside the sub-display area SA in the column direction Y, and at the same time, The second reset connection line LV4 is connected to the first reset segment LV1 between two adjacent sub-display areas SA, so that the second reset connection line LV4 can be used to bypass the sub-display area SA and transmit the first reset signal VI1 to the adjacent sub-display area SA. There is a reset segment LV1 between the two secondary display areas SA.

As shown in Figures 17 to 20, the second reset connection line LV4 can be located in the same gap area Gap as the first reset connection line LV3, but the interval is set on the side of the first reset connection line LV3 away from the light-transmitting area SA1. When , the first reset section LV1 between two adjacent sub-display areas SA is located on the same side of the second reset connection line LV4. Of course, the second reset connection line LV4 and the first reset connection line LV3 can be separated by at least one circuit group CM. Both sides of the second reset connection line LV4 have first reset sections LV1. At this time, the second reset connection line LV4 It crosses the connection unit VL of the first reset segment LV1, and the cross-connection unit VL of the second reset connection line LV4 is continuous in the row direction X without being disconnected, so as to ensure that the second reset connection line LV4 can transmit the first Reset signal VI1.

Furthermore, the second reset connection line LV4 can be provided on the same layer as the first reset connection line LV2. For example, both are provided on the first source-drain layer SD1, and can be provided on the same layer as the wiring unit VB. The second reset connection line LV4 may be located between two adjacent circuit groups CM in the main display area MA, or may be located between two adjacent circuit units CU.

As shown in FIG. 1 , the number of the second reset connection lines LV4 may be multiple and distributed along the row direction between the first reset segment LV1 connections. At the same time, the two second reset connection lines LV4 may be arranged symmetrically with respect to the central axis along the column direction Y of the area between two adjacent secondary display areas SA.

In other embodiments of the present disclosure, the second reset connection line LV4 may also be located on the side of the wiring unit VB away from the connection unit VL. At this time, the second reset connection line LV4 can overlap with the pixel circuit PC, as long as the first reset signal VI1 can be transmitted to the first reset section LV1 in the main display area MA between the two adjacent secondary display areas SA. .

As shown in FIG. 22 , in other embodiments of the present disclosure, for the first reset segment LV1 located on the same first reset signal line VIL1 and separated by the sub-display area SA, it is possible to bypass the sub-display area SA. The lead LV5 connects the first reset section LV1 on both sides of the secondary display area SA. The lead LV5 can be located on any film layer of the driving backplane BP, or on any film between the driving backplane BP and the light-emitting device LD. layer. At the same time, the lead LV5 can be located on the same film layer, or can include different line segments located on multiple film layers, as long as it can play the aforementioned connection role.

Further, as shown in Figure 22, two first reset segments LV1 of the same first reset signal line VIL1 separated by a secondary display area SA in the row direction The side of the first reset section LV1 close to the fan-out area FA, or at least part of the lead LV5 is located on the side of the first reset section LV1 connected to it that is away from the fan-out area FA. For example:

In some embodiments of the present disclosure, each lead LV5 can be divided into two parts, and the number of leads LV5 in the two parts can be the same or different; wherein, a part of the leads LV5 is located near the fan-out of the first reset section LV1 to which it is connected. On one side of the area FA, the other part of the lead LV5 is located on the side away from the fan-out area FA of the first reset section LV1 it is connected to, which can avoid the lead LV5 from being too concentrated and make full use of the space for routing.

In some embodiments of the present disclosure, each lead LV5 is located on a side of the first reset section LV1 to which it is connected, close to the fan-out area FA.

In some embodiments of the present disclosure, each lead LV5 is located on a side of the first reset section LV1 to which it is connected, away from the fan-out area FA.

The embodiments of the present disclosure also provide a display device. The display device may be a mobile phone, a tablet computer, a television, or other electronic equipment with an under-screen camera function, which will not be listed here. As shown in FIG. 23 , the display device of the present disclosure may include a display panel PNL and a photosensitive element CAU, where:

The display panel PNL can be the display panel PNL in any of the above embodiments. For its structure, reference can be made to the above embodiments of the display panel PNL, which will not be described in detail here.

The photosensitive element CAU may be disposed on a side of the driving backplane BP away from the light emitting device LD, and the orthographic projection of the photosensitive element CAU on the driving backplane BP at least partially overlaps with the orthographic projection of the light-transmitting area SA1 on the driving backplane BP.

In some embodiments of the present disclosure, there are multiple sub-display areas SA, the number of photosensitive elements CAU is the same as the number of sub-display areas SA, and each photosensitive element CAU is consistent with the light-transmitting area SA1 of each sub-display area SA. Overlapping settings corresponding to one another.

External light can pass through the light-transmitting area SA1 and illuminate the corresponding photosensitive element CAU. The photosensitive element CAU can generate an electrical signal according to the light transmitted through the corresponding light-transmitting area SA1 in order to generate an image. The photosensitive element CAU may include an image sensor, such as a CCD image sensor or a CMOS image sensor.

The photosensitive element CAU can generate an image based on visible light, or can also generate an image based on infrared rays or other light. For example, the photosensitive element CAU can include an infrared sensor, which forms an infrared image by receiving infrared rays from the outside, so as to identify fingerprint patterns and iris based on the infrared image. Patterns, facial patterns, etc. Alternatively, the photosensitive element CAU may further include an illuminance sensor that may measure illuminance around the display device, and the display panel PNL may adjust the brightness of the display panel based on the measured illuminance. In addition, the photosensitive element CAU can also use LiDAR (Light Detection and Ranging, LIDAR) sensors.

The photosensitive element CAU can be used not only in cameras that capture images, but also in small lamps that output light to measure distances by outputting and detecting light.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (18)

1. A display panel has a display area and a peripheral area at least partially surrounding the display area; the display area includes a secondary display area and a main display area located on at least one side of the secondary display area, and the secondary display area includes a transparent A light area and a circuit area located on at least one side of the light-transmitting area;

   The driving backplane includes a plurality of pixel circuits distributed in an array and a plurality of first reset signal lines. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit is located in the main display area and the main display area. The circuit area, the second pixel circuit is located in the circuit area; the plurality of first reset signal lines extend along the first direction, and part of the first reset signal in the plurality of first reset signal lines The lines are first type first reset signal lines, and part of the first reset signal lines are second type first reset signal lines; the second type first reset signal lines include a third type intermittently arranged along the first direction. A reset section and a second reset section; the first reset section is located in the main display area, and the second reset section is located in the circuit area;

   A plurality of light-emitting devices located on one side of the driving backplane, and including a first light-emitting device located in the main display area and the circuit area and a second light-emitting device located in the light-transmitting area; the first light-emitting device The device is connected to the first pixel circuit, and the second light-emitting device is connected to the second pixel circuit through a transfer line;

   The first reset section is connected to part of the first pixel circuit in the main display area, and the first reset section is configured to provide a first reset signal to the first pixel circuit in the main display area. ; The second reset section is connected to the first pixel circuit and the second pixel circuit of the circuit area, and the second reset section is configured to provide a signal to the first pixel circuit and the second pixel circuit of the circuit area. The second pixel circuit provides a second reset signal.
2. The display panel according to claim 1, wherein the driving backplane further includes:

   A first reset bus located in the peripheral area;

   A second reset bus is located in the peripheral area and is spaced apart from the first reset bus. The second reset bus is connected to the first reset segment of the main display area;

   A first reset connection line extends from the peripheral area to the display area along the second direction, and the first reset connection line connects the first reset bus and the second reset segment;

   The first direction and the second direction intersect.
3. The display panel according to claim 2, wherein in the first direction, there is a spacing area extending along the second direction between the main display area and the circuit area, and the first reset connection The line is located within the spacer area.
4. The display panel according to claim 3, wherein the number of circuit areas in the sub-display area is two, and they are respectively located on both sides of the light-transmitting area along the first direction; the two circuit areas The spacer area is provided between the main display area and the main display area;

   The number of the first reset connection lines is two, and the first reset connection lines are provided in the two separation areas, and the two first reset connection lines are connected to the first reset bus. .
5. The display panel according to claim 4, wherein the number of the secondary display areas is two, and the number of the first reset connection lines is four; the first reset connection is provided in each of the separation areas. lines, and the four first reset connection lines are all connected to the first reset bus.
6. The display panel according to claim 5, wherein among the two first reset connection lines located on both sides of one of the sub-display areas, the first ends of the two first reset connection lines are connected to the first reset connection lines. The first reset bus is connected, and the second ends of the two first reset connection lines are connected through connecting wires extending along the first direction.
7. The display panel according to claim 4, wherein the peripheral area includes a fan-out area extending in a direction away from the display area;

   The first reset bus includes a first bus segment, a second bus segment and a third bus segment, the first bus segment and the second bus segment are located on both sides of the display area and extend to the fan-out area; The third bus segment is located on a side of the display area away from the fan-out area and connects the first bus segment and the second bus segment; the first reset connection line and the third bus segment connect;

   The second reset bus is located on both sides of the display area and extends to the fan-out area. The second reset bus is disconnected on a side of the display area away from the fan-out area. A reset connection line passes through the disconnected position of the second reset bus.
8. The display panel according to claim 7, wherein the number of the secondary display areas is multiple, and they are spaced apart along the first direction;

   The main display area between two adjacent secondary display areas is provided with a second reset connection line extending along the second direction; at least one of the first type first reset signal lines is connected to two adjacent secondary display areas. The first reset sections between regions are connected by the second reset connection line.
9. The display panel according to claim 8, wherein the number of second reset connection lines between two sub-display areas is two, and they are spaced apart along the first direction; two adjacent sub-display areas The first reset sections between zones are connected by two second reset connection lines.
10. The display panel according to claim 7, wherein two first reset sections of the same first reset signal line separated by one of the secondary display areas in the first direction are connected by wires; at least Part of the lead wire is located on the side of the first reset section to which it is connected, close to the fan-out area, or at least part of the lead wire is located on the side of the first reset section to which it is connected, away from the fan-out area.
11. The display panel according to claim 8, wherein the first reset signal line includes a plurality of wiring units distributed along the first direction and a connection unit connected to two adjacent wiring units, and the The connection unit and the wiring unit are located on different layers;

    Both the first reset section and the second reset section include a plurality of wiring units and connection units;

    In a first reset signal line having the first reset section and the second reset section, a connection unit is intermittently provided in the spacing area, and one end is connected to an end of the first reset section. The wiring unit is connected, and the other end is connected to a wiring unit of the second reset section;

    The first reset connection line crosses the intermittently arranged connection units.
12. The display panel according to claim 11, wherein the wiring unit, the first reset connection line and the second reset connection line are arranged on the same layer, and are located on a side of the connection unit close to the light-emitting device. side.
13. The display panel according to claim 11, wherein the first reset connection line and the second reset connection line are arranged on the same layer and located on a side of the wiring unit away from the connection unit.
14. The display panel according to claim 11, wherein the second reset connection line is disposed across and connected to part of the connection unit.
15. The display panel of claim 3, wherein each of the pixel circuits is divided into a plurality of circuit groups distributed in an array; one of the circuit groups includes a plurality of circuit units distributed along the first direction; one of the circuits The unit includes two of the pixel circuits distributed along the first direction;

    In the first direction, the distance between two adjacent circuit groups is greater than the distance between two adjacent pixel circuits; two pixel circuits of the same circuit unit are aligned with a straight line extending along the second direction. Symmetrical settings;

    The spacing area is a partial area between two adjacent circuit groups.
16. The display panel of claim 12, wherein the pixel circuit includes a first reset transistor;

    In the circuit area, the second reset section is connected to the light-emitting device through the first reset transistor;

    In the main display area, the first reset segment is connected to the light-emitting device through the first reset transistor.
17. The display panel according to any one of claims 1-16, wherein the display panel further includes:

    A transfer layer is provided between the driving backplane and the light-emitting device, and includes the transfer line, which extends from the circuit area to the light-transmitting area, and at least one of the second light-emitting devices The device is connected to at least one of the second pixel circuits through at least one of the transfer lines.
18. A display device including:

    The display panel according to any one of claims 1-17;

    The photosensitive element is located on the side of the driving backplane away from the plurality of light-emitting devices. The orthographic projection of the photosensitive element on the driving backplane and the orthographic projection of the light-transmitting area on the driving backplane are at least partially overlap.

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