WO2024029765A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2024029765A1
WO2024029765A1 PCT/KR2023/009777 KR2023009777W WO2024029765A1 WO 2024029765 A1 WO2024029765 A1 WO 2024029765A1 KR 2023009777 W KR2023009777 W KR 2023009777W WO 2024029765 A1 WO2024029765 A1 WO 2024029765A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
capacitor
disposed
layer
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2023/009777
Other languages
English (en)
Korean (ko)
Inventor
신동희
손선권
박노경
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Priority to CN202380056611.5A priority Critical patent/CN119631596A/zh
Publication of WO2024029765A1 publication Critical patent/WO2024029765A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor

Definitions

  • Embodiments of the present invention relate to display devices.
  • the purpose of the present invention is to provide a display device that can improve display quality.
  • a display device includes a semiconductor pattern; a first capacitor electrode disposed below the semiconductor pattern; a second capacitor electrode disposed on the semiconductor pattern and partially forming a gate electrode; a first electrode and a second electrode disposed on the same layer on the second capacitor electrode; at least one light emitting element disposed between the first electrode and the second electrode; a first pixel electrode disposed on the first electrode and connected to a first end of the at least one light emitting element; and a second pixel electrode disposed on the second electrode and connected to a second end of the at least one light emitting element.
  • the first electrode is electrically connected to the first capacitor electrode and the semiconductor pattern, the semiconductor pattern and the gate electrode constitute a transistor, and the first capacitor is formed by the first capacitor electrode and the second capacitor electrode.
  • a second capacitor is formed by the second capacitor electrode and the first electrode.
  • Signal lines and power lines may not be disposed in the layer between the second capacitor electrode and the first electrode.
  • At least one of the source electrode and drain electrode of the transistor may be disposed on the same layer as the second capacitor electrode.
  • a data line connected to the transistor may be disposed on the same layer as the first capacitor electrode.
  • the power line connected to the transistor may be disposed on the same layer as at least one of the first capacitor electrode or the second capacitor electrode.
  • the first pixel electrode may be electrically connected to the transistor through the first electrode.
  • the display device further includes a bridge electrode disposed on the same layer as the first electrode and the second electrode and spaced apart from the first electrode and the second electrode, and the second pixel electrode is connected to the bridge electrode through the bridge electrode. Can be connected to a power line.
  • the second electrode extends across a plurality of sub-pixels, and the first electrode and the bridge electrode may be arranged in an island shape in each of the sub-pixels.
  • a first insulating layer may be disposed on the first electrode and the second electrode, and the first insulating layer may not be disposed in a boundary area between two adjacent sub-pixels among the plurality of sub-pixels.
  • the first electrode may cover the first capacitor electrode and the second capacitor electrode.
  • the first electrode may be connected to the first capacitor electrode and the semiconductor pattern through an opening of the second capacitor electrode.
  • the display device includes: a wavelength conversion pattern disposed on the at least one light-emitting element and emitting light by converting a wavelength band of light incident from the at least one light-emitting element; And it may further include a color filter disposed on the wavelength conversion pattern.
  • the at least one light emitting device may include inorganic light emitting diodes connected in parallel.
  • a display device includes a semiconductor pattern; a first capacitor electrode disposed below the semiconductor pattern; a gate electrode disposed on the semiconductor pattern; a first electrode and a second electrode disposed on the same layer on the gate electrode; at least one light emitting element disposed between the first electrode and the second electrode; a first pixel electrode disposed on the first electrode and connected to a first end of the at least one light emitting element; and a second pixel electrode disposed on the second electrode and connected to a second end of the at least one light emitting element.
  • the first electrode is electrically connected to the first capacitor electrode and the semiconductor pattern, the semiconductor pattern and the gate electrode constitute a transistor, and a portion of the semiconductor pattern doped with impurities constitutes a second capacitor electrode.
  • a first capacitor is formed by the first capacitor electrode and the second capacitor electrode
  • a second capacitor is formed by the second capacitor electrode and the first electrode overlapping the second capacitor electrode.
  • the gate electrode may be electrically connected to the second capacitor electrode.
  • Signal lines and power lines may not be disposed in the layer between the second capacitor electrode and the gate electrode.
  • Each of the data line and power line connected to the transistor may be disposed on the same layer as at least one of the first capacitor electrode or the second capacitor electrode.
  • the display device further includes a bridge electrode disposed on the same layer as the first electrode and the second electrode and spaced apart from the first electrode and the second electrode, and the second pixel electrode is connected to the bridge electrode through the bridge electrode. Can be connected to a power line.
  • a first insulating layer may be disposed on the first electrode and the second electrode, and the first insulating layer may not be disposed in a boundary area between two adjacent sub-pixels among the plurality of sub-pixels.
  • the first electrode may cover the first capacitor electrode and the second capacitor electrode.
  • a second capacitor electrode which is a gate electrode or a doped semiconductor pattern, and a first alignment electrode form a second capacitor, and the second capacitor is connected in parallel with the first capacitor to form a storage capacitor.
  • the capacitance (or capacity) of the storage capacitor can be more sufficiently secured.
  • the first alignment electrode may cover or shield the second capacitor electrode (or the gate electrode of the driving transistor). Accordingly, the influence of adjacent signal lines and/or power lines on the second capacitor electrode is excluded, a more accurate data signal is charged or maintained in the storage capacitor, the sub-pixel accurately emits light at the target luminance, and the image displayed on the display device The display quality can be improved.
  • FIG. 1 is a plan view showing a display device according to embodiments.
  • FIGS. 2A, 2B, 2C, and 2D are circuit diagrams showing examples of sub-pixels included in the display device of FIG. 1.
  • FIGS. 3 and 4 are layout diagrams showing an example of a pixel included in the display device of FIG. 1 .
  • FIG. 5 is a plan view illustrating embodiments of pixels included in the display device of FIG. 1 .
  • FIG. 6 is a cross-sectional view showing embodiments of the first sub-pixel along lines I-I' and II-II' of FIGS. 3 to 5.
  • FIGS. 7A and 7B are cross-sectional views showing examples of pixels included in the display device of FIG. 1 .
  • FIG. 8 is a layout diagram for explaining the manufacturing process of the display device of FIG. 1.
  • FIG. 9 is a layout diagram illustrating embodiments of pixels included in the display device of FIG. 1 .
  • FIG. 10 is a cross-sectional view showing embodiments of the first sub-pixel along lines III-III' and II-II' of FIG. 9.
  • Figure 11 is a diagram showing a light emitting device according to embodiments.
  • first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and similarly, the second component may also be named a first component without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.
  • the direction in which it is formed is not limited to the upper direction and includes formation in the side or bottom direction.
  • a part of a layer, membrane, region, plate, etc. is said to be “beneath” another part, this includes not only cases where it is “immediately below” another part, but also cases where there is another part in between.
  • connection between two components may mean using both electrical and physical connections.
  • FIG. 1 is a plan view showing a display device according to embodiments.
  • Figure 1 shows a display panel (PNL) provided in a display device.
  • PNL display panel
  • FIG. 1 shows the structure of the display panel PNL centered on the display area DA.
  • at least one driving circuit unit eg, at least one of a scan driver or a data driver
  • wires, and/or pads may be further disposed on the display panel PNL.
  • the display panel PNL may include a substrate SUB and pixels PXL disposed on the substrate SUB.
  • the substrate SUB (or base layer) constitutes the base member of the display panel PNL and may be a rigid or flexible substrate or film.
  • the substrate SUB may be a rigid substrate made of glass or tempered glass, a flexible substrate (or thin film) made of plastic or metal, or at least one layer of insulating layer.
  • the material and/or physical properties of the substrate (SUB) are not particularly limited.
  • the substrate SUB may be substantially transparent.
  • substantially transparent may mean that light can be transmitted beyond a predetermined transmittance.
  • the substrate SUB may be translucent or opaque. Additionally, the substrate SUB may include a reflective material depending on the embodiment.
  • the display panel (PNL) and the substrate (SUB) for forming the display panel (PNL) may include a display area (DA) for displaying an image and a non-display area (NDA) excluding the display area (DA).
  • the non-display area NDA may be located around the display area DA along an edge or periphery of the display area DA.
  • a pixel PXL may be disposed in the display area DA.
  • Various wires, pads, and/or built-in circuitry connected to the pixel PXL of the display area DA may be disposed in the non-display area NDA.
  • the pixel PXL includes sub-pixels SPX1 to SPX3.
  • the pixel PXL includes the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel. (SPX3) may be included.
  • Each of the sub-pixels (SPX1 to SPX3) may emit light of a certain color.
  • the sub-pixels SPX1 to SPX3 may emit light of different colors.
  • the first sub-pixel (SPX1) emits light of the first color
  • the second sub-pixel (SPX2) emits light of the second color
  • the third sub-pixel (SPX3) emits light of the third color.
  • the first sub-pixel (SPX1) may be a red pixel that emits red light
  • the second sub-pixel (SPX2) may be a green pixel that emits green light
  • the third sub-pixel (SPX3) may be a green pixel that emits green light.
  • ) may be a blue pixel that emits blue light, but is not limited thereto.
  • the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) are a first color light emitting device, a second color light emitting device, and a third color light emitting device, respectively.
  • the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) have light-emitting elements that emit light of the same color, and are disposed on each light-emitting element.
  • each pixel By including color conversion layers (or wavelength conversion layers) of different colors and/or color filters, light of the first color, second color, and third color may be emitted, respectively.
  • the color, type, and/or number of sub-pixels (SPX1 to SPX3) constituting each pixel (PXL) are not particularly limited. That is, the color of light emitted by each pixel (PXL) can be changed in various ways.
  • the sub-pixels may be arranged regularly according to a stripe or PENTILE ® array structure.
  • the PENTILE ® array structure may be referred to as an RGBG matrix structure (eg, a PENTILE ® array structure or a matrix structure (eg, a PENTILE ® structure)).
  • PENTILE ® is a registered trademark of Samsung Display Co., Ltd. in Korea.
  • the arrangement structure of the sub-pixels SPX1 to SPX3 is not limited to this, and the sub-pixels SPX1 to SPX3 may be arranged in the display area DA using various structures and/or methods.
  • the first, second, and third sub-pixels SPX1, SPX2, and SPX3 are sequentially and repeatedly arranged along the first direction DR1, and are also repeatedly arranged along the second direction DR2.
  • At least one first, second, and third sub-pixel (SPX1, SPX2, SPX3) arranged adjacent to each other may form one pixel (PXL) capable of emitting light of various colors.
  • the arrangement structure of the sub-pixels SPX1 to SPX3 is not limited to this, and the sub-pixels SPX1 to SPX3 may be arranged in the display area DA in various structures and/or methods.
  • each of the sub-pixels SPX1 to SPX3 may be configured as an active pixel.
  • each of the sub-pixels (SPX1 to SPX3) is driven by a predetermined control signal (eg, a scan signal and a data signal) and/or a predetermined power source (eg, a first power source and a second power source). It may include at least one light source (eg, a light emitting device).
  • a predetermined control signal eg, a scan signal and a data signal
  • a predetermined power source eg, a first power source and a second power source
  • It may include at least one light source (eg, a light emitting device).
  • the type, structure, and/or driving method of the sub-pixels (SPX1 to SPX3) that can be applied to the display device are not particularly limited.
  • FIGS. 2A, 2B, 2C, and 2D are circuit diagrams showing examples of sub-pixels included in the display device of FIG. 1.
  • the sub-pixel SPX shown in FIGS. 2A to 2D is the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX1) provided in the display panel (PNL) of FIG. 1. It may be any one of the pixels (SPX3).
  • the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have structures that are substantially the same or similar to each other.
  • the sub-pixel (SPX) includes a light source unit (LSU) for generating light with a luminance corresponding to the data signal, and a pixel circuit (PXC) for driving the light source unit (LSU). can do.
  • LSU light source unit
  • PXC pixel circuit
  • the light source unit (LSU) may include at least one light emitting element (LD) electrically connected between the first power source (VDD) and the second power source (VSS).
  • the first power source (VDD) and the second power source (VSS) may have different potentials so that the light emitting device (LD) can emit light.
  • the first power source (VDD) may be set as a high-potential power source
  • the second power source (VSS) may be set as a low-potential power source.
  • the potential difference between the first power source (VDD) and the second power source (VSS) may be set to be higher than the threshold voltage of the light emitting element (LD) at least during the light emission period of the sub-pixel (SPX).
  • the light emitting device LD may emit light with a luminance corresponding to the driving current supplied through the pixel circuit PXC.
  • the light emitting device (LD) may be composed of inorganic light emitting diodes, such as micro light emitting diodes and quantum dot light emitting diodes.
  • the light emitting device LD may be an ultra-small light emitting diode using an inorganic crystal structure material, with a size as small as nanoscale or microscale.
  • the present invention is not limited to this, and the light emitting device LD may be an organic light emitting diode.
  • the light source unit may include a plurality of light emitting elements (LD) connected in parallel to each other.
  • the light source unit includes a first electrode (CNE1) and a second electrode that are electrically connected to the first power source (VDD) via the pixel circuit (PXC) and the first power line (PL1).
  • the first electrode (CNE1) (or, first pixel electrode) is an anode electrode or corresponds to an anode electrode
  • the second electrode (CNE2) (or, second pixel electrode) is a cathode electrode or corresponds to a cathode electrode.
  • the light emitting device LD has a first end (for example, a p-type end) and a second electrode CNE2 that are electrically connected to the first power source VDD through the first electrode CNE1 and/or the pixel circuit PXC. ) may include a second end (for example, an n-type end) electrically connected to the second power source (VSS). That is, the light emitting device LD may be connected in parallel in the forward direction between the first and second electrodes CNE1 and CNE2.
  • Each light emitting element (LD) connected in the forward direction between the first power source (VDD) and the second power source (VSS) constitutes an effective light source, and these effective light sources are gathered to form a light source unit (LSU) of the pixel (PXL). can be configured.
  • One end (e.g., p-type end) of the light emitting element (LD) is commonly connected to the pixel circuit (PXC) through one electrode (e.g., first electrode (CNE1)) of the light source unit (LSU), It may be electrically connected to the first power source (VDD) through the pixel circuit (PXC) and the first power line (PL1).
  • the other end (for example, the n-type end) of the light emitting element (LD) is connected to the second power source (for example, the second electrode (CNE2)) and the second power line (PL2) of the light source unit (LSU).
  • VSS can be commonly connected.
  • the light source unit (LSU) may include a plurality of light emitting elements (LD) connected in series.
  • the light source unit (LSU) constitutes at least two series stages and may include light emitting elements (LD) connected in series/parallel to each other.
  • the light source unit constitutes two series stages and may include light emitting elements (LD) connected in series/parallel to each other.
  • each series stage may include a pair of electrodes (eg, two electrodes) and at least one light emitting element (LD) electrically connected between the pair of electrodes.
  • the number of light emitting elements LD constituting each series stage may be the same or different, and the number of light emitting elements LD is not particularly limited.
  • the first series stage includes at least one first light emitting element (LD1) electrically connected between the first electrode (CNE1) and the middle electrode (CTE) (or third electrode), and the second series stage
  • the stage may include at least one second light emitting element (LD2) electrically connected between the intermediate electrode (CTE) and the second electrode (CNE2).
  • the light source unit constitutes four series stages and may include light emitting elements (LD) connected in series/parallel to each other.
  • the first series stage includes at least one first light emitting element (LD1) electrically connected between the first electrode (CNE1) and the first intermediate electrode (CTE1)
  • the second series stage includes the first intermediate electrode (CTE1).
  • It includes at least one second light-emitting element (LD2) electrically connected between the electrode (CTE1) and the second intermediate electrode (CTE2)
  • the third serial stage has the second intermediate electrode (CTE2) and the third intermediate electrode (CTE3).
  • the fourth serial stage is at least one fourth light emitting element electrically connected between the third intermediate electrode (CTE3) and the second electrode (CNE2)
  • a light source unit When configuring a light source unit (LSU) by using light emitting elements (LDs) under the same conditions (e.g., the same size and/or number) as effective light sources, the light emitting elements (LDs) are arranged in series or in a series/parallel mixed structure. When connected, power efficiency can be improved.
  • a light source unit (LSU) in which light emitting elements (LDs) are connected in series or in series/parallel can express higher luminance with the same current compared to a light source unit (LSU) in which light emitting elements (LDs) are connected only in parallel. there is.
  • the light source unit (LSU) in which the light emitting elements (LD) are connected in series or in series/parallel can express the same luminance with a lower driving current compared to the light source unit (LSU) in which the light emitting elements (LD) are connected in parallel.
  • the sub-pixel (SPX) in which light-emitting devices (LDs) are connected in series or in a series/parallel mixed structure even if a short circuit occurs in some of the series, a certain level of luminance is maintained through the light-emitting devices (LDs) in the remaining series. can be expressed, the possibility of dark spot defects in the sub-pixel (SPX) can be reduced.
  • the pixel circuit (PXC) may be electrically connected between the first power source (VDD) and the light source unit (LSU).
  • the pixel circuit (PXC) may be electrically connected to the scan line (Si) (or gate line) and the data line (Dj). Additionally, the pixel circuit (PXC) may be further electrically connected to the sensing control line (SSi) and the sensing line (SLj).
  • the sub-pixel SPX is connected to the i (i is a natural number)-th horizontal line (or row, pixel row) and the j (j is a natural number)-th vertical line (or column, pixel column) of the display area DA.
  • the pixel circuit (PXC) of the display area (DA) includes the ith scan line (Si), the ith sensing control line (SSi), the jth data line (Dj), and the sensing line (Dj). It can be electrically connected to the line SLj.
  • the pixel circuit PXC may include a plurality of transistors and at least one capacitor.
  • the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst (e.g., C1 and C2). there is.
  • the first transistor T1 is electrically connected between the first power source VDD and the light source unit LSU.
  • the first electrode (or first terminal, first transistor electrode, for example, drain electrode) of the first transistor T1 is electrically connected to the first power source VDD, and the first transistor T1 ) may be electrically connected to one electrode (e.g., anode electrode) of the light source unit (LSU).
  • the gate electrode of the first transistor T1 is electrically connected to the first node N1.
  • the back gate electrode of the first transistor T1 may be electrically connected to the second node N2.
  • This first transistor T1 controls the driving current supplied to the light source unit LSU in response to the voltage of the first node N1. That is, the first transistor T1 may be a driving transistor that controls the driving current of the sub-pixel SPX.
  • the second transistor T2 is electrically connected between the data line Dj and the first node N1.
  • the first electrode of the second transistor T2 may be electrically connected to the data line Dj
  • the second electrode of the second transistor T2 may be electrically connected to the first node N1.
  • the gate electrode of the second transistor T2 is electrically connected to the scan line Si. This second transistor T2 is turned on when the scan signal SCi of the gate-on voltage (eg, high level voltage) is supplied from the scan line Si, and is connected to the data line Dj and the first node ( Connect N1) electrically.
  • SCi of the gate-on voltage eg, high level voltage
  • the data signal DSj of the frame is supplied to the data line Dj, and the data signal DSj is turned on during the period in which the scan signal SCi of the gate-on voltage is supplied. It is transmitted to the first node (N1) through the transistor (T2). That is, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to the inside of the sub-pixel SPX.
  • the third transistor T3 is electrically connected between the first transistor T1 and the sensing line SLj.
  • the first electrode of the third transistor T3 is electrically connected to the sensing line SLj
  • the second electrode of the third transistor T3 is connected to the second node N2 (or the first transistor ( It can be electrically connected to the second electrode of T1).
  • the gate electrode of the third transistor T3 is connected to the sensing control line SSi.
  • the sensing control line (SSi) is omitted, the gate electrode of the third transistor (T3) is connected to the scan line (Si) (or the previous scan line located in the previous row before the scan line (Si), or the next scan line located in the next row. ) can also be connected to.
  • This third transistor (T3) is turned on by the sensing control signal (SSCi) of the gate-on voltage supplied to the sensing control line (SSi) for a predetermined sensing period and is connected to the sensing line (SLj) and the first transistor ( Connect T1) electrically.
  • a predetermined reference voltage or initialization voltage
  • the sensing line (SLj) may have a voltage level between the first power source (VDD) and the second power source (VSS).
  • VDD first power source
  • VSS first power source
  • the storage capacitor Cst (eg, C1 and C2) may be formed or electrically connected between the first node N1 and the second node N2.
  • the storage capacitor Cst (eg, C1 and C2) may be charged with a voltage corresponding to the data signal DSj supplied to the first node N1 during each frame period.
  • the storage capacitor Cst may include a first capacitor C1 and a second capacitor C2 that are separated from each other.
  • the first capacitor C1 and the second capacitor C2 may be connected in parallel between the first node N1 and the second node N2.
  • the first electrode of each of the first capacitor (C1) and the second capacitor (C2) is electrically connected to the second node (N2)
  • the second electrode of each of the first capacitor (C1) and the second capacitor (C2) is electrically connected to the second node (N2). It is electrically connected to the first node (N1).
  • the first capacitor C1 and the second capacitor C2 may be formed to overlap each other.
  • the storage capacitor Cst includes a first capacitor C1 and a second capacitor C2 instead of one capacitor, and thus can have capacitance maximized in a limited space (or flat space).
  • a parasitic capacitor (or parasitic capacitance) is formed between the first node (N1) and the signal line and/or power line adjacent to the first node (N1), or the first node (N1) is connected to the signal line and/or power line. It can be coupled to a power line.
  • the parasitic capacitor or coupling affects the voltage (or voltage change) of the first node N1, which may result in the sub-pixel SPX not emitting light at the desired brightness.
  • the capacitance of the storage capacitor Cst is maximized by the first capacitor C1 and the second capacitor C2, other signal lines and/or power lines (for example, the first power line PL1) and the first
  • the influence of the parasitic capacitor formed between the nodes N1 can be alleviated or eliminated.
  • the influence of the parasitic capacitor is excluded, the sub-pixel SPX accurately emits light at the desired luminance, and the display quality of the image displayed on the display device can be improved.
  • the transistors included in the pixel circuit PXC are all shown as N-type transistors. It is not necessarily limited thereto, and the first transistor (T1), second transistor (T2), or third transistor (T3) may be changed to a P-type transistor.
  • the pixel circuit (PXC) may be composed of pixel circuits with various structures and/or driving methods.
  • FIGS. 3 and 4 are layout diagrams showing an example of a pixel included in the display device of FIG. 1 . 3 and 4 show the layout of sub-pixels centered on the pixel circuit (PXC) (or pixel circuit layer) of the sub-pixels (SPX) of FIGS. 2A to 2D.
  • PXC pixel circuit
  • SPX sub-pixels
  • the pixel PXL may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3). Since the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) have pixel structures (or circuit structures) that are substantially the same or similar to each other, the first sub-pixel (SPX1) , the common configuration of the second sub-pixel (SPX2), and the third sub-pixel (SPX3) will be described based on the first sub-pixel (SPX1), and overlapping descriptions will not be repeated.
  • the first vertical power line PL1_V, the sensing lines SL1 to SL3, the data lines D1 to D3, and the second vertical power line PL2_V generally extend in the second direction DR2 and extend in the first direction (DR2). It can be arranged along DR1).
  • the sensing lines SL1 to SL3 have a partially curved shape, but are not limited to this.
  • the first vertical power line PL1_V may be disposed in the left direction.
  • the sensing lines SL1 to SL3 and the data lines D1 to D3 may be disposed to the right of the first capacitor electrode CE1 of the corresponding sub-pixel.
  • each of the first sensing line SL1 and the first data line D1 may be disposed to the right of the first capacitor electrode CE1 of the first sub-pixel SPX1.
  • the second vertical power line PL2_V may be disposed to the right of the third sub-pixel SPX3 (or pixel PXL).
  • the first vertical power line (PL1_V), the sensing lines (SL1 to SL3), the data lines (D1 to D3), the second vertical power line (PL2_V), and the first capacitor electrode (CE1) contain the same material and are made of the same material. They can be placed on the same layer through the process.
  • the second horizontal power line PL2_H, the gate line SC, and the first horizontal power line PL1_H extend in the first direction DR1 and may be arranged along the second direction DR2. Based on the second capacitor electrode CE2 of the first sub-pixel SPX1, the second horizontal power line PL2_H and the gate line SC are located in the upper direction, and the first horizontal power line PL1_H is located in the lower direction. can be placed.
  • the gate line (SC) may correspond to the scanning line (Si) and the sensing control line (SSi) shown in FIGS. 2A to 2D.
  • a second horizontal power line (PL2_H), a gate line (SC), and a first horizontal power line (PL1_H), a second capacitor electrode (CE2), and first, second, and third bridge patterns (BRP1, BRP2, BRP3) (or connection patterns) contain the same material and can be placed on the same layer through the same process.
  • the second capacitor electrode CE2 and the first capacitor electrode CE1 may overlap each other and form the first capacitor C1.
  • the second capacitor electrode CE2 is generally covered by the first capacitor electrode CE1, and the area of the second capacitor electrode CE2 may be smaller than the area of the first capacitor electrode CE1.
  • Most of the area of the first capacitor electrode (CE1) may overlap the second capacitor electrode (CE2).
  • the second horizontal power line PL2_H intersects the second vertical power line PL2_V, and may be connected to the second vertical power line PL2_V through a contact hole (and bridge pattern) in the crossing area.
  • the second horizontal power line PL2_H and the second vertical power line PL2_V have an overall mesh structure and may form the second power line PL2 (see FIGS. 2A to 2D).
  • first horizontal power line (PL1_H) intersects the first vertical power line (PL1_V) and may be connected to the first vertical power line (PL1_V) through a contact hole (and bridge pattern) in the crossing area.
  • the first horizontal power line (PL1_H) and the first vertical power line (PL1_V) form an overall mesh structure and may form the first power line (PL1, see FIG. 2C).
  • the arrangement of the first horizontal power line (PL1_H) and the second horizontal power line (PL2_H) may be mutually changed.
  • the first semiconductor pattern ACT1 is located below the first and second capacitor electrodes CE1 and CE2, and may partially overlap the first and second capacitor electrodes CE1 and CE2.
  • the central portion of the first semiconductor pattern (ACT1) overlapping the first and second capacitor electrodes (CE1, CE2) forms a channel of the first transistor (T1 (see FIG. 2C)), and the second capacitor electrode (CE2) may form the gate electrode of the first transistor (T1), and the first capacitor electrode (CE1) may form the back gate electrode of the first transistor (T1).
  • the first portion (e.g., lower portion) of the first semiconductor pattern ACT1 is electrically connected to the protruding portion of the first vertical power line PL1_V through the first bridge pattern BRP1 (and a contact hole). You can.
  • the first portion of the first semiconductor pattern ACT1 or the first bridge pattern BRP1 may be the first electrode of the first transistor T1.
  • the second portion (e.g., the upper portion) of the first semiconductor pattern ACT1 in the opening portion (i.e., the opening portion exposing the first capacitor electrode CE1) of the second capacitor electrode CE2 is exposed to the first capacitor electrode CE2. It may be electrically connected to the first capacitor electrode (CE1) through the contact hole (CNT1, see FIG. 4) and the first alignment electrode (ELT1, see FIG. 4).
  • the second portion of the first semiconductor pattern ACT1 or the first alignment electrode ELT1 may be the second electrode of the first transistor T1.
  • the second semiconductor pattern ACT2 is located above the second capacitor electrode CE2 and may partially overlap the gate line SC.
  • the central portion of the second semiconductor pattern (ACT2) overlapping the gate line (SC) forms a channel of the second transistor (T2), and the gate line (SC) forms the gate electrode of the second transistor (T2). there is.
  • the second portion of the second semiconductor pattern ACT2 may be electrically connected to the second capacitor electrode CE2.
  • the second capacitor electrode CE2 may contact the second portion of the second semiconductor pattern ACT2 through a contact hole.
  • the second portion of the second semiconductor pattern ACT2 or the second capacitor electrode CE2 may be the second electrode of the second transistor T2.
  • the first portion of the second semiconductor pattern ACT2 may be electrically connected to the first data line D1 through the second bridge pattern BRP2 (and contact hole).
  • the first portion of the second semiconductor pattern ACT2 or the second bridge pattern BRP2 may be the first electrode of the second transistor T2.
  • the third semiconductor pattern ACT3 is located above the first capacitor electrode CE1 and may partially overlap the gate line SC.
  • the central portion of the third semiconductor pattern (ACT3) overlapping the gate line (SC) forms a channel of the third transistor (T3), and the gate line (SC) forms the gate electrode of the third transistor (T3).
  • the second portion of the third semiconductor pattern ACT3 may be electrically connected to the first capacitor electrode CE1 through the second contact hole CNT2 (see FIG. 4) and the first alignment electrode ELT1 (see FIG. 4). .
  • the second portion of the third semiconductor pattern ACT3 or the first alignment electrode ELT1 may be the second electrode of the third transistor T3.
  • the first portion of the third semiconductor pattern ACT3 may be electrically connected to the first sensing line SL1 through the third bridge pattern BRP3 (and contact hole).
  • the first portion of the third semiconductor pattern ACT3 or the third bridge pattern BRP3 may be the first electrode of the third transistor T3.
  • the semiconductor patterns (ACT1 to ACT3) contain the same material and can be placed on the same layer through the same process.
  • the semiconductor patterns (ACT1 to ACT3, ACT1_1 to ACT3_1) may include polycrystalline silicon, amorphous silicon, or oxide semiconductor.
  • the channel (or channel region) of the semiconductor patterns (ACT1 to ACT3) is a semiconductor pattern that is not doped with impurities, and the first and second portions (or regions excluding the channel) of the semiconductor patterns (ACT1 to ACT3) It may be a semiconductor pattern doped with silver impurities.
  • the first alignment electrode ELT1 (or first electrode, first reflective electrode) and the second alignment electrode ELT2 (or second electrode, second reflective electrode) are It may extend in two directions (DR2) and be arranged along the first direction (DR1).
  • the second alignment electrode ELT2 located to the right of the first sub-pixel SPX1 (or the corresponding sub-pixel) is called the third alignment electrode ELT3 (or the third electrode, the third reflective electrode). Let's call it .
  • the second alignment electrode ELT2 may extend to the first sub-pixel SPX1 and adjacent sub-pixels in the second direction DR2. That is, the second alignment electrode ELT2 may extend across a plurality of sub-pixels. The second alignment electrode ELT2 may overlap the first vertical power line PL1_V (and the second vertical power line PL2_V). The second alignment electrode ELT2 may be connected to the first vertical power line PL1_V (and the second vertical power line PL2_V) through the contact hole. PL1_V) and can be electrically connected.
  • the first alignment electrode ELT1 is located between the second alignment electrode ELT2 and the third alignment electrode ELT3, and is connected to the second horizontal power line PL2_H and the first horizontal power line (PL2_H) in the second direction DR2. PL1_H).
  • the first alignment electrode ELT1 may be spaced apart from another adjacent first alignment electrode in the second direction DR2 with the electrode opening ELO interposed therebetween.
  • the first alignment electrode ELT1 and the first alignment electrode adjacent thereto in the second direction DR2 are formed as one electrode, that is, integrally, and then, the electrode corresponding to the electrode opening ELO They can be separated from each other by removing some parts.
  • the first alignment electrode ELT1 may be arranged in an island shape in each of the sub-pixels SPXL1 to SPLX3 in a plan view.
  • the first alignment electrode ELT1 overlaps the first capacitor electrode CE1 and the second capacitor electrode CE2 and may cover the first capacitor electrode CE1 and the second capacitor electrode CE2 in a plan view.
  • the first alignment electrode ELT1 may overlap the second capacitor electrode CE2 and form the second capacitor C2.
  • the second capacitor C2 and the first capacitor C1 may share the second capacitor electrode CE2.
  • the first alignment electrode ELT1 may contact or be electrically connected to the first capacitor electrode CE1 through the first contact hole CNT1. Accordingly, the first capacitor C1 and the second capacitor C2 may be connected in parallel.
  • the first alignment electrode ELT1 may overlap most of the circuit configuration of the first sub-pixel SPX1.
  • the first alignment electrode ELT1 covers the first transistor T1, the second transistor T2, and the third transistor T3 (or the channel and gate electrode of the third transistor T3). Or it can be shielded.
  • the configuration disposed on the first alignment electrode ELT1 corresponds to the circuit configuration of the first sub-pixel SPX1 (for example, the second capacitor electrode CE2 or the gate electrode of the first transistor T1). The influence (or coupling) can be blocked.
  • the bridge electrode BRE may be spaced apart or separated from the first alignment electrode ELT1 and the second alignment electrode ELT2 and may overlap the second horizontal power line PL2_H.
  • the bridge electrode BRE may contact or be electrically connected to the second horizontal power line PL2_H through a contact hole.
  • the bridge electrode (BRE) and the first alignment electrode (ELT1) are formed as one electrode, that is, integrally, and then a portion of the electrode corresponding to the electrode opening (ELO) is removed to form a bridge electrode ( BRE) may be separated from the first alignment electrode ELT1.
  • the bridge electrode BRE may be arranged in an island shape in each of the sub-pixels SPXL1 to SPLX3 in the plan view.
  • the first alignment electrode ELT1, the second alignment electrode ELT2, and the bridge electrode BRE include the same material and may be disposed on the same layer through the same process.
  • the first capacitor electrode (CE1) and the second capacitor electrode (CE2) form the first capacitor (C1)
  • the second capacitor electrode (CE2) and the first alignment electrode (ELT1) form the second capacitor (C1).
  • (C2) can be formed. Accordingly, the capacitance (or capacity) of the storage capacitor Cst (eg, C1 and C2) can be more sufficiently secured.
  • the first alignment electrode ELT1 constituting one electrode of the second capacitor C2 may cover or shield the second capacitor electrode CE2 (or the gate electrode of the first transistor T1). Accordingly, a more accurate data signal can be charged or maintained in the storage capacitor Cst (or the gate electrode of the first transistor T1), the sub-pixel can accurately emit light at the target luminance, and display quality can be improved.
  • FIG. 5 is a plan view illustrating embodiments of pixels included in the display device of FIG. 1 .
  • the pixel PXL is briefly illustrated, focusing on the light source unit (LSU, see FIG. 2D ) of the sub-pixel SPX of FIG. 2D . Since the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) of the pixel (PXL) are substantially the same or similar to each other, the description will be based on the first sub-pixel (SPX1). , Overlapping explanations will not be repeated.
  • the alignment electrodes ELT1 to ELT3 may be used as alignment electrodes for aligning the light emitting device LD.
  • the light emitting element LD supplied to the light emitting area EMA may be aligned in a desired direction and/or position by an electric field formed between the alignment electrodes ELT1 to ELT3.
  • the light emitting element LD is positioned between the first alignment electrode ELT1 and the second alignment electrode ELT2 (or the third alignment electrode ELT3) so that the longitudinal direction is substantially parallel to the first direction DR1. can be sorted.
  • the first electrode CNE1 may overlap the first end of the first light emitting device LD1 and the first alignment electrode ELT1.
  • the first electrode CNE1 may electrically connect the first end of the first light emitting device LD1 and the first alignment electrode ELT1.
  • the first alignment electrode ELT1 constitutes one electrode of the storage capacitor Cst and is connected to the second electrode of the first transistor T1, and accordingly, the first electrode CNE1 ) may be electrically connected to the second electrode of the first transistor T1.
  • the first intermediate electrode CTE1 may overlap the second end of the first light emitting device LD1 and the second alignment electrode ELT2 (or the third electrode ELT3). Additionally, the first intermediate electrode CTE1 may overlap the first end of the second light emitting device LD2 and the first alignment electrode ELT1. To this end, a portion of the first intermediate electrode CTE1 may have a curved shape. The first intermediate electrode CTE1 may physically and/or electrically connect the second end of the first light-emitting device LD1 and the first end of the second light-emitting device LD2.
  • the second intermediate electrode CTE2 may overlap the second end of the second light emitting device LD2 and the second alignment electrode ELT2 (or the third electrode ELT3). Additionally, the second intermediate electrode CTE2 may overlap the first end of the third light emitting device LD3 and the first alignment electrode ELT1.
  • the second intermediate electrode CTE2 may have a shape that bypasses the first intermediate electrode CTE1.
  • the second intermediate electrode CTE2 may physically and/or electrically connect the second end of the second light-emitting device LD2 and the first end of the third light-emitting device LD3.
  • the third intermediate electrode CTE3 may overlap the second end of the third light emitting device LD3 and the second alignment electrode ELT2. Additionally, the third intermediate electrode CTE3 may be positioned to overlap the first end of the fourth light emitting device LD4 and the first alignment electrode ELT1. To this end, a portion of the third intermediate electrode CTE3 may have a curved shape. The third intermediate electrode CTE3 may physically and/or electrically connect the second end of the third light-emitting device LD3 and the first end of the fourth light-emitting device LD4.
  • the second electrode CNE2 may overlap the second end of the fourth light emitting device LD4 and the second alignment electrode ELT2. Additionally, the second electrode CNE2 overlaps the bridge electrode BRE and may be in contact with the bridge electrode BRE. The second electrode CNE2 may electrically connect the second end of the fourth light emitting element LD4 and the bridge electrode BRE. As described with reference to FIG. 4, the bridge electrode BRE is connected to the second horizontal power line PL2_H, and accordingly, the second electrode CNE2 is connected to the second horizontal power line PL2_H (or the second horizontal power line PL2_H). It can be electrically connected to the power line (PL2).
  • the light emitting elements LD1 to LD4 may be connected in series between the first electrode CNE1 and the second electrode CNE2.
  • the shape of each of the alignment electrodes (ELT1 to ELT3), the first and second electrodes (CNE1 and CNE2), and the intermediate electrodes (CTE1 to CTE3) is determined by the arrangement and/or series/parallel arrangement of the light emitting element (LD). It may be changed in various ways depending on the structure, and the first intermediate electrode (CTE1), the second intermediate electrode (CTE2), or the third intermediate electrode (CTE3) may be omitted.
  • FIG. 6 is a cross-sectional view showing an embodiment of the first sub-pixel along lines I-I' and II-II' of FIGS. 3 to 5.
  • the first sub-pixel SPX1 (or sub-pixel) is shown in a simplified manner, with each electrode shown as a single-film electrode and each insulating layer shown as a single-film insulating layer, for example.
  • the invention is not limited to this.
  • the first sub-pixel SPX1 may include a pixel circuit layer (PCL) and a display element layer (DPL) disposed on the substrate SUB.
  • PCL pixel circuit layer
  • DPL display element layer
  • the pixel circuit layer (PCL) will be described first, and then the display element layer (DPL) will be described.
  • the pixel circuit layer may include a first conductive layer (or first metal layer), a first transistor T1, and a second conductive layer (or second metal layer).
  • the first conductive layer is disposed on the substrate (SUB), and includes the first vertical power line (PL1_V), the back gate electrode (BGE), the first capacitor electrode (CE1), the first sensing line (SL1), and the first data It may include line D1.
  • the back gate electrode BGE is a portion (or, work area).
  • the first conductive layer may include a conductive material.
  • the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. there is.
  • the first conductive layer may form a single-layer, double-layer, or multi-layer structure.
  • the first conductive layer is a double film or multilayer of low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and/or silver (Ag). It can be formed into a membrane structure.
  • the buffer layer (BFL) is provided and/or formed on the substrate (SUB) and the first conductive layer, and can prevent impurities from diffusing into the first transistor (T1).
  • the buffer layer (BFL) may be an inorganic insulating film containing an inorganic material.
  • the inorganic material may include at least one of metal oxides such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ).
  • the buffer layer (BFL) may be provided as a single layer, but may also be provided as a multilayer, at least a double layer or more. When the buffer layer (BFL) is provided as a multilayer, each layer may be formed of the same material or may be formed of different materials.
  • the buffer layer BFL may be omitted depending on the material and process conditions of the substrate SUB.
  • the first semiconductor pattern ACT1 of the first transistor T1 may be provided and/or formed on the buffer layer BFL.
  • the first semiconductor pattern ACT1 may include a first contact area, a second contact area, and a channel area between the first and second contact areas.
  • the first contact area is in contact with the first transistor electrode TE1 (or first bridge pattern BRP1), and the second contact area is in contact with the second transistor electrode TE2 (or first alignment electrode ELT1). can be contacted.
  • the channel region may overlap the gate electrode (GE) of the first transistor (T1) in the third direction (DR3).
  • the first semiconductor pattern ACT1 may be a semiconductor pattern made of amorphous silicon, poly silicon, low temperature poly silicon, oxide semiconductor, or organic semiconductor.
  • the channel region is a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor.
  • the first contact area and the second contact area may be a semiconductor pattern doped with impurities.
  • the gate insulating layer GI may be disposed on the first semiconductor pattern ACT1 and the buffer layer BFL.
  • the gate insulating layer (GI) may include an inorganic material. Various materials that provide insulation to the gate insulating layer (GI) may be applied. As an example, the gate insulating layer (GI) may include an organic material.
  • the gate insulating layer (GI) may be provided as a single layer, but may also be provided as a multilayer, at least a double layer or more.
  • the second conductive layer is disposed on the gate insulating layer GI, and includes the first transistor electrode TE1 (or first bridge pattern BRP1), the gate electrode GE of the first transistor T1, and the second transistor electrode TE1. It may include a capacitor electrode (CE2) and a second horizontal power line (PL2_H).
  • the gate electrode GE may overlap the channel region of the first semiconductor pattern ACT1 in the third direction DR3.
  • the second capacitor electrode CE2 overlaps the first capacitor electrode CE1 and may form the first capacitor C1.
  • the second conductive layer may include a conductive material.
  • the second conductive layer may include the same material as the first conductive layer, or may include one or more materials selected from the materials exemplified as constituent materials of the first conductive layer.
  • the interlayer insulating layer (ILD) (or protective layer (PSV)) may be disposed on the second conductive layer and the gate insulating layer (GI).
  • the interlayer dielectric layer (ILD) (or protective layer (PSV)) may include organic and/or inorganic materials.
  • organic materials include polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, and unsaturated polyester. May contain unsaturated polyesters resin, poly-phenylene ethers resin, poly-phenylene sulfides resin, and/or benzocyclobutene resin. You can.
  • the interlayer insulating layer (ILD) may be provided as an organic layer, an inorganic layer, or an organic layer disposed on an inorganic layer.
  • a display element layer may be provided on the interlayer insulating layer (ILD) (or protective layer (PSV)).
  • ILD interlayer insulating layer
  • PSV protective layer
  • the display element layer includes an alignment electrode layer, first and second bank patterns (BNP1, BNP2) (or bank), a light emitting element (LD), first and second electrodes (CNE1, CNE2), and at least It may include a first intermediate electrode (CTE1). Additionally, the display device layer DPL may include first and second insulating layers INS1 and INS2.
  • the alignment electrode layer is disposed on the interlayer insulating layer (ILD) and may include a first alignment electrode (ELT1), a second alignment electrode (ELT2), and a bridge electrode (BRE).
  • ELT1 first alignment electrode
  • ELT2 second alignment electrode
  • BRE bridge electrode
  • the first alignment electrode ELT1 contacts the first semiconductor pattern ACT1 and the first capacitor electrode CE1 (and the back gate electrode BGE) of the first transistor T1 through the first contact hole CNT1. can do.
  • the first alignment electrode ELT1 may form the second capacitor C2 together with the second capacitor electrode CE2. 4 and 6, between the first alignment electrode ELT1 and the second capacitor electrode CE2, in addition to the interlayer insulating layer (ILD) (or insulating layer), a conductive material such as a signal line or a power line is formed. not placed
  • the first alignment electrode ELT1 may form an anode electrode of the first sub-pixel SPX1 together with the first electrode CNE1.
  • the second alignment electrode ELT2 may contact or be electrically connected to the vertical power line PL1_V through a contact hole, but is not limited to this.
  • the bridge electrode (BRE) may contact or be electrically connected to the second horizontal power line (PL2_H) through a contact hole.
  • the bridge electrode (BRE) may electrically connect the second electrode (CNE2) and the second horizontal power line (PL2_H).
  • the first alignment electrode ELT1 (or the first alignment electrode ELT1 before being separated from the bridge electrode BRE) and the second alignment electrode ELT2 receive a predetermined alignment signal (or It can be used as an alignment wiring to align light emitting devices (LD) by receiving an alignment voltage.
  • the first alignment electrode ELT1 receives the first alignment signal (or first alignment voltage) from a part of the pixel circuit layer PCL (for example, the second horizontal power line PL2_H) and 1 It can be used as an alignment wire
  • the second alignment electrode ELT2 receives a second alignment signal (or a second alignment signal) from another component of the pixel circuit layer PCL (for example, the first vertical power line PL1_V). Alignment voltage) can be transmitted and used as a second alignment wiring.
  • the alignment electrode layer may be made of a material having a certain reflectivity in order to allow light emitted from the light emitting device LD to travel in the image display direction of the display device (eg, the third direction DR3).
  • the alignment electrode layer may be made of a conductive material with a certain reflectance.
  • the conductive material may include an opaque metal suitable for reflecting light emitted from the light emitting element LD in the image display direction of the display device.
  • Opaque metals include, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), and iridium ( It may include metals such as Ir), chromium (Cr), titanium (Ti), and alloys thereof.
  • the alignment electrode layer may include a transparent conductive material.
  • Transparent conductive materials include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), and indium gallium zinc oxide (IGZO).
  • conductive oxides such as indium tin zinc oxide (ITZO), and/or conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT).
  • ITZO indium tin zinc oxide
  • PEDOT poly(3,4-ethylenedioxythiophene)
  • the alignment electrode layer includes a transparent conductive material, a separate conductive layer made of an opaque metal may be added to reflect the light emitted from the light emitting device LD in the image display direction of the display device.
  • the material of the alignment electrode layer is not limited to the materials described above.
  • the alignment electrode layer may be provided and/or formed as a single layer, but the present invention is not limited thereto. Depending on embodiments, the alignment electrode layer may be provided and/or formed as a multilayer layer of at least two materials selected from metals, alloys, conductive oxides, and conductive polymers. The alignment electrode layer may be formed of at least a double layer or a multilayer to reduce or minimize distortion due to signal delay when transmitting a signal (or voltage) to the light emitting device LD. As an example, the first alignment electrode ELT1 may be formed of a multilayer layer sequentially stacked in the order of indium tin oxide (ITO)/silver (Ag)/indium tin oxide (ITO). there is.
  • the first and second bank patterns BNP1 and BNP2 may be provided and/or formed on the alignment electrode layer.
  • the first bank pattern BNP1 may be disposed on the first alignment electrode ELT1
  • the second bank pattern BNP2 may be disposed on the second alignment electrode ELT2.
  • the first and second bank patterns BNP1 and BNP2 may be support members that support the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1.
  • the first and second bank patterns BNP1 and BNP2 may change the surface profile (or shape) of the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1.
  • the first and second bank patterns BNP1 and BNP2 may define the emission area EMA (see FIG. 5) of the first sub-pixel SPX1.
  • the first and second bank patterns (BNP1, BNP2) (or banks) are formed by forming a solution containing the light emitting device (LD) adjacent to the first insulating layer (INS1) in the step of supplying the light emitting device (LD). It may be a dam structure that prevents the solution from flowing into the sub-pixels or controls the supply of a certain amount of solution to each sub-pixel.
  • the first and second bank patterns BNP1 and BNP2 may include an inorganic material or an organic material.
  • the first and second bank patterns BNP1 and BNP2 may include a single organic layer and/or a single inorganic layer, but the present invention is not limited thereto.
  • the first and second bank patterns BNP1 and BNP2 may be provided in the form of a multilayer in which at least one organic layer and at least one inorganic layer are stacked.
  • the materials of the first and second bank patterns BNP1 and BNP2 are not limited to the above-described embodiments, and depending on the embodiments, the first and second bank patterns BNP1 and BNP2 are conductive. It may also contain substances.
  • the first and second bank patterns BNP1 and BNP2 may have a trapezoidal cross-section that becomes narrower as it goes upward (for example, along the third direction DR3), but is not limited to this. .
  • the first and second bank patterns BNP1 and BNP2 may include a curved surface having a cross-section such as a semi-elliptical shape or a semi-circular (or hemispherical) shape whose width becomes narrower toward the top. .
  • a semi-elliptical shape or a semi-circular (or hemispherical) shape whose width becomes narrower toward the top.
  • the first and second bank patterns BNP1 and BNP2 are disposed on the electrode layer, but the present invention is not limited thereto.
  • the first and second bank patterns BNP1 and BNP2 may be disposed between the electrode layer and the interlayer insulating layer ILD (or protective layer PSV).
  • the first and second bank patterns BNP1 and BNP2 may be formed through the same process as the interlayer insulating layer ILD (or protective layer PSV).
  • the first and second bank patterns BNP1 and BNP2 may be one area of the interlayer insulating layer ILD (or protective layer PSV).
  • the first and second bank patterns BNP1 and BNP2 may be omitted.
  • a first insulating layer INS1 may be provided and/or formed on the first and second bank patterns BNP1 and BNP2 and the electrode layers (eg, ELT1 and ELT2).
  • the first insulating layer INS1 may include an inorganic material.
  • the present invention is not limited thereto, and the first insulating layer INS1 may include an organic material suitable for flattening the support surface of the light emitting device LD.
  • the light emitting device LD may be disposed on the first insulating layer INS1 between the first and second bank patterns BNP1 and BNP2. In addition, the light emitting device LD is aligned between the first alignment electrode ELT1 (or first bank pattern BNP1) and the second alignment electrode ELT2 (or second bank pattern BNP2) in the plan view. It can be.
  • the light emitting device is an example of an ultra-small light emitting diode using an inorganic crystal structure material, and may be a light emitting diode with a size as small as nanoscale or microscale.
  • the light emitting device LD may include a first semiconductor layer, a second semiconductor layer, an active layer, and an insulating layer.
  • the first semiconductor layer may include a semiconductor layer of a predetermined type
  • the second semiconductor layer may include a semiconductor layer of a different type from the first semiconductor layer.
  • the first semiconductor layer may include an N-type semiconductor layer
  • the second semiconductor layer may include a P-type semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.
  • the active layer is located between the first semiconductor layer and the second semiconductor layer and may have a single or multiple quantum well structure. When an electric field exceeding a predetermined voltage is applied to both ends of the light emitting device LD, electron-hole pairs combine in the active layer and light may be emitted.
  • the number of light-emitting elements LD provided in the first sub-pixel SPX1 may be at least 2 to dozens. Depending on embodiments, the number of light emitting elements LD provided to the first sub-pixel SPX1 may vary.
  • the light emitting device LD may emit either color light and/or white light. In embodiments, the light emitting device LD may emit blue light in a short wavelength band, but is not limited thereto.
  • a second insulating layer INS2 (or a second insulating pattern) may be provided and/or formed on the light emitting device LD.
  • the second insulating layer INS2 may be provided and/or formed on the light emitting device LD to partially cover the outer surface (eg, outer peripheral surface or circumferential surface) of the light emitting device LD.
  • the active layer of the light emitting device LD may not be in contact with an external conductive material due to the second insulating layer INS2.
  • the second insulating layer INS2 may cover only a portion of the outer surface (eg, outer circumferential surface or circumferential surface) of the light emitting device LD, exposing both ends of the light emitting device LD to the outside.
  • the second insulating layer INS2 may be composed of a single layer or a multilayer, and may include at least one inorganic material or organic material.
  • the first electrode CNE1 is provided on the first bank pattern BNP1 and the first alignment electrode ELT1, and is connected to the first alignment electrode ELT1 through a contact hole penetrating the first bank pattern BNP1. You can. Additionally, the first electrode CNE1 may be provided and/or formed on the first end EP1 of the first light-emitting device LD1 and may be connected to the first end EP1 of the light-emitting device LD1.
  • the first electrode CNE1 when a capping layer is disposed on the first alignment electrode ELT1, the first electrode CNE1 is disposed on the capping layer and is connected to the first alignment electrode ELT1 through the capping layer.
  • the capping layer described above protects the first alignment electrode (ELT1) from defects that occur during the manufacturing process of the display device and further strengthens the adhesion between the first alignment electrode (ELT1) and the pixel circuit layer (PCL) located below it. You can do it.
  • the capping layer may include a transparent conductive material (or substance) such as indium zinc oxide (IZO).
  • the first intermediate electrode CTE1 may be provided on the second bank pattern BNP2 and the second alignment electrode ELT2. Additionally, the first intermediate electrode CTE1 may be provided and/or formed on the second end EP2 of the light emitting device LD and may be connected to the second end EP2 of the light emitting device LD.
  • the second electrode CNE2 may be provided on the second bank pattern BNP2 and the second alignment electrode ELT2. Additionally, the second electrode CNE2 overlaps the bridge electrode BRE and may be connected to the bridge electrode BRE through a contact hole penetrating the second bank pattern BNP2. As described with reference to FIG. 5 , the second electrode CNE2 may be electrically connected to the first intermediate electrode CTE1 through the light emitting element LD. Accordingly, the second end EP2 of the light emitting device LD may be electrically connected to the bridge electrode BRE through the first intermediate electrode CTE1 and the second electrode CNE2. According to embodiments, when the first intermediate electrode CTE1 is omitted (for example, in the case of the sub-pixel SPX in FIG. 2B), the second end EP2 of the light-emitting device LD is connected to the second electrode. It may be electrically connected to the bridge electrode (BRE) through (CNE2).
  • the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 are made of various transparent conductive materials. It can be configured. However, the materials of the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 are not limited to the above-described embodiment. Depending on embodiments, the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be made of various opaque conductive materials (or substances). The first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be formed of a single layer or a multilayer.
  • the shapes of the first and second electrodes (CNE1, CNE2) and the first intermediate electrode (CTE1) are not limited to a specific shape, and can be changed in various ways within the range of being stably electrically connected to the light emitting device (LD). there is. Additionally, the shapes of the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be changed in various ways considering their connection relationships with electrodes disposed below them.
  • the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be spaced apart from each other.
  • the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be spaced apart with the second insulating layer INS2 therebetween.
  • the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be formed on the same layer through the same process, but are not limited to this.
  • at least two of the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1 may be provided in different layers and formed through different processes.
  • a third insulating layer may be provided and/or formed on the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1.
  • the third insulating layer may include an inorganic material or an organic material.
  • the third insulating layer may have a structure in which at least one inorganic layer or at least one organic layer is alternately stacked.
  • the third insulating layer entirely covers the display device layer (DPL) and can block external moisture or humidity from flowing into the display device layer (DPL) including the light emitting device (LD).
  • the third insulating layer may flatten the top surface of the display element layer (DPL).
  • the display element layer DPL may optionally further include an optical layer.
  • the display element layer DPL may further include a color conversion layer including color conversion particles that convert light emitted from the light emitting elements LD into light of a specific color.
  • the display element layer (DPL) may further include a color filter that transmits only light in a specific wavelength band.
  • FIGS. 7A and 7B are cross-sectional views showing examples of pixels included in the display device of FIG. 1 .
  • the individual configurations of the pixel circuit layer (PCL) and display element layer (DPL) are briefly expressed in FIGS. 7A and 7B.
  • the light emitting elements LD disposed in each of the sub-pixels SPX1 to SPX3 may emit light of the same color.
  • the sub-pixels SPX1 to SPX3 may include a light emitting device LD that emits a third color, for example, blue light.
  • a color conversion unit (CCL) (or color conversion layer) and/or a color filter unit (CFL) are provided in these sub-pixels (SPX1 to SPX3) to display a full-color image.
  • the present invention is not limited thereto, and the sub-pixels SPX1 to SPX3 may include light emitting elements LD that emit light of different colors.
  • the color conversion unit (CCL) may be disposed on the same layer as the display element layer (DPL).
  • the color conversion unit (CCL) may be disposed between banks (BNK).
  • the bank (BNK) may be located in the non-emission area (NEA) of the sub-pixels (SPX1 to SPX3).
  • the bank BNK may be formed between the sub-pixels SPX1 to SPX3 to surround each light-emitting area EMA, thereby defining the light-emitting area EMA of each of the sub-pixels SPX1 to SPX3.
  • the bank (BNK) prevents the solution for forming the wavelength conversion pattern (WCP) and light transmission pattern (LTP) in the light emitting area (EMA) from flowing into the light emitting area (EMA) of the adjacent sub-pixel, or prevents the solution from flowing into the light emitting area (EMA) of the adjacent sub-pixel. It can function as a dam structure that controls a certain amount of solution to be supplied to the area (EMA).
  • the bank (BNK) may include an organic material or an inorganic material, and depending on embodiments, the bank (BNK) may include a black matrix material (or a light-blocking material).
  • the bank BNK is configured to transmit light generated from a sub-pixel (e.g., the second sub-pixel SPX2) to an adjacent sub-pixel (e.g., the first sub-pixel SPX1, the third sub-pixel SPX3). )) can be prevented from proceeding.
  • An opening may be formed in the bank BNK to expose the display element layer DPL corresponding to the light emitting area EMA.
  • the color conversion unit may include a wavelength conversion pattern (WCP) (or color conversion particle), a light transmission pattern (LTP), and a first capping layer (CAP1).
  • WCP wavelength conversion pattern
  • LTP light transmission pattern
  • CAP1 first capping layer
  • WCP wavelength conversion pattern
  • WCP2 second wavelength conversion pattern
  • the first wavelength conversion pattern WCP1 may be arranged to overlap the emission area EMA of the first sub-pixel SPX1.
  • the first wavelength conversion pattern WCP1 may be provided at the opening of the bank BNK.
  • the second wavelength conversion pattern WCP2 may be arranged to overlap the emission area EMA of the second sub-pixel SPX2.
  • the light transmission pattern (LTP) may be arranged to overlap the emission area (EMA) of the third sub-pixel (SPX3).
  • the first wavelength conversion pattern WCP1 may include first color conversion particles that convert third color light emitted from the light emitting device LD into first color light.
  • the first wavelength conversion pattern (WCP1) is a blue light-emitting device that emits blue light. It may include a first quantum dot that converts light into red light.
  • the first wavelength conversion pattern WCP1 may include a plurality of first quantum dots dispersed in a suitable matrix material (eg, a predetermined matrix material) such as a base resin.
  • the first quantum dot may absorb blue light and shift the wavelength according to energy transition to emit red light.
  • the first wavelength conversion pattern WCP1 may include a first quantum dot corresponding to the color of the first sub-pixel SPX1.
  • the second wavelength conversion pattern WCP2 may include second color conversion particles that convert third color light emitted from the light emitting device LD into second color light.
  • the light emitting device (LD) is a blue light emitting device that emits blue light
  • the second sub-pixel (SPX2) is a green pixel
  • the second wavelength conversion pattern (WCP2) is a blue light emitting device that emits blue light. It may include a second quantum dot that converts light into green light.
  • the second wavelength conversion pattern WCP2 may include a plurality of second quantum dots dispersed in a predetermined matrix material such as a base resin.
  • the second quantum dot may absorb blue light and shift the wavelength according to energy transition to emit green light.
  • first quantum dot and the second quantum dot are in the form of spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanoplate-shaped particles, etc. may have, but is not necessarily limited to this, and the shapes of the first quantum dot and the second quantum dot may be changed in various ways.
  • the absorption coefficients of the first quantum dot and the second quantum dot may be increased by making blue light having a relatively short wavelength in the visible light region incident on the first quantum dot and the second quantum dot, respectively. Accordingly, it is possible to ultimately increase the efficiency of light emitted from the first sub-pixel (SPX1) and the second sub-pixel (SPX2) and secure excellent color reproduction.
  • the manufacturing efficiency of the display device can be increased by constructing the pixel PXL using the same color light emitting device LD (for example, a blue light emitting device).
  • the light transmission pattern (LTP) may be provided to efficiently use the third color light emitted from the light emitting device (LD).
  • the light emitting device (LD) is a blue light emitting device that emits blue light and the third sub-pixel (SPX3) is a blue pixel
  • the light transmission pattern (LTP) efficiently transmits the light emitted from the light emitting device (LD). It may contain at least one type of light scattering particles for use as a light scattering particle.
  • the light transmission pattern (LTP) may include a plurality of light scattering particles dispersed within a suitable matrix material (eg, any matrix material) such as a base resin.
  • a suitable matrix material eg, any matrix material
  • the light transmission pattern (LTP) may include light scattering particles such as silica, but the constituent materials of the light scattering particles are not limited thereto.
  • the light scattering particles do not have to be disposed only in the light emitting area (EMA) for the third sub-pixel (SPX3).
  • light scattering particles may be selectively included in the first wavelength conversion pattern (WCP1) and/or the second wavelength conversion pattern (WCP2).
  • the first capping layer (CAP1) may seal (or cover) the wavelength conversion pattern (WCP) and the light transmission pattern (LTP).
  • the first capping layer CAP1 may be disposed between the low refractive index layer LRL and the display element layer DPL.
  • the first capping layer CAP1 may be provided across the sub-pixels SPX1 to SPX3.
  • the first capping layer (CAP1) can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion unit (CCL).
  • the first capping layer (CAP1) is made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), and titanium oxide (TiO x ) and may be composed of a single layer or multiple layers including at least one insulating material selected from among, but is not necessarily limited thereto.
  • the optical layer (OPL) may include a low refractive index layer (LRL) and a second capping layer (CAP2).
  • the optical layer (OPL) may be disposed on the color conversion unit (CCL).
  • the optical layer (OPL) may be disposed on the display element layer (DPL).
  • the low refractive layer LRL may be disposed between the first capping layer CAP1 and the second capping layer CAP2.
  • the low refractive layer (LRL) may be disposed between the color conversion unit (CCL) and the color filter unit (CFL).
  • the low refractive layer (LRL) may be provided across the sub-pixels (SPX1 to SPX3).
  • the low refractive layer (LRL) may play a role in improving light efficiency by recycling light provided from the color conversion unit (CCL) through total reflection.
  • the low refractive index layer (LRL) may have a relatively low refractive index compared to the color conversion unit (CCL).
  • the low refractive index layer may include a base resin and hollow particles dispersed within the base resin.
  • the hollow particles may include hollow silica particles.
  • the hollow particles may be pores formed by porogen, but are not necessarily limited thereto.
  • the low refractive index layer (LRL) may include at least one of zinc oxide (ZnO) particles, titanium dioxide (TiO2) particles, or nano silicate particles, but is not necessarily limited thereto.
  • the second capping layer (CAP2) may be disposed on the low refractive index layer (LRL).
  • the second capping layer (CAP2) may be disposed between the color filter unit (CFL) and the low refractive index layer (LRL).
  • the second capping layer CAP2 may be provided across the sub-pixels SPX1 to SPX3.
  • the second capping layer (CAP2) can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive index layer (LRL).
  • the second capping layer CAP2 may include the same material as the first capping layer CAP1, or may include one or more materials selected from the materials exemplified as constituent materials of the first capping layer CPA1.
  • the color filter unit (CFL) may be disposed on the second capping layer (CAP2).
  • the color filter unit (CFL) may be provided across the sub-pixels (SPX1 to SPX3).
  • the color filter unit (CFL) may include color filters (CF1 to CF3), a planarization layer (PLA), and an overcoat layer (OC).
  • the color filters CF1 to CF3 may be disposed on the second capping layer CAP2. When viewed on a plane, the color filters CF1 to CF3 may overlap the emission area EMA of the sub-pixels SPX1 to SPX3.
  • the first color filter CF1 may transmit first color light, but may not transmit second color light and third color light.
  • the first color filter CF1 may include a colorant for the first color.
  • the second color filter CF2 may transmit second color light, but may not transmit first color light and third color light.
  • the second color filter CF2 may include a color agent for the second color.
  • the third color filter CF3 may transmit third color light, but may not transmit first color light and second color light.
  • the third color filter CF3 may include a colorant for the third color.
  • the planarization layer (PLA) may be disposed on the color filters CF1 to CF3.
  • the planarization film (PLA) can cover the color filters (CF1 to CF3).
  • the planarization film (PLA) can offset the level difference caused by the color filters (CF1 to CF3).
  • the planarization layer (PLA) may be provided across the sub-pixels (SPX1 to SPX3).
  • the planarization layer (PLA) may include an organic material, but is not limited thereto.
  • the planarization layer (PLA) may include an inorganic material.
  • the overcoat layer (OC) may be disposed on the planarization layer (PLA).
  • the overcoat layer (OC) may be disposed between the upper film layer (UFL) and the planarization layer (PLA).
  • the overcoat layer (OC) may be provided over the sub-pixels (SPX1 to SPX3).
  • the overcoat layer (OC) may cover the lower member including the color filter unit (CFL).
  • the overcoat layer (OC) can prevent moisture or air from penetrating into the above-described lower member. Additionally, the overcoat layer (OC) can protect the above-described lower member from foreign substances such as dust.
  • the overcoat layer (OC) may include organic or inorganic materials.
  • the overcoat layer (OC) may include one or more materials selected from those exemplified as constituent materials of the planarization layer (PLA).
  • the upper film layer (UFL) may be disposed on the color filter unit (CFL).
  • the upper film layer (UFL) may be disposed on the outside of the display device to reduce external influences on the display device.
  • the upper film layer (UFL) may be provided over the sub-pixels (SPX1 to SPX3).
  • the upper film layer may include an anti-reflective coating (AR coating layer).
  • AR coating layer may refer to a composition in which a material with an anti-reflection function is applied to one surface of a specific composition.
  • the applied material may have a low reflectivity.
  • the material used in the AR coating layer may include any one of silicon oxide (SiO x ), aluminum oxide (AlO x ), and titanium oxide (TiO x ).
  • SiO x silicon oxide
  • AlO x aluminum oxide
  • TiO x titanium oxide
  • the color conversion unit CCL has been described as being disposed on the same layer as the display element layer DPL, but the present invention is not limited thereto.
  • the color conversion unit CCL may be disposed on the display element layer DPL.
  • the first capping layer (CAP1) may seal (or cover) the area where the light emitting elements (LD) are disposed, and the color conversion unit (CCL) may be disposed on the first capping layer (CAP1). there is.
  • the color conversion unit (CCL) may further include a light blocking layer (LBL) (or a light blocking pattern).
  • the light blocking layer (LBL) may be disposed on the display element layer (DPL) and the first capping layer (CAP1).
  • the light blocking layer (LBL) may be disposed between the first capping layer (CAP1) and the second capping layer (CAP2).
  • the light blocking layer (LBL) is formed at the boundary of the sub-pixels (SPX1 to SPX3) (for example, in the non-display area (NEA)), the first wavelength conversion pattern (WCP1), the second wavelength conversion pattern (WCP2), and It may be arranged to surround the light transmission pattern (LTP).
  • the light blocking layer (LBL) may define an emission area (EMA) and a non-emission area (NEA).
  • the light blocking layer (LBL) may not overlap the light emitting area (EMA) when viewed on a plane.
  • the light blocking layer (LBL) may overlap the non-emissive area (NEA) when viewed on a plane.
  • the area where the light blocking layer (LBL) is not disposed may be defined as the emission area (EMA) of the sub-pixels (SPX1 to SPX3).
  • the light blocking layer is formed of an organic material containing at least one of graphite, carbon black, black pigment, or black dye, or chromium ( It may be formed of a metal material containing Cr), but is not limited as long as it is a material that can block and absorb light transmission.
  • the second capping layer (CAP2) may seal (or cover) the first wavelength conversion pattern (WCP1), the second wavelength conversion pattern (WCP2), and the light transmission pattern (LTP).
  • the low refractive index layer (LRL) may be disposed between the second capping layer (CAP2) and the third capping layer (CAP3).
  • the third capping layer CAP3 may include the same material as the first capping layer CPA1, or may include one or more materials selected from materials exemplified as constituent materials of the first capping layer CPA1.
  • the color filter unit (CFL) and the upper film layer (UFL) may be disposed on the first capping layer (CPA1).
  • FIG. 8 is a layout diagram for explaining the manufacturing process of the display device of FIG. 1.
  • Figure 8 may correspond to Figure 4.
  • an electrode layer may be formed on the interlayer insulating layer (ILD).
  • the electrode layer may include a reference alignment electrode ELT0 (or first alignment wire) and a second alignment electrode ELT2 (or second alignment wire).
  • the reference alignment electrode ELT0 may be an electrode before being separated into the first alignment electrode ELT1 and the bridge electrode BRE of FIG. 4 . Similar to the second alignment electrode ELT2, the reference alignment electrode ELT0 may extend to sub-pixels adjacent to the first sub-pixel SPX1 in the second direction DR2.
  • first and second bank patterns (BNP1, BNP2) (or banks) shown in FIG. 6 are formed on the electrode layer, and the first and second bank patterns (BNP1, BNP2) are formed on the electrode layer and the first and second bank patterns (BNP1, BNP2).
  • INS1 An insulating layer
  • the light emitting device LD may be supplied to the light emitting area (EMA, see FIG. 5).
  • the light emitting element (LD) is prepared in a dispersed form in an appropriate solution (e.g., a predetermined solution, e.g., ink), and is formed into a light emitting area (EMA) through an inkjet printing method or a slit coating method.
  • an appropriate solution e.g., a predetermined solution, e.g., ink
  • EMA light emitting area
  • an alignment signal may be applied to the reference alignment electrode ELT0 and the second alignment electrode ELT2.
  • a ground voltage may be applied to the reference alignment electrode ELT0 and an alternating current voltage may be applied to the second alignment electrode ELT2, but the present invention is not limited thereto.
  • the solvent may be volatilized or removed in another manner.
  • the second insulating layer INS2 shown in FIG. 6 may be formed.
  • the reference alignment electrode (ELT0) is aligned with the first alignment electrode (ELT1) and the bridge. It can be separated by electrodes (BRE).
  • the first insulating layer INS1 of FIG. 6 may also be removed. Accordingly, the alignment electrode and the first insulating layer INS1 do not exist or are not disposed in the electrode opening ELO (i.e., the boundary area between adjacent sub-pixels in the second direction DR2) of FIG. 4, or the electrode opening ELO An opening may be formed in the first insulating layer INS1 corresponding to (ELO).
  • the first and second electrodes CNE1 and CNE2 (and the first intermediate electrode CTE1) shown in FIG. 6 may be formed.
  • the color conversion unit (CCL) and the color filter unit (CFL) shown in FIGS. 7A and 7B may be formed sequentially.
  • the first alignment electrode ELT1 (or the reference alignment electrode ELT0) is used as an electrode for aligning the light emitting device LD during the manufacturing process of the display device. Afterwards, the first alignment electrode ELT1 may be separated from the bridge electrode BRE and function as one electrode of the storage capacitor Cst.
  • FIG. 9 is a layout diagram illustrating embodiments of pixels included in the display device of FIG. 1 .
  • FIG. 9 shows the layout of sub-pixels centered on the pixel circuit (PXC) (or pixel circuit layer) of the sub-pixels (SPX) of FIGS. 2A to 2D.
  • Figure 9 may correspond to Figure 3.
  • FIG. 10 is a cross-sectional view showing embodiments of the first sub-pixel along lines III-III' and II-II' of FIG. 9.
  • Figure 10 may correspond to Figure 6.
  • the pixels (PXL) of FIGS. 9 and 10 are the same as those of FIG. 3. It may be substantially the same as or similar to the pixel (PXL) of FIGS. Therefore, overlapping explanations will not be repeated.
  • the second capacitor electrode (CE2_1) may be included in the same layer as the first semiconductor pattern (ACT1). As shown in FIG. 9 , the second capacitor electrode CE2_1 may be formed integrally with the second semiconductor pattern ACT2. For example, the second capacitor electrode CE2_1 may be a partial region of the second semiconductor pattern ACT2 doped with impurities. However, the present invention is not limited thereto, and for example, the second capacitor electrode CE2_1 may be a separate semiconductor pattern separated from the second semiconductor pattern ACT2.
  • the second capacitor electrode CE2_1 may overlap the first capacitor electrode CE1 and form the first capacitor C1_1.
  • the second capacitor electrode CE2_1 is generally covered in the third direction DR3 by the first capacitor electrode CE1, and the area of the second capacitor electrode CE2_1 is equal to the area of the first capacitor electrode CE1. It can be smaller than In order to increase or maximize the capacitance (or capacity) of the first capacitor C1, except for the area corresponding to the first contact hole CNT1 and the second contact hole CNT2 shown in FIG. 4, additional Excluding the area corresponding to the fourth bridge pattern BRP4 constituting the gate electrode of the first transistor T1, the second capacitor electrode CE2_1 overlaps most of the area of the first capacitor electrode CE1. can do.
  • the pixel PXL of FIGS. 9 and 10 has the configuration of the light source unit (LSU, see FIG. 2D) shown in FIG. 5 (i.e., first and second alignment electrodes ELT1 and ELT2, bridge electrode BRE, etc. ) can be included as is.
  • LSU light source unit
  • first and second alignment electrodes ELT1 and ELT2, bridge electrode BRE, etc. can be included as is.
  • the first alignment electrode ELT1 may overlap the second capacitor electrode CE2_1 and form the second capacitor C2_1.
  • the second capacitor C2_1 and the first capacitor C1_1 may share the second capacitor electrode CE2_1. Since the first alignment electrode ELT1 contacts or is electrically connected to the first capacitor electrode CE1 through the first contact hole CNT1, the first capacitor C1_1 and the second capacitor C2_1 may be connected in parallel. .
  • the fourth bridge pattern BRP4 may be included in the same layer as the gate electrode of the first transistor T1 and the other bridge patterns BRP1 to BPR3. That is, the fourth frit pattern BRP4 may be included in the second conductive layer described with reference to FIG. 6 .
  • One end (eg, upper end) of the fourth bridge pattern BRP4 overlaps the second capacitor electrode CE2_1 and may be in contact with or connected to the second capacitor electrode CE2_1 through a contact hole.
  • the other end (eg, lower end) of the fourth bridge pattern BRP4 overlaps the first semiconductor pattern ACT1 and may form a gate electrode of the first transistor T1.
  • a capacitor may be formed between the fourth bridge pattern (BRP4) and the first capacitor electrode (CE1) and between the fourth bridge pattern (BRP4) and the first alignment electrode (ELT1), and the capacitor may also be formed as a storage capacitor (Cst). may be included in
  • the second capacitor electrode CE2_1 (and the fourth bridge pattern BPR4), which is a doped partial semiconductor pattern (e.g., a partial region of the second semiconductor pattern ACT2) and the first capacitor electrode ( CE1) may form the first capacitor C1_1, and the second capacitor electrode CE2_1 (and the bridge pattern BPR4) and the first alignment electrode ELT1 may form the second capacitor C2_1. Accordingly, the capacitance (or capacity) of the storage capacitor Cst can be more sufficiently secured, the sub-pixel can accurately emit light at the target luminance, and display quality can be improved.
  • the second capacitor electrodes CE2 and CE2_1 which are common electrodes of the first capacitor C1 and the second capacitor C2, are explained as gate electrodes or semiconductor patterns, but are limited thereto. no.
  • part of the common electrode may be formed on the same layer as the gate electrode, and the remaining part of the common electrode may be formed of a semiconductor pattern.
  • FIG. 11 is a diagram showing a light emitting device according to embodiments. Although FIG. 11 shows a pillar-shaped light emitting device LD, the type and/or shape of the light emitting device LD is not limited thereto.
  • the light emitting device includes a first semiconductor layer 11 and a second semiconductor layer 13, and an active layer 12 interposed between the first and second semiconductor layers 11 and 13.
  • the light emitting device LD includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13.
  • the light emitting device LD may be provided in a pillar shape extending in one direction.
  • the light emitting device LD may have a first end EP1 and a second end EP2.
  • One of the first and second semiconductor layers 11 and 13 may be disposed at the first end EP1 of the light emitting device LD.
  • the remaining one of the first and second semiconductor layers 11 and 13 may be disposed at the second end EP2 of the light emitting device LD.
  • the light emitting device LD may be a light emitting device manufactured into a pillar shape through an etching method or the like.
  • the column shape refers to a rod-like shape or bar-like shape that is long in the length (L) direction (i.e., the aspect ratio is greater than 1), such as a circular column or a polygonal column. It encompasses, and the shape of its cross section is not particularly limited.
  • the length (L) of the light emitting device (LD) may be larger than its diameter (D) (or the width of the cross section).
  • the light emitting device (LD) may have a small size ranging from nanometer scale to micrometer scale.
  • the light emitting device LD may each have a diameter (D) (or width) and/or length (L) ranging from nanometer scale to micrometer scale.
  • D diameter
  • L length
  • the size of the light-emitting device (LD) is not limited to this, and the size of the light-emitting device (LD) may vary depending on the design conditions of various devices that use the light-emitting device (LD) as a light source, for example, a display device. It can be changed in various ways.
  • the first semiconductor layer 11 may be a semiconductor layer of a first conductivity type.
  • the first semiconductor layer 11 may include an n-type semiconductor layer.
  • the first semiconductor layer 11 includes a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a first conductivity type dopant such as Si, Ge, Sn, etc. It may include a type semiconductor layer.
  • the material constituting the first semiconductor layer 11 is not limited to this, and the first semiconductor layer 11 may be composed of various other materials.
  • the active layer 12 is disposed on the first semiconductor layer 11 and may be formed in a single-quantum well or multi-quantum well structure.
  • the position of the active layer 12 may vary depending on the type of light emitting device (LD).
  • a clad layer doped with a conductive dopant may be formed on the top and/or bottom of the active layer 12.
  • the clad layer may be formed of AlGaN or InAlGaN.
  • materials such as AlGaN and InAlGaN may be used to form the active layer 12, and various other materials may form the active layer 12.
  • the second semiconductor layer 13 is disposed on the active layer 12 and may include a different type of semiconductor layer from the first semiconductor layer 11.
  • the second semiconductor layer 13 may include a p-type semiconductor layer.
  • the second semiconductor layer 13 includes at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is a p-type semiconductor layer doped with a second conductivity type dopant such as Mg. It can be included.
  • the material constituting the second semiconductor layer 13 is not limited to this, and various other materials may constitute the second semiconductor layer 13.
  • the light emitting device LD When a voltage higher than the threshold voltage is applied to both ends of the light emitting device LD, electron-hole pairs combine in the active layer 12 and the light emitting device LD emits light.
  • the light emitting device LD can be used as a light source for various light emitting devices, including pixels of a display device.
  • the light emitting device (LD) may further include an insulating film (INF) provided on its surface.
  • the insulating film INF may be formed on the surface of the light emitting device LD to surround at least the outer surface (e.g., outer peripheral surface or circumferential surface) of the active layer 12, and in addition to the first and second semiconductor layers 11 , 13) can further surround the area.
  • the insulating film INF may expose both ends of the light emitting device LD having different polarities.
  • the insulating film INF may expose one end of each of the first and second semiconductor layers 11 and 13 located at the first and second ends EP1 and EP2 of the light emitting device LD.
  • the insulating film INF is formed on the sides of the first and second semiconductor layers 11 and 13 adjacent to the first and second ends EP1 and EP2 of the light emitting device LD having different polarities. may be exposed.
  • the insulating film (INF) is made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), and titanium oxide (TiO x It may include at least one selected insulating material and may be composed of a single layer or multiple layers (for example, a double layer composed of aluminum oxide (AlO x ) and silicon oxide (SiO x )), but is not necessarily limited thereto. Depending on the embodiment, the insulating film INF may be omitted.
  • the active layer 12 is the first pixel electrode or the first pixel electrode to be described later. 2 It can prevent short-circuiting with the pixel electrode, etc. Accordingly, the electrical stability of the light emitting device LD can be secured.
  • an insulating film (INF) is provided on the surface of the light emitting device (LD)
  • surface defects of the light emitting device (LD) can be reduced or minimized to improve lifespan and efficiency.
  • a plurality of light emitting elements LD are arranged close to each other, it is possible to prevent unwanted short circuits from occurring between the light emitting elements LD.
  • the light emitting device LD may further include additional components in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and/or an insulating film (INF) surrounding them.
  • the light emitting device LD may include one or more phosphor layers, an active layer, a semiconductor layer, and/or disposed on one end of the first semiconductor layer 11, the active layer 12, and/or the second semiconductor layer 13.
  • An electrode layer may additionally be included.
  • a contact electrode layer may be disposed on the first and second ends EP1 and EP2 of the light emitting device LD, respectively.
  • a pillar-shaped light emitting device (LD) is illustrated in FIG. 11, the type, structure, and/or shape of the light emitting device (LD) may be changed in various ways.
  • the light emitting device LD may be formed in a core-shell structure having a polygonal pyramid shape.
  • Light-emitting devices including the above-described light-emitting elements (LD) can be used in various types of devices that require a light source, including display devices.
  • a plurality of light-emitting devices (LD) may be disposed within each pixel of the display panel, and the light-emitting devices (LD) may be used as a light source for each pixel.
  • the application field of the light emitting device (LD) is not limited to the examples described above.
  • the light emitting device (LD) can also be used in other types of devices that require a light source, such as lighting devices.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

La présente invention concerne un dispositif d'affichage qui comprend un motif semi-conducteur. Une première électrode de condensateur est disposée au-dessous du motif semi-conducteur. Une seconde électrode de condensateur est disposée sur le motif semi-conducteur et une partie de celle-ci constitue une électrode de grille. Une première électrode et une seconde électrode sont disposées dans la même couche sur la seconde électrode de condensateur. Au moins un élément électroluminescent est disposé entre la première électrode et la seconde électrode. Une première électrode de pixel est disposée sur la première électrode et connectée à une première extrémité du ou des éléments électroluminescents. Une seconde électrode de pixel est disposée sur la seconde électrode et connectée à une seconde extrémité du ou des éléments électroluminescents. La première électrode est électriquement connectée à la première électrode de condensateur et au motif semi-conducteur. Le motif semi-conducteur et l'électrode de grille constituent un transistor. Un premier condensateur est formé par la première électrode de condensateur et la seconde électrode de condensateur.
PCT/KR2023/009777 2022-08-01 2023-07-10 Dispositif d'affichage Ceased WO2024029765A1 (fr)

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