WO2024027729A1 - 具有支护层的pmut结构及其制造方法 - Google Patents

具有支护层的pmut结构及其制造方法 Download PDF

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Publication number
WO2024027729A1
WO2024027729A1 PCT/CN2023/110643 CN2023110643W WO2024027729A1 WO 2024027729 A1 WO2024027729 A1 WO 2024027729A1 CN 2023110643 W CN2023110643 W CN 2023110643W WO 2024027729 A1 WO2024027729 A1 WO 2024027729A1
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layer
pmut
transistor
piezoelectric
conductive
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PCT/CN2023/110643
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English (en)
French (fr)
Inventor
庞慰
牛鹏飞
张孟伦
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天津大学
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Publication of WO2024027729A1 publication Critical patent/WO2024027729A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B3/00—Methods or apparatus specially adapted for transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
    • B06B2201/50—Application to a particular transducer type
    • B06B2201/55—Piezoelectric transducer

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular to a PMUT structure with a supporting layer and a manufacturing method thereof, a PMUT structure array, and an electronic device having the PMUT structure or the PMUT structure array.
  • PMUT Piezoelectric Micromachined Ultrasonic Transducer
  • PMUT is a MEMS device that uses the forward and reverse piezoelectric effects of piezoelectric materials to vibrate the piezoelectric film to emit or receive ultrasonic signals.
  • PMUT can be used as both an actuator (emitting sound waves) and a sensor (receiving sound waves).
  • the mass production and wafer-level packaging of PMUT based on MEMS standard technology greatly reduces the cost and is very suitable for large-scale commercial applications.
  • PMUT has good application prospects in ultrasonic ranging, ultrasonic imaging, ultrasonic non-destructive testing, ultrasonic fingerprint recognition, ultrasonic drivers, etc.
  • Ultrasonic ranging is one of the important applications of PMUT. It mainly uses Time of Flight (TOF), that is, the time interval from transmitting to receiving ultrasonic waves, to determine the distance. Based on this principle, PMUT ultrasonic ranging is used in scenarios such as car reversing radar, underwater sonar detection, sweeping robots, and ultrasonic smoke alarms.
  • the PMUT ultrasonic fingerprint sensor which is mainly based on Time of Flight (TOF), can detect fingerprints in the dermal layer of the finger, identify fake fingerprints made of resin, and can also enable those with epidermal fingerprint damage caused by mechanical wear. Smoothly reading fingerprints is another important application of PMUT, which plays a very important role in information security and other fields.
  • non-destructive testing is a typical application of PMUT in the industrial field.
  • Ultrasound detects object damage by detecting flight time and return signal strength. It has a very wide and urgent demand in the fields of power grid, rail and chemical industry.
  • PMUT array full-focus imaging also has the potential to realize 3D imaging, which is expected to break through the limitation of existing detection technology that cannot detect subtle damage; at the same time, its small size can fully meet the needs of non-destructive flaw detection in the industrial field in the field of portability and low power consumption. Require.
  • PMUT ultrasonic medical imaging detects the flight time and the strength of the return signal.
  • PMUT high-density array fully focused phased array imaging will The diagnostic speed and diagnostic accuracy are greatly improved. It will demonstrate strong application capabilities in the field of medical diagnosis.
  • PMUT can also be used as an energy source and can be used in fields such as ultrasonic excitation and energy transmission.
  • CMOS Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor
  • Solution 1 Use the CMOS wafer as the substrate and perform various thin film deposition and etching processes on it.
  • the PMUT manufacturing process includes the deposition of various thin films (such as piezoelectric films, electrode films, etc.) at different temperatures and the corresponding The etching of thin films in different atmospheres and liquid environments requires that the processing process does not cause damage to the CMOS circuit.
  • piezoelectric materials only a few piezoelectric films such as AlN-based piezoelectric materials have MEMS manufacturing processes that are compatible with CMOS. Therefore, this solution is mainly used for the development of integrated ultrasonic transducers based on corresponding piezoelectric materials. .
  • the piezoelectric properties of the piezoelectric film are a crucial determinant of PMUT performance.
  • PZT polycrystalline lead zirconate titanate
  • LiNbO 3 LiNbO 3
  • other piezoelectric materials with very excellent piezoelectric properties have more demanding processing techniques than AlN.
  • has poor compatibility with CMOS so the development of CMOS integrated PMUT based on the above process flow is more limited and difficult to implement.
  • the cavity size is the core factor that determines the PMUT ultrasonic frequency, and changes in the cavity size will lead to changes in the PMUT ultrasonic frequency.
  • alignment deviations inevitably occur, resulting in random deviations between the vibration unit area and its own design, resulting in frequency fluctuations of the developed CMOS integrated PMUT.
  • the diameter of PMUT transducers used in the field of ultrasound imaging is very small, usually tens of microns or even smaller. Even an alignment deviation of 1 micron will cause great adverse effects.
  • CMOS wafers as substrates, which are subjected to various thin film depositions (including but not limited to support layers, electrode layers, piezoelectric layers, etc.) and etching processes to achieve CMOS integration.
  • PMUT integrated on wafer CMOS wafers as substrates, which are subjected to various thin film depositions (including but not limited to support layers, electrode layers, piezoelectric layers, etc.) and etching processes to achieve CMOS integration.
  • thin film depositions including but not limited to support layers, electrode layers, piezoelectric layers, etc.
  • the PMUT unit integrated on CMOS exhibits a bending vibration mode, that is, the vibration unit bends and vibrates in the direction perpendicular to the thickness of the film and emits ultrasonic waves outward.
  • the CMOS side facing the PMUT vibration unit i.e., the front side of the CMOS
  • the overall thickness of the film on both sides of the PMUT piezoelectric film is inconsistent, with one side thicker than the other. , so that the center of mass of the entire vibrating unit is not at the center of the piezoelectric film, preventing the diaphragm from vibrating in the thickness expansion mode.
  • piezoelectric material itself.
  • the growth of piezoelectric films is carried out on CMOS-based wafers with very complex surfaces.
  • the surface of the CMOS wafer on which piezoelectric films are grown has different types of materials and uneven surfaces. steps, etc., so it is difficult to achieve the deposition of high-quality piezoelectric films, especially single crystal piezoelectric films.
  • Embodiments of the present invention relate to a PMUT structure, including:
  • a transistor unit one side of which includes a transistor
  • the PMUT unit includes a PMUT and a supporting layer.
  • the PMUT includes a first electrode layer, a second electrode layer and a piezoelectric layer.
  • the first electrode layer and the second electrode layer are respectively provided on one side and the other side of the piezoelectric layer.
  • the PMUT structure further includes a cavity for the PMUT;
  • One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat portion bonded to the other side of the piezoelectric layer.
  • Embodiments of the present invention also relate to a method of manufacturing a PMUT structure, the PMUT structure including a cavity for the PMUT, and the method includes the steps:
  • the PMUT unit connected to the transistor unit is provided.
  • the PMUT unit includes a PMUT and a supporting layer.
  • the PMUT includes a first electrode layer, a second electrode layer and a piezoelectric layer.
  • a first electrode layer is provided on one side and the other side of the piezoelectric layer. and the second electrode layer,
  • One side of the support layer is bonded to one side of the transistor unit, and the other side of the support layer includes a connection to the piezoelectric layer.
  • Embodiments of the present invention also relate to a PMUT structure array, including a plurality of the above-mentioned PMUT structures, or a plurality of PMUT structures manufactured by the above-mentioned manufacturing method.
  • Embodiments of the present invention also relate to an electronic device, including the above-mentioned PMUT structure, or the PMUT structure manufactured by the above-mentioned manufacturing method, or the above-mentioned PMUT structure array.
  • Figure 1 is a schematic structural diagram of a PMUT structure according to an exemplary embodiment of the present invention.
  • 2-9 are schematic cross-sectional views illustrating a manufacturing method of a PMUT structure according to an exemplary embodiment of the present invention.
  • Figure 10 is a schematic structural diagram of a PMUT structure according to another exemplary embodiment of the present invention.
  • Figure 11 is a schematic structural diagram of a PMUT structure according to yet another exemplary embodiment of the present invention.
  • Figure 12 is a schematic diagram of a PMUT structure array according to an exemplary embodiment of the present invention.
  • CMOS unit or transistor unit see Figure 1 and Figure 2).
  • CMOS substrate or transistor substrate optional materials are single crystal silicon, gallium nitride, gallium arsenide, sapphire, quartz, silicon carbide, diamond, etc.
  • Circuit protection layer which is an insulating material layer, which can be silicon dioxide, silicon nitride, etc.
  • the electrical connection layer within the transistor unit layer, corresponding to the first electrical connection layer, the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or their alloys etc., the above materials are also suitable for other electrical connection layers.
  • Supporting protective layer (supporting layer), the material of which can be one of aluminum nitride, silicon nitride, silicon carbide, polycrystalline silicon, single crystal silicon, silicon dioxide, amorphous silicon, and doped silicon dioxide.
  • Sacrificial material layer the material of which can be silicon dioxide, doped silicon dioxide, etc.
  • Support layer the material of which includes one of silicon, silicon dioxide, silicon nitride, aluminum nitride, molybdenum, platinum, etc.
  • the thickness of the support layer 210 is in the range of 0.1 ⁇ m-10 ⁇ m.
  • an electrical isolation layer (insulating film material can optionally be used) needs to be provided between the support layer 210 and the conductive layers 260A/260B mentioned later.
  • Electrode layer the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • the materials of the two electrode layers can be the same or different.
  • the materials can be polycrystalline aluminum nitride (AlN), polycrystalline zinc oxide, polycrystalline lead zirconate titanate (PZT), polycrystalline lithium niobate (LiNbO 3 ), polycrystalline Materials such as lithium tantalate (LiTaO 3 ), polycrystalline potassium niobate (KNbO 3 ), or single crystal aluminum nitride, single crystal gallium nitride, single crystal lithium niobate, single crystal lead zirconate titanate, single crystal niobate Materials such as potassium, single crystal quartz film, or single crystal lithium tantalate.
  • the above single crystal or polycrystalline materials may also include rare earth element doped materials with a certain atomic ratio, all of which are piezoelectric layers that can be used in the present invention. .
  • 260A, 260B conductive layer, the material of which can be selected from the materials used to form the electrode layer.
  • Device protective layer usually dielectric material, such as silicon dioxide, aluminum nitride, silicon nitride, etc.
  • Bonding material layer (for example, see FIG. 1 ), which is used to bond the support layer 200 and the circuit protection layer 110 , and may be a metal bonding layer, for example.
  • Auxiliary substrate, optional materials are single crystal silicon, gallium nitride, gallium arsenide, sapphire, quartz, silicon carbide, diamond, etc.
  • FIG. 1 is a schematic structural diagram of a PMUT structure according to an exemplary embodiment of the present invention. As shown in Figure 1, the PMUT structure 3000 includes:
  • the transistor unit 1000 includes a transistor (which includes a source electrode and a drain electrode 101, a gate electrode 111), a first electrical connection layer 113A and a second electrical connection layer 113B that are electrically insulated from each other, Circuit protection layer 110, the circuit protection layer 110 covers the transistor, the first electrical connection layer 113A and the second electrical connection layer 113B;
  • the PMUT unit 2000 (see Figure 1) includes a support layer 200 and a PMUT, which includes a first electrode layer 250, a second electrode layer 230 and a piezoelectric layer 240; and
  • the first conductive layer 260A and the second conductive layer 260B are electrically insulated from each other, see Figure 1,
  • the PMUT structure also includes a cavity 201 for PMUT.
  • a support layer 220 is provided on the upper side of the cavity 201.
  • Above the support layer 220 is a second electrode layer 230, as shown in Figure 1. It can be seen that in Figure In 1, the cavity 201 is provided in the supporting layer 200;
  • the piezoelectric layer 240 is a single crystal thin film layer.
  • One side of the supporting layer 200 (shown in FIG. 1 , is the lower side) and one side of the circuit protection layer 110 (shown in FIG. 1 , is the upper side). ) is provided between the flat surface portion of the other side of the supporting layer 200 (the upper side of the supporting layer 200 in FIG. 1 ) and the other side of the piezoelectric layer 240 (the upper side of the supporting layer 200 in FIG. 1 ). (underside of electrical layer 240).
  • joining not only includes the direct joining of the two as shown in Figure 1, such as direct bonding, but the bonding scheme can adopt a variety of methods, including silicon-silicon bonding, silicon -SiO 2 bonding, etc., may also include the case where other bonding layers or film layers are provided between the two, which are all within the scope of the present invention.
  • the bonding between the support layer 200 and the circuit protection layer 110 passes through the material bonding layer 300 , but the invention is not limited thereto.
  • the support layer 200 is directly connected to the circuit protection layer 110 .
  • these are all included in the scope of "joining one side of the supporting layer 200 and one side of the circuit protective layer 110", that is, the above-mentioned joining not only includes the direct joining of the supporting layer 200 and the circuit protective layer 110 as shown in Figure 11, but also includes As shown in FIG. 1 , another layer or film layer (for example, the bonding material layer 300 ) is provided between the two.
  • the other side of the support layer 200 (the upper side of the support layer 200 in the figure) is bonded to the piezoelectric layer 240 and is connected to one side of the support layer 200 with the circuit protection layer 110 Similar to "side joint", surface contact can be direct surface contact or indirect surface contact, both of which are within the protection scope of the present invention.
  • connection between the support layer 200 and the circuit protection layer 110 is taken as an example.
  • connection between the PMUT unit 2000 and the CMOS unit 1000 may be limited to CMOS.
  • the circuit protection layer on the surface of the unit can also be other layers that define the surface of the CMOS unit, which are all within the protection scope of the present invention.
  • the CMOS unit 1000 further includes a CMOS substrate 100 , one side of the circuit protection layer 110 is bonded to the PMUT unit 2000 , and the other side of the circuit protection layer 110 is bonded to the CMOS substrate 100 .
  • the PMUT unit can also be bonded to the CMOS substrate 100, which is also within the protection scope of the present invention.
  • CMOS is used as an example of a transistor
  • a CMOS unit is used as an example of a transistor unit.
  • the transistor can also be BiMOS (BI-polar Metal-Oxide). Semiconductor, bipolar metal oxide semiconductor) unit or BCD (Bipolar-CMOS-DMOS), etc., so the transistor unit can also be a BiMOS unit or BCD unit, etc.
  • the cavity 201 is disposed within the supporting layer 200, which not only includes the case where the lower side of the cavity 201 is defined by the supporting layer 200, but also includes the situation where the cavity 201 directly reaches the supporting layer.
  • the case where the lower side of 200 and thus the lower side of cavity 201 is defined by the bonding material layer 300 or the circuit protection layer 110 is within the scope of the present invention.
  • a support layer is usually included.
  • the support layer may be located on the side of the piezoelectric layer facing the transistor unit, for example, as shown in FIG. The upper side of an electrode layer 250 .
  • the support layer 220 may not be provided, as shown in FIG. 10 and FIG. 11 .
  • the difference between Figure 10 and Figure 11 is that in Figure 11, the bonding material layer 300 is not provided, while in the structure shown in Figure 10, the bonding material layer 300 is provided between the support layer 200 and the circuit bonding layer 110 .
  • the PMUT structure is provided with first conductive holes 500A, second conductive holes 500B, and third conductive holes 240A (see, for example, FIGS. 1 and 9 ).
  • the first conductive holes 500A Penetrating the piezoelectric layer 240, the supporting layer 200 and the bonding material layer 300 to reach the first electrical connection layer 113A in the circuit protection layer 110, the second conductive hole 500B penetrates the piezoelectric layer 240, the supporting layer 200 and the bonding material layer.
  • the third conductive hole 240A penetrates the piezoelectric layer 240 and reaches the second electrode layer 230.
  • the first conductive layer 260A electrically connects the first electrode layer 250 and the first electrical connection layer 113A via the first conductive hole 500A
  • the second conductive layer 260B connects the second conductive layer 260A with the second conductive hole 500B and the third conductive hole 240A.
  • the electrode layer 230 is electrically connected to the second electrical connection layer 113B.
  • first conductive layer 260A and the second conductive layer 260B may be electrically connected to the first electrical connection layer 113A and the second electrical connection layer 113B exposed on the side of the PMUT structure, respectively, which is also the purpose of the present invention. within the scope of protection.
  • the first electrical connection layer 113A is electrically connected to one of the electrodes of the transistor (for example, the source electrode), and the second electrical connection layer 113B is to another one of the electrodes of the transistor (for example, the gate electrode). Electrical connection.
  • the first electrical connection layer 113A and/or the second electrical connection layer 113B can also be electrically connected thereto, which is also within the scope of the present invention. within the range.
  • the transistor unit 1000 includes a transistor, a first electrical connection layer 113A and a second electrical connection layer 113B that are electrically insulated from each other, and a circuit protection layer 110 .
  • the circuit protection layer 110 covers transistor, first electrical connection layer 113A and second electrical connection layer 113B.
  • the first electrical connection layer 113A and the second electrical connection layer 113B may not be provided in the circuit protection layer 110 of the transistor unit, or the electrode power supply of the PMUT unit may not use the first electrical connection layer 113A. If other methods are used with the second electrical connection layer 113B, these are also within the protection scope of the present invention.
  • the present invention proposes a PMUT structure, including:
  • a transistor unit one side of which includes a transistor
  • the PMUT unit includes a PMUT and a supporting layer.
  • the PMUT includes a first electrode layer, a second electrode layer and a piezoelectric layer.
  • the first electrode layer and the second electrode layer are respectively provided on one side and the other side of the piezoelectric layer.
  • the PMUT structure further includes a cavity for the PMUT;
  • One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat portion bonded to the other side of the piezoelectric layer.
  • the side where the supporting layer 200 and the piezoelectric layer 240 are joined is a flat surface, which is helpful to overcome the problem in the prior art that the surface of the CMOS wafer for growing the piezoelectric film does not have a single type of material and the surface is uneven.
  • the piezoelectric film of the PMUT has a single crystal structure, that is, the piezoelectric film of the PMUT has a single crystal structure.
  • the electrical layer 240 is a single crystal piezoelectric film layer. This enables the corresponding single crystal piezoelectric film in the above structure to have higher piezoelectric constants, electromechanical coupling coefficients, and better thermal conductivity than polycrystalline piezoelectric films, thereby increasing the vibrator density and filling factor. High filling factor and array element density can improve the emission acoustic intensity and receiving sensitivity and resolution, obtain high-contrast ultrasound imaging images, and reduce energy loss.
  • single crystal piezoelectric films can achieve uniform stress throughout the entire wafer during the production process, reducing the impact of uneven stress on PMUT frequency. This is conducive to obtaining more stable and uniform PMUT devices and improving large-scale manufacturing. yield rate.
  • the good thermal conductivity brought by single crystal piezoelectric materials can increase the array element density, thereby improving the imaging resolution; the uniform stress brought by single crystal piezoelectric materials can improve frequency consistency, This further optimizes the imaging consistency; the high coupling coefficient brought by the single crystal piezoelectric material can improve the transmitting and receiving sensitivity of the array element, thereby improving the imaging contrast.
  • the piezoelectric layer 240 may also be a flat polycrystalline piezoelectric film layer, which is also within the scope of the present invention.
  • a transistor unit 1000 is provided.
  • the transistor unit 1000 includes a transistor (in FIG. 2 , 101 is the source and drain stages of the transistor, and 111 is the gate electrode of the transistor), a first electrical connection layer 113A that is electrically insulated from each other, and The second electrical connection layer 113B and the circuit protection layer 110 cover the transistor, the first electrical connection layer 113A and the second electrical connection layer 113B.
  • 113 and 115 are electrical connection layers within other CMOS layers
  • 112 and 114 are electrical connection layers between CMOS layers.
  • the transistor unit 1000 may include a transistor and a circuit protection layer 110, and may optionally include a first electrical connection layer 113A, a second electrical connection layer 113A, and a first electrical connection layer 113A.
  • Layer 113B is provided.
  • a single crystal piezoelectric film layer 240 is prepared on an auxiliary wafer or auxiliary substrate 400 .
  • a layer of other thin film materials can be disposed between the single crystal piezoelectric film layer or the single crystal piezoelectric layer 240 and the auxiliary substrate 400.
  • SOI Silicon On Insulator
  • 240 may also be a polycrystalline piezoelectric layer.
  • a second electrode layer 230 , a support layer 220 and a sacrificial material layer 210 are prepared on the single crystal piezoelectric film layer 240 .
  • the second electrode layer 230, the support layer 220 and the sacrificial material layer 210 are sequentially arranged on the single crystal piezoelectric film layer 240.
  • a support protection material is deposited on the structure shown in FIG. 4 and planarized to form a support layer 200 .
  • the structure shown in FIG. 5 and the structure shown in FIG. 2 are joined to each other, for example, an additional layer of bonding material (which forms the joining material layer 300 ) is used to connect the supporting layer 200 and the circuit protection layer 110 Engagement.
  • an additional layer of bonding material (which forms the joining material layer 300 ) is used to connect the supporting layer 200 and the circuit protection layer 110 Engagement.
  • the support layer 200 and the circuit protection layer 110 may also be directly bonded. Bonding solutions can take many forms, including silicon-silicon bonding, silicon- SiO2 bonding, metal bonding, etc.
  • the auxiliary substrate 400 is removed to expose the upper side of the single crystal piezoelectric film layer 240 .
  • a first electrode layer 250 is provided on the upper side of the single crystal piezoelectric film layer 240 .
  • the first conductive hole 500A, the second conductive hole 500B, and the third conductive hole 240A may be formed based on an etching process, and the sacrificial material layer in FIG. 8 is released to form the cavity 201 .
  • the first conductive hole 500A penetrates the piezoelectric layer 240, the support layer 200 and the bonding material layer 300 to reach the first electrical connection layer 113A in the circuit protection layer 110
  • the second conductive hole 500B penetrates the piezoelectric layer 240, the support layer 240 and the bonding material layer 300 to reach the first electrical connection layer 113A in the circuit protection layer 110.
  • the layer 200 and the bonding material layer 300 reach the second electrical connection layer 113B in the circuit protection layer 110
  • the third conductive hole 240A penetrates the piezoelectric layer 240 to reach the second electrode layer 230.
  • a conductive material is deposited to form a first conductive layer 260A and a second conductive layer 260B.
  • the first conductive layer 260A electrically connects the first electrode layer 250 and the first electrical connection layer 113A via the first conductive hole 500A
  • the second conductive layer 260B connects the second conductive layer 260A with the second conductive hole 500B and the third conductive hole 240A.
  • the electrode layer 230 is electrically connected to the second electrical connection layer 113B.
  • the device protection layer 270 may also be provided after the first conductive layer 260A and the second conductive layer 260B are deposited.
  • the manufacturing process of the PMUT structure is exemplified in the form of a single PMUT unit and a single transistor unit, as can be understood, the above process can also be performed at the wafer level. accomplish.
  • providing a transistor unit includes providing a transistor wafer, and the transistor wafer is formed with a plurality of transistor units based on the MEMS process; in the step of providing an initial structure of the piezoelectric layer, the auxiliary substrate is a PMUT auxiliary wafer, and the The single crystal piezoelectric layer is a single crystal piezoelectric film layer; based on the MEMS process, a second electrode layer, a sacrificial material layer and a first electrode layer corresponding to multiple PMUT units are formed; in the first conductive layer and the first conductive layer that provide electrical insulation from each other After the step of the second conductive layer, the method further includes the step of performing cutting to form a PMUT structure including a single PMUT unit and a single CMOS unit.
  • the present invention proposes a manufacturing method of a PMUT structure.
  • the PMUT structure includes a cavity for PMUT.
  • the method includes the steps:
  • the PMUT unit connected to the transistor unit is provided.
  • the PMUT unit includes a PMUT and a supporting layer.
  • the PMUT It includes a first electrode layer, a second electrode layer and a piezoelectric layer, and the first electrode layer and the second electrode layer are respectively provided on one side and the other side of the piezoelectric layer,
  • One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat portion bonded to the other side of the piezoelectric layer.
  • the present invention proposes an integration solution and a manufacturing method of a PMUT with a single crystal piezoelectric film and a traditional transistor wafer.
  • the present invention proposes a plan to transfer a "piezoelectric single-crystal film equivalent to the size of a transistor wafer" to a transistor wafer, and a manufacturing method for a transistor-integrated PMUT based on this , to overcome various limitations and difficulties in growing single crystal piezoelectric films on transistor wafers.
  • FIG 12 is a schematic diagram of a PMUT structure array according to an exemplary embodiment of the present invention.
  • the above-mentioned PMUT structure 3000 may be only one array element in the array 4000.
  • the hollow circle represents the PMUT vibration area of the PMUT structure 3000. In addition to the circle, it can be any desired shape such as an ellipse, a polygon, and a combination thereof.
  • the solid black circle represents the electrical connection between the PMUT unit and the CMOS unit, as shown in Figure 1 at the first electrical connection layer 113A and the second electrical connection layer 113B, which can also be in any desired shape.
  • the PMUT structures 3000 are combined to form a PMUT structure array 4000.
  • Each PMUT unit 2000 can be individually controlled through a matching CMOS circuit to form a two-dimensional PMUT structure array 4000.
  • Multiple PMUT structures 3000 can also be connected together.
  • the electrodes of the PMUT structures 3000 on the same column are interconnected to form a one-dimensional line array.
  • the electrical connection points between the circuit of the CMOS unit and the PMUT unit are reduced, and a pair of CMOS units are connected with each other.
  • the electrical connection points of the PMUT units control multiple PMUT units simultaneously.
  • An ultrasonic transducer can be formed based on a PMUT structure or a PMUT structure array.
  • the ultrasonic transducer can be used in an ultrasonic imager.
  • the PMUT structure or PMUT structure array can also be used in other electronic devices, such as ultrasonic rangefinders, Ultrasonic fingerprint sensors, non-destructive flaw detectors used in industrial fields, etc.
  • a PMUT structure including:
  • a transistor unit one side of which includes a transistor
  • the PMUT unit includes a PMUT and a supporting layer.
  • the PMUT includes a first electrode layer, a second electrode layer and a piezoelectric layer.
  • the first electrode layer and the second electrode layer are respectively provided on one side and the other side of the piezoelectric layer.
  • the PMUT structure further includes a cavity for the PMUT;
  • One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat portion bonded to the other side of the piezoelectric layer.
  • the piezoelectric layer is a single crystal thin film layer.
  • the transistor unit includes the transistor, a first electrical connection layer and a second electrical connection layer that are electrically insulated from each other;
  • the PMUT structure further includes a first conductive layer and a second conductive layer that are electrically insulated from each other;
  • the first electrode layer is electrically connected to the first electrical connection layer at least through the first conductive layer
  • the second electrode layer is electrically connected to the second electrical connection layer through at least the second conductive layer.
  • the first conductive layer electrically connects the first electrode layer and the first electrical connection layer through the first conductive hole
  • the second conductive layer electrically connects the second electrode layer and the second conductive layer through the second conductive hole and the third conductive hole. layer electrical connection.
  • the first electrical connection layer is electrically connected to one of the electrodes of the transistor, and the second electrical connection layer is electrically connected to the other one of the electrodes of the transistor.
  • One side of the support layer is directly bonded to one side of the transistor unit.
  • One side of the support layer is bonded to one side of the transistor cell via a further layer of bonding material.
  • the cavity is provided within the supporting layer.
  • a support layer disposed in the support layer and in contact with the second electrode layer, the support layer defines the distance from the cavity One side of the transistor unit.
  • the second electrode layer defines a side of the cavity remote from the transistor cell.
  • the transistor unit includes one of a CMOS unit, a BiMOS unit, and a BCD unit.
  • a method of manufacturing a PMUT structure comprising a cavity for a PMUT, the method comprising the steps:
  • the PMUT unit connected to the transistor unit is provided.
  • the PMUT unit includes a PMUT and a supporting layer.
  • the PMUT includes a first electrode layer, a second electrode layer and a piezoelectric layer.
  • a first electrode layer is provided on one side and the other side of the piezoelectric layer. and the second electrode layer,
  • One side of the supporting layer is bonded to one side of the transistor unit, and the other side of the supporting layer includes a flat portion bonded to the other side of the piezoelectric layer.
  • the piezoelectric layer is a single crystal thin film layer.
  • the transistor unit includes the transistor, a first electrical connection layer and a second electrical connection layer that are electrically insulated from each other;
  • the method further includes the step of: providing a first conductive layer and a second conductive layer that are electrically insulated from each other, the first electrode layer is electrically connected to the first electrical connection layer at least via the first conductive layer, and the second electrode layer is at least via the second conductive layer.
  • the layer is electrically connected to the second electrical connection layer.
  • the method further includes the step of forming a first conductive hole, a second conductive hole and a third conductive hole, the first conductive hole penetrating the piezoelectric
  • the first conductive hole penetrating the piezoelectric
  • the second conductive hole penetrates the piezoelectric layer, the support layer and the second electrical connection layer reaching the transistor unit, and the third conductive hole penetrates the support layer to reach the second electrode layer;
  • the first conductive layer electrically connects the first electrode layer and the first electrical connection layer through the first conductive hole, and the second conductive layer passes through the second conductive hole.
  • Conductive The second electrode layer and the second electrical connection layer are electrically connected using holes and third conductive holes.
  • the initial structure of the piezoelectric layer including an auxiliary substrate and a piezoelectric layer;
  • a second electrode layer and a sacrificial material layer are provided, a second electrode layer is provided on one side of the piezoelectric layer, and a sacrificial material layer is provided on one side of the second electrode layer;
  • the layer of sacrificial material is released to form the cavity.
  • Providing a transistor unit includes providing a transistor wafer based on a MEMS process, and the transistor wafer is formed with a plurality of transistor units;
  • the auxiliary substrate is a PMUT auxiliary wafer, and the piezoelectric layer is a piezoelectric film layer;
  • the method further includes the step of performing cutting to form a PMUT structure including a single PMUT unit and a single transistor unit.
  • the piezoelectric layer is a single crystal piezoelectric film layer.
  • the initial structure of the piezoelectric layer is an SOI structure.
  • the second electrode layer is arranged on one side of the piezoelectric layer
  • the supporting layer is arranged on one side of the second electrode layer
  • the sacrificial material layer is arranged on one side of the supporting layer.
  • a device protection layer is deposited, and the device protection layer covers the PMUT, the first conductive layer and the second conductive layer.
  • the first electrical connection layer is electrically connected to one of the electrodes of the transistor, and the second electrical connection layer is electrically connected to the other one of the electrodes of the transistor.
  • the transistor unit includes one of a CMOS unit, a BiMOS unit, and a BCD unit.
  • a PMUT structure array including a plurality of PMUT structures according to any one of 1-11, or a plurality of PMUT structures manufactured according to the manufacturing method according to any one of 12-23.
  • An electronic device comprising the PMUT structure according to any one of 1-11, or the PMUT structure manufactured according to the manufacturing method according to any one of 12-23, or the PMUT structure according to 24 array.
  • the electronic device includes at least one of the following: an ultrasonic imager, an ultrasonic range finder, an ultrasonic fingerprint sensor, a non-destructive flaw detector, a flow meter, a force feedback device, and a smoke alarm.

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Abstract

一种PMUT结构，包括：晶体管单元（1000）和PMUT单元（2000）；晶体管单元（1000）的一侧包括晶体管；PMUT单元（2000）包括PMUT和支护层（200），PMUT包括第一电极层（250）、第二电极层（230）与压电层（240），压电层（240）的一侧与另一侧分别设置第一电极层（250）和第二电极层（230）；还包括用于PMUT的空腔（201）；且支护层（200）的一侧与晶体管单元（1000）的一侧接合，支护层（200）的另一侧包括与压电层（240）的另一侧接合的平坦面部分。PMUT结构有利于形成高质量压电薄膜。还提供了一种PMUT结构的制造方法，一种PMUT结构阵列，以及一种电子设备。

Description

具有支护层的PMUT结构及其制造方法 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种具有支护层的PMUT结构及其制造方法、一种PMUT结构阵列、一种具有该PMUT结构或者PMUT结构阵列的电子设备。
背景技术
压电微机械超声换能器Piezoelectric Micromachined Ultrasonic Transducer，PMUT是利用压电材料的正逆压电效应使压电薄膜振动，从而发射或者接收超声波信号的MEMS器件。当PMUT既可以做执行器(发射声波)，又可以做传感器(接收声波)。基于MEMS标准工艺的PMUT批量化生产和晶圆级封装使其成本极大的降低，非常适合大规模商业应用。PMUT在超声测距、超声成像、超声无损检测、超声指纹识别、超声驱动器等方面都有较好的应用前景。
超声测距是PMUT的重要应用之一，主要利用飞行时间(Time of Flight,TOF)，即检测超声波从发射到接收所间隔的时间，来判断距离。基于此原理，PMUT超声测距在汽车倒车雷达、水下声纳探测、扫地机器人、超声烟雾报警器等场景都会用到。另外，PMUT超声指纹传感器，主要基于飞行时间(Time of Flight,TOF)，能够检测到手指真皮层的指纹，可以识别树脂做的假指纹，也可以使那些因为机械磨损造成表皮指纹损伤的人可以顺利读取指纹，是PMUT另一个重要应用，在信息安全等领域具有十分重要的作用。此外，无损探伤是PMUT在工业领域的一个典型应用，超声通过检测飞行时间和返回信号的强度，探测物体损伤，在电网、轨道和化工等领域有着非常广泛且迫切的需求。PMUT阵列全聚焦成像还具有实现3D成像的潜力，有望突破现有检测技术不能检测细微损伤的限制；同时其小尺寸在便携和低功耗的需求领域也都完全可以满足工业领域对无损探伤的要求。PMUT超声医学成像则通过检测飞行时间和返回信号的强度，针对现有超声探头尺寸较大、检测精度低、传播损耗大、检测时间长等限制，PMUT高密度阵列全聚焦相控阵成像，将使诊断速率和诊断精度大大提高， 在医疗诊断领域会展现强大的应用能力。另外，PMUT还可以作为能量源，可应用于超声激励、能量传输等领域。
现有PMUT与CMOS(Complementary Metal-Oxide-Semiconductor，互补金属氧化物半导体)的集成主要是通过如下两种方案实现的：
方案1.以CMOS晶圆为基片，对其进行各种薄膜沉积和刻蚀流程加工，然而PMUT制造流程包含多种薄膜(比如压电薄膜、电极薄膜等)在不同温度下的沉积以及相应薄膜在不同气氛、液体环境的刻蚀，这就需要该加工工艺流程不对CMOS电路造成破坏。目前已知压电材料中，仅有AlN基压电材料等少数几种压电薄膜的MEMS制造流程与CMOS兼容，故而这种方案主要用于相应压电材料基集成化超声换能器的开发。然而压电薄膜的压电特性是PMUT性能的至关重要的决定部分，比如多晶锆钛酸铅(PZT)、LiNbO3等具有非常优异压电特性的压电材料，其加工工艺较AlN苛刻，与CMOS兼容性较差，故而基于上述工艺流程的CMOS集成化PMUT的开发受限较多，很难实现。
方案2.分别加工PMUT晶圆和CMOS晶圆，设定PMUT晶圆的设置压电薄膜的一侧以及CMOS晶圆的设置晶体管的一侧为相应晶圆的正面，将PMUT晶圆的正面和CMOS正面键合，构建CMOS集成化PMUT。与上述方案1相比，该方案对压电材料的局限性较小，然而，PMUT机械振动单元的有效振动是高效地发射和接受超声波的关键，这需要振动单元下方含有空腔结构，提供空间供振动单元有效振动，这需要CMOS上含有相应空腔。然而空腔尺寸是决定PMUT超声频率的核心要素，空腔尺寸的变化将导致PMUT超声频率的变化。在PMUT和CMOS两片晶圆键合时，不可避免的存在对准偏差，导致振动单元区域与本身设计之间存在随机偏差，造成所开发的CMOS集成化PMUT的频率波动。值得指出的是，应用于超声成像领域的PMUT振元的直径都非常小，通常在几十微米甚至更小，即使1微米的对准偏差也将造成很大的不利影响。
因此现有技术中存在开发出如下的CMOS与PMUT集成方案的需求：对压电材料本身普适性强，和/或CMOS单元与PMUT单元的集成过程不对空腔尺寸产生影响。
现有PMUT与CMOS的集成主要是以CMOS晶圆为基片，对其进行多种薄膜沉积(包括但不局限于支撑层、电极层、压电层等)和刻蚀加工流程，实现在CMOS晶圆上集成PMUT。
通常CMOS上集成的PMUT单元呈弯曲振动模式，即振动单元在垂直于薄膜厚度方向上弯曲振动，向外发射超声波。为实现有效的PMUT单元弯曲振动，首先面向PMUT振动单元的CMOS一侧(即CMOS的正面)需含有空腔，同时PMUT压电薄膜两侧的薄膜整体厚度不一致，其中一侧较另一侧厚，使整个振动单元的质量中心不在压电薄膜的中心，避免振膜呈现厚度伸缩模式的振动。
决定PMUT性能关键因素之一是压电材料本身。基于上述方案构建PMUT与CMOS集成芯片时，压电薄膜的生长是在表面非常复杂的CMOS基晶圆上进行的，比如生长压电薄膜的CMOS晶圆表面的材料种类不单一、表面不平整存在台阶等，因此很难实现高质量的压电薄膜，尤其是单晶压电薄膜的沉积。
因此需要开发一种有利于形成高质量压电薄膜的PMUT单元与传统CMOS单元的集成方案。
发明内容
为缓解或解决现有技术中的上述问题的至少一个方面，提出本发明。
本发明的实施例涉及一种PMUT结构，包括：
晶体管单元，晶体管单元的一侧包括晶体管；和
PMUT单元，包括PMUT和支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
其中：
所述PMUT结构还包括用于PMUT的空腔；且
支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
本发明的实施例还涉及一种PMUT结构的制造方法，所述PMUT结构包括用于PMUT的空腔，所述方法包括步骤：
提供晶体管单元，晶体管单元的一侧包括晶体管；和
设置与晶体管单元接合的PMUT单元，PMUT单元包括PMUT以及支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
其中：
支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的 另一侧接合的平坦面部分。
本发明的实施例也涉及一种PMUT结构阵列，包括多个上述的PMUT结构，或者多个上述制造方法制造的PMUT结构。
本发明的实施例还涉及一种电子设备，包括上述的PMUT结构，或者上述制造方法制造的PMUT结构，或者上述的PMUT结构阵列。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1为根据本发明的一个示例性实施例的PMUT结构的结构示意图；
图2-9为根据本发明的一个示例性实施例的示例性示出PMUT结构的制造方法的截面示意图；
图10为根据本发明的另一个示例性实施例的PMUT结构的结构示意图；
图11为根据本发明的还一个示例性实施例的PMUT结构的结构示意图；
图12为根据本发明的一个示例性实施例的PMUT结构阵列的示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。发明的一部分实施例，而并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
首先，本发明的附图中的附图标记说明如下：
1000：CMOS单元或晶体管单元(参见图1和图2)。
100：CMOS基底或晶体管基底，可选材料为单晶硅、氮化镓、砷化镓、蓝宝石、石英、碳化硅、金刚石等。
101：晶体管的源极和漏极。
110：电路保护层，其为绝缘材料层，可以是二氧化硅、氮化硅等。
111：晶体管的栅极。
113A：晶体管单元层内电连接层，对应于第一电连接层，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等，上述材料也适用于其他电连接层。
113B：晶体管单元层内电连接层，对应于第二电连接层。
113、115：其他晶体管单元层内电连接层。
112和114：晶体管单元层间电连接层。
2000：PMUT单元。
200：支撑保护层(支护层)，其材料可以为氮化铝、氮化硅、碳化硅、多晶硅、单晶硅、二氧化硅、无定形硅、掺杂二氧化硅中的一种。
201：空腔。
210：牺牲材料层，其材料可以是二氧化硅、掺杂二氧化硅等。
220：支撑层，其材料包括硅、二氧化硅、氮化硅、氮化铝、钼、铂等中的一种。在可选的实施例中，支撑层210的厚度在0.1μm-10μm的范围内。如能够理解的，当支撑层210的材料为金属时，支撑层210和后续提及的导电层260A/260B之间需要设置电学隔离层(可选用绝缘薄膜材料)。
230、250：电极层，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。两个电极层的材料可以相同也可以不同。
240：压电层或压电膜层，材料可选多晶氮化铝(AlN)、多晶氧化锌、多晶锆钛酸铅(PZT)、多晶铌酸锂(LiNbO3)、多晶钽酸锂(LiTaO3)、多晶铌酸钾(KNbO3)等材料，或者单晶氮化铝、单晶氮化镓、单晶铌酸锂、单晶锆钛酸铅、单晶铌酸钾、单晶石英薄膜、或者单晶钽酸锂等材料，上述的单晶或多晶材料还可以包括一定原子比的稀土元素掺杂材料，均属于本发明可以使用的压电层。。
240A,500A，500B：导电用孔。
260A，260B：导电层，其材料可以选自用于形成电极层的材料。
270：器件保护层，一般为介质材料，如二氧化硅、氮化铝、氮化硅等。
300：接合材料层(例如参见图1)，其用于将支护层200与电路保护层110接合，例如可以是金属键合层。
400：辅助基底，可选材料为单晶硅、氮化镓、砷化镓、蓝宝石、石英、碳化硅、金刚石等。
3000：PMUT结构(参见图1和图12)。
4000：PMUT结构阵列(参见图12)。
图1为根据本发明的一个示例性实施例的PMUT结构的结构示意图，如图1所示，该PMUT结构3000包括：
晶体管单元1000(参见图1和图2)，晶体管单元1000包括晶体管(其包括源极和漏极101，栅极111)、彼此电绝缘的第一电连接层113A和第二电连接层113B、电路保护层110，电路保护层110覆盖晶体管、第一电连接层113A和第二电连接层113B；
PMUT单元2000(参见图1)，包括支护层200和PMUT，PMUT包括第一电极层250、第二电极层230与压电层240；和
彼此电绝缘的第一导电层260A与第二导电层260B，参见图1，
其中：
所述PMUT结构还包括用于PMUT的空腔201，空腔201的上侧设置有支撑层220，支撑层220之上是第二电极层230，如图1所示，可以看到，在图1中，空腔201设置在支护层200内；
如图1所示，压电层240为单晶薄膜层，支护层200的一侧(如图1所示，为下侧)与电路保护层110的一侧(如图1，为上侧)之间设置有接合材料层300，支护层200的另一侧(图1中为支护层200的上侧)的平坦面部分与压电层240的另一侧(图1中为压电层240的下侧)接合。
需要指出的是，在本发明中，“接合”不仅包括如图1所示的两者直接接合的情况，例如直接键合，键合方案可以采用多种方式，包括硅-硅键合、硅-SiO2键合等，还可以包括在两者之间设置有其他接合用层或膜层的情况，这些均在本发明的保护范围之内。
在图1所示的实施例中，支护层200与电路保护层110之间的接合通过了材料接合层300，但是本发明不限于此。如图11所示，支护层200与电路保护层110直接接合。这些都包括在“支护层200的一侧与电路保护层110的一侧接合”的范围内，即上述接合不仅包括如图11所示支护层200与电路保护层110直接接合，还包括如图1所示在两者之间设置有其他层或膜层(例如接合材料层300)的情况。
此外，如图1、图10和图11所示，支护层200的另一侧(图中为支护层200的上侧)与压电层240接合，与“支护层200的一侧与电路保护层110的一 侧接合”相似，面接触可以是直接面接触，也可以是间接面接触，均在本发明的保护范围之内。
需要专门指出的是，在本发明的具体的实施例中，以支护层200与电路保护层110接合为例作了示例性说明，但是，PMUT单元2000与CMOS单元1000的接合可以是限定CMOS单元的表面的电路保护层，也可以是限定CMOS单元的表面的其他层，均在本发明的保护范围之内。
如图1所示的实施例中，CMOS单元1000还包括CMOS基底100，电路保护层110的一侧与PMUT单元2000接合，电路保护层110的另一侧与CMOS基底100接合。可选的，在有些情况下，PMUT单元也可以与CMOS基底100接合，这也在本发明的保护范围之内。
还需要专门指出的是，在本发明中，以CMOS作为晶体管的一个示例，从而以CMOS单元作为晶体管单元的一个示例，但是本发明不限于此，晶体管还可以是BiMOS(BI-polar Metal-Oxide Semiconductor，双极金属氧化物半导体)单元或BCD(Bipolar-CMOS-DMOS)等，从而晶体管单元还可以是BiMOS单元或BCD单元等。
如图1、图10和图11所示，空腔201设置在支护层200内，不仅包括空腔201的下侧由支护层200限定的情况，还可以包括空腔201直抵支护层200的下侧从而空腔201的下侧由接合材料层300限定或者电路保护层110限定的情况，这些均在本发明的保护范围之内。
对于PMUT单元，通常含有支撑层。支撑层可以位于压电层的面向晶体管单元的一侧，例如如图1所示设置在第二电极层230的下侧；也可以位于压电层的远离晶体管单元的一侧，即可以在第一电极层250的上侧。还需要指出的是，通过电极层本身的结构设计，支撑层220也可以不设置，如图10所示和图11所示。图10与图11之间的区别在于在图11中，没有设置接合材料层300，而在图10所示的结构中，在支护层200与电路接合层110之间设置了接合材料层300。
在图1所示的实施例中，PMUT结构设置有第一导电用孔500A、第二导电用孔500B和第三导电用孔240A(例如参见图1和图9)，第一导电用孔500A贯穿压电层240、支护层200和接合材料层300以抵达电路保护层110内的第一电连接层113A，第二导电用孔500B贯穿压电层240、支护层200和接合材料层300 以抵达电路保护层110内的第二电连接层113B，第三导电用孔240A贯穿压电层240而抵达第二电极层230。第一导电层260A经由第一导电用孔500A将第一电极层250与第一电连接层113A电连接，第二导电层260B经由第二导电用孔500B以及第三导电用孔240A将第二电极层230与第二电连接层113B电连接。
虽然没有示出，第一导电层260A和第二导电层260B可以在PMUT结构的侧面分别与在侧面露出的第一电连接层113A和第二电连接层113B电连接，这也在本发明的保护范围之内。
在可选的实施例中，第一电连接层113A与晶体管的电极中的一个(例如源极)电连接，第二电连接层113B与晶体管的电极中的另外的一个电极(例如栅极)电连接。不过，在晶体管单元中存在其他的电连接结构的情况下，基于需要和要求，第一电连接层113A和/或第二电连接层113B也可以与之电连接，这也在本发明的保护范围之内。
在图1、图10和图11所示的实施例中，晶体管单元1000包括晶体管、彼此电绝缘的第一电连接层113A和第二电连接层113B、电路保护层110，电路保护层110覆盖晶体管、第一电连接层113A和第二电连接层113B。在可选的实施例中，第一电连接层113A和第二电连接层113B也可不设置在晶体管单元的电路保护层110中，或者，PMUT单元的电极供电可以不使用第一电连接层113A和第二电连接层113B而采用其他的方式，这些也在本发明的保护范围之内。
基于以上，本发明提出了一种PMUT结构，包括：
晶体管单元，晶体管单元的一侧包括晶体管；和
PMUT单元，包括PMUT和支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
其中：
所述PMUT结构还包括用于PMUT的空腔；且
支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
在本发明中，支护层200与压电层240接合的一侧为平坦面，这有利于克服现有技术中“生长压电薄膜的CMOS晶圆表面的材料种类不单一、表面不平整存在台阶等”导致的压电膜层质量不高的技术问题。
在图1、图10和图11所示的结构中，PMUT的压电薄膜呈单晶结构，即压 电层240为单晶压电膜层。这使得上述结构中相应的单晶压电薄膜与多晶压电薄膜相比，拥有更高的压电常数和机电耦合系数，更优异的导热性能，进而提高振元密度和填充因子。高填充因子和阵元密度能够使发射声学强度和接收灵敏度及分辨率提高，获得高对比度的超声成像图像，降低能量损耗。此外，单晶压电薄膜可以在制作过程中在整片晶圆范围内实现薄膜的应力均匀，减少应力不均匀对PMUT频率的影响，这有利于获得更加稳定均匀的PMUT器件，提高大规模制造的良品率。
此外，对于成像应用：在成像性能方面，单晶压电材料带来的导热性好可以提高阵元密度，进而提高成像分辨率；单晶压电材料带来的应力均匀可以提高频率一致性，进而优化成像一致性；单晶压电材料带来的高耦合系数可以提高阵元的发射和接收灵敏度，进而提高成像对比度。
不过，在可选的实施例中，压电层240也可以为平坦的多晶压电膜层，这也在本发明的保护范围之内。
下面参照图2-图9示例性说明图1所示的PMUT结构的制造方法。
如图2所示，提供晶体管单元1000，晶体管单元1000包括晶体管(图2中，101为晶体管的源极和漏级，111为晶体管的栅极)、彼此电绝缘的第一电连接层113A和第二电连接层113B、电路保护层110，电路保护层110覆盖晶体管、第一电连接层113A和第二电连接层113B。在图2中，113、115为其他CMOS层内电连接层，而112和114为CMOS层间电连接层。需要指出的是，图2所示结构为示例性的，对于本发明而言，晶体管单元1000可以包括晶体管和电路保护层110，还可以可选的包括第一电连接层113A、第二电连接层113B。
如图3所示，在辅助晶圆或者辅助基底400上制备单晶压电膜层240。单晶压电膜层或单晶压电层240与辅助基底400之间可以设置有一层其他薄膜材料，例如在SOI(Silicon On Insulator)晶圆中，在单晶压电膜层与辅助基底之间设置有一层绝缘层。如之前提及的，240也可以是多晶压电层。
如图4所示，在图3所示结构中，在单晶压电膜层240上制备第二电极层230、支撑层220以及牺牲材料层210。第二电极层230、支撑层220以及牺牲材料层210在单晶压电膜层240上依次设置。
如图5所示，在图4所示结构上沉积支撑保护材料，以及对其平坦化，以形成支护层200。
如图6所示，将图5所示的结构与图2所示的结构彼此接合，例如采用额外的一层键合材料(其形成接合材料层300)将支护层200与电路保护层110接合。如之前提及的，也可以将支护层200与电路保护层110直接键合。键合方案可以采用多种方式，包括硅-硅键合、硅-SiO2键合、金属键合等。
如图7所示，移除辅助基底400以露出单晶压电膜层240的上侧。
如图8所示，在单晶压电膜层240的上侧设置第一电极层250。
如图9所示，可以基于刻蚀工艺，形成第一导电用孔500A、第二导电用孔500B、第三导电用孔240A，以及释放图8中的牺牲材料层以形成空腔201。第一导电用孔500A贯穿压电层240、支护层200和接合材料层300以抵达电路保护层110内的第一电连接层113A，第二导电用孔500B贯穿压电层240、支护层200和接合材料层300以抵达电路保护层110内的第二电连接层113B，第三导电用孔240A贯穿压电层240而抵达第二电极层230。
接着，如图1所示，沉积导电材料，以形成第一导电层260A和第二导电层260B。第一导电层260A经由第一导电用孔500A将第一电极层250与第一电连接层113A电连接，第二导电层260B经由第二导电用孔500B以及第三导电用孔240A将第二电极层230与第二电连接层113B电连接。
还可以在沉积了第一导电层260A和第二导电层260B之后，设置器件保护层270。
在上述图1-图9所示的实施例中，虽然以单个PMUT单元与单个晶体管单元的形式示例性说明了PMUT结构的制造过程，但是如能够理解的，上述过程也可以在晶圆级别上实现。具体的：提供晶体管单元包括提供晶体管晶圆，基于MEMS工艺，所述晶体管晶圆形成有多个晶体管单元；提供压电层初始结构的步骤中，所述辅助基底为PMUT辅助晶圆，所述单晶压电层为单晶压电膜层；基于MEMS工艺，形成对应于多个PMUT单元的第二电极层、牺牲材料层和第一电极层；在提供彼此电绝缘的第一导电层与第二导电层的步骤之后，所述方法还包括步骤：执行切割以形成包括单个PMUT单元与单个CMOS单元的PMUT结构。
基于图1-图9所示的制造工艺，本发明提出了一种PMUT结构的制造方法，所述PMUT结构包括用于PMUT的空腔，所述方法包括步骤：
提供晶体管单元，晶体管单元的一侧包括晶体管；和
设置与晶体管单元接合的PMUT单元，PMUT单元包括PMUT以及支护层，PMUT 包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
其中：
支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
综上，本发明提出了一种具有单晶压电薄膜的PMUT和传统晶体管晶圆的集成方案及其制造方法。在PMUT压电薄膜呈单晶结构的情况下，本发明提出了将“与晶体管晶圆尺寸相当的压电单晶薄膜”转移到晶体管晶圆的方案，及基于此的晶体管集成PMUT的制造方法，以克服在晶体管晶圆上生长单晶压电薄膜的种种限制和难度。
图12为根据本发明的一个示例性实施例的PMUT结构阵列的示意图。如图12所示，上述的PMUT结构3000可以仅仅是阵列4000中的一个阵元。图12中，空心圆代表PMUT结构3000的PMUT振动区域，除了圆形之外，其可以是椭圆、多边形及其组合等任意需要的形状。黑实心圆代表PMUT单元与CMOS单元实现电连接，如图1所示的第一电连接层113A和第二电连接层113B处，其也可以是任意需要的形状。PMUT结构3000组合构成PMUT结构阵列4000。
每个PMUT单元2000可以通过与之匹配的CMOS电路单独控制，形成二维PMUT结构阵列4000。
也可以将多个PMUT结构3000连接在一起，比如同一列上的PMUT结构3000的电极互联，形成一维线阵列，此时CMOS单元的电路与PMUT单元的电连接点减少，一对CMOS单元与PMUT单元的电连接点对多个PMUT单元同时控制。
可以基于PMUT结构或者PMUT结构阵列，形成超声换能器，该超声换能器可以用在超声成像仪上，PMUT结构或者PMUT结构阵列也可以用在其他的电子设备上，例如超声测距仪、超声指纹传感器、用于工业领域的无损探伤仪等。
基于以上，本发明提出了如下技术方案：
1、一种PMUT结构，包括：
晶体管单元，晶体管单元的一侧包括晶体管；和
PMUT单元，包括PMUT和支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
其中：
所述PMUT结构还包括用于PMUT的空腔；且
支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
2、根据1所述的PMUT结构，其中：
压电层为单晶薄膜层。
3、根据1所述的PMUT结构，其中：
晶体管单元包括所述晶体管、彼此电绝缘的第一电连接层和第二电连接层；
所述PMUT结构还包括彼此电绝缘的第一导电层与第二导电层；
第一电极层至少经由第一导电层与第一电连接层电连接，第二电极层至少经由第二导电层与第二电连接层电连接。
4、根据3所述的PMUT结构，还包括：
第一导电用孔、第二导电用孔和第三导电用孔，第一导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第一电连接层，第二导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第二电连接层，第三导电用孔贯穿压电层而抵达第二电极层，
其中：
第一导电层经由第一导电用孔将第一电极层与第一电连接层电连接，第二导电层经由第二导电用孔以及第三导电用孔将第二电极层与第二电连接层电连接。
5、根据3所述的PMUT结构，其中：
第一电连接层与晶体管的电极中的一个电连接，第二电连接层与晶体管的电极中的另外的一个电极电连接。
6、根据1所述的PMUT结构，其中：
支护层的一侧与晶体管单元的一侧直接接合。
7、根据1所述的PMUT结构，其中：
支护层的一侧与晶体管单元的一侧通过另外的接合材料层接合。
8、根据1所述的PMUT结构，其中：
所述空腔设置在所述支护层内。
9、根据8所述的PMUT结构，还包括：
支撑层，设置在支护层中且与第二电极层面接触，支撑层限定空腔的远离 晶体管单元的一侧。
10、根据8所述的PMUT结构，其中：
第二电极层限定空腔的远离晶体管单元的一侧。
11、根据1所述的PMUT结构，其中：
所述晶体管单元包括CMOS单元、BiMOS单元、BCD单元中的一种。
12、一种PMUT结构的制造方法，所述PMUT结构包括用于PMUT的空腔，所述方法包括步骤：
提供晶体管单元，晶体管单元的一侧包括晶体管；和
设置与晶体管单元接合的PMUT单元，PMUT单元包括PMUT以及支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
其中：
支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
13、根据12所述的方法，其中：
压电层为单晶薄膜层。
14、根据12所述的方法，其中：
所述晶体管单元包括所述晶体管、彼此电绝缘的第一电连接层和第二电连接层；
所述方法还包括步骤：提供彼此电绝缘的第一导电层与第二导电层，第一电极层至少经由第一导电层与第一电连接层电连接，第二电极层至少经由第二导电层与第二电连接层电连接。
15、根据14所述的方法，其中：
在提供彼此电绝缘的第一导电层与第二导电层的步骤之前，还包括步骤：形成第一导电用孔、第二导电用孔和第三导电用孔，第一导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第一电连接层，第二导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第二电连接层，第三导电用孔贯穿支护层而抵达第二电极层；
在提供彼此电绝缘的第一导电层与第二导电层的步骤中，第一导电层经由第一导电用孔将第一电极层与第一电连接层电连接，第二导电层经由第二导电 用孔以及第三导电用孔将第二电极层与第二电连接层电连接。
16、根据12所述的方法，其中，设置与晶体管单元接合的PMUT单元包括步骤：
提供压电层初始结构，所述压电层初始结构包括辅助基底以及压电层；
设置第二电极层与牺牲材料层，在压电层的一侧设置第二电极层以及在第二电极层的一侧设置牺牲材料层；
设置支护层，以支护材料覆盖所述压电层、第二电极层和牺牲材料层，以及使得支护材料平坦化以形成支护层；
将支护层的一侧与晶体管单元的一侧接合；
移除辅助基底以露出支护层的另一侧；
在支护层的另一侧设置第一电极层；以及
释放牺牲材料层以形成所述空腔。
17、根据16所述的方法，其中：
提供晶体管单元包括提供晶体管晶圆，基于MEMS工艺，所述晶体管晶圆形成有多个晶体管单元；
提供压电层初始结构的步骤中，所述辅助基底为PMUT辅助晶圆，所述压电层为压电膜层；
基于MEMS工艺，形成对应于多个PMUT单元的第二电极层、牺牲材料层和第一电极层；
在提供彼此电绝缘的第一导电层与第二导电层的步骤之后，所述方法还包括步骤：执行切割以形成包括单个PMUT单元与单个晶体管单元的PMUT结构。
18、根据17所述的方法，其中：
所述压电层为单晶压电膜层。
19、根据16所述的方法，其中：
所述压电层初始结构为SOI结构。
20、根据16所述的方法，其中：
在设置第二电极层与牺牲材料层的步骤中，在压电层的一侧设置第二电极层、在第二电极层的一侧设置支撑层以及在支撑层的一侧设置牺牲材料层。
21、根据14所述的方法，还包括步骤：
沉积器件保护层，所述器件保护层覆盖PMUT、第一导电层与第二导电层。
22、根据14所述的方法，其中：
第一电连接层与晶体管的电极中的一个电连接，第二电连接层与晶体管的电极中的另外的一个电极电连接。
23、根据12所述的方法，其中：
所述晶体管单元包括CMOS单元、BiMOS单元、BCD单元中的一种。
24、一种PMUT结构阵列，包括多个根据1-11中任一项所述的PMUT结构，或者多个根据12-23中任一项所述的制造方法制造的PMUT结构。
25、一种电子设备，包括包括根据1-11中任一项所述的PMUT结构，或者根据12-23中任一项所述的制造方法制造的PMUT结构，或者根据24所述的PMUT结构阵列。
26、根据25所述的电子设备，其中：
所述电子设备包括如下中的至少一种：超声成像仪、超声测距仪、超声指纹传感器、无损探伤仪、流量计、力觉反馈设备、烟雾报警器。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (26)

  1. 一种PMUT结构，包括：
    晶体管单元，晶体管单元的一侧包括晶体管；和
    PMUT单元，包括PMUT和支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
    其中：
    所述PMUT结构还包括用于PMUT的空腔；且
    支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
  2. 根据权利要求1所述的PMUT结构，其中：
    压电层为单晶薄膜层。
  3. 根据权利要求1所述的PMUT结构，其中：
    晶体管单元包括所述晶体管、彼此电绝缘的第一电连接层和第二电连接层；
    所述PMUT结构还包括彼此电绝缘的第一导电层与第二导电层；
    第一电极层至少经由第一导电层与第一电连接层电连接，第二电极层至少经由第二导电层与第二电连接层电连接。
  4. 根据权利要求3所述的PMUT结构，还包括：
    第一导电用孔、第二导电用孔和第三导电用孔，第一导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第一电连接层，第二导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第二电连接层，第三导电用孔贯穿压电层而抵达第二电极层，
    其中：
    第一导电层经由第一导电用孔将第一电极层与第一电连接层电连接，第二导电层经由第二导电用孔以及第三导电用孔将第二电极层与第二电连接层电连接。
  5. 根据权利要求3所述的PMUT结构，其中：
    第一电连接层与晶体管的电极中的一个电连接，第二电连接层与晶体管的电极中的另外的一个电极电连接。
  6. 根据权利要求1所述的PMUT结构，其中：
    支护层的一侧与晶体管单元的一侧直接接合。
  7. 根据权利要求1所述的PMUT结构，其中：
    支护层的一侧与晶体管单元的一侧通过另外的接合材料层接合。
  8. 根据权利要求1所述的PMUT结构，其中：
    所述空腔设置在所述支护层内。
  9. 根据权利要求8所述的PMUT结构，还包括：
    支撑层，设置在支护层中且与第二电极层面接触，支撑层限定空腔的远离晶体管单元的一侧。
  10. 根据权利要求8所述的PMUT结构，其中：
    第二电极层限定空腔的远离晶体管单元的一侧。
  11. 根据权利要求1所述的PMUT结构，其中：
    所述晶体管单元包括CMOS单元、BiMOS单元、BCD单元中的一种。
  12. 一种PMUT结构的制造方法，所述PMUT结构包括用于PMUT的空腔，所述方法包括步骤：
    提供晶体管单元，晶体管单元的一侧包括晶体管；和
    设置与晶体管单元接合的PMUT单元，PMUT单元包括PMUT以及支护层，PMUT包括第一电极层、第二电极层与压电层，压电层的一侧与另一侧分别设置第一电极层和第二电极层，
    其中：
    支护层的一侧与晶体管单元的一侧接合，支护层的另一侧包括与压电层的另一侧接合的平坦面部分。
  13. 根据权利要求12所述的方法，其中：
    压电层为单晶薄膜层。
  14. 根据权利要求12所述的方法，其中：
    所述晶体管单元包括所述晶体管、彼此电绝缘的第一电连接层和第二电连接层；
    所述方法还包括步骤：提供彼此电绝缘的第一导电层与第二导电层，第一电极层至少经由第一导电层与第一电连接层电连接，第二电极层至少经由第二导电层与第二电连接层电连接。
  15. 根据权利要求14所述的方法，其中：
    在提供彼此电绝缘的第一导电层与第二导电层的步骤之前，还包括步骤：形成第一导电用孔、第二导电用孔和第三导电用孔，第一导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第一电连接层，第二导电用孔贯穿压电层、支护层以及抵达晶体管单元内的第二电连接层，第三导电用孔贯穿支护层而抵达第二电极层；
    在提供彼此电绝缘的第一导电层与第二导电层的步骤中，第一导电层经由第一导电用孔将第一电极层与第一电连接层电连接，第二导电层经由第二导电用孔以及第三导电用孔将第二电极层与第二电连接层电连接。
  16. 根据权利要求12所述的方法，其中，设置与晶体管单元接合的PMUT单元包括步骤：
    提供压电层初始结构，所述压电层初始结构包括辅助基底以及压电层；
    设置第二电极层与牺牲材料层，在压电层的一侧设置第二电极层以及在第二电极层的一侧设置牺牲材料层；
    设置支护层，以支护材料覆盖所述压电层、第二电极层和牺牲材料层，以及使得支护材料平坦化以形成支护层；
    将支护层的一侧与晶体管单元的一侧接合；
    移除辅助基底以露出支护层的另一侧；
    在支护层的另一侧设置第一电极层；以及
    释放牺牲材料层以形成所述空腔。
  17. 根据权利要求16所述的方法，其中：
    提供晶体管单元包括提供晶体管晶圆，基于MEMS工艺，所述晶体管晶圆形成有多个晶体管单元；
    提供压电层初始结构的步骤中，所述辅助基底为PMUT辅助晶圆，所述压电层为压电膜层；
    基于MEMS工艺，形成对应于多个PMUT单元的第二电极层、牺牲材料层和第一电极层；
    在提供彼此电绝缘的第一导电层与第二导电层的步骤之后，所述方法还包括步骤：执行切割以形成包括单个PMUT单元与单个晶体管单元的PMUT结构。
  18. 根据权利要求17所述的方法，其中：
    所述压电层为单晶压电膜层。
  19. 根据权利要求16所述的方法，其中：
    所述压电层初始结构为SOI结构。
  20. 根据权利要求16所述的方法，其中：
    在设置第二电极层与牺牲材料层的步骤中，在压电层的一侧设置第二电极层、在第二电极层的一侧设置支撑层以及在支撑层的一侧设置牺牲材料层。
  21. 根据权利要求14所述的方法，还包括步骤：
    沉积器件保护层，所述器件保护层覆盖PMUT、第一导电层与第二导电层。
  22. 根据权利要求14所述的方法，其中：
    第一电连接层与晶体管的电极中的一个电连接，第二电连接层与晶体管的电极中的另外的一个电极电连接。
  23. 根据权利要求12所述的方法，其中：
    所述晶体管单元包括CMOS单元、BiMOS单元、BCD单元中的一种。
  24. 一种PMUT结构阵列，包括多个根据权利要求1-11中任一项所述的PMUT结构，或者多个根据权利要求12-23中任一项所述的制造方法制造的PMUT结构。
  25. 一种电子设备，包括包括根据权利要求1-11中任一项所述的PMUT结构，或者根据权利要求12-23中任一项所述的制造方法制造的PMUT结构，或者根据权利要求24所述的PMUT结构阵列。
  26. 根据权利要求25所述的电子设备，其中：
    所述电子设备包括如下中的至少一种：超声成像仪、超声测距仪、超声指纹传感器、无损探伤仪、流量计、力觉反馈设备、烟雾报警器。
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