WO2024027716A1

WO2024027716A1 - Display panel, manufacturing method for display panel and display apparatus

Info

Publication number: WO2024027716A1
Application number: PCT/CN2023/110581
Authority: WO
Inventors: 龚又又; 谭颖亮; 王彦林; 徐玉伟
Original assignee: 华为技术有限公司
Priority date: 2022-08-03
Filing date: 2023-08-01
Publication date: 2024-02-08
Also published as: CN117580389A

Abstract

The present application relates to the technical field of displaying. Disclosed are a display panel (20), a manufacturing method for the display panel (20) and a display apparatus. The display panel (20) comprises: an interlayer dielectric layer (240), a planarization layer (250), and a pixel defining layer (260) which are arranged in a stacked manner. An inscribed structure and one or a plurality of electrode lap joint structures are arranged in a first functional layer in a non-pixel region (202) of the display panel (20), each electrode lap joint structure comprising an auxiliary electrode (205) and an application electrode (206), the application electrode (206) being connected to a first cathode layer (281) of the display panel (20) by means of the inscribed structure, and the inscribed structure being used for partitioning the first functional layer. Since the auxiliary electrode (205) and the application electrode (206) are arranged in the first functional layer; and by means of the inscribed structure, the interlayer dielectric layer (240), the planarization layer (250), and the pixel defining layer (260) of the display panel (20) are partitioned off, the application electrode (206) is lap-jointed with the auxiliary electrode (205), and the auxiliary electrode (205) is lap-jointed with a cathode layer. Therefore, by applying an auxiliary voltage to the auxiliary electrode (205), assistance can be provided for regions with a larger voltage drop in the display panel (20), so as to reduce voltage division effects of resistors on the cathode layer, thus reducing voltage drops.

Description

Display panel, preparation method of display panel and display device

This application requests the priority of the Chinese patent application submitted to the State Intellectual Property Office on August 3, 2022, with the application number 202210926344.X and the application name "Display panel, display panel preparation method and display device", and its entire content incorporated herein by reference.

Technical field

The present application relates to the field of display technology, and in particular to a display panel, a preparation method of a display panel, and a display device.

Background technique

With the advancement of organic light-emitting semiconductor (organic light-emitting diode, OLED) technology, OLED display panels are also developing towards large sizes. However, when a large-size OLED display panel is working, there is a problem of voltage drop. That is, during the transmission process of the power supply voltage, due to the voltage division of the wire or electrode resistance, the voltage actually loaded on both ends of the component is reduced, causing the OLED display panel to display uneven brightness. . Therefore, additional auxiliary electrodes can usually be made on the OLED display panel to provide assistance to areas with large voltage drops in the OLED panel, so that the OLED display panel displays a uniform picture.

In the existing technology, the method of inverted trapezoidal isolation pillars is usually used to isolate the OLED functional layer, and then the cathode is connected to the auxiliary electrode through methods such as magnetron sputtering. However, this method requires the production of inverted trapezoidal isolation columns, which makes the entire process cost high and the process flow relatively complex.

Contents of the invention

The present application provides a display panel, a display panel preparation method and a display device, which are used to solve the problem of voltage drop caused by cathode resistor voltage division in display panels, especially large-size OLED display panels.

The technical solutions are as follows:

In a first aspect, a display panel is provided. The display panel is divided into a pixel area and a non-pixel area. The pixel area is used to display an image. The display panel includes a stacked interlayer dielectric layer and a planarization layer. and pixel bounding layers. An inscribed structure and one or more electrode overlapping structures are provided in the non-pixel area. The one or more electrode overlapping structures are located in the first functional layer. The electrode overlapping structures include auxiliary electrodes and An application electrode above the auxiliary electrode, the application electrode is connected to the auxiliary electrode, and the first functional layer is any one of the interlayer dielectric layer and the planarization layer;

The inscribed structure penetrates from the pixel definition layer to the upper surface of the first functional layer, and the application electrode exposes the upper surface of the first functional layer through the inscribed structure to connect with the display panel. The first cathode layer is connected, and the inscribed structure is used to isolate the first functional layer and the functional layer above the first functional layer among the interlayer dielectric layer, the planarization layer and the pixel definition layer.

In the display panel provided by the embodiment of the present application, since an auxiliary electrode is provided in the first functional layer, and an application electrode is provided above the auxiliary electrode, the interlayer dielectric layer of the display panel is cut off by arranging an inscribed structure on the display panel. , flattening layer, pixel definition layer. The application electrode and the auxiliary electrode are overlapped, and a cathode layer is provided on the auxiliary electrode to realize the overlap between the cathode layer and the auxiliary electrode. By applying an auxiliary voltage to the auxiliary electrode, assistance can be provided to the area with a large voltage drop in the display panel. This reduces the voltage dividing effect of the resistor on the cathode layer and reduces the voltage drop. The embodiment of the present application uses the applied electrode as a bridge, and the preparation of the cathode layer does not require bypassing the partition. Therefore, the solution of the present application avoids the costly inverted trapezoidal isolation column.

In a possible implementation of the present application, the inscribed structure includes a first contact hole opened on the upper surface of the first functional layer and penetrating the interlayer dielectric layer, the planarization layer and the pixel definition layer. A second contact hole of a functional layer other than the first functional layer, the position of the second contact hole is opposite to the position of the first contact hole, and the size of the first contact hole is larger than that of the first contact hole. The size of two contact holes, the auxiliary electrode exposes the first functional layer through the first contact hole, the size of the first contact hole is less than or equal to the size of the auxiliary electrode, the size of the auxiliary electrode is greater than or equal to the size of the applied electrode. In a possible implementation of the present application, the first functional layer is the interlayer dielectric layer, or the first functional layer is the planarization layer.

In a possible implementation of the present application, there is an OLED functional layer between the application electrode and the auxiliary electrode, the OLED functional layer is smaller in size than the application electrode, and the application electrode wraps the OLED functional layer .

In a possible implementation of the present application, the first functional layer is the interlayer dielectric layer, the upper surface of the interlayer dielectric layer is in contact with the planarization layer, the auxiliary electrode and the application layer The electrodes are located in the interlayer dielectric layer, and the interlayer A first contact hole for exposing the application electrode is opened on the upper surface of the dielectric layer.

In a possible implementation of the present application, the distribution state of a plurality of the electrode overlapping structures is a lattice pattern, a gradient distribution or an irregular distribution, and each of the electrode overlapping structures is located in one of the inscribed structures. middle.

In a possible implementation of the present application, the display panel further includes a baffle electrode, the baffle electrode is located on a second functional layer, and the second functional layer is the interlayer dielectric layer, the planarization layer, and the interlayer dielectric layer. The baffle electrode is located on the side of the contact hole of the second functional layer.

In a possible implementation of the present application, the material of the baffle electrode is one or more of titanium, aluminum, titanium, molybdenum, tungsten, and molybdenum-tungsten alloy.

In a possible implementation of the present application, the auxiliary electrode is a patterned auxiliary electrode, and there is a hollow area inside the patterned auxiliary electrode.

In a possible implementation of the present application, the display panel further includes a substrate, which includes in order from bottom to top: a substrate, a buffer layer and a gate insulating layer located on the substrate, the interlayer dielectric layer disposed on the gate insulating layer.

In a possible implementation of the present application, the pixel area is provided with sub-pixels of the display panel and driving TFTs of the sub-pixels.

In a possible implementation of the present application, the driving TFT includes: a source-drain electrode, a semiconductor layer, a first gate layer, a second gate layer, and an anode, and the source-drain electrode is located in the planarization layer, The source electrode of the source and drain electrode is connected to the semiconductor layer; the semiconductor layer is provided in the pixel area and is located on the buffer layer of the substrate; the first gate electrode layer and the second gate electrode layer are connected to the semiconductor layer. The electrode layers are all located in the pixel area of the display panel, the first gate layer is located in the interlayer dielectric layer, and the second gate layer is located in the interlayer dielectric layer or the planarization layer; The anode is provided in the pixel defining layer of the display panel and connected to the source electrode.

In a possible implementation of the present application, the display panel further includes an OLED functional layer, a second cathode layer and a film encapsulation layer, the second cathode layer is connected to the first cathode layer filled in the inscribed structure , the second cathode layer is located on the OLED functional layer, the first cathode layer is in contact with the application electrode; the thin film encapsulation layer is located on the first cathode layer and the second cathode layer , used to encapsulate the first cathode layer and the second cathode layer; the OLED functional layer is in contact with the upper surface of the pixel defining layer, and the inscribed structure penetrates from the OLED functional layer to the third On the upper surface of a functional layer, the OLED functional layer located in the pixel area is in contact with the anode provided in the pixel defining layer.

In a possible implementation of the present application, the material of the thin film encapsulation layer is selected from silicon nitride and/or resin, or the thin film encapsulation layer adopts a silicon nitride stack.

In a second aspect, a method for preparing a display panel is provided, which is characterized in that it includes: forming an interlayer dielectric layer, a planarization layer, and a pixel defining layer on a substrate from bottom to top; and preparing an auxiliary layer in the first functional layer. electrode, the first functional layer is any one of the interlayer dielectric layer and the planarization layer; formed between the interlayer dielectric layer, the planarization layer and the pixel definition layer from the pixel The defining layer penetrates into the inscribed structure on the upper surface of the first functional layer, and the inscribed structure is used to isolate the interlayer dielectric layer, the planarization layer and the pixel defining layer located on the first functional layer. a functional layer to expose the auxiliary electrode located in the first functional layer; and an application electrode located on the auxiliary electrode and in contact with the auxiliary electrode is prepared in the first functional layer through the endo-cut structure ; Filling the inscribed structure with cathode material to form the first cathode layer of the display panel, so that the first cathode layer is in contact with the application electrode to obtain the display panel.

In a possible implementation of the present application, an upper surface penetrating from the pixel defining layer to the first functional layer is formed between the interlayer dielectric layer, the planarization layer and the pixel defining layer. The inscribed structure includes: etching a first contact hole in the first functional layer; and a functional layer located under the first functional layer in the interlayer dielectric layer, planarization layer and pixel definition layer. Etching a second contact hole, the position of the first contact hole being opposite to the position of the second contact hole, to obtain the inscribed structure, wherein the size of the second contact hole is larger than the first contact hole hole size.

In a possible implementation of the present application, etching a first contact hole on the first functional layer includes: etching a first contact hole on the first functional layer using an etching method; Etching the second contact hole in the functional layer located below the first functional layer in the interlayer dielectric layer, the planarization layer and the pixel definition layer includes: using an acidic etching liquid to etch the second contact hole in the interlayer dielectric layer. The second contact hole is etched on the functional layer located on the first functional layer among the layer, the planarization layer and the pixel definition layer.

In a possible implementation of the present application, the method further includes: during the process of making the second gate layer located in the first functional layer in the pixel area of the display panel, The first functional layer located in the non-pixel area is prepared The auxiliary electrode in .

In a possible implementation of the present application, the auxiliary electrode is a patterned auxiliary electrode. Before preparing the auxiliary electrode in the first functional layer, the method further includes: preparing a patterned auxiliary electrode, the The patterned auxiliary electrode includes a hollowed area and a non-hollowed area, and the hollowed area runs through the patterned auxiliary electrode.

In a third aspect, a display device is provided, which includes the above-mentioned display panel.

In a fourth aspect, an electronic device is provided. The device includes a display device, and the display device has the above-mentioned display panel.

It can be understood that the beneficial effects of the above-mentioned second aspect, third aspect and fourth aspect can be referred to the relevant descriptions in the above-mentioned first aspect, and will not be described again here.

Description of the drawings

Figure 1 is a top view of a display panel provided by an embodiment of the present application;

Figure 2 is a cross-sectional view of a display panel provided by an embodiment of the present application;

Figure 3 is an internal structural diagram of a display panel provided by an embodiment of the present application;

Figure 4 is a structural diagram of a display panel with baffle electrodes provided by an embodiment of the present application;

Figure 5 is a schematic diagram of a display panel with patterned auxiliary electrodes provided by an embodiment of the present application;

Figure 6 is an internal structural diagram of a display panel provided by an embodiment of the present application;

Figure 7 is a method for manufacturing a display panel provided by an embodiment of the present application.

Detailed ways

In order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as “first” and “second” are used to distinguish the same or similar items with basically the same functions and effects. For example, the first component and the second component are only used to distinguish different components, and their sequence is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and words such as "first" and "second" do not limit the number and execution order.

It should be noted that in this application, words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "such as" is not intended to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application will be described first.

This application can be applied to display panels, especially in medium and large-sized OLED display panels. As the area of the display panel becomes larger and larger, the problem of voltage drop becomes more and more apparent, which leads to uneven brightness of the OLED display panel. . Therefore, in the process of making an OLED display panel, additional auxiliary electrodes are made on the panel to provide assistance to areas with large voltage drops in the OLED display panel, so that the OLED display panel can display uniform images.

The method commonly used in the industry at present is to prepare patterned auxiliary electrodes on the substrate surface of the OLED display panel, prepare pixel defining layers above and on the sides of the auxiliary electrodes, and etch the pixel defining layers on the sides to obtain an inscribed structure, using this inscribed structure The structure cuts off the light-emitting functional layer of the OLED display panel; after cutting off the light-emitting functional layer, the second electrode layer overlaps the auxiliary electrode along the inscribed structure, and finally applies an auxiliary voltage to the auxiliary electrode to solve the problem of medium and large-sized OLED display panels. Voltage drop problem. However, this method is difficult to implement. After etching the pixel definition layer on the side at a fixed point to prepare the incision structure, it is more difficult to effectively isolate the light-emitting functional layer so that it does not overlap along the side. If the light-emitting functional layer is blocked, At this time, the second electrode layer is also easily blocked during actual production. Secondly, new process requirements are also required for OLED manufacturing, which increases the cost.

The inverted trapezoidal isolation column method is also one of the commonly used methods. The inverted trapezoidal isolation column isolates the light-emitting functional layer of the OLED display panel, and connects the cathode and the auxiliary electrode through magnetron sputtering and other methods. However, preparing inverted trapezoidal isolation pillars requires adding specific materials and processes to the existing OLED process, which also increases the cost.

A display panel, a display panel preparation method and an OLED display device provided by embodiments of the present application are explained in detail below.

A display panel 10 provided by an embodiment of the present application includes a display area 101, one or more electrode overlapping structures 102, and a non-display area 103. The electrode overlapping structure 102 is provided in the display area 101 of the display panel 10, as shown in FIG. 1 . Specifically, the electrode overlapping structures 102 are specifically distributed between the display pixels of the display panel 10. The distribution state of the multiple electrode overlapping structures 102 can be dot matrix type, density gradient type, irregular distribution, etc., as shown in Figure 1 It is a dot matrix distribution.

Among them, the display area 101 of the display panel 10 is divided into a pixel area and a non-pixel area. OLED sub-pixels and their driving thin film transistors are prepared in the pixel area to realize the display function. An electrode overlap structure is prepared in the non-pixel area to overlap the OLED cathode layer with the preset auxiliary electrode. An auxiliary voltage is applied to the auxiliary electrode to solve the voltage drop problem of the OLED display panel and achieve uniform brightness of the OLED display panel. .

In one embodiment of the present application, a display panel 20 is shown in Figure 2. The display panel 20 is divided into a pixel area 201 and a non-pixel area 202. The pixel area 201 is used to display images. The display panel 20 includes a stacked interlayer dielectric layer 240, a planarization layer 250, and a pixel definition layer 260. An inscribed structure and one or more electrode overlapping structures are provided in the non-pixel area 202, and the one or more electrode overlapping structures are located in the first functional layer. The electrode overlap structure includes an auxiliary electrode 205 and an application electrode 206 located above the auxiliary electrode 205. The application electrode 206 is connected to the auxiliary electrode 205. The first functional layer is any one of the interlayer dielectric layer 240 and the planarization layer 250 . The inscribed structure penetrates from the pixel definition layer 260 to the upper surface of the first functional layer. The application electrode 206 exposes the upper surface of the first functional layer through the inscribed structure to connect with the cathode layer 281 of the display panel. The inscribed structure is used to isolate the layer. The interlayer dielectric layer 240 and the functional layer located above the interlayer dielectric layer 240 among the interlayer dielectric layer 240 , the planarization layer 250 and the pixel definition layer 260 .

Among them, there is an OLED functional layer 271 between the application electrode 206 and the auxiliary electrode 205. The size of the application electrode 206 is larger than the size of the OLED functional layer 271. As shown in FIG. 2, the application electrode 206 wraps the OLED functional layer 271, separates the OLED functional layer 271, and is connected to the auxiliary electrode 205 through both ends.

In the display panel provided by the embodiment of the present application, since an auxiliary electrode is provided in the first functional layer, and an application electrode is provided above the auxiliary electrode, the interlayer dielectric layer of the display panel is cut off by arranging an inscribed structure on the display panel. , flattening layer, pixel definition layer. The application electrode and the auxiliary electrode are overlapped, and a cathode layer is provided on the auxiliary electrode to realize the overlap between the cathode layer and the auxiliary electrode. Since there is a voltage drop on the surface cathode without the auxiliary electrode and before the electrode is applied, the actual effect is that the voltage at both ends of the display panel decreases, resulting in a decrease in display brightness. By adding the auxiliary electrode and the applied electrode, the voltage of the OLED cathode does not pass through the surface cathode, but passes through the auxiliary electrode and the applied electrode, thus eliminating the surface cathode voltage drop. Therefore, by applying an auxiliary voltage to the auxiliary electrode, the embodiment of the present application can provide assistance to the area of the display panel with a large voltage drop, thereby reducing the voltage dividing effect of the resistor on the cathode layer and reducing the voltage drop. The embodiment of the present application uses the applied electrode as a bridge, and the preparation of the cathode layer does not require bypassing the partition. Therefore, the solution of the present application avoids the costly inverted trapezoidal isolation column.

It can be understood that each functional layer in the interlayer dielectric layer 240, the planarization layer 250, and the pixel definition layer 260 includes two surfaces, such as an upper surface and a lower surface. In one embodiment of the present application, the upper surface of the interlayer dielectric layer 240 is in contact with the lower surface of the planarization layer 250 , and the upper surface of the planarization layer 250 is in contact with the upper surface of the pixel definition layer 260 . The lower surface is in contact with the substrate. In other words, the interlayer dielectric layer 240 is located on the upper surface of the substrate.

Optionally, the display panel in the embodiment of the present application may be an OLED display panel.

In a possible embodiment of the present application, the material filled in the interlayer dielectric layer 240 is silicon nitride. The planarization layer 250 is selected from one or more of resin (Resin), silicon nitride (SiN _x ), silicon oxide (SiO _x ), and silicon oxynitride (SiO _x N _y ). The material of the planarization layer 250 is the same as the material of the pixel defining layer 260 .

The material filled in the interlayer dielectric layer 240 may also be one of silicon nitride (SiN _x ), silicon oxide (SiO _x ), and silicon oxynitride (SiO _x N _y ).

In one embodiment of the present application, the inscribed structure includes a first contact hole opened on the upper surface of the first functional layer and penetrating the interlayer dielectric layer 240 , the planarization layer 250 and the pixel definition layer 260 except for the first functional layer. second contact hole outside the functional layer. The position of the second contact hole is opposite to the position of the first contact hole, and the size of the first contact hole is larger than the size of the second contact hole. The auxiliary electrode 205 exposes the first functional layer through the first contact hole. The size of the first contact hole is smaller than or equal to the size of the auxiliary electrode 205 , and the size of the auxiliary electrode 205 is larger than or equal to the size of the application electrode 206 .

In a possible implementation manner of the present application, taking the first functional layer as the interlayer dielectric layer 240 as an example, as shown in Figure 2, inscribed The structure can be divided into two areas, a first area 203 and a second area 204. The first region 203 separates the planarization layer 250 , the pixel definition layer 260 and the OLED functional layer 270 . The second region 204 is used to isolate the interlayer dielectric layer 240 . Among them, the OLED functional layer 270 is located on the pixel definition layer 260. The auxiliary electrode 205 is located on the interlayer dielectric layer 240 , and the application electrode 206 is located on the auxiliary electrode 205 , wherein the application electrode 206 fills the second region 204 . The cathode layer 281 is provided on the auxiliary electrode 205 . As shown in FIG. 2 , the cathode layer 281 mainly includes a portion located on the OLED functional layer 270 and a portion filled in the first region 203 .

Among them, FIG. 2 is a cross-sectional view of the display panel. The contact hole is a hole etched on the panel. Usually, the cross-sectional shape of the contact hole is circular. The first contact hole and the second contact hole may both be circular holes, and the size of the contact hole represents the diameter of the circular contact hole. It can be understood that the cross-sectional shape of the contact hole can also be other shapes, which is not limited in this application.

In a possible implementation manner of the present application, as shown in Figure 2, taking the first functional layer as the interlayer dielectric layer 240 as an example, opening a first contact hole on the interlayer dielectric layer 240 can form as shown in Figure 2 Second area 204. Opening a second contact hole through the planarization layer 250 and the pixel definition layer 260 may form the first region 203 as shown in FIG. 2 . The first contact hole is located above the auxiliary electrode 205 , and the size of the first contact hole is smaller than or equal to the size of the auxiliary electrode 205 , so that the auxiliary electrode 205 exposes the interlayer dielectric layer 240 .

In one embodiment of the present application, when the first functional layer is an interlayer dielectric layer 240, as shown in FIG. 2, the interlayer dielectric layer 240 includes a first interlayer dielectric layer 242 and a A second interlayer dielectric layer 241 above 242. The auxiliary electrode 205 and the application electrode 206 are both located on the second interlayer dielectric layer 241 , and the upper surface of the second interlayer dielectric layer 241 is in contact with the planarization layer 250 . A first contact hole for exposing the application electrode 206 is formed on the upper surface of the second interlayer dielectric layer 241 .

Specifically, the lower surface of the first interlayer dielectric layer 242 is in contact with the gate insulating layer 230 in the substrate, and the upper surface of the first interlayer dielectric layer 242 is in contact with the lower surface of the second interlayer dielectric layer 241 .

In a possible embodiment of the present application, as shown in FIG. 2 , the interlayer dielectric layer 240 also has a first gate layer 62 and a second gate layer 63 , and the planarization layer 250 also has a source and drain electrode 60 . , there is also an anode 64 in the pixel definition layer 260. Specifically, the first gate layer 62 is located in the first interlayer dielectric layer 242 , and the second gate layer 63 is located in the second interlayer dielectric layer 241 .

In a possible implementation of the present application, taking the first functional layer as the planarization layer 250 as an example, as shown in FIG. 3 , the inscribed structure can be divided into two regions, the first region 203 and the second region 204 . The first region 203 is used to isolate the pixel definition layer 260 and the OLED functional layer 270 . Among them, when preparing the OLED functional layer 270, the OLED functional layer 271 will inevitably be formed in the endostructure, that is, the OLED functional layer 271 will be formed on the auxiliary electrode 205, and the applied electrode 206 is used to isolate the OLED functional layer 271. The second area 204 is used to isolate the planarization layer 250 . Among them, the OLED functional layer 270 is located on the pixel definition layer 260. The auxiliary electrode 205 is located on the planarization layer 250, the application electrode 206 is also located on the planarization layer 250, and the application electrode 206 is located on the auxiliary electrode 205 and is in contact with the auxiliary electrode 205 to achieve connection, wherein the application electrode 206 fills the second region 204. The cathode layer 281 is provided on the auxiliary electrode 205 . As shown in FIG. 2 , the cathode layer 281 mainly includes a portion located on the OLED functional layer 270 and a portion filled in the first region 203 . In one embodiment of the present application, taking the first functional layer as the planarization layer 250 as an example, as shown in FIG. 3 , the second region 204 is used to isolate the planarization layer 250 . When the second region 204 is used to isolate the planarization layer 250, the first region 203 is used to isolate the pixel definition layer 260 and the OLED functional layer 270, the auxiliary electrode 205 is located in the planarization layer 250, and the cathode layer is located in the pixel definition layer 260, And connected to the application electrode 206 .

It can be understood that the inscribed structure of the display panel, that is, the first contact hole and the second contact hole, can be in different film layers. That is, depending on the position of the auxiliary electrode, the inscribed structure is also located in different film layers, which can block the OLED function. The layer 270, the pixel definition layer 260, the planarization layer 250 and the interlayer dielectric layer 240 can also isolate the OLED functional layer 270, the pixel definition layer 260 and the planarization layer 250.

In one embodiment of the present application, as shown in FIG. 4 , the display panel further includes a baffle electrode 401 . The baffle electrode 401 is located on the second functional layer. The second functional layer is the functional layer in contact with the first functional layer among the interlayer dielectric layer 240, the planarization layer 250 and the pixel definition layer 260. The baffle electrode 401 is located on the second functional layer. side of the contact hole. As an example, a through hole is opened on the baffle electrode, the position of the through hole is opposite to the position of the first contact hole, and the size of the through hole is equal to the size of the second contact hole.

In a possible implementation of the present application, taking the first functional layer as the interlayer dielectric layer 240 as an example, the auxiliary electrode 205 is located on the interlayer dielectric layer 240, the application electrode 206 is provided in the interlayer dielectric layer 240, and the second The functional layer is the planarization layer 250, and the baffle electrodes 401 are located on both sides of the first contact hole. The baffle electrodes 401 are provided to prevent or slow down the inscribed structure formed by the first contact hole and the second contact hole, and the etching process. The mid-corners are overetched.

As an example, the baffle electrode 401 is made of titanium-aluminum-titanium material.

In one embodiment of the present application, as shown in (a) of FIG. 5 , the auxiliary electrode 500 is a patterned auxiliary electrode with a hollow area in the middle, that is, the auxiliary electrode is hollowed out. The patterned auxiliary electrode is used to increase the contact area between the auxiliary electrode 500 and the application electrode 206. When the auxiliary electrode 500 is not a patterned auxiliary electrode, the contact area between the application electrode 206 and the auxiliary electrode 500 is the area of the contact surface between the two. When the auxiliary electrode 500 is a patterned auxiliary electrode, the hollow area of the auxiliary electrode 500 is filled with the application electrode 206, and The contact area of application electrode 206 increases the side area. It can be understood that the shape of the hollow area can be any shape, and is not limited in this application.

Specifically, (a) in Figure 5 is a cross-sectional view of the auxiliary electrode 500, (b) in Figure 5 is a top view of the auxiliary electrode 500, the dotted line 501 is the cross-section of the auxiliary electrode 500, and the hollow area 502 is the cross-section of the auxiliary electrode 500. For example, if the pattern is made by etching, the auxiliary electrode 500 will penetrate through it. It can be understood that there is a height difference between the auxiliary electrode 500 and the first interlayer dielectric layer 242, that is, the hollow area 502 makes the application electrode 206 equal to the thickness difference between the first interlayer dielectric layer 242 and the OLED functional layer 271, and the non-hollow area is the thickness difference between the first interlayer dielectric layer 242 and the OLED functional layer 271. The difference between the thickness of the interlayer dielectric layer and the thickness of the auxiliary electrode 500 plus the OLED functional layer 271 uses the height difference to more effectively isolate the first interlayer dielectric layer 242, and the side or corner of the hollow area of the auxiliary electrode 500 Exposed, the contact area between the auxiliary electrode 500 and the application electrode 206 is increased. The height difference between the patterned auxiliary electrode and the underlying substrate blocks the OLED functional layer for a second time, further improving the conduction effect of the electrode overlap structure.

In one embodiment of the present application, as shown in FIG. 2 , the display panel 20 further includes: a substrate 210, a buffer layer 220 and a gate insulation layer 230. The buffer layer 220 is located on the substrate 210, and the gate insulation layer 230 is located on the buffer layer 220. The interlayer dielectric layer 240 is located on the gate insulating layer 230 .

In one embodiment of the present application, the pixel area of the display panel is provided with sub-pixels and driving TFTs of the sub-pixels. As shown in (a) of FIG. 6 , the auxiliary electrode 205 is located in the second interlayer dielectric layer 241 , and the driving TFT includes: source and drain electrodes 60 , semiconductor layer 61 , first gate layer 62 , and second gate layer 63 , and anode 64. The source and drain electrodes 60 are located in the planarization layer 250 , wherein the source and drain electrodes 603 are connected to the semiconductor layer 61 . The semiconductor layer 61 is provided in the pixel area and is located on the buffer layer 220 . The first gate layer 62 and the second gate layer 63 are both located in the pixel area. The first gate layer 62 is located in the interlayer dielectric layer 240 , and the second gate layer 63 is located in the second layer of the interlayer dielectric layer 240 Intermediate layer 241 or planarization layer 250. The anode 64 is disposed in the pixel defining layer 260 and connected to the source and drain electrodes 604 .

In one embodiment of the present application, the display panel further includes an OLED functional layer 270, a second cathode layer 280, and a thin film encapsulation layer 290, as shown in (c) of FIG. 6 . The second cathode layer 280 is connected to the first cathode layer 281 in the endostructure, which is in contact with the application electrode 206 . The thin film encapsulation layer 290 is located on the second cathode layer 280 and the first cathode layer 281 and is used to encapsulate the second cathode layer 280 and the first cathode layer 281 . The OLED functional layer 270 is in contact with the upper surface of the pixel defining layer 260. Correspondingly, the inscribed structure penetrates from the OLED functional layer 270 to the upper surface of the first functional layer (such as the interlayer dielectric layer 240). The OLED functional layer located in the pixel area In contact with the anode provided in the pixel defining layer.

As an example, the material of the thin film encapsulation layer 290 is selected from silicon nitride and/or resin, or a silicon nitride stack is used.

This embodiment provides a method for preparing a display panel, as shown in Figure 7. The method includes:

Step 701: Form an interlayer dielectric layer, a planarization layer, and a pixel definition layer on the substrate in order from bottom to top.

The material of the planarization layer 250 may be selected from one or more of resin (Resin), silicon nitride (SiN _x ), silicon oxide (SiO _x ), and silicon oxynitride (SiO _x N _y ). In some embodiments, the material of planarization layer 250 is the same as the material of pixel defining layer 260 . The interlayer dielectric layer 240 is silicon nitride. Among them, x ranges from 0 to 5, and y ranges from 0 to 5, which are not limited here.

As an example, a display panel structure as shown in (a) in Figure 6 is prepared according to a traditional display panel manufacturing process. The structure includes an interlayer dielectric layer 240, a planarization layer 250 and a pixel definition layer 260, where the interlayer The dielectric layer 240 includes a first interlayer dielectric layer 242 and a second interlayer dielectric layer 241 .

Step 702: Prepare an auxiliary electrode in the first functional layer, which is any one of an interlayer dielectric layer and a planarization layer.

As an example, taking the first functional layer as the interlayer dielectric layer 240 as shown in (a) of FIG. 6 , the auxiliary electrode 205 is located in the second interlayer dielectric layer 241 , while the second gate electrode layer 63 is being prepared. , prepare the auxiliary electrode 205. The material of the auxiliary electrode is molybdenum. The source and drain electrodes 60 are located in the planarization layer 250 , the semiconductor layer 61 is located in the gate insulating layer 230 , the first gate layer 62 is located in the first interlayer dielectric layer 242 , and the anode 64 is located in the pixel defining layer 260 .

Step 703: An inscribed structure penetrating from the pixel defining layer to the upper surface of the first functional layer is formed between the interlayer dielectric layer 240, the planarization layer 250 and the pixel defining layer 260. The inscribed structure isolates the interlayer dielectric layer 240, Planarization layer 250 and pixel definition The functional layer in the layer 260 is located on the first functional layer to expose the auxiliary electrode 205 located in the first functional layer.

In one embodiment of the present application, the inscribed structure includes etching a first contact hole in the first functional layer, on the functional layer above the first functional layer among the interlayer dielectric layer, the planarization layer and the pixel definition layer. Etch the second contact hole. The position of the first contact hole is opposite to the position of the second contact hole. Wherein, the size of the second contact hole is larger than the size of the first contact hole.

As an example, as shown in (b) of FIG. 6 , the first functional layer is the second interlayer dielectric layer 241 in the interlayer dielectric layer 240 , and area 1 and area 2 are inscribed structures. Among them, area 1 is the first contact hole, and area 2 is the second contact hole.

In a possible implementation of the present application, etching the first contact hole in the first functional layer includes: using an etching method, such as wet photolithography technology, and using an alkaline etching solution to etch the first contact hole on the first functional layer. The first contact hole is etched, and the alkaline etching solution may be sodium bicarbonate solution, potassium hydroxide solution, tetramethylammonium hydroxide solution, etc. In another possible implementation manner, the first contact hole can also be etched by dry etching, such as using oxygen, hydrogen fluoride and other gases. Etching the second contact hole in the functional layer below the first functional layer in the interlayer dielectric layer 240 , the planarization layer 250 and the pixel definition layer 260 includes using an acidic etching liquid to etch the second contact hole in the interlayer dielectric layer 240 , the planarization layer 250 and etching the second contact hole in the functional layer located below the first functional layer in the pixel defining layer 260 .

Step 704: Prepare an application electrode located on the auxiliary electrode and in contact with the auxiliary electrode in the first functional layer through an endocut structure.

In one embodiment of the present application, inkjet printing is used to prepare the application electrode 206. Silver paste of the application electrode 206 is filled in the first contact hole by inkjet printing. The silver paste is connected to both sides of the auxiliary electrode 205 to achieve conduction.

Before step 704, the OLED functional layer 270 is prepared by evaporation. It is inevitable that an OLED functional layer 271 is also evaporated in the endostructure, that is, on the auxiliary electrode 205. The OLED function 271 is blocked by the application electrode 206 and connected to the auxiliary electrode 205 .

Step 705: Fill the cathode material in the endostructure to form the first cathode layer 281 of the display panel, so that the first cathode layer 281 is in contact with the application electrode 206 to obtain a display panel.

As an example, as shown in (c) of FIG. 6 , the application electrode 206 is filled in the first contact hole in the endostructure, and the application electrode 206 is in contact with the auxiliary electrode 205 . A first cathode layer 281 is provided above the application electrode 206 . The application electrode 206 is prepared by filling the first contact hole by inkjet or the like.

In one embodiment of the present application, the method for preparing a display panel further includes preparing a patterned auxiliary electrode, as shown in (b) of Figure 5 . The hollow area 502 of the auxiliary electrode 500 is the thickness of the first interlayer dielectric layer 242, and the other areas are the difference between the thickness of the first interlayer dielectric layer and the thickness of the auxiliary electrode 500. The height difference is used to more effectively isolate the first interlayer dielectric layer. 242, and the sides or corners of the hollow area of the auxiliary electrode 500 are exposed, which increases the contact area between the auxiliary electrode 500 and the application electrode 206.

In one embodiment of the present application, the preparation method of the display panel further includes evaporating the OLED functional layer 270 of the display panel, and the OLED functional layer 270 is located on the pixel defining layer 260 . The first cathode layer 281 and the second cathode layer 280 of the display panel are evaporated on the application electrode 206 and the OLED functional layer 270, and the thin film encapsulation layer 290 of the display panel is evaporated on the first cathode layer 281 and the second cathode layer 280. , (c) in Figure 6.

Among them, the first cathode layer 281 is prepared on the application electrode 206 by evaporation method, and the second cathode layer 280 is prepared on the OLED functional layer 270. The first cathode layer 281 and the second cathode layer 280 are connected to form a display. The cathode layer of the panel. Among them, the cathode material is magnesium silver, and the thin film encapsulation layer material is a stack of alternating inorganic layers and organic layers. The inorganic layer is usually one or more of silicon nitride, silicon oxide, and silicon oxynitride. Oxidation can also be used. Aluminum or magnesium oxide, the organic layer is resin material, such as hexamethyldisilyl ether, polymethyl methacrylate, etc.

An embodiment of the present application provides a display device. The display device includes the above-mentioned display panel, and an encapsulation layer used to encapsulate the display panel.

In the above embodiment, the application electrode can be introduced as a bridge to realize the connection between the auxiliary electrode and the cathode layer. In another possible embodiment of the present application, the application electrode may not be introduced, but a special process can be used to make the cathode layer span the inscribed The structure is directly connected to the auxiliary electrode. For example, magnetron sputtering, tilted evaporation and other processes are used to prepare the cathode, while increasing the thickness of the cathode layer.

In another possible embodiment of the present application, the inscribed structure of this solution can be prepared in the AA hole area to block the side penetration of water and oxygen. In this area, no application electrode is provided, and the inscribed structure is used to separate the OLED functional layer and the OLED cathode, completely blocking the side penetration path of water and oxygen.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not detailed or documented in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein The steps can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

In the embodiments provided in this application, it should be understood that the disclosed apparatus/computer equipment and methods can be implemented in other ways. For example, the apparatus/computer equipment embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components. can be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.

The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still implement the above-mentioned implementations. The technical solutions described in the examples are modified, or some of the technical features are equivalently replaced; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of this application, and should be included in within the protection scope of this application.

Claims

A display panel, characterized in that the display panel is divided into a pixel area and a non-pixel area, the pixel area is used to display images, and the display panel includes a stacked interlayer dielectric layer, a planarization layer and a pixel defining layer,

An inscribed structure and one or more electrode overlapping structures are provided in the non-pixel area. The one or more electrode overlapping structures are located in the first functional layer. The electrode overlapping structures include auxiliary electrodes and An application electrode above the auxiliary electrode, the application electrode is connected to the auxiliary electrode, and the first functional layer is any one of the interlayer dielectric layer and the planarization layer;

The inscribed structure penetrates from the pixel definition layer to the upper surface of the first functional layer, and the application electrode exposes the upper surface of the first functional layer through the inscribed structure to connect with the display panel. The first cathode layer is connected, and the inscribed structure isolates the first functional layer and the functional layer above the first functional layer among the interlayer dielectric layer, the planarization layer and the pixel definition layer.
The display panel according to claim 1, wherein the inscribed structure includes a first contact hole opened on the upper surface of the first functional layer and a first contact hole penetrating the interlayer dielectric layer, the planarization layer and the pixel. A second contact hole defining a functional layer other than the first functional layer in the layer, the position of the second contact hole being opposite to the position of the first contact hole, and the size of the first contact hole being larger than The size of the second contact hole, the auxiliary electrode exposing the first functional layer through the first contact hole, the size of the first contact hole being less than or equal to the size of the auxiliary electrode, the auxiliary electrode The size is greater than or equal to the size of the application electrode.
The display panel according to claim 1 or 2, characterized in that there is an OLED functional layer between the applying electrode and the auxiliary electrode, the size of the applying electrode is larger than the size of the OLED functional layer, and the applying electrode Electrodes wrap the OLED functional layer.
The display panel according to any one of claims 1 to 3, wherein the first functional layer is the interlayer dielectric layer, and the upper surface of the interlayer dielectric layer is in contact with the planarization layer, The auxiliary electrode and the application electrode are both located in the interlayer dielectric layer, and a first contact hole for exposing the application electrode is opened on the upper surface of the interlayer dielectric layer.
The display panel according to any one of claims 1 to 4, characterized in that the distribution state of the plurality of electrode overlapping structures is dot matrix, gradient distribution or irregular distribution;

Each of the electrode overlapping structures is located within one of the inscribed structures.
The display panel according to any one of claims 1 to 5, wherein the display panel further includes a baffle electrode,

The baffle electrode is located on a second functional layer, and the second functional layer is a functional layer in contact with the first functional layer among the interlayer dielectric layer, the planarization layer and the pixel definition layer, so The baffle electrode is located on the side of the contact hole of the second functional layer.
The display panel according to claim 6, wherein the baffle electrode is made of one or more materials selected from the group consisting of titanium, aluminum, titanium, molybdenum, tungsten, and molybdenum-tungsten alloy.
The display panel according to any one of claims 1 to 7, wherein the auxiliary electrode is a patterned auxiliary electrode, and the patterned auxiliary electrode has a hollow area.
The display panel according to any one of claims 1 to 8, characterized in that the display panel further includes a substrate, and the substrate includes in order from bottom to top: a base, a buffer layer located on the base, and a gate insulation. layer, the interlayer dielectric layer is provided on the gate insulating layer.
The display panel according to any one of claims 1 to 9, characterized in that the display panel further includes an OLED functional layer, a second cathode layer and a film encapsulation layer, the second cathode layer is connected and filled in the inner The first cathode layer in the cut structure, the second cathode layer is located on the OLED functional layer, and the first cathode layer is in contact with the application electrode;

The thin film encapsulation layer is located on the first cathode layer and the second cathode layer, and is used to encapsulate the first cathode layer and the second cathode layer;

The OLED functional layer is in contact with the upper surface of the pixel definition layer, and the inscribed structure penetrates from the OLED functional layer to the upper surface of the first functional layer.
A method for preparing a display panel, characterized by including:

Form an interlayer dielectric layer, a planarization layer, and a pixel definition layer on the substrate in order from bottom to top;

Prepare an auxiliary electrode in a first functional layer, which is any one of the interlayer dielectric layer and the planarization layer;

Between the interlayer dielectric layer, the planarization layer and the pixel defining layer, a penetrating layer is formed from the pixel defining layer to the The inscribed structure on the upper surface of the first functional layer blocks the functional layer located on the first functional layer among the interlayer dielectric layer, planarization layer and pixel defining layer to expose the functional layer located on the upper surface of the first functional layer. the auxiliary electrode in the first functional layer;

An application electrode located on the auxiliary electrode and in contact with the auxiliary electrode is prepared in the first functional layer through the endostructure;

The cathode material is filled in the inscribed structure to form the first cathode layer of the display panel, so that the first cathode layer is in contact with the application electrode, thereby obtaining the display panel.
The method according to claim 11, characterized in that: forming from the pixel defining layer to the first functional layer between the interlayer dielectric layer, the planarization layer and the pixel defining layer. Inscribed structures on the upper surface include:

Etching a first contact hole in the first functional layer;

A second contact hole is etched into the functional layer below the first functional layer in the interlayer dielectric layer, the planarization layer and the pixel definition layer, the position of the first contact hole and the second contact hole The positions are opposite to obtain the inscribed structure, wherein the size of the second contact hole is larger than the size of the first contact hole.
The method of claim 12, wherein etching a first contact hole in the first functional layer includes:

Using an etching method to etch a first contact hole on the first functional layer;

Etching a second contact hole on the functional layer located on the first functional layer among the interlayer dielectric layer, the planarization layer and the pixel definition layer includes:

An acidic etching liquid is used to etch the second contact hole in the functional layer located below the first functional layer among the interlayer dielectric layer, the planarization layer and the pixel definition layer.
The method according to any one of claims 11 to 13, characterized in that the method further includes:

In the process of preparing the second gate layer located in the first functional layer in the pixel area of the display panel, the auxiliary gate layer located in the first functional layer is prepared in the non-pixel area of the display panel. electrode.
The method according to any one of claims 11 to 13, wherein the auxiliary electrode is a patterned auxiliary electrode. Before preparing the auxiliary electrode in the first functional layer, the method further includes:

A patterned auxiliary electrode is prepared, and the patterned auxiliary electrode includes a hollowed-out area and a non-hollowed-out area.
A display device, characterized in that the display device includes the display panel according to any one of claims 1 to 10.
An electronic device, characterized in that the device includes a display device, and the display device has the display panel according to any one of claims 1 to 10.