WO2024021693A1

WO2024021693A1 - Semiconductor structure and manufacturing method therefor

Info

Publication number: WO2024021693A1
Application number: PCT/CN2023/089000
Authority: WO
Inventors: 毛宇
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-07-28
Filing date: 2023-04-18
Publication date: 2024-02-01
Also published as: CN117525031A

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate (10), metal pads (11), through silicon via structures (12), and isolation ring structures (13). The substrate (10) has a first surface (10a) and a second surface (10b) opposite to each other. The metal pads (11) are located on the side of the second surface (10b) facing away from the substrate (10). The through silicon via structures (12) penetrate through the substrate (10) through the first surface (10a) in the thickness direction and are in contact connection with the metal pads (11); the orthographic projections of the metal pads (11) on the second surface (10b) cover the bottom surfaces of the through silicon via structures (12). The isolation ring structures (13) are formed in the substrate (10) and surround the through silicon via structures (12), wherein the inner side wall and the outer side wall of each isolation ring structure (13) have a preset distance.

Description

Semiconductor structures and preparation methods

Cross-references to related applications

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on July 28, 2022, with the application number 202210901242.2 and the invention title "Semiconductor Structure and Preparation Method thereof". The entire content of the patent application is incorporated by reference in This disclosure is ongoing.

Technical field

The present disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a preparation method thereof.

Background technique

With the rapid development of integrated circuit technology, three-dimensional packaging technology is widely used in various high-speed circuits and miniaturized systems due to its good electrical performance and high reliability. Through Silicon Via (TSV) technology is an emerging three-dimensional integrated circuit manufacturing process that stacks chips to achieve interconnection. It achieves electrical interconnection between different chips by producing several vertical interconnection TSV structures on the wafer. even. TSV technology has enabled the layout of integrated circuits to evolve from traditional two-dimensional side-by-side arrangement to more advanced three-dimensional stacking. It can maximize the density of chip stacking in the three-dimensional direction, the shortest interconnection lines between chips, and the smallest overall size, thus greatly improving the efficiency of the circuit. Frequency characteristics and power characteristics are very important technologies in current electronic packaging technology.

In TSV process technology, since the thinned wafer is usually also at the micron level, holes or trenches with a high aspect ratio need to be produced. For deep hole etching with a high aspect ratio, etching is usually strengthened. The energy causes etching appendages to be sputtered to the sidewalls of holes or trenches and gradually accumulate and diffuse, reducing the isolation performance of adjacent through silicon holes and causing the risk of conduction.

Contents of the invention

In order to achieve the above objects and other related objects, one aspect of the present disclosure provides a semiconductor structure, including a substrate, a metal pad, a through silicon via structure and an isolation ring structure; the substrate has an opposite first surface and a second surface; a metal The pad is located on a side of the second surface facing away from the substrate; the through-silicon via structure penetrates the substrate along the thickness direction through the first surface and is in contact with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through-silicon via structure; The isolation ring structure is formed in the substrate and surrounds the through silicon via structure, wherein the inner side wall and the outer side wall of the isolation ring structure have a preset distance.

In some embodiments, the isolation ring structure penetrates the substrate along the thickness direction through the first surface and extends to the second surface.

In some embodiments, an isolation protective layer is included between the inner side wall of the isolation ring structure and the outer side wall of the through silicon via structure.

In some of these embodiments, the isolation protective layer includes an insulating material.

In some embodiments, the semiconductor structure further includes an annular barrier layer; the annular barrier layer surrounds the through silicon via structure and is located between the isolation protection layer and the through silicon via structure.

In some of these embodiments, the annular barrier layer extends through the substrate through the first surface in the thickness direction and to the metal pad.

In some embodiments, the minimum distance between the inner side wall of the isolation ring structure and the outer side wall of the through silicon via structure is greater than or equal to 1 μm.

In some embodiments, the minimum distance between the outer side walls of adjacent isolation ring structures is greater than or equal to 1 μm.

In some embodiments, the preset distance is 2 μm-10 μm.

In some embodiments, the material of the isolation ring structure includes a first low-k material layer, a metal barrier layer, and a second low-k material layer, wherein the first low-k material layer surrounds the through silicon via. In the structure, the metal barrier layer surrounds the first low dielectric constant material layer, and the second low dielectric constant material layer surrounds the metal barrier layer.

In some embodiments, the thickness of the metal barrier layer is less than the sum of the thicknesses of the first low-k material layer and the second low-k material layer.

In some embodiments, the thickness of the metal barrier layer is 1/3-2/3 of the sum of the thicknesses of the first low dielectric constant material layer and the second low dielectric constant material layer.

In some of these embodiments, the material of the first low dielectric constant material layer is selected from the group consisting of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, fluorocarbons, and combinations thereof.

In some of these embodiments, the material of the metal barrier layer is selected from tantalum, tantalum nitride, titanium nitride, and combinations thereof.

In some of these embodiments, the material of the second low-k material layer is selected from the group consisting of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, fluorocarbons, and combinations thereof.

In some embodiments, the material of the annular barrier layer includes at least one of tantalum, tantalum nitride, and titanium nitride.

Another aspect of the present disclosure provides a method for preparing a semiconductor structure, including the following steps: providing a substrate with opposing first and second surfaces, and forming a metal pad on a side of the second surface facing away from the substrate; An isolation ring structure is formed in the substrate, and there is a preset distance between the inner wall and the outer wall of the isolation ring structure; a through silicon via structure is formed in the substrate within the isolation ring structure, and the through silicon via structure passes through the first surface along the thickness direction It penetrates the substrate and is in contact with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure.

In some embodiments, a first dielectric layer is formed between the metal pad and the second surface; the isolation ring structure includes a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer. A low dielectric constant material layer surrounds the through silicon via structure, a metal barrier layer surrounds the first low dielectric constant material layer, and a second low dielectric constant material layer surrounds the metal barrier layer; an isolation ring structure is formed in the substrate The steps include: forming a second dielectric layer on the first surface of the substrate; etching the second dielectric layer and the substrate to obtain an isolation ring gap, which exposes part of the first dielectric layer; forming a first dielectric layer in the isolation ring gap. A low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer to obtain an isolation ring structure.

In some embodiments, the step of forming a through silicon via structure in the substrate in the isolation ring structure includes: etching the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, and the through hole exposes part of the metal pad; form an isolation protective layer on the side wall of the through hole; deposit an annular barrier layer on the side wall of the isolation protective layer; fill the through hole with a conductive material layer and perform planarization to obtain a through silicon hole structure.

In some embodiments, the preset distance is 2 μm-10 μm.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of drawings

To better describe and illustrate the disclosed embodiments and/or examples disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the figures should not be construed as limiting the scope of any of the disclosed disclosures, the embodiments and/or examples presently described, and the best mode currently understood of these disclosures.

1-2 are schematic cross-sectional views of a semiconductor structure in the process of etching TSVs in traditional technology according to an embodiment of the present disclosure;

Figure 3 shows a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

Figure 4 shows a schematic cross-sectional view of the semiconductor structure along the direction AA' in Figure 3 provided in an embodiment of the present disclosure;

Figure 5 shows a schematic flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

Figure 6 shows a schematic flow chart of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure;

Figure 7 shows a schematic flow chart of a semiconductor structure preparation method provided in yet another embodiment of the present disclosure;

FIG. 8 is a schematic cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure.

Detailed ways

To facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. There is illustrated in the accompanying drawings a preferred embodiment of the present disclosure. However, the present disclosure may be implemented in many different forms and is not limited to those described herein. the described embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer , adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

The disclosed embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. Thus, variations from the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein but include deviations in shapes due to, for example, manufacturing. The regions shown in the figures are schematic in nature and their shapes are not intended to be The actual shapes of the regions of the device are shown and are not intended to limit the scope of the present disclosure.

See Figure 1-Figure 8. It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show the components related to the present disclosure and do not follow the actual implementation of the component number, shape and Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

With the development of integrated circuits and changes in the times, people's requirements for electronic products have moved closer to smaller sizes, more functions, and greener features. Therefore, people are working hard to make electronic systems smaller and more integrated. The higher the level, the more functions the technology direction leads to, and therefore many new technologies, new materials and new designs have been produced. Moore's Law predicts that when prices remain unchanged, the number of components that can be accommodated on an integrated circuit will double approximately every 18-24 months. However, with the development of Complementary Metal-Oxide-Semiconductor , CMOS) transistor's physical size is gradually approaching the limit, and it is no longer reasonable to simply rely on reducing transistor size to improve integrated circuit performance. Therefore, it has become unfeasible to rely on reducing the size of transistors to improve integrated circuit performance and reduce power consumption. Three-dimensional integrated circuits are considered to be a feasible solution to continue Moore's Law, further improve integrated circuit performance and reduce power consumption. Among them, stacked chips Packaging technology is a typical representative of these technologies. Stacked chip packaging technology, referred to as 3D packaging technology, refers to a packaging technology that stacks two or more chips in the same package in the vertical direction without changing the size of the package. technique. 3D packaging has two methods: package stacking (Package-on-Package, POP) and chip stacking packaging. Package stacking technology usually uses stacked thin small outline packaging (Thin Sma11 Outline Package, TSOP) or chip size packaging based on traditional packaging technology ( Chip Scale Package (CSP), however, there are long interconnect lines between chips, which limits the high-frequency and high-speed performance of the package stack. Currently, TSV technology based on wafer manufacturing technology has attracted more and more attention from the semiconductor manufacturing industry. TSV technology achieves electrical interconnection between upper and lower chips by creating vertical interconnection vias on the wafer. Compared with wire bonds, Hehe flip-chip welding and other processes. TSV technology can reduce the interconnection length between two nodes, so it has the following advantages compared to two-dimensional integrated circuits: shorter signal delay, higher operating frequency, smaller parasitic capacitance and lower energy consumption , can effectively realize 3D chip stacking and create packages with more complex structures, more powerful performance, and cost-efficiency.

As an example, please refer to Figures 1-2. In the fabrication process of three-dimensional integrated circuits, TSV has been used to form stacked arrangements in devices such as MEMS (Micro-Electro-Mechanical System) and semiconductor devices. Or the electrical connection between layers in a 3D layout. As an important technology in advanced packaging platforms, TSV needs to etch the thinned wafer and other dielectric layers, and finally connect them to the metal pads. Due to the thinned wafer, Circles are also typically micron thick, so advanced etching processes are required to create holes or trenches in the substrate with extremely large aspect ratios. In Figure 1, in deep hole etching of a substrate with a high aspect ratio, the energy of the etched material is usually enhanced. At this time, bombardment of the underlying metal pad is inevitable, resulting in etching appendages 111 Sputtered to the sidewalls of holes or trenches and gradually accumulated, the etching appendages 111 sputtered to the sidewalls will gradually penetrate into the sidewalls and diffuse; in Figure 2, when the TSV process is completed, although a barrier is formed layer, but the etching appendages 111 sputtered to the side walls of the holes have diffused into the inside of the substrate. When the etching appendages 111 diffused into the depth of the substrate gradually increase, the adjacent through silicon holes will become conductive. The risk is that the isolation performance of adjacent through-silicon vias will be reduced, and such TSV manufacturing defects will have a serious impact on the production yield of semiconductor products. Therefore, in order to solve the problems in the above-mentioned technologies, the present disclosure provides a semiconductor structure and a preparation method thereof, which can prevent the etching appendages 111 from diffusing into the interior of the substrate, that is, preventing the material in the metal pad from diffusing into the sidewalls and opposing each other. The interference caused by adjacent TSVs can effectively improve the degradation of TSV isolation performance caused by deep hole etching and improve the yield.

As an example, please refer to Figure 3. An embodiment of the present disclosure provides a semiconductor structure, including a substrate 10, a metal pad 11, a through silicon via structure 12 and an isolation ring structure 13; the substrate 10 has an opposite first surface 10a and the second surface 10b; the metal pad 11 is located on the side of the second surface 10b away from the substrate 10; the through silicon via structure 12 penetrates the substrate 10 along the thickness direction through the first surface 10a and is in contact with the metal pad 11; the metal pad 11 The orthographic projection on the second surface 10b covers the bottom surface of the through silicon via structure 12; the isolation ring structure 13 is formed in the substrate 10 and surrounds the through silicon via structure 12, wherein the inner and outer walls of the isolation ring structure 13 have predetermined Set distance.

In the above embodiment, the metal pad 11 is located on the second surface 10b of the substrate 10 and on the side away from the substrate 10, and an isolation ring structure 13 is provided in the area surrounding the through silicon via structure 12, which is formed during the TSV etching process. The through-silicon via structure 12 with a high aspect ratio will be etched using an etching material with high energy. When the substrate 10 is etched to form a through-silicon via, the etching process proceeds to the substrate 10 When the bottom is close to the upper surface of the metal pad 11, the high-energy etching material will bombard the metal pad 11, and the metal material in the metal pad 11 will splash to the side wall of the etching hole. Then, the material in the metal pad 11 will hit the metal pad 11. Diffusion inside the sidewall and in the substrate 10 , but due to the arrangement of the isolation ring structure 13 , the material in the metal pad 11 will not appear on the side of the isolation ring structure 13 away from the through silicon via structure 12 , that is, it will not diffuse to the substrate 10 deep, thereby avoiding the situation that adjacent through silicon holes are connected due to the gradual diffusion of metal inside the substrate 10 during or even after the etching of the through silicon via structure 12, thereby improving the through silicon via structure 12 isolation performance. In traditional technology, deep hole etching with high aspect ratio usually intensifies the energy of the etching material, which inevitably bombards the underlying metal pad 11, thereby sputtering to the side walls of the hole and gradually diffusing the adjacent silicon. The through-hole isolation performance is reduced and there is a risk of conduction. Compared with the traditional technology, the semiconductor structure provided by the present disclosure prevents the metal pad 11 from sputtering out during the etching of the through-silicon via structure 12 through the arrangement of the isolation ring structure 13 The metal material diffuses into the interior of the substrate 10, thereby improving the isolation performance of the through silicon via structure 12, reducing the risk of interconnection between adjacent through silicon via structures 12, and improving the yield of semiconductor products.

As an example, the substrate may be constructed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 10 may have a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic Indium oxide (InAs) substrate, indium phosphide (InP) substrate or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, as another example, the substrate 10 may be a layered substrate including, for example, Si/SiGe, Si/SiC, silicon on insulator (SOI), or silicon germanium on insulator. Those skilled in the art can select the substrate type according to the type of transistors formed on the substrate 10, and therefore the type of the substrate 10 should not limit the scope of the present disclosure.

As an example, please continue to refer to FIG. 3 . The isolation ring structure 13 penetrates the substrate 10 along the thickness direction through the first surface 10 a and extends to the second surface 10 b to prevent the metal material in the metal pad 11 from appearing in the isolation ring structure 13 away from the silicon. The metal material on one side of the through-hole structure 12 , that is, the metal pad 11 will not diffuse deep into the substrate 10 , thereby avoiding the connection between adjacent through silicon holes due to the gradual diffusion of metal inside the substrate 10 .

As an example, please continue to refer to FIG. 3 . An isolation protective layer 14 is included between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 . The isolation protective layer 14 includes an insulating material. Specifically, the material of the isolation protective layer 14 may be silicon dioxide (SiO ₂ ).

As an example, the semiconductor structure further includes an annular barrier layer 15; the annular barrier layer 15 surrounds the through silicon via structure 12 and is located between the isolation protection layer 14 and the through silicon via structure 12. The annular barrier layer 15 penetrates the substrate 10 in the thickness direction through the first surface 10 a and extends to the metal pad 11 .

As an example, the minimum distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 is greater than or equal to 1 μm. For example, the minimum distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 may be 1 μm, 1.5 μm, 2 μm, or 3 μm, etc.

As an example, the minimum distance between the outer side walls of adjacent isolation ring structures 13 is greater than or equal to 1 μm. For example, the minimum distance between the outer side walls of adjacent isolation ring structures 13 may be 1 μm, 1.5 μm, 2 μm or 2.5 μm, etc.

As an example, the preset distance is 2μm-10μm. For example, the preset distance may be 2 μm, 3 μm, 6 μm, or 10 μm, etc.

As an example, please refer to FIG. 8 . In FIG. 8 , the material of the isolation ring structure 13 includes a first low dielectric constant material layer 131 , a metal barrier layer 132 and a second low dielectric constant material layer 133 , where the first The low dielectric constant material layer 131 is located in the substrate 10 and surrounds the through silicon via structure 12. The metal barrier layer 132 surrounds the first low dielectric constant material layer 131, and the second low dielectric constant material layer 133 surrounds the metal barrier layer. 132. The first low dielectric constant material layer 131 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), fluorocarbon (a-C:F), etc., and the metal barrier layer 132 may include tantalum ( Ta), tantalum nitride (TaN) and titanium nitride (Ti), the second low dielectric constant material layer 133 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC) And fluorocarbons (a-C:F), etc. For example, the material of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 may be carbon-doped silicon dioxide, and the material of the metal barrier layer 132 may be tantalum nitride. Inside the semiconductor device, parasitic capacitance inevitably exists between the filling material in the through silicon via structure 12 and the metal barrier layer 132. The parasitic capacitance not only affects the speed of the chip, but also poses a serious threat to the working reliability, and due to Reducing the dielectric constant value of the dielectric can reduce the capacitance of the capacitor. Therefore, when the metal barrier layer 132 is used as the isolation ring structure 13, a first low dielectric constant material layer 131 is formed on the inner and outer walls of the isolation ring structure 13. With the second low dielectric constant material layer 133, the parasitic capacitance between the through silicon via structure 12 and the isolation ring structure 13 can be effectively reduced, thereby improving the overall performance of the semiconductor product.

As an example, please continue to refer to FIG. 8 . The thickness of the metal barrier layer 132 may be less than the sum of the thicknesses of the first low-dielectric constant material layer 131 and the second low-dielectric constant material layer 133 to ensure the isolation ring structure 13 at the same time. Insulating properties and metal barrier properties.

As an example, please continue to refer to FIG. 8 . The thickness of the metal barrier layer 132 may be 1/3-2/3 of the sum of the thicknesses of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 . For example, the thickness of the metal barrier layer 132 may be 1/3, 0.5, 0.55 or 2/3 of the sum of the thicknesses of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133, and so on. The thickness of the metal barrier layer 132 cannot be too thin to prevent the sputtering and diffusion of etching appendages during the preparation of the through-silicon via structure from interfering with adjacent semiconductor structures or electronic components; the thickness of the metal barrier layer 132 should not be too thin. No It can be too thick to avoid the problem of increasing parasitic capacitance caused by relatively reducing the thickness of the first low dielectric constant material layer 131 or the second low dielectric constant material layer 133 .

As an example, please continue to refer to FIG. 3 and FIG. 8 . The material of the annular barrier layer 15 includes at least one of tantalum, tantalum nitride, and titanium nitride; the material of the isolation protective layer 14 includes an insulating material and/or a low dielectric constant. Material, specifically, the material of the isolation protective layer 14 may be silicon dioxide.

As an example, please refer to FIG. 4. FIG. 4 is a top view of the semiconductor structure in the above embodiment, that is, a cross-sectional view along the direction AA' in FIG. 3. The annular barrier layer 15, the isolation protection layer 14 and the isolation ring structure 13 are concentric. ring, and has the same center as the through silicon via structure 12. The annular barrier layer 15, the isolation protection layer 14, the isolation ring structure 13 and the through silicon via structure 12 all penetrate the substrate 10 along the thickness direction, where the preset distance is 2 μm-10 μm, and the minimum distance between the inner wall of the isolation ring structure 13 and the outer wall of the through silicon via structure 12 is greater than or equal to 1 μm. The above structure can avoid metal sputtering caused by etching the metal pad 11 from diffusing into the depth of the substrate 10 during the etching of the through silicon via structure 12, thereby causing the connection between the adjacent through silicon via structures 12 and improving the The isolation performance of the through silicon via structure 12.

As an example, please refer to Figure 5. An embodiment of the present disclosure also provides a method for preparing a semiconductor structure, including the following steps:

Step S10: Provide a substrate with opposing first and second surfaces, and form a metal pad on the side of the second surface facing away from the substrate;

Step S20: Form an isolation ring structure in the substrate, with a preset distance between the inner wall and the outer wall of the isolation ring structure;

Step S30: Form a through silicon via structure in the substrate within the isolation ring structure. The through silicon via structure penetrates the substrate along the thickness direction through the first surface and is in contact with the metal pad; the orthographic projection of the metal pad on the second surface covers the silicon The bottom surface of the through-hole structure.

In step S10 , please refer to step S10 in FIG. 3 and FIG. 5 , a substrate 10 having opposite first surfaces 10 a and second surfaces 10 b is provided, and a metal pad 11 is formed on the second surface 10 b.

As an example, step S10 may also include the following steps: thinning the substrate 10 to a preset thickness. The thinning method may include grinding, and the grinding may include different processing procedures such as rough grinding, fine grinding, and polishing. For example, the thickness of the substrate 10 after thinning is less than 100 μm. After the substrate 10 is thinned to a preset thickness, a rapid wet etching is performed on the surface of the substrate 10. The isotropy of the wet etching allows the stress on the substrate 10 to be eliminated; because the thinned substrate 10 There is a surface damage layer on the back, and its residual stress will cause the thinned epitaxial wafer to bend and easily break in subsequent processes, thus affecting the yield. Therefore, the back side of the substrate 10 can be polished after thinning. Specifically, the polishing process technology can use chemical mechanical polishing (CMP) technology.

In step S20 , please refer to step S20 in FIG. 3 and FIG. 5 , an isolation ring structure 13 is formed in the substrate 10 , and there is a preset distance between the inner side wall and the outer side wall of the isolation ring structure 13 . Since the material of the isolation ring structure 13 is selected to be a material that can block the metal in the metal pad, when the etching causes the etching accessory, that is, the metal material in the metal pad to splash when the through-silicon via structure 12 is subsequently formed, splashing can be avoided. The etching appendages diffuse into the side of the isolation ring structure 13 away from the through-silicon via structure 12 along the width direction, thereby preventing the adjacent through-silicon via structures 12 from being interconnected; and preventing the etching appendages from being sputtered and diffusing to the adjacent through-silicon via structures 12 Interference occurs in semiconductor structures or electronic components and improves the performance and reliability of semiconductor products.

In step S30 , please refer to step S30 in FIG. 3 and FIG. 5 , a through silicon via structure 12 is formed in the substrate 10 in the isolation ring structure 13 , and the through silicon via structure 12 penetrates the substrate along the thickness direction through the first surface 10 a. The bottom 10 is in contact with the metal pad 11; the orthographic projection of the metal pad 11 on the second surface 10b covers the bottom surface of the through silicon via structure 12. Since the isolation ring structure 13 is formed before the through-silicon via structure 12, during the process of forming the through-silicon via structure 12, when the etching of the through-silicon via structure by the high-energy etching material is about to end, the through-silicon via structure 12 is formed. The metal pad 11 in contact with the hole structure 12 is bombarded until the metal is sputtered. At this time, the metal is sputtered to the side wall and diffuses to the isolation ring structure 13 to stop. It will not diffuse into the interior of the substrate 10, that is, no adjacent silicon will appear. The phenomenon that the through-hole structure 12 is connected.

In the above embodiment, the metal pad 11 is formed on the side of the second surface 10b of the substrate 10 away from the substrate 10, and Before the through silicon via structure 12 is formed, the isolation ring structure 13 is formed first. The isolation ring structure 13 surrounds the through silicon via structure 12 that will be formed later. When the through silicon via structure 12 is formed in the substrate 10 , the substrate 10 needs to be High-energy etching is performed. When the etching is close to the upper surface of the metal pad 11, the metal pad 11 will inevitably be etched, causing the metal material in the metal pad 11 to be sputtered onto the side walls of the etching holes and gradually diffuse. , since the isolation ring structure 13 has been formed before etching the hole, the metal material sputtered on the side wall stops the diffusion movement when it diffuses and contacts the isolation ring structure 13, and will not appear when the isolation ring structure 13 moves away in the width direction. One side of the through-silicon via structure 12 prevents the sputtered metal material from diffusing deep into the substrate 10 and connecting with the adjacent through-silicon via structure 12 , thus avoiding the possibility of electrical connection between different through-silicon via structures 12 risk, improving the isolation performance of the through silicon via structure 12 and improving the yield of semiconductor products.

As an example, please refer to Figure 6. A first dielectric layer is formed between the metal pad and the second surface; the steps of forming the isolation ring structure in the substrate include:

Step S21: Form a second dielectric layer on the first surface of the substrate;

Step S22: Etch the second dielectric layer and the substrate to obtain an isolation ring gap, which exposes part of the first dielectric layer;

Step S23: Form a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer in the isolation ring gap to obtain an isolation ring structure.

In step S21 , please refer to step S21 in FIG. 8 and FIG. 6 , a second dielectric layer 17 is formed on the first surface 10 a of the substrate 10 . The second dielectric layer 17 can be formed using a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO).

In step S22, please refer to step S22 in FIG. 8 and FIG. 6. A dry etching process may be used to etch the second dielectric layer 17 and the substrate 10 to obtain an isolation ring gap. The isolation ring gap exposes part of the first medium. layer. The etching process may include, but is not limited to, dry etching process and/or wet etching process. The dry etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), high concentration plasma etching (HDP), and the like.

In step S23, please refer to step S23 of Figure 8 and Figure 6 to deposit an initial low dielectric constant material layer on the inner wall and bottom of the isolation ring gap. The deposition process may include physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor phase Any one or more of deposition (Chemical Vapor Deposition, CVD) and Atomic Layer Deposition (ALD) processes, etching and removing the portion of the initial low dielectric constant material layer located at the bottom of the isolation ring gap and exposing it The first dielectric layer 16 forms a first low dielectric constant material layer 131 surrounding the through silicon via structure 12 and a second low dielectric constant material layer 133 surrounding the first low dielectric constant material layer 131; and then the first low dielectric constant material layer 133 is formed around the first low dielectric constant material layer 131. A metal barrier layer 132 is formed in the gap between the dielectric constant material layer 131 and the second low dielectric constant material layer 133 . The process of forming the metal barrier layer 132 may include any one or more of CVD, PVD, and ALD processes.

As an example, please continue to refer to FIG. 8 , the isolation ring structure 13 includes a first low-k material layer 131 , a metal barrier layer 132 and a second low-k material layer 133 , where the first low-k material layer 131 is located in the substrate 10 and surrounds the through silicon via structure 12 , the metal barrier layer 132 surrounds the first low dielectric constant material layer 131 , and the second low dielectric constant material layer 133 surrounds the metal barrier layer 132 . When the metal barrier layer 132 is used as the isolation ring structure 13, forming the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 on the inner and outer walls of the isolation ring structure 13 can effectively reduce through silicon vias. The parasitic capacitance between the structure 12 and the isolation ring structure 13 can improve the overall performance of the semiconductor device.

As an example, please refer to Figure 7. The steps of forming a through silicon via structure in the substrate within the isolation ring structure include:

Step S31: Etch the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, which exposes part of the metal pad;

Step S32: Form an isolation protective layer on the side wall of the through hole;

Step S33: Deposit an annular barrier layer on the sidewall of the isolation protective layer; Step S34: Fill the through hole with a conductive material layer and perform planarization to obtain a through silicon hole structure.

In step S31, please refer to step S31 in FIG. 8 and FIG. 7 to etch the second dielectric layer 17 and the isolation ring structure. The substrate 10 in 13 obtains a through hole, which exposes part of the metal pad 11. Specifically, the etching process to obtain the through hole may use plasma etching technology.

As an example, before step S31 and after step S23, the following steps may also be included: spin-coating photoresist on the first surface 10b of the substrate 10, and forming pattern openings through a photolithography process; and removing the photoresist after step S31. glue.

In step S32, please refer to step S32 in FIG. 8 and FIG. 7 to form an isolation protective layer 14 on the side wall of the through hole. The isolation protective layer 14 can be formed using a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO), a low pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition, LPCVD) or a sub-atmospheric pressure chemical vapor deposition method (Selected Area Chemical Vapor Deposition, SACVD).

In step S33 , please refer to step S33 in FIG. 8 and FIG. 7 , an annular barrier layer 15 is deposited on the sidewall of the isolation protection layer 14 . The annular barrier layer 15 may be formed using a physical vapor deposition process (Physical Vapor Deposition, PVD). Generally, the electroplating process is used to fill the through holes in the TSV process. For example, the electroplating copper process is used to fill the through holes. However, the diffusion speed of copper in the isolation protective layer is very fast, which can easily cause severe degradation of its dielectric properties. Furthermore, copper has a strong trapping effect on semiconductor carriers. When copper diffuses into the semiconductor body material, it will seriously affect the electrical characteristics of the semiconductor device, and the adhesion strength between copper and the isolation protective layer 14 is poor. Therefore, depositing an annular barrier layer 15 between the through silicon via structure 12 and the isolation protection layer 14 can prevent the diffusion of the conductive material layer filled in the subsequently formed through silicon via structure 12 and improve the performance of the semiconductor device. .

In step S34 , please refer to step S34 in FIG. 8 and FIG. 7 , a conductive material layer is filled in the through hole and is planarized to obtain the through silicon via structure 12 .

As an example, the method of filling the conductive material layer can use electroplating. In step S34, the step of filling the conductive layer material in the through hole and planarizing it can include: first, physically exhausting the air in the cavity, for example, using ultrasonic waves. , spraying, vacuuming, etc. to allow the electroplating liquid to enter the cavity smoothly; secondly, the electroplating copper process is used to fill the conductive material layer. The process of the electroplating copper process includes oil removal, micro-etching, pickling and plating conductive materials, among which, Degreasing includes removing oil stains and fingerprints on the board surface, micro-etching includes cleaning and roughening the copper surface, and removing oxides and debris from the board surface, and pickling includes removing the oxide film on the surface of the metal pad 11 and activating the surface of the metal pad 11 , and can reduce impurities. Copper plating includes using a DC electroplating method to deposit a conductive material layer on the surface of the metal pad 11 and in the hole; after electroplating, due to excessive internal stress accumulated in the electroplated conductive material layer, many problems will occur. To prevent protrusion defects, a low-temperature annealing process can be used to suppress the occurrence of protrusion defects; in addition, after the low-temperature annealing process, the through silicon via structure 12 can be planarized. The planarization process can use CMP process, dry etching process and planarization process. Any one or more of the push processes.

It should be understood that although the various steps in the flowcharts of FIGS. 5 to 7 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, although at least some of the steps in Figures 5-7 may include multiple steps or stages, these steps or stages are not necessarily executed at the same time, but may be executed at different times. These steps or stages The order of execution is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.

As an example, the minimum distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 is greater than or equal to 1 μm, for example, the distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 The minimum distance can be 1μm, 1.5μm, 2μm or 3μm etc.

As an example, the minimum distance between the outer side walls of adjacent isolation ring structures 13 is greater than or equal to 1 μm. For example, the minimum distance between the outer side walls of adjacent isolation ring structures 13 may be 1 μm, 1.5 μm, 2 μm, or 2.5 μm, etc. wait.

As an example, the preset distance is 2 μm-10 μm. For example, the preset distance may be 2 μm, 3 μm, 6 μm, or 10 μm, etc.

As an example, the above method of forming a semiconductor structure can be combined with an existing semiconductor element forming process. For example, a semiconductor element (not shown) can be formed on the substrate 10 first, such as a metal oxide semiconductor transistor (MOS transistor). ) or dynamic random access memory (Dynamic Random Access Memory After accessing Memory (DRAM), the isolation ring structure 13 and the through silicon via structure 12 are formed using the steps of the present disclosure.

In the semiconductor structure and its preparation method described in the above embodiments, first, a substrate is provided, and a metal pad is formed on the side of the second surface of the substrate facing away from the substrate; then, an isolation ring structure is formed in the substrate , there is a preset distance between the inner wall and the outer wall of the isolation ring structure; then, a through silicon via structure is formed in the substrate within the isolation ring structure, and the through silicon via structure penetrates the substrate along the thickness direction through the first surface and is connected with Metal pad contact connection. In the process of etching the through-silicon via structure, since the metal pad covers the bottom surface of the through-silicon via structure in the orthographic projection of the second surface, when the etching process proceeds to a position close to the metal pad, the metal pad will be etched, and then the metal pad will be etched. The metal material in the metal pad is sputtered into the sidewall of the through-silicon via structure. Since the isolation ring structure is formed in the semiconductor structure of the present disclosure before the through-silicon via structure is formed, the metal material sputtered into the sidewall is isolated. The ring structure blocks the side of the isolation ring structure that is close to the through-silicon via structure along the width direction, and does not diffuse into the depth of the substrate, thereby preventing adjacent through-silicon via structures from being connected to improve through-silicon vias. The isolation performance of the structure and improve the reliability of semiconductor products.

Please note that the above-described embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the disclosed patent. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed shall be determined by the appended claims.

Claims

A semiconductor structure including:

A substrate (10) having opposite first surfaces (10a) and second surfaces (10b);

A metal pad (11) located on the side of the second surface (10b) facing away from the substrate (10);

A through silicon via structure (12) penetrates the substrate (10) along the thickness direction through the first surface (10a) and is in contact with the metal pad (11); the metal pad (11) is in the The orthographic projection of the second surface (10b) covers the bottom surface of the through silicon via structure (12);

An isolation ring structure (13) is formed in the substrate (10) and surrounds the through silicon via structure (12), wherein the inner wall and outer wall of the isolation ring structure (13) have a preset distance .
The semiconductor structure according to claim 1, wherein the isolation ring structure (13) penetrates the substrate (10) along the thickness direction via the first surface (10a) and extends to the second surface (10b).
The semiconductor structure according to claim 1 or 2, wherein an isolation protection layer (14) is included between the inner side wall of the isolation ring structure (13) and the outer side wall of the through silicon via structure (12).
The semiconductor structure of claim 3, wherein the isolation protective layer (14) includes an insulating material.
The semiconductor structure according to claim 3 or 4, further comprising:

An annular barrier layer (15) surrounds the through silicon via structure (12) and is located between the isolation protection layer (14) and the through silicon via structure (12).
The semiconductor structure according to claim 5, wherein the annular barrier layer (15) penetrates the substrate (10) in a thickness direction through the first surface (10a) and extends to the metal pad (11 ).
The semiconductor structure according to any one of claims 3 to 6, wherein the minimum distance between the inner side wall of the isolation ring structure (13) and the outer side wall of the through silicon via structure (12) is greater than or equal to 1 μm. .
The semiconductor structure according to any one of claims 1 to 7, wherein the minimum distance between the outer side walls of adjacent isolation ring structures (13) is greater than or equal to 1 μm.
The semiconductor structure according to any one of claims 1-8, wherein the preset distance is 2 μm-10 μm.
The semiconductor structure according to any one of claims 1 to 9, wherein the isolation ring structure (13) includes a first low dielectric constant material layer (131), a metal barrier layer (132) and a second low dielectric constant material layer (131). Electric constant material layer (133), wherein the first low dielectric constant material layer (131) surrounds the through silicon via structure (12), and the metal barrier layer (132) surrounds the first low dielectric constant material layer (133). Electric constant material layer (131), the second low dielectric constant material layer (133) surrounds the metal barrier layer (132).
The semiconductor structure according to claim 10, wherein the metal barrier layer (132) has a thickness smaller than the first low dielectric constant material layer (131) and the second low dielectric constant material layer (133). ) thickness.
The semiconductor structure according to claim 10 or 11, wherein the thickness of the metal barrier layer (132) is the thickness of the first low dielectric constant material layer (131), the second low dielectric constant material layer (133) thickness and 1/3-2/3.
The semiconductor structure according to any one of claims 10 to 12, wherein the material of the first low dielectric constant material layer (131) is selected from the group consisting of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, fluorocarbons and its combination.
The semiconductor structure according to any one of claims 10 to 13, wherein the material of the metal barrier layer (132) is selected from the group consisting of tantalum, tantalum nitride, titanium nitride and combinations thereof.
The semiconductor structure according to any one of claims 10 to 14, wherein the material of the second low dielectric constant material layer (133) is selected from the group consisting of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, fluorocarbons and its combination.
The semiconductor structure according to any one of claims 5 to 15, wherein the material of the annular barrier layer (15) includes at least one of tantalum, tantalum nitride and titanium nitride.
A method for preparing a semiconductor structure, including:

Provide a substrate (10) with opposing first surfaces (10a) and second surfaces (10b), and form a metal pad (11) on a side of the second surface (10b) away from the substrate (10);

An isolation ring structure (13) is formed in the substrate (10), and there is a preset distance between the inner wall and the outer wall of the isolation ring structure (13);

A through silicon via structure (12) is formed in the substrate (10) in the isolation ring structure (13), and the through silicon via structure (12) penetrates through the first surface (10a) in the thickness direction The substrate (10) is in contact with the metal pad (11); the orthographic projection of the metal pad (11) on the second surface (10b) covers the bottom surface of the through silicon via structure (12) .
The preparation method according to claim 17, wherein a first dielectric layer (16) is formed between the metal pad (11) and the second surface (10b); the isolation ring structure (13) includes a A low dielectric constant material layer (131), a metal barrier layer (132) and a second low dielectric constant material layer (133), the first low dielectric constant material layer (131) surrounding the through silicon via Structure (12), the metal barrier layer (132) surrounds the first low dielectric constant material layer (131), and the second low dielectric constant material layer (133) surrounds the metal barrier layer (131). 132); The step of forming an isolation ring structure (13) in the substrate (10) includes:

Forming a second dielectric layer (17) on the first surface (10a) of the substrate (10);

Etch the second dielectric layer (17) and the substrate (10) to obtain an isolation ring gap, which exposes part of the first dielectric layer (16);

The first low dielectric constant material layer (131), the metal barrier layer (132) and the second low dielectric constant material layer (133) are formed in the isolation ring gap to obtain the Isolating ring structure (13).
The preparation method according to claim 18, wherein the step of forming a through silicon via structure (12) in the substrate (10) within the isolation ring structure (13) includes:

Etch the second dielectric layer (17) and the substrate (10) in the isolation ring structure (13) to obtain a through hole, which exposes part of the metal pad (11);

Form an isolation protective layer (14) on the side wall of the through hole;

Deposit an annular barrier layer (15) on the sidewall of the isolation protective layer (14);

The through hole is filled with a conductive material layer and planarized to obtain the through silicon hole structure (12).
The preparation method according to any one of claims 17-19, further comprising at least one of the following features:

The minimum distance between the inner wall of the isolation ring structure (13) and the outer wall of the through silicon via structure (12) is greater than or equal to 1 μm;

The minimum distance between the outer side walls of adjacent isolation ring structures (13) is greater than or equal to 1 μm;

The preset distance is 2 μm-10 μm.