WO2024021365A1 - Memory unit, array circuit structure, and data processing method - Google Patents

Abstract

Provided are a memory unit, an array circuit structure, and a data processing method. The memory unit (100) comprises at least one resistive switching device and at least two switch elements. The at least one resistive switching device comprises a first resistive switching device (10), and the at least two switch elements comprise a first switch element (20) and a second switch element (30). A first end of the first resistive switching device (10) is connected to a first bit line end. A first pole of the first switch element (20) is connected to a second end of the first resistive switching device (10), a second pole of the first switch element (20) is connected to a first pole of the second switch element (30), and a control pole of the first switch element (20) is connected to a first word line end. A second pole of the second switch element (30) is connected to a source line end, and a control pole of the second switch element (30) is connected to a selection control end. The memory unit can achieve independent control of the at least one resistive device, and when a plurality of the memory units are arranged in an array circuit for parallel computing, the array circuit structure can have high control flexibility and low power consumption and computational results can be highly accurate.

Description

Memory unit, array circuit structure and data processing method

This application claims the priority of Chinese Patent Application No. 202210876166.4 submitted on July 25, 2022. The disclosure of the above Chinese patent application is hereby cited in its entirety for all purposes as part of this application.

Technical field

Embodiments of the present disclosure relate to a memory unit, an array circuit structure, and a data processing method.

Background technique

In recent years, using physical laws to implement analog calculations based on memristor arrays has become an emerging research hotspot. Memristor is a new type of micro-nano electronic device whose resistance state can be adjusted by external voltage excitation. Memristor-based neuromorphic computing breaks through the von Neumann architecture of traditional computing devices. Computation and storage are completed in the same place, reducing data transfer time. Computation requires higher energy efficiency, lower power consumption, and smaller area. smaller.

Contents of the invention

Embodiments of the present disclosure provide a memory unit, an array circuit structure, and a data processing method.

Embodiments of the present disclosure provide a memory unit, including: at least one resistive switching device and at least two switching elements, each switching element includes a first pole, a second pole and a control pole, wherein the at least one resistive switching device Comprising a first resistive switching device, the at least two switching elements include a first switching element and a second switching element, the first end of the first resistive switching device is connected to the first line terminal; the first switching element The first pole of the first switching element is connected to the second end of the first resistive switching element, the second pole of the first switching element is connected to the first pole of the second switching element, and the control pole of the first switching element It is connected to the first word line terminal; the second pole of the second switching element is connected to the source line terminal, and the control pole of the second switching element is connected to the selection control terminal.

For example, in some embodiments of the present disclosure, the at least one resistive switching device further includes a second resistive switching device, the at least two switching elements further include a third switching element and a fourth switching element, and the second resistive switching element The first end of the resistive switching device is connected to the second bit line end; the first pole of the third switching element is connected to the second end of the second resistive switching device, and the second pole of the third switching element is connected to the second bit line end. The first pole of the fourth switching element is connected, the control pole of the third switching element is connected to the second word line terminal; the second pole of the fourth switching element is connected to the source line terminal, and the fourth switching element is connected to the source line terminal. The control pole of the switching element is connected to the selection control terminal.

For example, in some embodiments of the present disclosure, the at least one resistive switching device further includes a third resistive switching device, the at least two switching elements further include a fifth switching element, and the first switching element of the third resistive switching device The terminal is connected to the second bit line terminal; the first terminal of the fifth switching element is connected to the second terminal of the third resistive switching element, and the second terminal of the fifth switching element is connected to the source line terminal. , the control electrode of the fifth switching element is connected to the second word line terminal.

For example, in some embodiments of the present disclosure, the resistive switching device is any one of resistive switching memory (RRAM), Flash, SRAM, DRAM, PCRAM, MRAM, and FeRAM; and the switching element is a transistor.

Embodiments of the present disclosure provide an array circuit structure, including: a plurality of memory cells as described in any of the above arrays arranged in M rows and N columns; a plurality of signal control lines, including: M first bit lines , M first word lines, N selection control lines and N source lines, M and N are positive integers; the M first bit lines and the M first word lines are respectively in line with the M rows. One-to-one correspondence, the N selection control lines and the N source lines correspond to the N columns respectively, and each first bit line corresponds to the first bit in a row of memory cells corresponding to the first bit line. Line terminals are connected, each first word line is connected to a first word line terminal in a row of memory cells corresponding to the first word line, and each selection control line is connected to a selection in a column of memory cells corresponding to the selection control line. The control end is connected, and each source line is connected to a source line end in a column of memory cells corresponding to the source line.

For example, in some embodiments of the present disclosure, in the case where the memory unit further includes the second resistive switching device, the third switching element, and the fourth switching element, the second resistive switching device The first end is connected to the second bit line end; the control electrode of the third switching element is connected to the second word line end; the plurality of signal control lines also include M second bit lines and M second word lines. lines, the M second bit lines and the M second word lines correspond to the M rows respectively, and each second bit line corresponds to the second bit line in a row of memory cells corresponding to the second bit line. Two bit line terminals are connected, and each second word line is connected to a second word line terminal in a row of memory cells corresponding to the second word line.

For example, in some embodiments of the present disclosure, in the case where the array circuit structure further includes the third resistive switching device and the fifth switching element, the first terminal of the third resistive switching device is connected to the fifth switching element. The two bit line terminals are connected; the control electrode of the fifth switching element is connected to the second word line terminal; the plurality of signal control lines also include M second bit lines and M second word lines, the M The second bit line and the M second word lines correspond to the M rows respectively, and each second bit line is connected to the second bit line terminal in a row of memory cells corresponding to the second bit line, Each second word line is respectively connected to a second word line end in a row of memory cells corresponding to the second word line.

An embodiment of the present disclosure also provides a data processing method, including: selecting at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines; The at least one memory unit performs a data processing operation to perform corresponding data processing using the at least one memory unit.

For example, in some embodiments of the present disclosure, each of the plurality of memory cells is turned on upon receiving a turn-on signal applied by a corresponding first word line and a turn-on signal applied by a corresponding selection control line, Selecting the at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines includes: targeting any memory unit in the at least one memory unit. : Determine the target row and target column in which any of the memory cells are located; apply a turn-on signal to the target row through the first word line corresponding to the target row; apply a turn-on signal to the target through the selection control line corresponding to the target column. The column applies an enable signal to select any of the memory cells.

For example, in some embodiments of the present disclosure, in the case where the plurality of signal control lines also include M second word lines, each of the plurality of memory cells receives a corresponding first word line. The array circuit is selected by at least the M first word lines and the N selection control lines. The at least one memory unit in the structure includes: for any memory unit in the at least one memory unit: determining the target row and target column where the any memory unit is located; passing the first corresponding to the target row The word line applies a turn-on signal to the target row; applies a turn-on signal to the target column through a selection control line corresponding to the target column; applies a turn-on signal to the target row through a second word line corresponding to the target row, to select any of the memory cells.

For example, in some embodiments of the present disclosure, each of the plurality of memory cells is turned on when receiving a turn-on signal applied by a corresponding first word line and a turn-on signal applied by a corresponding selection control line, so The at least one memory unit is arranged in an array form of W rows and U columns, W is a positive integer and less than or equal to M, and U is a positive integer and less than or equal to N. The at least one memory unit is arranged through at least the M first word lines, the N Selecting the control line to select the at least one memory cell in the array circuit structure includes: applying turn-on to the W rows respectively through W first word lines corresponding to the W rows of memory cells arranged in the array form. signals, respectively applying turn-on signals to the U columns through U selection control lines corresponding to the U column memory cells arranged in the array form, so as to select the at least one memory cell.

For example, in some embodiments of the present disclosure, in the case where the plurality of signal control lines also include M second word lines, each of the plurality of memory cells receives the corresponding first word line and The at least one memory cell is turned on when the turn-on signal applied by the second word line and the turn-on signal applied by the corresponding selection control line are arranged in an array of W rows and U columns, where W is a positive integer and is less than or equal to M, U is a positive integer and less than or equal to N. Selecting the at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines includes: by arranging the The W first word lines corresponding to the W rows of memory cells in the array form apply turn-on signals to the W rows respectively; the U selection control lines corresponding to the U columns of memory cells arranged in the array form apply to the W rows respectively. The U column applies a turn-on signal; the W second word lines corresponding to the W rows of memory cells arranged in the array form apply turn-on signals to the W rows respectively to select the at least one memory cell.

For example, in some embodiments of the present disclosure, performing a data processing operation on the at least one memory unit to perform corresponding data processing using the at least one memory unit includes: performing a data processing operation on the selected at least one memory unit. The unit performs a set operation or a reset operation; wherein the set operation includes causing the resistive switching device to change from a first resistance state to a second resistance state, and the reset operation includes making the resistive switching device change from the first resistance state to a second resistance state. The two resistance states change into the first resistance state, and the resistance value of the resistive switching device in the first resistance state is greater than the resistance value in the second resistance state.

For example, in some embodiments of the present disclosure, performing a data processing operation on the at least one memory unit to perform corresponding data processing using the at least one memory unit further includes: performing a data processing operation on the selected at least one memory unit. The memory unit performs a read operation; wherein the read operation includes: applying a read voltage to a bit line corresponding to the at least one memory unit, and reading a resistive switching device generated by the resistive switching device in the memory unit corresponding to the resistive voltage. The reading current that changes the resistance of the device.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure. .

Figure 1A is a schematic diagram of a 1T1R memristor array.

Figure 1B is a schematic diagram of another 1T1R memristor array.

Figure 1C is a schematic diagram of a 2T2R memristor array.

Figure 1D is a schematic diagram of another 2T2R memristor array.

FIG. 2 is a schematic diagram of a memory unit provided by at least one embodiment of the present disclosure.

FIG. 3 is a schematic diagram of another memory unit provided by at least one embodiment of the present disclosure.

FIG. 4 is a schematic diagram of yet another memory unit provided by at least one embodiment of the present disclosure.

FIG. 5 is a schematic diagram of an array circuit structure provided by at least one embodiment of the present disclosure.

FIG. 6 is a schematic diagram of an array circuit structure corresponding to the memory cell shown in FIG. 2 .

FIG. 7 is a schematic diagram of another array circuit structure provided by at least one embodiment of the present disclosure.

FIG. 8A is a schematic diagram of an array circuit structure corresponding to the memory cell shown in FIG. 3 .

FIG. 8B is a schematic diagram of an array circuit structure corresponding to the memory cell shown in FIG. 4 .

Figure 9 is a schematic diagram of a data processing method provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words such as "includes" or "includes" mean that the elements or things listed before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

With the advancement of science and technology and the rapid development of information technology, the computing architecture based on memristor arrays is considered to be a new generation of data processing with great potential due to its advantages of integrated storage and calculation, low energy consumption, large-scale integration and parallel operation. device.

Memristor (such as resistive memory, phase change memory, conductive bridge memory, etc.) is a new type of micro-nano electronic device that can adjust its conductance state by applying external excitation. The working mechanism of memristors has certain similarities with synapses and neurons in the human brain, so they have broad application prospects in neuromorphic computing. According to Kirchhoff's current law and Ohm's law, an array composed of such devices can complete multiplication and accumulation calculations in parallel, and both storage and calculation occur in each device of the array. Based on this computing architecture, integrated storage and computing can be realized that does not require large amounts of data movement.

For example, a memristor array may be composed of multiple memristor units, and the multiple memristor units form an array with M rows and N columns, where M and N are both positive integers. Each memristor cell includes a switching element and one or more memristors.

For example, when operating a memristor unit in a memristor array, for example, when performing a read operation, you first need to turn on the transistor in the selected memristor unit, that is, you can use the selected memristor unit corresponding to The word line applies a turn-on voltage to the gate of the transistor; in turn, it provides an input signal (for example, a DC voltage) to the resistance of the selected memristor cell. The above-mentioned memristor array can complete the product-accumulation calculation in parallel, and select the memristor cell. The calculation result is obtained by determining the signal output end of the source line corresponding to the memristor unit.

Figure 1A is a schematic diagram of a 1T1R memristor array.

For example, as shown in FIG. 1A , the memristor array includes memristor units arranged in M rows and N columns, such as the memristor unit 101 , the memristor unit 102 , and the memristor unit shown in FIG. 1A . Unit 103, memristor unit 104. For example, the structure of each memristor unit is 1T1R, that is, it includes one memristor R1 and one switching element M1.

In addition, the memristor array also includes N word lines, N source lines, and M bit lines. For example, the word lines and source lines are set parallel at this time.

In Figure 1A, WL1, WL2...WLN respectively represent the word lines of the first column, the second column...the Nth column, and the control electrode of the switching element M1 (such as the gate of the transistor) in the memristor unit circuit of each column. pole) and connected to the word line corresponding to the column; BL1, BL2...BLM respectively represent the bit lines of the first row, the second row...the Mth row, the memristor in each row of memristor unit circuit and the row The corresponding bit line connections; SL1, SL2...SLN respectively represent the source lines of the first column, the second column...the Mth column. The source of the switching element M1 in the memristor unit circuit of each column corresponds to the column. source line connection.

It can be seen from the memristor array structure shown in Figure 1A that the on-state of the switching element M1 of the memristor unit in the same column is controlled by the same word line, that is, applying conduction to a word line in the memristor array. When the voltage is turned on, all the memristor cells in the column where the word line is located will be turned on. Therefore, when it is necessary to operate the selected memristor cell in the memristor array, the memristor array is difficult to Achieve flexible control.

Specifically, for example, as shown in FIG. 1A , the selected memristor units may be located in different rows and columns of the memristor array respectively. Memristor units 101 and memristor units 102 in different rows and columns in the device array. When operating the memristor unit 101 and the memristor unit 102, it is necessary to apply a turn-on voltage to the word line WL1 and the word line WL2 respectively, and to the corresponding bit line BL1 of the memristor unit 101 and the corresponding bit line BL1 of the memristor unit 102. Bit line BL2 provides the input signal. As a result, the N memristor units in the first column and the N memristor units in the second column of the memristor array are all turned on. Therefore, the memristor array structure shown in Figure 1A is difficult to achieve individual control. Randomly selecting memristor units for calculation has poor flexibility when performing array calculations, and the array calculation overhead is large. However, when using the memristor array for parallel computing, the voltage in the source line of the memristor unit participating in the calculation usually needs to be set within a small error range, so that the voltage in the source line is consistent with the voltage in the bit line. The difference in voltage can remain relatively constant, making the calculation results highly accurate. At the same time, the voltage drop problem (IR drop) on the bit line and source line makes it difficult to keep the read voltage of the memristor cells involved in the calculation consistent in the array, especially for advanced processes (such as below the 28nm node). Therefore, the results of parallel computation of this memristor array are greatly affected by voltage errors in the source lines (such as clamping errors and voltage drops on the bit lines and source lines, etc.).

Figure 1B is a schematic diagram of another 1T1R memristor array.

For example, as shown in FIG. 1B , the memristor array includes memristor units arranged in an array of M rows and N columns, such as the memristor unit 105 shown in FIG. 1B . Each memristor unit is a 1T1R structure, including a memristor R1 and a switching element M1.

In addition, the memristor array also includes M word lines, N source lines, and M bit lines. For example, word lines and bit lines are arranged in parallel at this time.

In Figure 1B, WL1, WL2...WLM respectively represent the word lines of the first row, the second row...the Mth row, and the control electrode of the switching element M1 (such as the gate of the transistor) in the memristor unit circuit of each row. pole) and connected to the corresponding word line of the row; BL1, BL2...BLM respectively represent the bit lines of the first row, the second row...the Mth row, the memristors in each row of memristor unit circuits and the row The corresponding bit line connections; SL1, SL2...SLN respectively represent the source lines of the first column, the second column...the Mth column. The source of the switching element M1 in the memristor unit circuit of each column corresponds to the column. source line connection.

It can be seen from the memristor array structure shown in Figure 1B that the on-state of the switching element M1 of the memristor unit in the same row is controlled by the same word line, that is, applying conduction to a word line in the memristor array. When the voltage is applied, all memristor cells in the row of the word line will be turned on. For example, when any one memristor unit in the memristor array is used for calculation, for example, the selected memristor unit is the memristor unit 105 located in the second row and the first column. The turn-on signal can be applied to the memristor unit 105 through the word line WL1, and the input signal can be provided to the memristor unit 105 through the bit line BL2, and the output signal after the memristor unit 105 completes the calculation is obtained from the source line SL1. At this time, all the memristor cells located in the same row as the memristor 105 will perform calculations at the same time, and there will be output signals in the source lines of each column. Therefore, it is impossible to make only the selected memristor cells in the memristor array. The calculation is performed on the source line corresponding to the resistor unit.

For example, compared to the memristor unit in Figure 1A, the memristor array in Figure 1B can be added to the array through the word line terminals (for example, supporting one bit of data input at a time) when computing in parallel. Therefore, the signal error at the source line end has less impact on the calculation results, and the calculation accuracy is higher. For example, the memristor array in Figure 1B has less voltage drop (IR drop) on the bit lines and source lines. However, due to the limitations of the array structure, when any memristor unit is selected for calculation, all memristor units located in the same row as the memristor unit will participate in the calculation. Therefore, when it is necessary to calculate only the memristor unit When the memristor units in selected columns (rather than all columns) in the array perform parallel calculations, the memristor array shown in Figure 1B is difficult to achieve flexible control, resulting in high computing overhead of the array and loss of power of the array. The cost is high.

Figure 1C is a schematic diagram of a 2T2R memristor array; Figure 1D is a schematic diagram of another 2T2R memristor array.

Correspondingly, corresponding to the memristor array in Figure 1A, in the 2T2R memristor array shown in Figure 1C, negative weights can be implemented when a turn-on voltage is applied to a word line in the memristor array. , all memristor cells in the column where the word line is located will be turned on. Therefore, the memristor array structure shown in Figure 1C is also difficult to individually control randomly selected memristor units for calculation. Its array calculation flexibility is also poor, and the array calculation overhead is high and the power consumption is large; And the results of the parallel calculation of the memristor array will also be affected to a large extent by the voltage error at the source line end.

Correspondingly, corresponding to the memristor array in Figure 1B, in a 2T2R memristor array shown in Figure 1D, the signal error at the source line end has a small impact on the calculation results, and negative weights can be achieved. However, when a turn-on voltage is applied to a word line in a memristor array, all memristor cells in the row of that word line are turned on. Therefore, when calculating a part of the memristor units in the memristor array, it is difficult to individually control the randomly selected memristor units to calculate the memristor, resulting in poor flexibility of the array and relatively high computational overhead. High; and when calculating for any memristor unit in the memristor array, there will be output signals on the source lines in all columns, and the power consumption of the array will be large.

Based on this, at least one embodiment of the present disclosure provides a memory unit including at least one resistive switching device and at least two switching elements. Each switching element includes a first pole, a second pole and a control pole, at least one resistive switching device includes a first resistive switching device, at least two switching elements include a first switching element and a second switching element, and the first resistive switching device The first terminal is connected to the first terminal; the first pole of the first switching element is connected to the second terminal of the first resistive switching element; the second pole of the first switching element is connected to the first pole of the second switching element; The control electrode of the first switching element is connected to the first word line terminal; the second electrode of the second switching element is connected to the source line terminal; the control electrode of the second switching element is connected to the selection control terminal.

The memory unit of at least one embodiment of the present disclosure can realize independent control of the memristor unit by setting at least two switching elements. The memory unit has the advantages of simple structure, low power consumption, high calculation accuracy, and easy control.

In some embodiments, when multiple memory units are arranged in an array circuit for parallel computing, the array circuit structure can have higher control flexibility, reduce the computing overhead and power consumption overhead of the memristor array, and make the memristor array more flexible. The resistor array can be used in low-power scenarios, such as low-power edge intelligence scenarios. At the same time, the memristor array can apply a voltage signal through at least one word line terminal (for example, the first word line terminal) during parallel calculation, thereby reducing the impact of the signal error at the source line terminal on the calculation results and making the calculation accurate. The degree is higher. This memory unit supports the realization of integrated storage and computing technology with high array configuration freedom and high calculation accuracy, which is beneficial to improving the operating performance of the array circuit. At least one embodiment of the present disclosure also provides an array circuit structure and a data processing method. The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

FIG. 2 is a schematic diagram of a memory unit provided by at least one embodiment of the present disclosure.

As shown in FIG. 2 , the memory unit 100 includes at least one resistive switching device and at least two switching elements. Each switching element includes a first pole, a second pole and a control pole.

For example, as shown in Figure 2, at least one resistive switching device includes a first resistive switching device 10, at least two switching elements include a first switching element 20 and a second switching element 30, and the first terminal of the first resistive switching device 10 is connected to The first line terminal BLP is connected; the first pole of the first switching element 20 is connected to the second end of the first resistive switching device 10, and the second pole of the first switching element 20 is connected to the first pole of the second switching element 30. , the control electrode of the first switching element 20 is connected to the first word line terminal WLVP; the second electrode of the second switching element 30 is connected to the source line terminal SL, and the control electrode of the second switching element 30 is connected to the selection control terminal WLP.

For example, as shown in Figure 2, the first resistive switching device 10, the first switching element 20 and the second switching element 30 are connected in series, and the first switching element 20 and the second switching element 30 respectively have independent control terminals. The on or off states are independent of each other. For example, the first word line terminal WLVP can apply a turn-on signal to the control electrode of the first switching element 20 to turn on the first switching element 20 ; the selection control terminal WLP can apply a turn-on signal to the control electrode of the second switching element 30 , causing the first switching element 30 to be turned on. That is to say, for the memory unit 100, the memory unit 100 is turned on when the first word line terminal WLVP and the selection control terminal WLP apply the turn-on signal at the same time. At this time, a formation is formed between the first bit line terminal BLP and the source line terminal SL. A path can implement data processing operations on the memory unit 100, such as set operations, reset operations, etc. This enables the memory unit 100 to be independently controlled, reducing the cost of the entire computing circuit and improving the control flexibility of the memory unit.

For example, as shown in FIG. 2 , the first resistive switching device 10 can be a resistive switching memory (RRAM, also known as a memristor), and the first switching element 20 and the second switching element 30 can be transistors. Of course, the first resistive switching device 10 can also be a resistive switching memory (RRAM), a flash memory (Flash), a static random access memory (SRAM), a dynamic random access memory (DRAM), a phase change random access memory (PCRAM), Any one of magnetic random access memory (MRAM) and ferroelectric random access memory (FeRAM) can realize resistance change control. The switching element can also be implemented as other structures that can control the switching element to be turned on or off. This invention The disclosure places no restrictions on the specific structures of the resistive switching device and the switching element.

In addition, it should be noted that when the switching element is implemented as a transistor, the present disclosure does not specifically limit the type of the transistor. For example, the first switching element 20 and the second switching element 30 can use the same type of transistors, such as N-type transistors or P-type transistors, or different types of transistors, such as one using an N-type transistor and the other using a P-type transistor. The transistors, connection relationships and control signals can be adjusted accordingly. Moreover, the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin film transistors are used as examples for explanation. The source and drain of the transistor used here can be symmetrical in structure, so there can be no structural difference between the source and drain. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate electrode, one of the poles is directly described as the first pole and the other pole is the second pole.

Detailed description will be given below taking an example in which the first switching element 20 and the second switching element 30 adopt N-type transistors.

For example, as shown in FIG. 2 , the gate electrode of the first switching element 20 serves as a control electrode and is connected to the first word line terminal WLVP; the gate electrode of the second switching element 30 serves as a control electrode and is connected to the selection control terminal WLP. The first electrodes of the first switching element 20 and the second switching element 30 may be drain electrodes, and the second electrodes of the first switching element 20 and the second switching element 30 may be source electrodes. For example, the source of the second switching element 30 is configured to be connected to the source line terminal SL. For example, the second switching element 30 can receive the reset voltage through the source line terminal SL; the drain of the second switching element 30 and the first switching element 20 The source of , for example, the first resistive switching device 10 can receive the setting voltage through the first bit line terminal BLP.

For example, as shown in Figure 2, the memristor array can apply a voltage signal through at least one word line terminal during parallel calculation, thereby reducing the impact of signal errors at the source line terminal on the calculation results. For example, in some examples of the present disclosure, when the data to be input to the memory unit 100 is 0, for a common memristor unit, the voltage in the bit line terminal BL needs to be set to the same voltage as the source line terminal SL, Then get the output value. During this process, when the voltage at the source line terminal SL fluctuates and causes errors, it will directly affect the accuracy of the output value. For the memory cell 100 as shown in FIG. 2 , for example, a voltage that can turn off the first switching element 20 can be input to the first word line terminal WLVP, so that no current flows in the first resistive switching device 10 . This results in an output value (i.e. 0). Therefore, the calculation result of the memory unit 100 can be less affected by the voltage error of the source line terminal SL, and the calculation result has higher accuracy. For example, the memristor array may be less affected by voltage drops (IR drops) on the bit and source lines.

Therefore, the memory unit 100 shown in FIG. 2 can realize independent control of the dual switches of the resistive switching device, and has the advantages of simple structure, low power consumption, small area, and easy control. At the same time, when multiple memory units 100 are arranged in an array circuit for parallel computing, each memory unit 100 can be independently controlled, so that the array circuit structure has higher control flexibility, which is beneficial to improving the operating performance of the array circuit. Reduce the computational overhead and power consumption of the entire computing circuit, making the circuit more suitable for low-power scenarios. At the same time, the calculation result of the memory unit 100 can be less affected by the voltage error at the source line end, and the calculation result has higher accuracy.

FIG. 3 is a schematic diagram of another memory unit provided by at least one embodiment of the present disclosure.

For example, as shown in Figure 3, the memory unit 200 is a 4T2R type memory cell circuit structure based on the 2T1R circuit structure shown in Figure 2. For example, in the memory unit 200, a first memory sub-unit having the 2T1R structure shown in Figure 2 The unit 110 and the second memory subunit 120 are arranged symmetrically so that the memory unit 200 can implement negative values.

As shown in Figure 3, the first memory sub-unit 110 in the memory unit 200 includes a first resistive switching device 101, a first switching element 201 and a second switching element 301; the second memory sub-unit 120 in the memory unit 200 includes a first Regarding the connection relationship between the two resistive switching devices 12, the third switching element 22 and the fourth switching element 32, please refer to the relevant description in Figure 2 for the connection relationship between the first resistive switching device 101, the first switching element 201 and the second switching element 301. I won’t go into details here.

As shown in FIG. 3 , in the memory unit 200 , the first terminal of the second resistive switching device 12 is connected to the second bit line terminal BLN; the first pole of the third switching element 22 is connected to the second terminal of the second resistive switching device 12 . terminal is connected, the second pole of the third switching element 22 is connected to the first pole of the fourth switching element 32, the control pole of the third switching element 22 is connected to the second word line terminal WLVN; the second pole of the fourth switching element 32 It is connected to the source line terminal SL, and the control electrode of the fourth switching element 32 is connected to the selection control terminal WLP.

For example, as shown in FIG. 3 , the first resistive switching device 101 , the first switching element 201 , the second switching element 301 , the fourth switching element 32 , the third switching element 22 and the second resistive switching device 12 are connected in series in sequence. The first switching element 201 and the third switching element 22 respectively have independent control terminals, and their open or closed states are independent of each other. The control terminals of the second switching element 301 and the fourth switching element 32 are both connected to the selection control terminal WLP, and both have the same on state or off state. For example, the control terminal WLP can be selected by applying a turn-on signal to the control electrodes of the second switching element 301 and the fourth switching element 32, so that the first switching element 301 and the fourth switching element 32 are turned on, and the second word line terminal WLVN can pass A turn-on signal is applied to the control electrode of the third switching element 22 so that the third switching element 22 is turned on. That is to say, for the memory unit 200, when the first word line terminal WLVP, the second word line terminal WLVN, and the selection control terminal WLP apply the turn-on signal at the same time, the memory unit 200 can be turned on, thereby realizing the data processing of the memory unit 200. Operations, such as set operations, reset operations, etc. This achieves independent control of the memory unit 200, reduces the cost of the entire computing circuit, and improves the control flexibility of the memory unit 200.

For example, as shown in Figure 3, the first resistive switching device 101 and the second resistive switching device 12 can be implemented as a resistive switching memory (RRAM). The first switching element 201, the second switching element 301, the third switching element 22 and The fourth switching element 32 can be implemented as a transistor.

For example, as shown in FIG. 3 , the first switching element 201 , the second switching element 301 , the third switching element 22 and the fourth switching element 32 can all be N-type transistors, or they can all be P-type transistors, or they can be N-type transistors. The embodiments of the present disclosure do not limit the combination of transistors and P-type transistors.

The following description assumes that the first switching element 201, the second switching element 301, the third switching element 22 and the fourth switching element 32 are all N-type transistors.

For example, as shown in FIG. 3 , the first word line terminal WLVP can be turned on by inputting a high level to the gate of the first switching element 201 ; the second word line terminal WLVN can be turned on by inputting a high level to the gate of the third switching element 22 input a high level to the gate to turn it on.

For example, as shown in FIG. 3 , the first electrodes of the third switching element 22 and the fourth switching element 32 may be drain electrodes, and the second electrodes of the third switching element 22 and the fourth switching element 32 may be source electrodes. The source electrode of the fourth switching element 32 is connected to the source electrode of the second switching element 301, and together they are connected to the source line terminal SL connection. For example, the fourth switching element 32 and the second switching element 301 may receive the reset voltage through the source line terminal SL. The first terminal (such as the positive electrode) of the second resistive switching device 12 is connected to the second bit line terminal BLN, and the second terminal (such as the negative electrode) of the second resistive switching device 12 is connected to the drain of the third switching element 22. For example, the second resistive switching device 12 may receive the set voltage through the second bit line terminal BLN.

For example, the first resistive switching memory 101 in the memory unit 200 receives an input signal through its connected first bit line terminal BLP, and the second resistive switching memory 12 in the memory unit receives the input signal through its connected second bit line terminal BLN. The inverted input signal corresponds to the signal, so that the conductance values of the two memristors can be used to implement negative weights to achieve richer and more complex data processing through the memory unit. For example, when multiple memory cells 200 are disposed in an array circuit to perform parallel calculations, a voltage signal can also be applied through at least one word line terminal, thereby reducing the impact of signal errors at the source line terminal SL on the calculation results.

Therefore, the memory unit 200 shown in FIG. 3 includes two memory sub-units that are independent of each other, and each memory sub-unit can be independently controlled, reducing the control association with other circuit components and having a high degree of configuration freedom. It reduces the overhead of the entire computing circuit and can use two memristor units to realize negative values of parameter elements to perform richer and more complex computing processing. It also makes the calculation results less affected by the voltage error at the source line. impact, with higher calculation accuracy.

FIG. 4 is a schematic diagram of yet another memory unit provided by at least one embodiment of the present disclosure. Compared with the memory unit 200 shown in FIG. 3 , the memory unit 300 shown in FIG. 4 eliminates any one of the two switching elements connected to the selection control terminal WLP.

As shown in FIG. 4 , the memory unit 300 includes a first resistive switching device 102 , a first switching element 202 , a second switching element 302 , and a third resistive switching device 13 and a fifth switching element 23 . Regarding the first resistive switching device 102 , the connection relationship between the first switching element 202 and the second switching element 302 can refer to the relevant description shown in Figure 2, and will not be described again here.

As shown in FIG. 4 , in the memory unit 300 , the first terminal of the third resistive switching device 13 is connected to the second bit line terminal BLN; the first pole of the fifth switching element 23 is connected to the second terminal of the third resistive switching device 13 . terminal is connected, the second pole of the fifth switching element 23 is connected to the source line terminal SL, and the control pole of the fifth switching element 23 is connected to the second word line terminal WLVN.

For example, as shown in FIG. 4 , the first resistive switching device 102 , the first switching element 202 , the second switching element 302 , the fifth switching element 23 and the third resistive switching device 13 are connected in series in sequence. For example, the second word line terminal WLVP can apply a turn-on signal to the control electrode of the fifth switching element 23 to turn on the fifth switching element 23 . That is to say, for the memory unit 300, when the first word line terminal WLVP, the second word line terminal WLVN, and the selection control terminal WLP apply the turn-on signal at the same time, the memory unit 300 is turned on, and the data of the memory unit 300 can be realized. Processing operations, such as set operations, reset operations, etc. This achieves independent control of the memory unit 300, reduces the cost of the entire computing circuit, improves the control flexibility of the memory unit, and increases the freedom of array configuration.

For example, as shown in FIG. 4 , the first resistive switching device 102 and the third resistive switching device 13 may be resistive switching memories (RRAM), and the first switching element 202 , the second switching element 302 and the fifth switching element 23 may be transistor.

For example, embodiments of the present disclosure do not limit the type of transistors. The following description assumes that the first switching element 202, the second switching element 302 and the fifth switching element 23 are N-type transistors.

For example, as shown in FIG. 4 , the second word line terminal WLVN can turn on or off the fifth switching element 23 by applying a corresponding voltage to the control electrode of the fifth switching element 23 , that is, the gate electrode. For example, the second word line terminal WLVN can be turned on by inputting a high level to the gate of the fifth switching element 23 . The first electrode of the fifth switching element 23 may be a drain electrode, and the second electrode thereof may be a source electrode. The second pole of the fifth switching element 23 is connected to the source line terminal. For example, the third resistive switching device 13 can receive the reset voltage through the source line terminal SL. The first terminal (eg, the positive electrode) of the third resistive switching device 13 is connected to the second bit line terminal BLN, and the second terminal (eg, the negative electrode) of the third resistive switching device 13 is connected to the drain of the fifth switching element 23 .

Similarly, the memory unit 100 shown in Figure 4 can also use two memristor units to realize positive, zero, and negative values of parameter elements, and make the calculation results less affected by the voltage error at the source line end, and the calculation accuracy Higher, the relevant description can be found in the above description and will not be repeated here.

For example, in some embodiments of the present disclosure, the resistive switching device, such as the first resistive switching device 10, the second resistive switching device 12, the third resistive switching device 13, etc. may be a resistive switching memory (RRAM), a flash memory ( Any of Flash), static random access memory (SRAM), dynamic random access memory (DRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM) ; Switching elements, such as the above-mentioned first switching element 20, second switching element 30, third switching element 22, fourth switching element 32 and fifth switching element 23, etc. can be transistors, such as thin film transistors or field effect transistors or other characteristics Same switching device. As a result, the memory unit provided by at least one embodiment of the present disclosure can be applied to more scenarios, and thus can perform more flexible and complex computing processing.

FIG. 5 is a schematic diagram of an array circuit structure provided by at least one embodiment of the present disclosure.

As shown in FIG. 5 , an embodiment of the present disclosure also provides an array circuit structure 1000, which includes a plurality of memory cells arranged in an array of M rows and N columns, and a plurality of signal control lines. The plurality of signal control lines include M first bit lines, M first word lines, N selection control lines and N source lines, where M and N are positive integers.

For example, the memory unit in the array circuit structure 1000 may adopt the structure described in any of the above embodiments. For example, the memory unit structure provided in the relevant embodiment of FIG. 2 may be adopted.

As shown in FIG. 5 , M first bit lines and M first word lines respectively correspond to M rows of the array circuit structure 1000 , and N selection control lines and N source lines respectively correspond to N rows of the array circuit structure 1000 . There is a one-to-one correspondence between columns, each first bit line is connected to the first bit line end of a row of memory cells corresponding to the first bit line, and each first word line is connected to the first bit end of a row of memory cells corresponding to the first word line. The word line end is connected, each selection control line is connected to the selection control end of a column of memory cells corresponding to the selection control line, and each source line is connected to the source line end of a column of memory cells corresponding to the source line.

For example, the i-th first bit line is connected to the first bit line terminal BLPi of the i-th row of memory cells in the array circuit structure 1000, and the i-th first word line is connected to the i-th row of memory cells in the array circuit structure 1000. The first word line terminal WLVPi is connected, the jth source line is connected to the source line terminal SLj of the jth column memory unit in the array circuit structure 1000, and the jth selection control line is connected to the jth column memory unit in the array circuit structure 1000. The selection control terminal WLpj is connected, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N.

When the memory unit in the array circuit structure 1000 adopts the structure shown in FIG. 2 , the schematic structural diagram of the array circuit composed of multiple memory units is as shown in FIG. 6 .

For example, in the circuit array structure 1010 shown in Figure 6, the control electrodes of all the first switching elements of the i-th row memory cells are connected to the first word line terminal WLVPi (that is, the i-th first word line WLVPi). When When a turn-on signal is applied to the first word line WLVPi, all the first switching elements 20 in the i-th row can be turned on. The control electrodes of all the second switching elements 30 of the memory cells in the jth column are connected to the selection control terminal WLPj (that is, the jth selection control line WLPj). When the turn-on signal is applied to the selection control line WLPj, the jth selection control line WLPj can be connected to the selection control terminal WLPj. All second switching elements 30 in the column are conductive.

For example, multiple memory cells form an array circuit structure in the form of an array, so that computing processing can be completed in parallel. For example, each of the plurality of memory cells is turned on when receiving the turn-on signal applied by the corresponding first word line and the turn-on signal applied by the corresponding selection control line. Therefore, the selection control line and the third word line can be used according to actual needs. One word line selects one or more memory cells in the array circuit structure for operation without having to turn on other unrelated memory cells, which improves the control flexibility of the array circuit structure and can realize operation on only some of the source line terminals. There is a calculation current in the array circuit, and the array circuit can only use part of the source line terminals when performing calculations, which reduces the power consumption of the circuit. At the same time, the voltage signal can be applied through at least one word line terminal, so that the calculation result is less affected by the voltage error of the source line terminal and has higher calculation accuracy.

FIG. 7 is a schematic diagram of another array circuit structure provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 7 , the memory unit in the array circuit structure 2000 can adopt the structure described in the above embodiment. For example, the memory unit structure provided in the relevant embodiment of FIG. 3 or FIG. 4 can be adopted.

For example, as shown in Figure 7, the plurality of signal control lines include M first bit lines, M first word lines, N selection control lines, and N source lines. In addition, M second bit lines and M second word lines.

Regarding the connection relationship between the M first bit lines, M first word lines, N selection control lines and N source lines, please refer to the relevant description in Figure 5 and will not be repeated here.

For example, M second bit lines and M second word lines respectively correspond to M rows of the array circuit structure, and each second bit line corresponds to the second bit line in a row of memory cells corresponding to the second bit line. terminals are connected, and each second word line is connected to a second word line terminal in a row of memory cells corresponding to the second word line.

For example, as shown in FIG. 7 , the i-th second bit line is connected to the second bit line terminal BLNi of the i-th row of memory cells in the array circuit structure 2000, and the i-th second word line is connected to the i-th row memory cell in the array circuit structure 2000. The second word line terminal WLVNi of the i-th row memory cell is connected.

When the memory unit in the array circuit structure 2000 adopts the structure shown in FIG. 3 , the schematic structural diagram of the array circuit composed of multiple memory units is as shown in FIG. 8A . When the memory cells in the array circuit structure 2000 adopt the structure shown in FIG. 4 , the schematic structural diagram of the array circuit composed of multiple memory cells is shown in FIG. 8B .

Regarding the connection relationship of FIG. 8A , please refer to the relevant descriptions of FIG. 3 and FIG. 7 , and regarding the connection relationship of FIG. 8B , please refer to the relevant descriptions of FIG. 4 and FIG. 7 , which will not be described again here.

For example, as shown in Figure 8A, when the memory unit in the array circuit structure 2010 adopts the memory unit 200 as shown in Figure 3, the first end of the first resistive switching device 101 is connected to the first bit line terminal BLNi, and the first The control electrode of the switching element 201 is connected to the first word line terminal WLVPi, the control electrode of the second switching element 301 and the control electrode of the fourth switching element 32 are both connected to the selection control terminal WLPi, and the first terminal of the second resistive switching device 12 The control electrode of the third switching element 22 is connected to the second bit line terminal BLNi. The control electrode of the third switching element 22 is connected to the second word line terminal WLVNi. The second electrode of the second switching element 301 and the second electrode of the fourth switching element 32 are both connected to the source line terminal. SLj connection.

For example, as shown in FIG. 8A , the control electrodes of all third switching elements 22 of the i-th row memory cells are connected to the second word line terminal WLVNi (that is, the i-th second word line WLVNi). That is, when the i-th second word line WLVNi When a turn-on signal is applied to the second word line, all third switching elements 22 in the i-th row can be turned on. The control electrodes of all the fourth switching elements 32 of the second memory sub-unit 120 in the j-th column are connected to the selection control terminal WLPj (that is, the j-th selection control line WLPj), that is, when the enable signal is applied to the selection control line When , all the fourth switching elements 32 in the j-th column can be turned on.

For example, as shown in Figure 8B, when the memory unit in the array circuit structure 2020 adopts the memory unit 300 as shown in Figure 4, the first end of the first resistive switching device 102 is connected to the first bit line terminal BLPi, and the first The control electrode of the switching element 202 is connected to the first word line terminal WLVPi, the control electrode of the second switching element 302 is connected to the selection control terminal WLPi, and the first end of the third resistive switching device 13 is connected to the second bit line terminal BLNi; The control electrode of the fifth switching element 23 is connected to the second word line terminal WLVPi, and the second electrode of the second switching element 302 and the second electrode of the fifth switching element 23 are both connected to the source line terminal SLj.

For example, as shown in FIG. 8B , the control electrodes of all the fifth switching elements 23 of the memory cells in the i-th row are connected to the second word line terminal WLVNi (that is, the i-th second word line WLVNi). That is, when the i-th second word line WLVNi When a turn-on signal is applied to the second word line, all the fifth switching elements 23 in the i-th row can be turned on.

For example, when multiple memory cells form an array circuit structure in the form of an array, each of the multiple memory cells is activated when receiving a turn-on signal applied by the corresponding first word line, second word line, and selection control line. Open, so one or more memory cells in the array circuit structure can be selected for operation as needed without having to open other unrelated memory cells, and it can be realized that the calculation current exists only in some of the source line terminals, and the array circuit Only part of the source line ends can be used when performing calculations, which improves the control flexibility of the array circuit structure and reduces the power consumption of the circuit. At the same time, when the input signals of the first bit line and the second bit line have opposite polarities, Implement negative weighting of memory cells to perform richer and more complex computational processing. At the same time, the voltage signal can be applied through at least one word line terminal, so that the calculation result is less affected by the voltage error of the source line terminal and has higher calculation accuracy.

At least one embodiment of the present disclosure also provides a data processing method. Figure 9 is a schematic diagram of a data processing method provided by at least one embodiment of the present disclosure.

As shown in Figure 9, at least one embodiment of the present disclosure also provides a data processing method, including step S1 and step S2.

S1: Select at least one memory unit in the array circuit structure through at least M first word lines and N selection control lines.

S2: Perform a data processing operation on at least one memory unit to perform corresponding data processing using at least one memory unit.

For example, the data processing method can be applied to the array circuit structure described in any embodiment of the present disclosure, for example, the array circuit structure shown in FIGS. 5-8B.

For example, when the array circuit structure is the circuit structure shown in Figure 5, each of the plurality of memory cells receives an enable signal applied by the corresponding first word line and an enable signal applied by the corresponding selection control line. is opened. For example, step S1 may include: for any memory unit among the at least one memory unit, determining the target row and target column in which any memory unit is located; applying a turn-on signal to the target row through the first word line corresponding to the target row; The select control line corresponding to the column applies an enable signal to the target column to select any memory cell.

For example, as shown in Figure 5, M first word lines correspond to M rows in the array circuit structure, and N selection control lines correspond to N columns in the array circuit structure. For any memory cell that needs to be turned on, first determine The target row and target column where it is located, for example, if the memory cell is located in the i-th row and j-th column, then the turn-on signal can be applied to the first word line terminal WLVPi through the i-th first word line to turn on the memory cell. The first switching element is turned on, and by applying a turn-on signal to the j-th selection control line to the selection control terminal WLPj, the second switching element in the memory unit can be turned on. As a result, one or more memory cells in the selection array circuit are turned on, and multiple memory cells are not limited to being in the same row or column, supporting an integrated storage and computing technology with high array configuration freedom and high calculation accuracy. implementation, and can utilize some of the N source lines to reduce power consumption overhead.

For example, the turn-on signal applied to the first word line terminal WLVPi and the turn-on signal applied to the selection control terminal WLPj may be voltage signals. For example, when the turn-on signal is applied to the switching element, the switching element is in a conductive state. For example, no enable signal is input to other first word lines and selection control lines except the first word line and selection control line corresponding to the selected memory cell, so that other rows and columns except the row and column of the selected memory cell are The switching elements in the memory cells of the column are in the off state.

Therefore, this data processing method can realize independent control of any selected memory unit in the array circuit, and can reduce the control association with other circuit elements, so as to reduce the power consumption overhead of the entire operation array circuit structure, making the array circuit The structure has high control flexibility.

Of course, since each memory unit is independently controlled, it is also possible to select some or all of the memory units in the array circuit structure in a matrix form through the first word line and the selection control line to turn on, and perform corresponding data processing operations.

For example, at least one memory unit is arranged in an array with W rows and U columns, W is a positive integer and less than or equal to M, and U is a positive integer and less than or equal to N. Step S1 may include: applying turn-on signals to W rows respectively through W first word lines corresponding to W rows of memory cells arranged in array form, and applying turn-on signals to W rows respectively through U selection control lines corresponding to U columns of memory cells arranged in array form. Column U applies an enable signal to select at least one memory cell.

For example, as shown in Figure 5, for some or all memory cells that need to be turned on in array form, the target row and target column need to be determined first. For example, the array form can be expressed as {Di,j|1≤X1≤i≤X2≤M,1≤Y1≤j≤Y2≤N}, that is, the X1 to X2 rows and the The memory cells in column Y1 to column Y2, here, X2-X1+1=W, Y2-Y1+1=U. For example, enable signals can be applied to the first word line terminals of the memory cells in the X1 to X2 rows respectively through the W first word lines corresponding to the memory cells in the X1 to The switching element is turned on, and a turn-on signal is applied to the selection control terminal of the memory unit of the Y1 to Y2 columns respectively through the U selection control lines corresponding to the memory cells of the Y1 to Y2 columns, so as to switch the second terminal of the memory unit of the Y1 to Y2 columns. The switching element is turned on. X1 and X2 are positive integers and less than or equal to M, Y1 and Y2 are positive integers and less than or equal to N.

For example, when a turn-on signal is applied to the switching element, the switching element is in a conductive state. For example, no enable signal is input to other first word lines and selection control lines except the first word line and selection control line corresponding to the selected memory cell, so that other rows and columns except the row and column of the selected memory cell are The switching elements in the memory cells of the column are in the off state.

Thus, some or all of the memory cells in the array circuit structure 1000 shown in FIG. 5 can be selected to facilitate subsequent data processing.

For example, data processing operations may include set operations, reset operations, and read operations.

For example, step S2 may include: performing a set operation or a reset operation on the selected at least one memory unit. For example, the set operation includes causing the resistive switching device to change from the first resistance state to the second resistance state, the reset operation includes causing the resistive switching device to change from the second resistance state to the first resistance state, and when the resistive switching device is in the first resistance state The resistance value is greater than the resistance value in the second resistance state.

For example, referring to FIG. 5, a voltage can be applied to the resistive switching device through the source line and the first bit line to change the resistance state of the resistive switching device. For example, a set voltage can be applied through the first bit line, so that the resistive switching device is in a low resistance state; for another example, a reset voltage can be applied through the source line, so that the resistive switching device is in a high resistance state. For example, the resistance value of the high-resistance state is more than 100 times, for example, 1000 times more than the resistance value of the low-resistance state.

By applying voltage to the first word line and the first bit line at the same time, the resistance value of the resistive switching device can be made smaller and smaller, that is, the resistive switching device changes from a high resistance state to a low resistance state, which will cause the resistive switching device to change from a high resistance state to a low resistance state. The operation of changing to a low-resistance state is called a set operation; by applying voltage to the first word line and the source line at the same time, the resistance value of the resistive-switching device can be made larger and larger, that is, the resistive-switching device changes from a low-resistance state to a high-resistance state. state, the operation that changes the resistive switching device from a low resistance state to a high resistance state is called a reset operation.

For example, a resistive switching device has a threshold voltage. When the input voltage amplitude is less than the threshold voltage of the resistive switching device, the resistance value (or conductance value) of the resistive switching device will not change. In this case, the resistance value (or conductance value) of the resistive switching device can be calculated by inputting a voltage smaller than the threshold voltage; the resistance value (or conductance value) of the resistive switching device can be changed by inputting a voltage larger than the threshold voltage. ).

For example, when performing a setting operation on the resistive switching device, the input voltage of the first word line can be set to 2-5V (volts), for example, 4V. For example, when performing a reset operation on the resistive switching device, the first word line can be set to The input voltage of the word line is set to 2-5V, for example, 4V.

For example, when performing a setting operation on a resistive switching device, the input voltage of the source line can be set to any value from 0 to the power supply voltage VDD, such as 0V. When performing a reset operation on the resistive switching device, the input voltage of the source line can be set to The voltage is set to 2-5V, for example, 5V.

For example, when performing a setting operation on a resistive switching device, the input voltage of the first bit line can be set to 2-5V, for example, 5V; for example, when performing a reset operation on a resistive switching device, the input voltage of the first bit line can be set to 2-5V. The input voltage is set to any value from 0 to the supply voltage VDD, for example, 0V.

For example, step S2 may also include: performing a read operation on the selected at least one memory cell; wherein the read operation includes: applying a read voltage to a bit line corresponding to the at least one memory cell, and reading the resistive switch in the memory cell. The read current generated by the device corresponds to the resistance of the resistive switching device.

When the memory unit is in computing mode, the resistive switching device in the memory unit is in a conductive state that can be used for calculations, and the input voltage provided by the first bit line does not change the conductance value of the resistive switching device. At this time, it can be performed through the array circuit structure Multiplication and sum operations complete data processing.

For example, when performing a read operation using a memory cell, the input voltage of the first word line may be set to 4-5V, for example, 4V; for example, when the first word line does not apply a turn-on signal, the input voltage may be set to 0V ; For example, the input voltage of the source line can be set to 0V, so that the output current of the memory cell can be output; For example, the input voltage of the first bit line can be set to 0.1V-0.3V, such as 0.2V, thereby utilizing the array circuit The structure can perform multiplication and sum operations to complete data processing.

For example, when the array circuit structure is the circuit structure shown in Figure 7, the multiple signal control lines include M first word lines, M second word lines, M first bit lines, and M second bit lines , N source lines and N selection control lines, each of the plurality of memory cells receives a turn-on signal applied by the corresponding first word line and second word line and a turn-on signal applied by the corresponding selection control line. is opened.

For example, step S1 at this time may include: for any memory unit among the at least one memory unit: determining the target row and target column where any memory unit is located; applying a turn-on signal to the target row through the first word line corresponding to the target row; A turn-on signal is applied to the target column through a selection control line corresponding to the target column; and a turn-on signal is applied to the target row through a second word line corresponding to the target row to select any memory cell.

For example, as shown in Figure 7, M first word lines and M second word lines correspond to M rows in the array circuit structure, and N selection control lines correspond to N columns in the array circuit structure. For any memory cell, first determine the target row and column in which it is located. For example, if the memory cell is located in the i-th row and j-th column, then the turn-on function can be applied to the first word line terminal WLVPi through the i-th first word line. The signal is used to turn on the first switching element in the memory cell, and a turn-on signal is applied to the second word line terminal WLVNi through the i-th second word line to turn on the third switching element in the memory unit. The j selection control lines apply a turn-on signal to the selection control terminal WLPj, which can turn on the second switching element and the fourth switching element in the memory unit. As a result, one or more memory cells in the selection array circuit are turned on, and multiple memory cells are not limited to being in the same row or column, supporting an integrated storage and computing technology with high array configuration freedom and high calculation accuracy. implementation, and can utilize some of the N source lines to reduce power consumption overhead.

For example, as shown in Figure 7, since each memory unit is independently controlled, it is also possible to select some or all of the memory units in the array circuit structure to turn on in a matrix form through the first word line, the second word line, and the selection control line, and execute the corresponding data processing operations.

For example, at least one memory unit is arranged in an array with W rows and U columns, W is a positive integer and less than or equal to M, and U is a positive integer and less than or equal to N. At this time, step S1 may include: applying turn-on signals to W rows respectively through W first word lines corresponding to W rows of memory cells arranged in an array form; and controlling selection through U lines corresponding to U columns of memory cells arranged in an array form. The lines apply turn-on signals to the U columns respectively; W second word lines corresponding to the W rows of memory cells arranged in an array form apply turn-on signals to the W rows respectively to select at least one memory cell.

For example, as shown in Figure 7, for some or all memory cells that need to be turned on in array form, the target row and target column need to be determined first. For example, the array form can be expressed as {Di,j|1≤X3≤i≤X4≤M,1≤Y3≤j≤Y4≤N}, that is, the X3 to X4 rows and the The memory cells in the Y3 column to the Y4 column, here, X4-X3+1=W, Y4-Y3+1=U. For example, the W first word lines corresponding to the memory cells in the X3 to X4 rows arranged in an array form can respectively apply turn-on signals to the first word line terminals of the memory cells in the X3 to The first switching element of the memory unit is turned on, and a turn-on signal is applied to the selection control terminals of the memory units in columns Y3 to Y4 respectively through the U selection control lines corresponding to the memory units in columns Y3 to Y4, so as to switch the memory units in columns Y3 to Y4. The second switching element and the fourth switch of the unit are both turned on, and a turn-on signal is applied to the second word line terminal of the memory unit in the X3 to X4 rows through the W second word lines corresponding to the memory cells in the X3 to X4 rows to Turn on the third switching elements of the memory cells in rows X3 to X4.

For example, no enable signal is input to the first word line, the second word line and the selection control line except the first word line, the second word line and the selection control line corresponding to the selected memory cell, so that except for the selected memory cell The switching elements in the memory cells in rows and columns other than the row and column in which the cell is located are turned off.

Therefore, some or all of the memory cells in the array circuit structure 2000 shown in FIG. 7 can be selected to facilitate subsequent data processing.

For example, the data processing operations of the array circuit structure 2000 shown in FIG. 7 may also include set operations, reset operations and read operations. Regarding the method of applying signals to the resistive switching device, please refer to the relevant descriptions of the above embodiments. Here No repetition.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (14)

1. A memory unit including:

   At least one resistive switching device and at least two switching elements, each switching element includes a first pole, a second pole and a control pole,

   Wherein, the at least one resistive switching device includes a first resistive switching device, and the at least two switching elements include a first switching element and a second switching element,

   The first terminal of the first resistive switching device is connected to the first line terminal; the first pole of the first switching element is connected to the second terminal of the first resistive switching device. The second pole is connected to the first pole of the second switching element, the control pole of the first switching element is connected to the first word line terminal; the second pole of the second switching element is connected to the source line terminal, so The control pole of the second switching element is connected to the selection control terminal.
2. The memory unit of claim 1, wherein the at least one resistive switching device further includes a second resistive switching device, and the at least two switching elements further include a third switching element and a fourth switching element,

   The first end of the second resistive switching device is connected to the second bit line end; the first pole of the third switching element is connected to the second end of the second resistive switching device, and the third switching element The second pole is connected to the first pole of the fourth switching element, the control pole of the third switching element is connected to the second word line terminal, and the second pole of the fourth switching element is connected to the source line terminal. , the control electrode of the fourth switching element is connected to the selection control terminal.
3. The memory unit of claim 1, wherein the at least one resistive switching device further includes a third resistive switching device, and the at least two switching elements further include a fifth switching element,

   The first end of the third resistive switching device is connected to the second bit line end; the first pole of the fifth switching element is connected to the second end of the third resistive switching device, and the fifth switching element The second pole is connected to the source line terminal, and the control pole of the fifth switching element is connected to the second word line terminal.
4. The memory unit according to any one of claims 1-3, wherein,

   The resistive switching device is any one of resistive switching memory (RRAM), Flash, SRAM, DRAM, PCRAM, MRAM, and FeRAM;

   The switching element is a transistor.
5. An array circuit structure includes:

   The memory unit according to any one of claims 1 to 4 arranged in a plurality of arrays into M rows and N columns;

   Multiple signal control lines, including: M first bit lines, M first word lines, N selection control lines and N source lines, M and N are positive integers;

   The M first bit lines and the M first word lines are respectively in one-to-one correspondence with the M rows, and the N selection control lines and the N source lines are in one-to-one correspondence with the N columns respectively. ,

   Each first bit line is connected to a first bit line terminal in a row of memory cells corresponding to the first bit line, and each first word line is connected to a first word in a row of memory cells corresponding to the first word line. Line terminals are connected, each selection control line is connected to a selection control terminal in a column of memory cells corresponding to the selection control line, and each source line is connected to a source line terminal in a column of memory cells corresponding to the source line.
6. The array circuit structure according to claim 5, in the case where the memory unit further includes the second resistive switching device, the third switching element and the fourth switching element,

   The first end of the second resistive switching device is connected to the second bit line end; the control electrode of the third switching element is connected to the second word line end;

   The plurality of signal control lines also include M second bit lines and M second word lines, and the M second bit lines and the M second word lines respectively correspond to the M rows one-to-one,

   Each second bit line is connected to a second bit line terminal in a row of memory cells corresponding to the second bit line, and each second word line is connected to a second word in a row of memory cells corresponding to the second word line. Wire end connections.
7. The array circuit structure according to claim 5, when the array circuit structure further includes the third resistive switching device and the fifth switching element,

   The first end of the third resistive switching device is connected to the second bit line end; the control electrode of the fifth switching element is connected to the second word line end;

   The plurality of signal control lines also include M second bit lines and M second word lines, and the M second bit lines and the M second word lines correspond to the M rows respectively,

   Each second bit line is connected to a second bit line terminal in a row of memory cells corresponding to the second bit line, and each second word line is connected to a second word in a row of memory cells corresponding to the second word line. The wire ends are connected separately.
8. A data processing method for the array circuit structure according to any one of claims 5-7, the data processing method includes:

   Select the at least one memory cell in the array circuit structure through at least the M first word lines and the N selection control lines;

   A data processing operation is performed on the at least one memory unit to perform corresponding data processing using the at least one memory unit.
9. The data processing method according to claim 8, wherein each of the plurality of memory cells is activated when receiving a turn-on signal applied by a corresponding first word line and a turn-on signal applied by a corresponding selection control line. Open,

   Selecting the at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines includes:

   For any one of the at least one memory unit:

   Determine the target row and target column where any of the memory cells is located;

   Apply a turn-on signal to the target row through the first word line corresponding to the target row;

   A turn-on signal is applied to the target column through a selection control line corresponding to the target column to select any of the memory cells.
10. The data processing method according to claim 8, wherein in the case where the plurality of signal control lines further include M second word lines, each of the plurality of memory cells receives a corresponding first The word line and the second word line are turned on when the turn-on signal is applied and the corresponding select control line is turned on.

    Selecting the at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines includes:

    For any one of the at least one memory unit:

    Determine the target row and target column where any of the memory cells is located;

    Apply a turn-on signal to the target row through the first word line corresponding to the target row;

    Apply a turn-on signal to the target column through the selection control line corresponding to the target column;

    A turn-on signal is applied to the target row through the second word line corresponding to the target row to select any of the memory cells.
11. The data processing method according to any one of claims 8 and 9, wherein each of the plurality of memory cells receives a turn-on signal applied by a corresponding first word line and a turn-on signal applied by a corresponding selection control line. is turned on when the signal is turned on,

    The at least one memory unit is arranged in an array of W rows and U columns, W is a positive integer and less than or equal to M, U is a positive integer and less than or equal to N,

    Selecting the at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines includes:

    Turn-on signals are respectively applied to the W rows through the W first word lines corresponding to the W rows of memory cells arranged in the array form,

    Turn-on signals are respectively applied to the U columns through U selection control lines corresponding to the U column memory cells arranged in the array form to select the at least one memory cell.
12. The data processing method according to any one of claims 8 and 10, wherein in the case where the plurality of signal control lines further include M second word lines, each of the plurality of memory cells receives is turned on when the turn-on signal applied to the corresponding first word line and the second word line and the turn-on signal applied to the corresponding selection control line,

    The at least one memory unit is arranged in an array of W rows and U columns, W is a positive integer and less than or equal to M, U is a positive integer and less than or equal to N,

    Selecting the at least one memory unit in the array circuit structure through at least the M first word lines and the N selection control lines includes:

    Apply turn-on signals to the W rows respectively through the W first word lines corresponding to the W rows of memory cells arranged in the array form;

    Apply turn-on signals to the U columns respectively through U selection control lines corresponding to the U column memory cells arranged in the array form;

    Turn-on signals are respectively applied to the W rows through W second word lines corresponding to the W rows of memory cells arranged in the array form to select the at least one memory cell.
13. The data processing method according to any one of claims 8-12, said performing a data processing operation on the at least one memory unit to utilize the at least one memory unit to perform corresponding data processing includes:

    Perform a set operation or a reset operation on the selected at least one memory unit;

    Wherein, the setting operation includes causing the resistive switching device to change from the first resistance state to the second resistance state, and the reset operation includes causing the resistive switching device to change from the second resistance state to the first resistance state. resistance state, the resistance value of the resistive switching device in the first resistance state is greater than the resistance value in the second resistance state.
14. The data processing method according to any one of claims 8-13, said performing a data processing operation on the at least one memory unit to utilize the at least one memory unit to perform corresponding data processing, further comprising:

    Perform a read operation on the selected at least one memory cell;

    Wherein, the read operation includes:

    A read voltage is applied to the bit line corresponding to the at least one memory cell, and a read current generated by the resistive switching device in the memory cell corresponding to the resistance of the resistive switching device is read.

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