WO2024016649A1

WO2024016649A1 - Bus transmission structure and method, and chip

Info

Publication number: WO2024016649A1
Application number: PCT/CN2023/076237
Authority: WO
Inventors: 蔡凯; 田佩佳; 刘明; 张雨生; 闫超
Original assignee: 声龙(新加坡)私人有限公司
Priority date: 2022-07-22
Filing date: 2023-02-15
Publication date: 2024-01-25
Also published as: CN114968865B; CN114968865A

Abstract

A bus transmission structure and method, and a chip. The bus transmission structure comprises: a plurality of data sources, a plurality of data endpoints, a bus compression structure, a bus decompression structure, N transmitting buses, N receiving buses and M transmission buses, wherein the N transmitting buses are respectively connected to the plurality of data sources and the bus compression structure, the M transmission buses are respectively connected to the bus compression structure and the bus decompression structure, and the N receiving buses are respectively connected to the bus decompression structure and the plurality of data endpoints, N being greater than 1, M being greater than or equal to 1, and N being greater than M; the bus compression structure distributes data on the N transmitting buses to the M transmission buses; and the bus decompression structure distributes data on the M transmission buses to the data endpoints corresponding to the data.

Description

Bus transmission structure and method, chip

This application claims priority to the Chinese patent application filed with the China Patent Office on July 22, 2022, with the application number CN202210860285.0 and the invention title "Bus Transmission Structure and Method, Chip". The content should be understood as being incorporated by reference. are incorporated into this application.

Technical field

The embodiments of the present disclosure relate to, but are not limited to, the technical field of chip design, and in particular, to a bus transmission structure and method, and a chip.

Background technique

In chip design, a large number of buses will be used. Too many buses will occupy a lot of resources, causing difficulties in back-end layout and wiring, high power consumption, and even making it physically impossible to implement.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

The embodiment of the present disclosure provides a bus transmission structure, including: multiple data sources, multiple data destinations, a bus compression structure, a bus decompression structure, N sending buses, N receiving buses and M transmission buses, N The sending buses are respectively connected to multiple data sources and bus compression structures, the M transmission buses are respectively connected to the bus compression structure and the bus decompression structure, and the N receiving buses are respectively connected to the bus decompression structure and multiple data endpoints, where N is greater than 1 of natural numbers, M is a natural number greater than or equal to 1, and N>M;

The bus compression structure is configured to distribute data on N transmission buses to M transmission buses;

The bus decompression structure is configured to distribute data on M transmission buses to data destinations corresponding to the data.

Embodiments of the present disclosure also provide a bus transmission method, including:

Multiple data sources output data to the bus compression structure through N transmission buses, where N is a large A natural number greater than 1;

The bus compression structure distributes the received data to M transmission buses for transmission, where M is a natural number greater than or equal to 1, and N>M;

The bus decompression structure receives data from the M transmission buses and distributes the received data to corresponding data destinations through the N receiving buses.

An embodiment of the present disclosure also provides a chip, including the bus transmission structure described in any embodiment of the present disclosure.

The bus transmission structure, method, and chip of the embodiment of the present disclosure distribute the data on N transmission buses to M transmission buses (N>M) through the bus compression structure, and distribute the data on the M transmission buses through the bus decompression structure. The data is distributed to the data endpoint corresponding to the data, and the N groups of buses are compressed into M groups during transmission. When the data is needed, the buses are restored to N groups, using fewer buses to transmit data without affecting the chip function. , can reduce the resources required for chip implementation, reduce chip power consumption, and reduce the difficulty of digital backend implementation.

Additional features and advantages of the disclosure will be set forth in the description which follows, and, in part, will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure can be realized and obtained by the arrangements described in the specification and accompanying drawings.

After reading and understanding the drawings and detailed description, other aspects can be understood.

Description of drawings

The drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. They are used to explain the technical solution of the present disclosure together with the embodiments of the present disclosure and do not constitute a limitation of the technical solution of the present disclosure.

Figure 1 is a schematic diagram of a bus transmission structure according to an exemplary embodiment of the present disclosure;

Figure 2 is a schematic diagram of another bus transmission structure (compression ratio 4:3) according to an exemplary embodiment of the present disclosure;

Figure 3 is a schematic diagram of another bus transmission structure (compression ratio 5:3) according to an exemplary embodiment of the present disclosure;

Figure 4 is a schematic diagram of yet another bus transmission structure (compression ratio 5:3) according to an exemplary embodiment of the present disclosure;

Figure 5 is a schematic diagram of yet another bus transmission structure (compression ratio 5:3) according to an exemplary embodiment of the present disclosure;

Figure 6 is a schematic flowchart of a bus transmission method according to an exemplary embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments can be arbitrarily combined with each other.

Unless otherwise defined, the technical terms or scientific terms used in the disclosure of the embodiments of the present disclosure shall have the usual meanings understood by those with ordinary skill in the art to which the disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "include" mean that the elements or things preceding the word include the elements or things listed after the word and their equivalents, without excluding other elements or things.

As shown in Figure 1, the embodiment of the present disclosure provides a bus transmission structure, including: multiple data sources S0, multiple data destinations S6, bus compression structure S2, bus decompression structure S4, N sending buses S1, N There are three receiving buses S5 and M transmission buses S3. The N sending buses S1 are respectively connected to multiple data sources S0 and the bus compression structure S2. The M transmission buses S3 are respectively connected to the bus compression structure S2 and the bus decompression structure S4. N receiving buses Bus S5 connects bus decompression structure S4 and multiple data terminals S6 respectively, where N is a natural number greater than 1, M is a natural number greater than or equal to 1, and N>M;

The bus compression structure S2 is configured to distribute data on N transmission buses S1 to M transmission buses S3;

The bus decompression structure S4 is configured to distribute the data on the M transmission buses S3 to the data destination S6 corresponding to the data through the N receiving buses S5.

The bus transmission structure provided by the embodiment of the present disclosure can compress N groups of buses into M during transmission. Groups, when data needs to be used, the bus is restored to N groups (that is, a compression ratio of N:M is achieved), so that fewer buses can be used to transmit data without affecting the chip function, and can reduce the resources required for chip implementation. , reduce chip power consumption and reduce the difficulty of digital backend implementation.

Theoretically, the bus interfaces have a one-to-one correspondence. If there is a many-to-one situation, for example, the bus transmission structure includes N1 sending buses, N receiving buses and M transmission buses. Among them, N1 is greater than N. The N1 sending buses can be merged into N through the sending arbiter. By sending the bus and then using the bus transmission structure described in this disclosure for compression/decompression, a bus compression ratio of N:M can still be achieved.

In some exemplary embodiments, the bus compression structure S2 may include: at least one data distributor, at least M originating buffers and M originating arbiters, and the plurality of data sources S0 are divided into two groups, wherein one group includes M (For the convenience of distinction, the data source of this group can be called the first data source), and the other group includes (N-M) (for the convenience of distinction, the data sources of this group can be called the second data source), where:

Each first data source is connected to an input port of an originating arbiter via a sending bus S1; each second data source is connected to an input port of a data distributor via a sending bus S1, and each output of the data distributor The ports are respectively connected to another input port of the originating arbiter through a originating buffer, and the output port of each originating arbiter is connected to a transmission bus S3;

The data distributor is set to distribute the data sent by the connected data source S0 to the originating arbiter according to the data storage status of the originating buffer; the originating arbiter is set to output the data of multiple input ports to the originating arbiter according to its own arbitration rules. The output port is connected to the transmission bus S3.

In this embodiment, the originating buffer may be used to buffer data output by the data distributor. The data distributor can decide which originating arbiter to distribute the data of the data source S0 connected to itself according to the data storage status in the originating buffer. For example, a data volume threshold can be set in advance. When the data volume in a certain sending buffer is greater than or equal to the data volume threshold, it means that the bandwidth usage of the branch where the sending buffer is located is high, and the data distributor should be used as soon as possible. Avoid the branch where the originating buffer is located, and try to use other branches where the originating buffer is located to transmit data.

For example, as shown in Figure 2, assume that the amount of data stored in the sending buffer S210 is greater than or equal to the preset data amount threshold, and the amount of data stored in the sending buffers S211 and S212 are both less than the preset The data amount threshold, then the data distributor S20 can distribute the data on the sending bus S13 (that is, the data sent by the data source S03) to the sending buffer S211 or S212, and the sending arbiter S221 via the transmission bus S31 or the sending arbiter S222 is transmitted to the bus decompression structure S4 via the transmission bus S32.

In some exemplary embodiments, the originating arbiter may be any one of a round robin arbiter, a fixed priority arbiter, or a weighted round robin arbiter, wherein the round robin arbiter is configured to The output is polled to the output port one by one; the fixed priority arbiter is set to output the data of multiple input ports to the output port according to the preset priority order; the weighted polling arbiter is set to output the data of multiple input ports to the output port according to the preset weight ratio. The data of each input port is polled and output to the output port. When data is output from the input port of the originating arbiter to the output port, different address information will be added according to different input ports.

For example, as shown in Figure 2, when the polling arbiter is a weighted polling arbiter and the compression ratio is 4:3, the weight ratios of the two input ports of the originating arbiter S220, S221 and S222 can be set to respectively 3:1. For example, for the sending arbiter S220, the weight of the input port connected to the sending bus S10 is 3, and the weight of the input port connected to the sending buffer S210 is 1. When both the sending bus S10 and the sending buffer S210 contain more When the data amount is , the originating arbiter S220 outputs the data of the originating buffer S210 once every three times on average, after outputting the data of the sending bus S10 . This can make the data amount of each of the M transmission buses still uniform. Improve the transmission efficiency of the transmission bus. When the amount of data on the sending bus S10 is less than three times the amount of data in the sending buffer S210, the amount of data actually output by the sending arbiter S220 does not need to be distributed according to the weight of 3:1, that is, it can be distributed according to the weight of 2:1, 1 Sent with weight of :1 or 0:1. By using the weighted polling arbiter, the data on the sending buses S10, S11, S12 and S13 can be output reasonably and evenly, making data blocking less likely and improving the compression effect.

For a fixed-priority arbiter, as long as the input port with a higher priority always has data to be sent, the fixed-priority arbiter must finish sending the data from the input port with a higher priority before sending data with a higher priority. Low priority input port data. For the polling arbiter, if multiple input ports have data to be sent, the data from multiple input ports are polled to the output port one by one.

As shown in Figure 3, when the bus compression ratio of a certain branch is 2:1, the bus compression structure of the branch It is not necessary to set up a data distributor and a sending buffer.

In some exemplary embodiments, the bus decompression structure S4 may include: M data forwarders and at least one end-end arbiter; multiple data end points S6 are divided into two groups, where one group includes M (for ease of distinction, The data end point of this group can be called the first data end point), and the other group includes (N-M) (for the convenience of distinction, the data end point of this group can be called the second data end point), where:

The input ports of the M data transponders are respectively connected to one of the M transmission buses S3. An output port of the M data transponders is respectively connected to a first data terminal through a receiving bus. The M data transponders The other output port is respectively connected to an input port of a receiving arbiter, and the data forwarder is configured to transmit the data to the first data terminal or the receiving arbiter according to the address information carried by the data;

The output port of each receiving arbiter is connected to a second data terminal through a receiving bus. The receiving arbiter is configured to output data from multiple input ports to the second data terminal connected to the output port according to its own arbitration rules. .

In this embodiment, it is considered that a buffer is usually provided inside the data transponder. Therefore, it is not necessary to provide a receiving buffer between the data forwarder and the receiving arbiter. In other exemplary embodiments, as shown in FIG. 4 , a receiving end buffer may also be provided between the data forwarder and the receiving end arbiter, and the receiving end buffer may be used to cache data output by the data forwarder. Since when data is output from the input port of the originating arbiter to the output port, different address information will be added according to different input ports. Therefore, when decompressing the data, the data forwarder can transmit the data according to the address information carried by the data. to the first data destination or end arbiter.

In some exemplary embodiments, the end arbiter may be any one of a polling arbiter or a fixed priority arbiter, wherein the polling arbiter is configured to poll and output data from multiple input ports to Output ports; a fixed-priority arbiter configured to output data from multiple input ports to an output port in a preset priority order.

Correspondingly, as shown in Figure 3, when the bus compression ratio of a certain branch is 2:1, the bus decompression structure S4 of the branch does not need to set an end arbiter.

In some exemplary embodiments, M=N-1. For example, as shown in Figure 2, N=4 and M=3.

In this embodiment, M may be equal to N-1, N-2, N-3, etc.

In some exemplary embodiments, the data branches between the data source and the data destination include I group, and the compression rate of the i-th group of data branches is N _i : Mi _, M and I are natural numbers greater than 1, 1≤i≤I, N _i and M _i are both natural numbers greater than or equal to 1.

In actual use, the data branches between the data source and the data destination may be grouped or not grouped, and the embodiment of the present disclosure does not limit this. For example, the bus transmission structures in Figures 3 and 4 both achieve a bus compression ratio of 5:3. The bus transmission structure in Figure 3 divides the branches from five groups of data sources to data destinations into two groups, where One group achieved a compression ratio of 3:2, and the other group achieved a compression ratio of 2:1, resulting in an overall compression ratio of 5:3. The bus transmission structure in Figure 4 does not group the branches between the data source and the data destination, and also achieves a compression ratio of 5:3. The bus compression structure in this bus transmission structure uses 2 data distributors. and 6 transmitting buffers (in other exemplary embodiments, 3 transmitting buffers may also be used, that is, the data of the transmitting buses S13 and S14 are stored in one transmitting buffer). In actual use, whether multiple groups of branches need to be grouped and the compression ratio of each group can be set as needed.

In some exemplary embodiments, the bus compression structure includes 2 levels. The first-level bus compression structure has a compression rate of N: K ₁ . The second-level bus compression structure has a compression rate of K ₁ :M. K ₁ is greater than 1. of natural numbers;

The bus decompression structure includes two levels. The decompression rate of the first-level bus decompression structure is M:K ₁ , and the decompression rate of the second-level bus decompression structure is K ₁ :N.

In other exemplary embodiments, the bus compression structure includes K levels, the compression rate of the first-level bus compression structure is N: K ₁ , the compression rate of the k-th level bus compression structure is K _k-1 :K _k ,… , the compression rate of the K-th level bus compression structure is K _K-1 :M, K is a natural number greater than or equal to 3, 2≤k<K, K ₁ to K _K-1 are all natural numbers greater than 1;

The bus decompression structure includes K levels. The decompression rate of the first-level bus decompression structure is M:K _K-1 , and the decompression rate of the k-th level bus decompression structure is K _K-k+1 :K _Kk ,… , the decompression rate of the K-th level bus decompression structure is K ₁ :N.

Embodiments of the present disclosure can be connected in series through a multi-level bus compression structure at the sending end, and connected in series through a multi-level bus decompression structure at the receiving end to achieve a higher compression/decompression rate. As shown in Figure 5, the two-level bus compression structures S2-1 and S2-2 are connected in series. The first-level bus compression structure S2-1 includes a data partition Transmitter S20, four transmitting buffers S210/S211/S212/S213, four transmitting arbiters S220/S221/S222/S223, the second level bus compression structure S2-2 includes a data distributor S21, three transmitting buffers S214/S215/S216, three originating arbiters S224/S225/S226, two-level bus decompression structures S4-1 and S4-2 are connected in series, and the first-level bus decompression structure S4-1 includes three data transponders S400 /S401/S402, a receiving arbiter S41, the second-level bus decompression structure S4-2 includes four data transponders S403/S404/S405/S406, a receiving arbiter S42, among which the first-level bus compression structure S2-1 achieves a compression ratio of 5:4, the second-level bus compression structure S2-2 achieves a compression ratio of 4:3, the first-level bus decompression structure S4-1 achieves a decompression rate of 3:4, and the second-level bus compression structure S4-1 achieves a decompression rate of 3:4. The bus decompression structure S4-2 achieves a decompression ratio of 4:5, thus achieving an overall compression ratio of 5:3. In actual use, the number of series of bus compression structures and the compression ratio of each level of bus compression structure can be set as needed. Correspondingly, the number of series of bus decompression structures and the decompression ratio of each level of bus decompression structure can also be set. Set as needed, and the embodiment of the present disclosure does not limit this.

The bus transmission structure of the embodiment of the present disclosure will be described in detail below, taking the compression and restoration of four groups of buses shown in Figure 2 as an example.

Among them, S00, S01, S02 and S03 are data sources, and the data sources S00, S01, S02 and S03 are connected to the sending buses S10, S11, S12 and S13 respectively.

The transmit buses S10, S11, S12 and S13 are connected to the bus compression structure S2. Among them, the sending buses S10, S11 and S12 are respectively connected to the sending arbiters S220, S221 and S222 in the bus compression structure S2. The sending bus S13 is connected to the input port of the data distributor S20 in the bus compression structure S2. The data distributor S20 includes three output ports, and each output port is connected to the sending buffer S210, S211 and S212 respectively. The originating buffers S210, S211 and S212 are connected to the originating arbiters S220, S221 and S222 respectively.

For example, the originating arbiters S220, S221 and S222 may be weighted polling arbiters. In the compression restoration application scenario of the four groups of buses, the weight ratio of the originating arbiters S220, S221 and S222 may be set to 3:1; By using the weighted polling arbiter, the data on the sending buses S10, S11, S12 and S13 can be output reasonably and evenly, making data blocking less likely and improving the compression effect.

In other examples, the originating arbiters S220, S221, and S222 may also use ordinary arbiters (ie, fixed priority arbiters) or polling arbiters, and this disclosure does not limit this.

The multiple output ports of the data distributor S20 in the bus compression structure S2 are respectively connected with the originating cache. Devices S210, S211 and S212 are connected.

The output ports of the originating buffers S210, S211 and S212 are respectively connected to the originating arbiters S220, S221 and S222.

The output ports of the originating arbiters S220, S221, and S222 are respectively connected to the compressed transmission buses S30, S31, and S32.

The transmission buses S30, S31 and S32 are connected to the bus decompression structure S4. Among them, the transmission buses S30, S31 and S32 are respectively connected to an input port of the data transponders S400, S401 and S402 in the bus decompression structure S4.

One output port in the data transponders S400, S401 and S402 is connected to the restored receiving buses S50, S51 and S52 respectively.

Another output port of the data transponders S400, S401 and S402 is respectively connected to an input port of the receiving arbiter S41.

The receiving arbiter S41 can be a polling arbiter or an ordinary arbiter. Using the polling arbiter can output the data of the other output port of the data transponder S400, S401 and S402 more reasonably and evenly, which is not easy. Generate data blocking and improve compression effect.

The output port of the receiving arbiter S41 is connected to the restored receiving bus S53.

The receiving buses S50, S51, S52 and S53 are respectively connected to the data terminals S60, S61, S62 and S63.

The workflow of the bus transmission structure shown in Figure 2 is as follows:

Data sources S00, S01, S02 and S03 send data to the sending buses S10, S11, S12 and S13 respectively;

The data distributor S20 divides the data of the sending bus S13 into three parts and buffers them into the sending buffers S210, S211 and S212 respectively;

The originating arbiter S220 generates the data of the transmission bus S30 based on the data of the originating buffer S210 and the data of the sending bus S10; the originating arbiter S221 generates the data of the transmission bus S31 based on the data of the originating buffer S211 and the data of the sending bus S11; The originating arbiter S222 generates the data of the transmission bus S32 based on the data of the originating buffer S212 and the data of the transmission bus S12. At this point, the data compression is completed, and the transmission buses S30, S31 and S32 may be physically very long.

Transmission buses S30, S31 and S32 transfer data to the bus decompression structure S4;

The data transponder S400 receives the data of the transmission bus S30, separates the data of the sending bus S10 and sends it to the receiving bus S50, and completes the restoration of the data of the sending bus S10; and separates the data of the sending bus S13 and sends it to the receiving arbiter S41. The data transponder S401 receives the data of the transmission bus S31, separates the data of the sending bus S11 and sends it to the receiving bus S51, and completes the restoration of the data of the sending bus S11; and separates the data of the sending bus S13 and sends it to the receiving arbiter S41. The data transponder S402 receives the data of the transmission bus S32, separates the data of the sending bus S12 and sends it to the receiving bus S52, completing the restoration of the data of the sending bus S12; and separates the data of the sending bus S13 and sends it to the receiving arbiter S41;

The receiving arbiter S41 receives the data from the data transponders S400, S401 and S402, sends it to the receiving bus S53, and completes the data restoration of the sending bus S13;

The receiving buses S50, S51, S52 and S53 send data to the data destinations S60, S61, S62 and S63 respectively.

For the working process of the bus transmission structure shown in Figure 3, Figure 4 and Figure 5, reference can be made to the working process of the bus transmission structure of Figure 2, which will not be described in detail here.

In chip design, a large number of buses will be used. Too many buses will occupy a lot of resources, causing difficulties in back-end layout and wiring, high power consumption, and even making it physically impossible to implement. The chip of the embodiment of the present disclosure distributes the data on N transmission buses to M transmission buses (N>M) through the bus compression structure, and distributes the data on the M transmission buses to the data correspondence through the bus decompression structure. At the end of the data, N groups of buses are compressed into M groups during transmission, and the buses are restored to N groups when data is needed. Using fewer buses to transmit data without affecting the chip function can reduce the resources required for chip implementation. , reduce chip power consumption and reduce the difficulty of digital backend implementation.

As shown in Figure 6, an embodiment of the present disclosure also provides a bus transmission method, including the following steps:

Step 601: Multiple data sources output data to the bus compression structure through N transmission buses, where N is a natural number greater than 1;

Step 602: The bus compression structure distributes the received data to M transmission buses for transmission. Among them, M is a natural number greater than or equal to 1, and N>M;

Step 603: The bus decompression structure receives data from M transmission buses, and distributes the received data to data destinations corresponding to the data through N receiving buses.

In some exemplary embodiments, the bus compression structure includes at least one data distributor, at least M transmitting buffers, and M transmitting arbiters; the bus compression structure distributes received data to M transmission buses for transmission, including:

The data distributor distributes the data sent by the connected data source to the originating arbiter according to the status of the originating buffer;

The originating arbiter outputs data from multiple input ports to the transmission bus connected to the output port according to its own arbitration rules.

In some exemplary embodiments, the bus decompression structure includes: M data forwarders and at least one receiving arbiter; the bus decompression structure distributes data on M transmission buses to data destinations corresponding to the data, including:

The data forwarder transmits the data to the data destination or the receiving arbiter according to the address information carried by the data;

The receiving arbiter outputs data from multiple input ports to the data end point connected to the output port according to its own arbitration rules.

The disclosed bus transmission method can compress N groups of buses into M groups during transmission, and then restore the buses to N groups when data needs to be used. It uses fewer buses to transmit data without affecting chip functions, and can reduce the number of chips. Implement the required resources, reduce chip power consumption, and reduce the difficulty of digital backend implementation.

In the description of the embodiments of the present disclosure, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a fixed connection. Detachable connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the meanings of the above terms in this disclosure can be understood according to the circumstances.

Those of ordinary skill in the art can understand that all or some steps, Functional modules/units in systems and devices may be implemented as software, firmware, hardware and appropriate combinations thereof. In hardware implementations, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may consist of several physical components. Components execute cooperatively. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

Although the embodiments disclosed in the present disclosure are as above, the described contents are only used to facilitate the understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the field to which this disclosure belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of this disclosure. However, the protection scope of this disclosure must still be The scope defined by the appended claims shall prevail.

Claims

A bus transmission structure, including: multiple data sources, multiple data destinations, bus compression structure, bus decompression structure, N sending buses, N receiving buses and M transmission buses. The N sending buses are connected to multiple Data source and bus compression structure, M transmission buses are respectively connected to the bus compression structure and bus decompression structure, and N receiving buses are respectively connected to the bus decompression structure and multiple data destinations, where N is a natural number greater than 1, and M is greater than Or a natural number equal to 1, and N>M;

The bus compression structure is configured to distribute data on the N transmission buses to the M transmission buses;

The bus decompression structure is configured to distribute the data on the M transmission buses to the data destination corresponding to the data through the N receiving buses.
The bus transmission structure according to claim 1, wherein the bus compression structure includes: at least one data distributor, at least M originating buffers and M originating arbiters, and the plurality of data sources include at least one first data source and at least one secondary data source, where:

Each of the first data sources is connected to an input port of the originating arbiter through a sending bus; each of the second data sources is connected to an input of the data distributor through a sending bus. Port connection, each output port of the data distributor is connected to another input port of the originating arbiter through one of the originating buffers, and the output port of each of the originating arbiters is connected to a transmission bus;

The data distributor is configured to distribute the data sent by the connected data source to the originating arbiter according to the data storage status of the originating buffer; the originating arbiter is configured to distribute multiple data according to its own arbitration rules. The data from each input port is output to the transmission bus connected to the output port.
The bus transmission structure according to claim 2, wherein the originating arbiter is any one of a polling arbiter, a fixed priority arbiter or a weighted polling arbiter, wherein the polling arbiter will The data of the multiple input ports are polled and output to the output port one by one; the fixed priority arbiter outputs the data of the multiple input ports to the output port in accordance with the preset priority order; the weighted polling arbiter outputs the data of the multiple input ports to the output port in accordance with the preset priority order. The weight proportion of the data polling output of multiple input ports is output to the output port.
The bus transmission structure according to claim 1, wherein the bus decompression structure includes: M data forwarders and at least one end arbiter, and the plurality of data end points include at least one first data end point and at least one Second data end point, where:

The input ports of the M data transponders are respectively connected to one of the M transmission buses, and one output port of the M data transponders is respectively connected to one of the first data terminals through one of the receiving buses. , another output port of the M data transponders is respectively connected to an input port of a receiving arbiter, and the data transponder is configured to transmit the data to the first according to the address information carried by the data. a data endpoint or the end-end arbiter;

The output port of each of the receiving arbiters is connected to one of the second data terminals through one of the receiving buses, and the receiving arbiter is configured to output data from multiple input ports to The output port is connected to the second data endpoint.
The bus transmission structure according to claim 4, wherein the end arbiter is any one of a polling arbiter or a fixed priority arbiter, wherein the polling arbiter is configured to The data of the ports are polled and output to the output ports one by one; the fixed priority arbiter is configured to output the data of the multiple input ports to the output ports according to a preset priority order.
The bus transmission structure according to claim 1, wherein M=N-1 or M=N-2.
The bus transmission structure according to claim 1, wherein the data branches between the data source and the data destination include I group, and the compression rate of the i-th group of data branches is Ni : Mi , I is a natural number greater than 1, 1≤i≤I, N i and M i are both natural numbers greater than or equal to 1.
The bus transmission structure according to claim 1, wherein the bus compression structure includes 2 levels, the compression rate of the bus compression structure at the first level is N: K 1 , and the compression rate of the bus compression structure at the second level is K 1 :M, K 1 is a natural number greater than 1;

The bus decompression structure includes two levels. The decompression rate of the bus decompression structure at the first level is M:K 1 , and the decompression rate of the bus decompression structure at the second level is K 1 :N.
The bus transmission structure according to claim 1, wherein the bus compression structure includes K levels, the compression rate of the bus compression structure at the first level is N: K 1 , and the compression rate of the bus compression structure at the kth level is K k-1 :K k ,..., the compression rate of the K-th level bus compression structure is K K-1 :M, K is a natural number greater than or equal to 3, 2≤k＜K, K 1 to K K -1 are all natural numbers greater than 1;

The bus decompression structure includes K levels, the decompression rate of the bus decompression structure at the first level is M:K K-1 , and the decompression rate of the bus decompression structure at the kth level is K K-k+ 1 :K Kk ,..., the decompression rate of the bus decompression structure at the Kth level is K 1 :N.
A chip including the bus transmission structure according to any one of claims 1 to 9.
A bus transmission method, including:

Multiple data sources output data to the bus compression structure through N transmission buses, where N is a natural number greater than 1;

The bus compression structure distributes the received data to M transmission buses for transmission, where M is a natural number greater than or equal to 1, and N>M;

The bus decompression structure receives data from the M transmission buses and distributes the received data to corresponding data destinations through the N receiving buses.
The bus transmission method according to claim 11, wherein the bus compression structure includes at least one data distributor, at least M sending buffers and M sending arbiters; the bus compression structure distributes the received data Transmission to M transmission buses, including:

The data distributor distributes the data sent by the connected data source to the originating arbiter according to the status of the originating buffer;

The originating arbiter outputs data from multiple input ports to a transmission bus connected to the output port according to its own arbitration rules.
The bus transmission method according to claim 11, wherein the bus decompression structure includes: M data transponders and at least one receiving arbiter; the bus decompression structure distributes data on M transmission buses to The data endpoints corresponding to the data include:

The data forwarder transmits the data to the data center according to the address information carried by the data. According to the end point or the end arbiter;

The receiving arbiter outputs data from multiple input ports to the data end point connected to the output port according to its own arbitration rules.