WO2024016485A1 - Circuit simulation method and electronic device - Google Patents

Abstract

A circuit simulation method and an electronic device. The method comprises: acquiring electrostatic protection actual measurement data corresponding to one or more target electrostatic protection circuits and a plurality of preset electrostatic pulses of different amplitudes (S1); for each target electrostatic protection circuit, establishing, according to the actual measurement data, a virtual circuit model in one-to-one correspondence with the target electrostatic protection circuit (S2); acquiring a post-simulation netlist of a circuit to be simulated, the circuit to be simulated comprising one or more target electrostatic protection circuits, and the post-simulation netlist comprising one or more first-type sub-netlists corresponding to the one or more target electrostatic protection circuits (S3); replacing information in the first-type sub-netlist corresponding to each target electrostatic protection circuit with information of a virtual circuit model corresponding thereto (S4); and simulating the circuit to be simulated on the basis of the replaced post-simulation netlist. According to embodiments of the present disclosure, circuit simulation of an ESD device having a folding characteristic can be achieved.

Description

Circuit Simulation Methods and Electronic Equipment

cross reference

This disclosure claims priority from the Chinese patent application with application number 202210869337.0 and entitled "Circuit Simulation Method and Electronic Device" filed on July 22, 2022, the entire content of which is incorporated herein by reference.

Technical field

The present disclosure relates to the technical field of integrated circuit testing, and specifically to a circuit simulation method and electronic equipment.

Background technique

The electrostatic protection circuit is an important functional module in the chip, and is usually implemented using an ESD (Electro-Static discharge, electrostatic protection) device connected to the electrostatic input port. When a large electrostatic voltage from any direction of the electrostatic input port reaches one end of the ESD device, the ESD device turns on to discharge the electrostatic charge, thereby protecting the chip circuit.

ESD devices have snapback characteristics (Snapback): before the voltage across the ESD device reaches the trigger voltage, the ESD device does not conduct; when the voltage across the ESD device reaches the trigger voltage, the ESD device conducts, and there is a discharge current, and the voltage at both ends It decreases as the discharge current increases; when the voltage across the ESD device reaches the maintenance voltage, the ESD device is broken down, and the voltage at both ends and the conduction current increase simultaneously. Therefore, during the conduction period of the ESD device, one voltage across both ends corresponds to two values of discharge current.

In chip design, it is usually necessary to use simulation software to simulate the circuit to verify the operation of the circuit. Each device in the simulation software needs to have a fixed voltage-current correspondence. Therefore, due to the foldback characteristics of ESD devices, the simulation software cannot simulate ESD devices and circuits using ESD devices, which brings difficulties to the verification process of chip design.

It should be noted that the information disclosed in the above background section is only used to enhance understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of the present disclosure is to provide a circuit simulation method and electronic equipment to overcome, at least to a certain extent, the problem that ESD devices cannot perform circuit simulation due to the foldback characteristics due to limitations and defects in related technologies.

According to a first aspect of an embodiment of the present disclosure, a circuit simulation method is provided, including: acquiring measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and a plurality of preset electrostatic pulses of different amplitudes, the electrostatic protection The actual measured data includes the voltage data that changes with time and the discharge current data that changes with time of the target electrostatic protection circuit under the preset electrostatic pulse excitation; for each of the target electrostatic protection circuits, according to the actual measurement of the electrostatic protection The data establishes a virtual circuit model corresponding to the target electrostatic protection circuit one-to-one; obtains a post-simulation netlist of the circuit to be simulated, the circuit to be simulated includes the one or more target electrostatic protection circuits, and the post-simulation netlist including one or more first-type subnet tables corresponding to the one or more target electrostatic protection circuits; replacing the information in the first-type subnet table corresponding to each of the target electrostatic protection circuits with its corresponding information of the virtual circuit model; and simulate the circuit to be simulated based on the replaced post-simulation netlist.

In an exemplary embodiment of the present disclosure, obtaining actual electrostatic protection measurement data corresponding to one or more target electrostatic protection circuits and a plurality of preset electrostatic pulses of different amplitudes includes: providing the target electrostatic protection circuit with The preset electrostatic pulse is used to excite, and the voltage value and discharge current value between the input end and the output end of the target electrostatic protection circuit are sampled at fixed time intervals within the duration of the preset electrostatic pulse, and all the values are recorded. The corresponding relationship between the voltage value, the discharge current value, the sampling time and the amplitude of the preset electrostatic pulse.

In an exemplary embodiment of the present disclosure, for each target electrostatic protection circuit, establishing a virtual circuit model corresponding to the target electrostatic protection circuit one-to-one according to the electrostatic protection measured data includes: according to the predetermined Assuming the amplitude of the electrostatic pulse, the sampling time and its corresponding voltage value and the discharge current value, the virtual circuit model is configured to output a variable voltage value that changes with time under the preset electrostatic pulse. and variable current values.

In an exemplary embodiment of the present disclosure, the virtual circuit model includes a variable voltage source and a variable current source, the variable current source being connected in parallel with the variable voltage source.

In an exemplary embodiment of the present disclosure, the internal resistance of the variable voltage source is set to infinity.

In an exemplary embodiment of the present disclosure, the fixed time interval is 0.1 nanoseconds.

In an exemplary embodiment of the present disclosure, the target electrostatic protection circuit includes a power clamp circuit, two ends of the power clamp circuit are respectively connected to the power supply and zero potential, and the acquisition of one or more target electrostatic protection circuits The actual measured electrostatic protection data of the circuit corresponding to multiple preset electrostatic pulses of different amplitudes includes: obtaining the voltage data and the discharge current data of the power supply clamp circuit corresponding to the multiple preset electrostatic pulses from the power supply. ; Acquire the voltage data and discharge current data at both ends of the power clamp circuit corresponding to multiple preset electrostatic pulses from the zero potential; wherein, the preset electrostatic pulse, the voltage data at both ends and the The above-mentioned bleeder current data all contain directional information.

In an exemplary embodiment of the present disclosure, replacing the information in the first type subnet table corresponding to each target electrostatic protection circuit with the information of the virtual circuit model corresponding thereto includes: In the post-simulation netlist, the first subnetlist corresponding to the power supply clamp circuit is set to invalid; the virtual circuit model corresponding to the power supply clamp circuit is set between the power supply and the between zero potential.

In an exemplary embodiment of the present disclosure, the target electrostatic protection circuit includes a pin protection circuit, the pin protection circuit includes a first part and a second part, the first part connects the input pin and the power supply, so The second part is connected to the input pin and zero potential, and obtaining the measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and multiple preset electrostatic pulses of different amplitudes includes: obtaining the pin protection The circuit has a first part of voltage data across both ends, a first part of discharge current data, a second part of voltage data across both ends, and a second part of discharge current corresponding to a plurality of preset electrostatic pulses in the first direction input from the input pin. Data; obtaining the first part of the voltage data across both ends, the first part of the discharge current data, and the second part of the voltage across the pin protection circuit corresponding to a plurality of preset electrostatic pulses in the second direction input from the input pin. data, the second part of the discharge current data, the second direction is opposite to the first direction; wherein, the preset electrostatic pulse, the first part of the voltage data across both ends, the first part of the discharge current data, the second part of the two The terminal voltage data and the second part of the discharge current data both contain direction information.

In an exemplary embodiment of the present disclosure, for each of the target electrostatic protection circuits, establishing a virtual circuit model that corresponds one-to-one to the target electrostatic protection circuit based on the measured electrostatic protection data includes: The pin protection circuit establishes a first partial virtual voltage source model corresponding to the plurality of preset electrostatic pulses based on the first partial voltage data across both ends, and establishes a first partial virtual voltage source model corresponding to the plurality of preset electrostatic pulses based on the first partial discharge current data. The first part of the virtual current source model corresponding to the preset electrostatic pulse. The output voltage of the first part of the virtual voltage source model and the discharge current of the first part of the virtual current source are both based on the amplitude and input direction of the preset electrostatic pulse. changes over time; establishing a second part of the virtual voltage source model corresponding to the plurality of preset electrostatic pulses based on the voltage data across the second part, and establishing a model corresponding to the plurality of preset electrostatic pulses based on the second part of the discharge current data. A second partial virtual current source model corresponding to the preset electrostatic pulse. The output voltage of the second partial virtual voltage source model and the discharge current of the second partial virtual current source are both based on the amplitude of the preset electrostatic pulse. and the input direction changes with time; according to the first partial virtual voltage source model, the second partial virtual voltage source model, the first partial virtual current source model, the second partial virtual current source model and the introduction A virtual circuit model corresponding to the foot protection circuit. The virtual circuit model includes three terminals. The first terminal is connected to the input pin, the second terminal is connected to the power supply, and the third terminal is connected to the zero potential. The virtual circuit The voltage and current at at least one of the three terminals vary with time during the duration of the preset electrostatic pulse.

In an exemplary embodiment of the present disclosure, replacing the information in the first type subnet table corresponding to each target electrostatic protection circuit with the information of the virtual circuit model corresponding thereto includes: In the post-simulation netlist, the first subnetlist corresponding to the pin protection circuit is set to invalid; the first end of the virtual circuit model corresponding to the pin protection circuit is connected to the to-be-protected Input pin, connect the second end of the virtual circuit model to the power supply voltage, and connect the third end of the virtual circuit model to zero potential.

In an exemplary embodiment of the present disclosure, simulating the circuit to be simulated based on the replaced post-simulation netlist includes: during simulation, inputting the multiplexed power supply to the circuit to be simulated. preset electrostatic pulses to obtain the first electrostatic simulation data corresponding to the circuit to be simulated; input the plurality of preset electrostatic pulses to the zero potential of the circuit to be simulated to obtain the second electrostatic simulation data corresponding to the circuit to be simulated Simulation data; inputting the plurality of preset electrostatic pulses in the first direction to each input pin of the circuit to be simulated to obtain third electrostatic simulation data corresponding to the circuit to be simulated; Each input pin inputs the plurality of preset electrostatic pulses in a second direction to obtain fourth electrostatic simulation data corresponding to the circuit to be simulated, and the second direction is opposite to the first direction.

In an exemplary embodiment of the present disclosure, the plurality of preset electrostatic pulses corresponding to the third electrostatic simulation data are generated based on a human body discharge model.

In an exemplary embodiment of the present disclosure, the circuit to be simulated is determined based on the first electrostatic simulation data, the second electrostatic simulation data, the third electrostatic simulation data, and the fourth electrostatic simulation data. Dynamic voltage distribution diagram under each preset electrostatic pulse of each input source. According to whether there is a point in the dynamic voltage distribution diagram where the voltage exceeds the corresponding preset value, the electrostatic protection of the circuit to be simulated is determined. Whether the capability meets the design requirements.

According to a second aspect of an embodiment of the present disclosure, an electronic device is provided, including: a memory; and a processor coupled to the memory, the processor being configured to perform, based on instructions stored in the memory, the above any of the methods described.

Embodiments of the present disclosure test the time-varying data of the voltage at both ends of the ESD device and the time-varying data of the discharge current under multiple preset electrostatic pulses of different amplitudes, thereby equating an ESD device to a parallel time-varying device. Voltage sources and current sources can overcome the problem that simulation software cannot simulate the foldback characteristics of ESD devices, thereby achieving accurate circuit simulation of the electrical characteristics of ESD devices.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a flowchart of a circuit simulation method in an exemplary embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a target electrostatic protection circuit in an embodiment of the present disclosure.

Figure 3 is a schematic diagram of a TLP pulse in one embodiment of the present disclosure.

Figure 4 is a schematic diagram of the current-voltage curve of the ESD device.

Figure 5 is a schematic diagram of a virtual circuit model in an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a virtual circuit model corresponding to the pin protection circuit 22 .

Figure 7 is a schematic diagram of the processing of the post-simulation netlist of the circuit to be simulated.

Figure 8 is a sub-flow chart of step S5 in an embodiment of the present disclosure.

FIG. 9 is a block diagram of an electronic device in an exemplary embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details being omitted, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.

In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

Example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a flowchart of a circuit simulation method in an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , circuit simulation method 100 may include:

Step S1: Obtain actual measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and multiple preset electrostatic pulses of different amplitudes. The actual measured electrostatic protection data includes the target electrostatic protection circuit when the preset electrostatic pulses are present. Time-varying voltage data and time-varying discharge current data under excitation;

Step S2: For each target electrostatic protection circuit, establish a virtual circuit model corresponding to the target electrostatic protection circuit one-to-one according to the measured electrostatic protection data;

Step S3: Obtain a post-simulation netlist of the circuit to be simulated. The circuit to be simulated includes the one or more target electrostatic protection circuits. The post-simulation netlist includes a network corresponding to the one or more target electrostatic protection circuits. or multiple first-class subnet tables;

Step S4: Replace the information in the first type subnet table corresponding to each target electrostatic protection circuit with the information of the corresponding virtual circuit model;

Step S5: Simulate the circuit to be simulated based on the replaced post-simulation netlist.

Embodiments of the present disclosure test the time-varying data of the voltage at both ends of the ESD device and the time-varying data of the discharge current under multiple preset electrostatic pulses of different amplitudes, thereby equating an ESD device to a parallel time-varying device. Voltage sources and current sources can overcome the problem that simulation software cannot simulate the foldback characteristics of ESD devices, thereby achieving accurate circuit simulation of the electrical characteristics of ESD devices.

Next, each step of the circuit simulation method 100 is described in detail.

In step S1, actual measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and a plurality of preset electrostatic pulses with different amplitudes are obtained. The actual measured electrostatic protection data includes the target electrostatic protection circuit when the preset electrostatic pulses are generated. Time-varying voltage data and time-varying discharge current data under pulse excitation.

The target electrostatic protection circuit may include, for example, a power clamp circuit (Power Clamp) and a pin protection circuit.

FIG. 2 is a schematic diagram of a target electrostatic protection circuit in an embodiment of the present disclosure.

Referring to FIG. 2 , the power clamp circuit 21 is connected between the power supply voltage VDD and the zero potential VSS, and is used to automatically turn on to discharge the electrostatic charge when triggered by an electrostatic pulse from VDD or VSS. The pin protection circuit 22 is connected between the power supply voltage VDD, zero potential VSS, and the input pin IO. The pin protection circuit 22 includes a first part 221 and a second part 222. The first part 221 is connected to the input pin IO and the power supply VDD. The second part 222 is connected to the input pin IO and the zero-potential VSS. The pin protection circuit 22 is used to conduct to discharge the electrostatic voltage and protect the input when triggered by an electrostatic pulse from the input pin IO, the power supply VDD, and the zero-potential VSS. Pin IO. Among them, the input pin IO is connected to the internal circuit of the chip, such as the output driver (Output Driver) or the input buffer (Input Buffer), which is briefly shown in Figure 2. Since the power clamp circuit 21 and the pin protection circuit 22 are commonly used circuits in chips, their internal structures will not be described in detail here. The method of the embodiment of the present disclosure can be applied to the power supply clamp circuit 21 and the pin protection circuit 22 of any structure. For simplicity of description, the target electrostatic protection circuit is also referred to as an ESD device in the following text.

In the embodiment of the present disclosure, the preset electrostatic pulses with different amplitudes may be, for example, TLP (Transmission Line Pulse). TLP is an electrostatic simulation square wave, which includes a set of square waves with gradually increasing amplitude. By adjusting the rising edge and pulse width, it indirectly simulates the damage ability of some electrostatic pulse forms and the triggering ability of ESD devices by different rising edges. Due to the use of square waves, TLP can obtain an I-V (current-voltage) point by applying one pulse each time, and continuously apply currents of different amplitudes to the ESD device until the ESD device fails, and obtain the ESD device's response to electrostatic pulses. The complete I-V curve of the response.

Figure 3 is a schematic diagram of a TLP pulse in one embodiment of the present disclosure.

Referring to Figure 3, the widths of multiple TLP pulses 300 are equal, and the amplitude increases with time. Each TLP pulse lasts for T duration, and T is a preset value that can be set according to the test environment.

Figure 4 is a schematic diagram of the current-voltage curve of the ESD device.

The curve shown in Figure 4 is between the input end and the output end of an ESD device (such as a voltage clamp device with both ends connected to power and ground respectively) measured under different TLP test pulses when the TLP pulse duration is t. The corresponding relationship between the voltage and the discharge current of the ESD device. When the duration of the TLP pulse is T, the value of t is between 70%T and 80%T.

Referring to Figure 4, the horizontal axis of the I-V curve of the ESD device is the voltage between the input terminal and the output terminal of the ESD device measured at the above t time point under each TLP pulse (this voltage is later referred to as the test voltage), The vertical axis is the discharge current (also called on-current) of the ESD device measured at time point t under each TLP pulse.

Each point on the I-V curve 20 of the ESD device corresponds to a test voltage value V and a discharge current value I. The curve 20 can be divided into four stages: A, B, C, and D according to the four states of the ESD device.

In stage A, before the voltage V across the ESD device (i.e., the test voltage) reaches the trigger voltage Vt1 of the ESD device, the ESD device does not discharge and the discharge current I is low. Phase A is also called the untriggered phase.

In stage B, after the voltage V across the ESD device reaches the trigger voltage Vt1 of the ESD device and before reaching the sustaining voltage Vh, the ESD device discharges, the discharge current I rises, and the voltage V across the ESD device drops. Phase B is also called the trigger phase.

In stage C, after the voltage V across the ESD device reaches the sustaining voltage Vh of the ESD device and before reaching the failure voltage Vt2, the ESD device discharges and the discharge current I and the voltage V across the ESD device rise simultaneously. Phase C is also called the maintenance phase.

In stage D, after the voltage V across the ESD device reaches the failure voltage Vt2 of the ESD device, the ESD device is broken down and the discharge current I suddenly increases. Phase D is also called the failure phase.

The input port for inputting multiple TLP test pulses to the target electrostatic protection circuit (ESD device) can be determined according to the type and connection method of the target electrostatic protection circuit. When the target electrostatic protection circuit is the power supply clamp circuit 21, that is, it is connected between the power supply (VDD) and the zero point (VSS) to perform a voltage clamping function (clamp), the multiple inputs can be input to the power supply (VDD) respectively. TLP test pulse; when the target electrostatic protection circuit is the pin protection circuit 22, that is, it is connected to the IO (input/output, input/output) pin and plays the role of electrostatic protection for the IO pin, the IO pin can be pin to input the multiple TLP test pulses.

As can be seen from Figure 4, for ESD devices, one voltage can correspond to two currents during the discharge process, which does not meet the requirements of simulation software (such as the traditional BSIM SPICE model) for the linear I-V characteristics of simulated devices. ESD devices cannot Implement simulation.

Each point in the curve 20 in Figure 4 corresponds to a voltage between the input terminal and the output terminal of the ESD device measured at time point t of the TLP pulse, but in the actual application of the ESD device, during the duration of the TLP pulse Within T, the voltage between the input terminal and the output terminal of the ESD device is constantly changing, and the discharge current is also constantly changing.

Therefore, when the TLP pulse 300 shown in FIG. 3 is used to test the ESD device, a preset electrostatic pulse can be provided to the ESD device for excitation within the duration T of each TLP pulse 300, and the preset electrostatic pulse can be excited at a fixed time interval. It is assumed that the voltage value and discharge current value between the input and output ends of the ESD device are sampled during the duration of the electrostatic pulse, and the corresponding relationship between the voltage value and discharge current value, the sampling time and the amplitude of the preset electrostatic pulse are recorded. . This fixed time interval is 0.1ns.

Table 1 shows the data of the voltage V between the input terminal and the output terminal of the ESD device and the discharge current I of the ESD device sampled at a time interval of 0.1ns during the duration T of a TLP pulse with an amplitude of Vs. Correspondence. The first column is the duration of the TLP pulse at the time of sampling.

t(ns)	V(t)(V)	I(t)(mA)	t(ns)	V(t)(V)	I(t)(mA)
1.00	0	0	3.10	2.46	0.18
1.10	0.85	0	3.20	2.6	0.23
1.20	0.89	0	3.30	2.6	0.28
1.30	1.23	0.01	3.40	2.74	0.32
1.40	1.38	0.01	3.50	2.5	0.42
1.50	1.65	0.02	3.60	2.83	0.51
1.60	2.04	0.01	3.70	2.91	0.6
1.70	1.72	0.03	3.80	3.05	0.69
1.80	1.92	0.04	3.90	2.96	0.79
1.90	1.91	0.05	4.00	3.23	0.88
2.00	2	0.05	4.10	3.06	0.98
2.10	1.81	0.06	4.20	3.22	1.07
2.20	2.14	0.07	4.30	3.57	1.16
2.30	2.23	0.08	4.40	3.37	1.26
2.40	2.32	0.08	4.50	3.44	1.35
2.50	2.4	0.09	4.60	4	1.43
2.60	2.31	0.1	4.70	3.72	1.55
2.70	2.4	0.11	4.80	4.06	1.63
2.80	2.38	0.12	4.90	4.44	1.73
2.90	2.35	0.13	5.00	4.4	1.81
3.00	2.4	0.14	​	​	​

It can be seen from Table 1 that as the duration of the TLP pulse increases, both the voltage V and the current I show a non-linear increasing trend.

In addition, since electrostatic pulses can have different sources, in step S1, tests can be performed on TLP pulses from different sources according to the type of the target electrostatic protection circuit.

When the target electrostatic protection circuit is the power supply clamp circuit 21, the voltage data and discharge current data at both ends corresponding to the power supply clamp circuit 21 and multiple preset electrostatic pulses from the power supply VDD can be obtained, and then the power supply clamp circuit 21 can be obtained Voltage data V across both ends and discharge current data I corresponding to multiple preset electrostatic pulses from zero potential VSS, where the preset electrostatic pulses, voltage data across both ends and discharge current data all include direction information.

When the target electrostatic protection circuit is the pin protection circuit 22, the first part of the voltage data across both ends of the pin protection circuit and the first part of the discharge corresponding to the plurality of preset electrostatic pulses in the first direction input from the input pin IO can be obtained. Current data, voltage data across the second part, discharge current data of the second part, and then obtain both ends of the first part of the pin protection circuit 22 corresponding to a plurality of preset electrostatic pulses in the second direction input from the input pin IO The voltage data, the first part of the discharge current data, the second part of the voltage data at both ends, the second part of the discharge current data, the second direction is opposite to the first direction. Among them, the preset electrostatic pulse, the first part of voltage data across both ends, the first part of discharge current data, the second part of voltage data across both ends, and the second part of discharge current data all include direction information.

In step S2, for each target electrostatic protection circuit, a virtual circuit model corresponding one-to-one to the target electrostatic protection circuit is established based on the measured electrostatic protection data.

In embodiments of the present disclosure, the virtual circuit model can be configured to operate under the preset electrostatic pulse according to the amplitude of the preset electrostatic pulse (the amplitude of the TLP pulse), the sampling time and its corresponding voltage value and discharge current value. The time changes output variable voltage value and variable current value.

Figure 5 is a schematic diagram of a virtual circuit model in an embodiment of the present disclosure.

Referring to FIG. 5 , in one embodiment, the virtual circuit model 500 of the target electrostatic protection circuit, that is, the ESD device, may include a variable voltage source Vs-V(t) and a variable current source Vs-I(t). The variable current source Vs-V(t) is connected in parallel with the variable voltage source Vs-I(t). Among them, Vs is the amplitude of the electrostatic pulse. In the embodiment shown in Figure 5, in order to prevent the virtual circuit model from short-circuiting the simulation circuit, the internal resistance of the variable voltage source Vs-V(t) can be set to infinity.

When the external voltage at one end of the variable voltage source Vs-V(t) (that is, the voltage between the input terminal and the output terminal of the corresponding ESD device) is Vs, the output voltage of the variable voltage source Vs-V(t) The output current of the variable current source Vs-I(t) forms I(t) that changes with time according to the measured electrostatic protection data corresponding to Vs. When the external voltage Vs changes, the variable voltage source Vs-V(t) automatically adjusts the output voltage according to the current external voltage Vs and the duration of the external voltage Vs. The variable current source Vs-I(t) automatically adjusts the output voltage according to the current external voltage Vs. The external voltage Vs and the duration of the external voltage Vs automatically adjust the output current.

Table 2 is a data representation of the change of the variable voltage source Vs-V(t) with the duration of Vs for an external voltage with an amplitude Vs.

Table 2:

t(ns)	V(t)(V)	t(ns)	V(t)(V)
1.00	0	3.10	2.46

1.10	0.85	3.20	2.6
1.20	0.89	3.30	2.6
1.30	1.23	3.40	2.74
1.40	1.38	3.50	2.5
1.50	1.65	3.60	2.83
1.60	2.04	3.70	2.91
1.70	1.72	3.80	3.05
1.80	1.92	3.90	2.96
1.90	1.91	4.00	3.23
2.00	2	4.10	3.06
2.10	1.81	4.20	3.22
2.20	2.14	4.30	3.57
2.30	2.23	4.40	3.37
2.40	2.32	4.50	3.44
2.50	2.4	4.60	4
2.60	2.31	4.70	3.72
2.70	2.4	4.80	4.06
2.80	2.38	4.90	4.44
2.90	2.35	5.00	4.4
3.00	2.4	​	​

Table 3 is a data representation of the change of the variable current source Vs-I(t) with the duration of Vs for an external voltage with an amplitude Vs.

table 3:

t(ns)	I(t)(mA)	t(ns)	I(t)(mA)
1.00	0	3.10	0.18
1.10	0	3.20	0.23
1.20	0	3.30	0.28
1.30	0.01	3.40	0.32
1.40	0.01	3.50	0.42
1.50	0.02	3.60	0.51
1.60	0.01	3.70	0.6
1.70	0.03	3.80	0.69
1.80	0.04	3.90	0.79
1.90	0.05	4.00	0.88
2.00	0.05	4.10	0.98
2.10	0.06	4.20	1.07
2.20	0.07	4.30	1.16
2.30	0.08	4.40	1.26
2.40	0.08	4.50	1.35
2.50	0.09	4.60	1.43

2.60	0.1	4.70	1.55
2.70	0.11	4.80	1.63
2.80	0.12	4.90	1.73
2.90	0.13	5.00	1.81
3.00	0.14	​	​

For a power supply clamp circuit 21, a parallel variable current source Vs-V can be established directly based on the voltage changes of the power supply VDD and zero potential VSS connected to the power supply clamp circuit 21 and the electrostatic protection measured data of the power supply clamp circuit 21. (t) and the variable voltage source Vs-I(t). It should be noted that due to the different input sources of the TLP test pulses, the variable current source Vs-V(t) of the power supply clamp circuit 21 is different from the variable voltage source. The judgment result of Vs-I(t) on the external voltage Vs and the output current/voltage all have direction information, that is, under the same external voltage Vs, with different sources of electrostatic pulses, the variable current source Vs-V(t ) and the variable voltage source Vs-I(t) may show different changes, which changes can be determined based on the electrostatic protection measured data in step S1.

For a pin protection circuit 22, since it is divided into a first part 221 and a second part 222, the first part 221 and the second part 222 react differently to electrostatic pulses from different sources. Therefore, when establishing a virtual circuit model, it is necessary to consider Voltage changes and current changes to first part 221 and second part 222 for the same electrostatic pulse (eg, a TLP test pulse from input pin IO).

In one embodiment, the first part of the virtual voltage source model Vs-V1(t corresponding to the plurality of preset electrostatic pulses can be established based on the first part of the voltage data across the pin protection circuit 22 obtained during the test process of step S1 ), based on the first part of the discharge current data, the first part of the virtual current source model Vs-I1(t) corresponding to the plurality of preset electrostatic pulses is established. The output voltage V1 of the first part of the virtual voltage source model Vs-V1(t) and the The discharge current I1 of a part of the virtual current source Vs-I1(t) changes with time according to the amplitude and input direction of the preset electrostatic pulse.

Then, a second part of the virtual voltage source model Vs-V2(t) corresponding to the plurality of preset electrostatic pulses is established based on the voltage data across the second part of the pin protection circuit 22 obtained during the test process of step S1. According to The second part of the discharge current data establishes the second part of the virtual current source model Vs-I2(t) corresponding to multiple preset electrostatic pulses, the output voltage of the second part of the virtual voltage source model and the discharge of the second part of the virtual current source. The discharge current changes with time according to the amplitude and input direction of the preset electrostatic pulse.

Finally, according to the first part of the virtual voltage source model Vs-V1(t), the second part of the virtual voltage source model Vs-V2(t), the first part of the virtual current source model Vs-I1(t), the second part of the virtual current source model Vs-I2(t) constructs a virtual circuit model corresponding to the pin protection circuit.

FIG. 6 is a schematic diagram of a virtual circuit model corresponding to the pin protection circuit 22 .

Referring to Figure 6, the virtual circuit model 600 of the pin protection circuit 22 includes three terminals, the first terminal is connected to the input pin IO, the second terminal is connected to the power supply VDD, and the third terminal is connected to the zero potential VSS. At least one of the three terminals of the virtual circuit 600 The voltage and current at one end vary with time for the duration of a preset electrostatic pulse.

Similar to the virtual circuit module of the power clamp circuit 21 , the first part of the virtual voltage source model Vs-V1(t) and the second part of the virtual voltage source model Vs-V2(t) in the virtual circuit module 600 of the pin protection circuit 22 , the first part of the virtual current source model Vs-I1(t), and the second part of the virtual current source model Vs-I2(t) both have direction information, that is, under the same external voltage Vs, with different sources of electrostatic pulses, the Part of the virtual voltage source model Vs-V1(t), the second part of the virtual voltage source model Vs-V2(t), the first part of the virtual current source model Vs-I1(t), the second part of the virtual current source model Vs-I2( t) The output voltage/current shows different direction changes or value changes, and these changes can be determined based on the electrostatic protection measured data in step S1.

After establishing the virtual circuit model of the target electrostatic protection circuit in step S2, the data of the circuit to be simulated including the target electrostatic protection circuit can be processed. First, in step S3, a post-simulation netlist of the circuit to be simulated may be obtained. The circuit to be simulated includes one or more target electrostatic protection circuits. The post-simulation netlist includes one or more third netlists corresponding to the one or more target electrostatic protection circuits. A class of subnet tables. Then, in step S4, the information in the first type subnet table corresponding to each target electrostatic protection circuit is replaced with the information of its corresponding virtual circuit model.

Figure 7 is a schematic diagram of the post-simulation netlist processing of the circuit to be simulated.

Referring to FIG. 7 , the post-simulation netlist 700 includes multiple target electrostatic protection circuits 71 . The multiple target electrostatic protection circuits 71 may be power supply clamp circuits or pin protection circuits. Each target electrostatic protection circuit 71 corresponds to a first-type subnet table. The post-simulation netlist 700 may also include other circuit modules, such as circuit module 1, circuit module 2..., and each circuit module corresponds to a first-type subnet list. That is, the post-simulation netlist 700 includes the first type sub-netlist corresponding to all components in the circuit to be simulated. The first type of subnet list is, for example, a netlist generated based on the SPICE model.

Next, the first sub-net list corresponding to each target electrostatic protection circuit 71 can be set as invalid in the post-simulation netlist 700, and data replacement processing can be performed on each target electrostatic protection circuit 71.

When a target electrostatic protection circuit is a power supply clamp circuit, the virtual circuit model corresponding to the power supply clamp circuit is set between the power supply VDD and zero potential VSS.

When a target electrostatic protection circuit is a pin protection circuit, connect the first end of the virtual circuit model corresponding to the pin protection circuit to the input pin to be protected, the second end to the power supply VDD, and the third end to the zero potential VSS. .

After replacement, the virtual circuit model corresponding to the ESD device in the post-simulation netlist 700 can independently change the output voltage and output current with the external voltage Vs and the duration of the external voltage Vs, which meets the circuit simulation requirements. Other circuit modules connected to the ESD use models corresponding to normal simulation circuits, such as SPICE models.

Therefore, the processed post-simulation netlist 700 as a whole meets the circuit simulation requirements and can realize circuit simulation.

In step S5, the circuit to be simulated is simulated based on the replaced post-simulation netlist.

Figure 8 is a sub-flow chart of step S5 in an embodiment of the present disclosure.

Referring to Figure 8, in one embodiment, during simulation, step S5 may include:

Step S51: Input multiple preset electrostatic pulses to the power supply of the circuit to be simulated to obtain first electrostatic simulation data corresponding to the circuit to be simulated;

Step S52: Input multiple preset electrostatic pulses to the zero potential of the circuit to be simulated to obtain second electrostatic simulation data corresponding to the circuit to be simulated;

Step S53, input a plurality of preset electrostatic pulses in the first direction to each input pin of the circuit to be simulated to obtain third electrostatic simulation data corresponding to the circuit to be simulated;

Step S54, input a plurality of preset electrostatic pulses in a second direction to each input pin of the circuit to be simulated to obtain fourth electrostatic simulation data corresponding to the circuit to be simulated. The second direction is opposite to the first direction.

The plurality of preset electrostatic pulses used in the simulation of step S5 may be exactly the same as the preset electrostatic pulses used in the test of step S1. By using the same preset electrostatic pulse during testing and simulation, the virtual circuit model of the target electrostatic protection device can show the same changes as the measured electrostatic protection data. Of course, in some embodiments, the number of multiple preset electrostatic pulses used in the simulation can also be less than the number of preset electrostatic pulses used in the test to improve simulation efficiency, and the present disclosure does not impose special limitations on this.

In one embodiment, the plurality of preset electrostatic pulses corresponding to the third electrostatic simulation data may be generated based on a human body discharge model (Human Body Model, HBM), for example, and are HBM pulses. Correspondingly, during the test in step S1, the preset electrostatic pulse input to the input pin IO is an HBM pulse with different amplitudes, not a TLP pulse. That is, the amplitude, duration, pulse type, and pulse input port (VDD, VSS, IO) of the electrostatic pulse used in the simulation should be as consistent as possible with the preset electrostatic pulse used in the test, or the preset electrostatic pulse used in the test should be within the range.

Finally, the dynamic voltage distribution diagram of the circuit to be simulated under each preset electrostatic pulse of each input source can be determined based on the first electrostatic simulation data, the second electrostatic simulation data, the third electrostatic simulation data, and the fourth electrostatic simulation data. , based on whether there is a point in the dynamic voltage distribution diagram where the voltage exceeds the corresponding preset value, it is determined whether the electrostatic protection capability of the circuit to be simulated meets the design requirements.

In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

Those skilled in the art will understand that various aspects of the present disclosure may be implemented as systems, methods, or program products. Therefore, various aspects of the present disclosure may be embodied in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which may be collectively referred to herein as "Circuits", "modules" or "systems".

An electronic device 900 according to this embodiment of the present disclosure is described below with reference to FIG. 9 . The electronic device 900 shown in FIG. 9 is only an example and should not impose any limitations on the functions and scope of use of the embodiments of the present disclosure.

As shown in Figure 9, electronic device 900 is embodied in the form of a general computing device. The components of the electronic device 900 may include, but are not limited to: the above-mentioned at least one processing unit 910, the above-mentioned at least one storage unit 920, and a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910).

Wherein, the storage unit stores program code, and the program code can be executed by the processing unit 910, so that the processing unit 910 performs various exemplary methods according to the present disclosure described in the "Example Method" section of this specification. Implementation steps. For example, the processing unit 910 may perform the method shown in the embodiment of the present disclosure.

The storage unit 920 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 9201 and/or a cache storage unit 9202, and may further include a read-only storage unit (ROM) 9203.

Storage unit 920 may also include a program/utility 9204 having a set of (at least one) program modules 9205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.

Bus 930 may be a local area representing one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or using any of a variety of bus structures. bus.

Electronic device 900 may also communicate with one or more external devices 1000 (e.g., keyboard, pointing device, Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with electronic device 900, and/or with Any device that enables the electronic device 900 to communicate with one or more other computing devices (eg, router, modem, etc.). This communication may occur through an input/output (I/O) interface 950. Furthermore, the electronic device 900 may also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through the network adapter 960. As shown, network adapter 960 communicates with other modules of electronic device 900 via bus 930. It should be understood that, although not shown in the figures, other hardware and/or software modules may be used in conjunction with electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives And data backup storage system, etc.

Through the above description of the embodiments, those skilled in the art can easily understand that the example embodiments described here can be implemented by software, or can be implemented by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, a network device, etc.) to execute a method according to an embodiment of the present disclosure.

In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the method described above in this specification is stored. In some possible implementations, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to cause the terminal device to execute the above described instructions. The steps according to various exemplary embodiments of the present disclosure are described in the "Exemplary Methods" section.

The Program Product may take the form of one or more readable media in any combination. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A readable signal medium may also be any readable medium other than a readable storage medium that can send, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical cable, RF, etc., or any suitable combination of the foregoing.

Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., as well as conventional procedural programming. Language—such as "C" or a similar programming language. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on. In situations involving remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., provided by an Internet service). (business comes via Internet connection).

In addition, the above-mentioned drawings are only schematic illustrations of processes included in the methods according to the exemplary embodiments of the present disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal sequence of these processes. In addition, it is also easy to understand that these processes may be executed synchronously or asynchronously in multiple modules, for example.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Industrial applicability

Embodiments of the present disclosure test the time-varying data of the voltage at both ends of the ESD device and the time-varying data of the discharge current under multiple preset electrostatic pulses of different amplitudes, thereby equating an ESD device to a parallel time-varying device. Voltage sources and current sources can overcome the problem that simulation software cannot simulate the foldback characteristics of ESD devices, thereby achieving accurate circuit simulation of the electrical characteristics of ESD devices.

Claims (15)

1. A circuit simulation method, including:

   Obtain measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and multiple preset electrostatic pulses of different amplitudes. The measured electrostatic protection data includes the target electrostatic protection circuit's subsequent activation under the preset electrostatic pulse excitation. Time-varying voltage data and time-varying discharge current data;

   For each target electrostatic protection circuit, establish a virtual circuit model corresponding to the target electrostatic protection circuit one-to-one according to the measured electrostatic protection data;

   Obtain a post-simulation netlist of the circuit to be simulated, the circuit to be simulated includes the one or more target electrostatic protection circuits, and the post-simulation netlist includes one or more target electrostatic protection circuits corresponding to the one or more target electrostatic protection circuits. The first type of subnet table;

   Replace the information in the first type subnet table corresponding to each target electrostatic protection circuit with the information of the corresponding virtual circuit model;

   The circuit to be simulated is simulated based on the replaced post-simulation netlist.
2. The circuit simulation method according to claim 1, wherein said obtaining the measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and a plurality of preset electrostatic pulses of different amplitudes includes:

   Provide the preset electrostatic pulse to the target electrostatic protection circuit for excitation, and sample the voltage value between the input end and the output end of the target electrostatic protection circuit at fixed time intervals within the duration of the preset electrostatic pulse. and a discharge current value, and record the corresponding relationship between the voltage value, the discharge current value, the sampling time and the amplitude of the preset electrostatic pulse.
3. The circuit simulation method of claim 2, wherein, for each target electrostatic protection circuit, establishing a virtual circuit model corresponding to the target electrostatic protection circuit one-to-one according to the measured electrostatic protection data includes:

   The virtual circuit model is configured to output a time-varying output under the preset electrostatic pulse according to the amplitude of the preset electrostatic pulse, the sampling time and its corresponding voltage value and the discharge current value. Variable voltage values and variable current values.
4. The circuit simulation method of claim 3, wherein the virtual circuit model includes a variable voltage source and a variable current source, and the variable current source is connected in parallel with the variable voltage source.
5. The circuit simulation method according to claim 4, wherein the internal resistance of the variable voltage source is set to infinity.
6. The circuit simulation method according to claim 5, wherein the fixed time interval is 0.1 nanoseconds.
7. The circuit simulation method according to any one of claims 1 to 6, wherein the target electrostatic protection circuit includes a power clamp circuit, two ends of the power clamp circuit are respectively connected to the power supply and zero potential, and the acquisition of a Or the measured electrostatic protection data corresponding to multiple target electrostatic protection circuits and multiple preset electrostatic pulses with different amplitudes include:

   Obtain voltage data and discharge current data at both ends of the power supply clamp circuit corresponding to a plurality of preset electrostatic pulses from the power supply;

   Obtain voltage data and discharge current data at both ends of the power clamp circuit corresponding to a plurality of preset electrostatic pulses from the zero potential;

   Wherein, the preset electrostatic pulse, the voltage data at both ends and the discharge current data all include direction information.
8. The circuit simulation method according to claim 7, wherein said replacing the information in the first type subnet table corresponding to each of the target electrostatic protection circuits with the information of the corresponding virtual circuit model includes :

   In the post-simulation netlist, the first subnetlist corresponding to the power clamp circuit is set to invalid;

   The virtual circuit model corresponding to the power supply clamp circuit is set between the power supply and the zero potential.
9. The circuit simulation method according to any one of claims 1 to 6, wherein the target electrostatic protection circuit includes a pin protection circuit, the pin protection circuit includes a first part and a second part, and the first part is connected to an input pin and power supply, the second part is connected to the input pin and zero potential, and obtaining the measured electrostatic protection data corresponding to one or more target electrostatic protection circuits and multiple preset electrostatic pulses of different amplitudes includes:

   Obtain the first part of the voltage data across both ends, the first part of the discharge current data, the second part of the voltage data across both ends of the pin protection circuit corresponding to a plurality of preset electrostatic pulses in the first direction input from the input pin, Part 2 Discharge current data;

   Obtain the first part of the voltage data across both ends, the first part of the discharge current data, the second part of the voltage data across both ends of the pin protection circuit corresponding to a plurality of preset electrostatic pulses input from the input pin in the second direction, The second part of the discharge current data, the second direction is opposite to the first direction;

   Wherein, the preset electrostatic pulse, the first part of the voltage data across both ends, the first part of the discharge current data, the second part of the voltage data across both ends, and the second part of the discharge current data all include direction information.
10. The circuit simulation method according to claim 9, wherein, for each target electrostatic protection circuit, establishing a virtual circuit model corresponding to the target electrostatic protection circuit one-to-one according to the measured electrostatic protection data includes:

    For one of the pin protection circuits, a first partial virtual voltage source model corresponding to the plurality of preset electrostatic pulses is established based on the first partial voltage data across both ends, and a first partial virtual voltage source model corresponding to the plurality of preset electrostatic pulses is established based on the first partial discharge current data. A first partial virtual current source model corresponding to a plurality of preset electrostatic pulses. The output voltage of the first partial virtual voltage source model and the discharge current of the first partial virtual current source are both based on the amplitude and sum of the preset electrostatic pulses. Input direction changes over time;

    A second partial virtual voltage source model corresponding to the plurality of preset electrostatic pulses is established based on the second partial voltage data across both ends, and a second partial virtual voltage source model corresponding to the plurality of preset electrostatic pulses is established based on the second partial discharge current data. Corresponding to the second partial virtual current source model, the output voltage of the second partial virtual voltage source model and the discharge current of the second partial virtual current source vary according to the amplitude and input direction of the preset electrostatic pulse. Change of time;

    A virtual circuit corresponding to the pin protection circuit is constructed according to the first partial virtual voltage source model, the second partial virtual voltage source model, the first partial virtual current source model, and the second partial virtual current source model. Model, the virtual circuit model includes three terminals, the first terminal is connected to the input pin, the second terminal is connected to the power supply, the third terminal is connected to the zero potential, the voltage of at least one terminal of the three terminals of the virtual circuit and current changes over time for the duration of a preset electrostatic pulse.
11. The circuit simulation method according to claim 10, wherein said replacing the information in the first type subnet table corresponding to each of the target electrostatic protection circuits with the information of the corresponding virtual circuit model includes :

    In the post-simulation netlist, the first subnetlist corresponding to the pin protection circuit is set to invalid;

    Connect the first end of the virtual circuit model corresponding to the pin protection circuit to the input pin to be protected, connect the second end of the virtual circuit model to the power supply voltage, and connect the third end of the virtual circuit model Connect to zero potential.
12. The circuit simulation method of claim 1, wherein said simulating the circuit to be simulated based on the replaced post-simulation netlist includes:

    During simulation, input the plurality of preset electrostatic pulses to the power supply of the circuit to be simulated to obtain the first electrostatic simulation data corresponding to the circuit to be simulated;

    Input the plurality of preset electrostatic pulses to the zero potential of the circuit to be simulated to obtain second electrostatic simulation data corresponding to the circuit to be simulated;

    Input the plurality of preset electrostatic pulses in the first direction to each input pin of the circuit to be simulated to obtain third electrostatic simulation data corresponding to the circuit to be simulated;

    The plurality of preset electrostatic pulses in a second direction are input to each input pin of the circuit to be simulated to obtain the fourth electrostatic simulation data corresponding to the circuit to be simulated, and the second direction and the The first direction is opposite.
13. The circuit simulation method of claim 12, wherein the plurality of preset electrostatic pulses corresponding to the third electrostatic simulation data are generated based on a human body discharge model.
14. The circuit simulation method of claim 12, wherein the to-be-simulated electrostatic simulation data is determined based on the first electrostatic simulation data, the second electrostatic simulation data, the third electrostatic simulation data, and the fourth electrostatic simulation data. The dynamic voltage distribution diagram of the circuit under each preset electrostatic pulse of each input source. According to whether there is a point in the dynamic voltage distribution diagram where the voltage exceeds the corresponding preset value, the static electricity of the circuit to be simulated is determined. Whether the protection capability meets the design requirements.
15. An electronic device including:

    memory; and

    A processor coupled to the memory, the processor configured to perform the circuit simulation method of any one of claims 1-14 based on instructions stored in the memory.

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