WO2024011603A1

WO2024011603A1 - Chip package structure, electronic device, and packaging method of chip package structure

Info

Publication number: WO2024011603A1
Application number: PCT/CN2022/106047
Authority: WO
Inventors: 蒋尚轩; 孙梦龙; 马泽宇
Original assignee: 华为技术有限公司
Priority date: 2022-07-15
Filing date: 2022-07-15
Publication date: 2024-01-18

Abstract

Embodiments of the present application relate to the technical field of chip packaging, and provide a chip package structure, an electronic device, and a packaging method of the chip package structure, which can improve the reliability of a chip interconnection structure. The chip package structure comprises: a first die, a second die, and an interposer; the interposer comprises a first redistribution layer, a buried die, a plastic package body, and a dielectric layer, the first die and the second die are disposed on a first surface of the first redistribution layer, the buried die is disposed on a second surface of the first redistribution layer, and the buried die is wrapped by the plastic package body disposed on one side of the second surface; pins are provided on one side of a passive surface of the buried die; the dielectric layer is disposed on the side of the plastic package body away from the first redistribution layer, solder bumps are provided on the side of the dielectric layer away from the plastic package body, and the pins pass through the dielectric layer and are in contact with the solder bumps. In this way, the pins passing through the dielectric layer are in direct contact with the solder bumps, thereby achieving interconnection between the buried die and the solder bumps.

Description

Chip packaging structure, electronic equipment and packaging method of chip packaging structure

Technical field

The present application relates to the field of chip packaging technology, and in particular, to a chip packaging structure, electronic equipment and a packaging method of the chip packaging structure.

Background technique

As the demand for computing power from high-speed data communications and artificial intelligence surges, it not only challenges the density of chip integration, but also requires continuous shrinkage of package size, which has given rise to many chip packaging forms.

For example, Figure 1 shows a silicon bridge across fanout package (SBAFOP) structure. In this packaging structure, as shown in FIG. 1 , the first die 11 and the second die 22 are integrated on a silicon interposer 2 , and the silicon interposer 2 is disposed on the substrate 3 through solder joints 5 . Among them, the silicon interposer 2 includes a through silicon via (TSV) 22 that penetrates the silicon wafer and a wiring layer 21 formed on the TSV 22 . The signal interconnection between the first die 11 and the second die 22 is realized through the wiring layer 21 in the silicon interposer 2 , and the signal interconnection between the first die 21 or the second die 22 and the peripheral circuit is through the silicon interposer. Routing layer 21 and TSV22 are implemented in layer 2.

On the basis of what is shown in Figure 1, if it is necessary to increase the chip interconnection integration density, the die can be buried in the silicon interposer 2. However, such a design will not only increase the reliability of the interconnection structure between the buried die and the solder joints 5 Raising challenges will also pose challenges to the packaging process of this structure.

Contents of the invention

Embodiments of the present application provide a chip packaging structure, an electronic device including the chip packaging structure, and a packaging method of the chip packaging structure.

This application is mainly designed for multi-chip packaging. This chip packaging structure can not only improve the reliability of the interconnection between buried bare chips and peripheral circuits, but also reduce the difficulty of the preparation process; in addition, it can also increase the chip interconnection integration density. , without making the package size larger.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In the first aspect, this application provides a chip packaging structure, that is, the chip packaging structure is a multi-chip module (MCM) package. This MCM package can effectively shorten the length of interconnection traces between chips, providing feasibility for high-density packaging.

The chip packaging structure may include: a first die and an interposer; wherein the interposer includes a buried die and a plastic package, as well as a dielectric layer, the embedded die is wrapped by the plastic package, and the first die is disposed on opposite sides of the plastic package. One of the two sides, and the first bare chip is electrically connected to the buried bare chip, and the dielectric layer is provided on the other side of the opposite sides of the plastic package; the passive surface of the buried bare chip faces away from the first bare chip, and the buried bare chip Pins are provided on one side of the passive surface, and solder joints are provided on the side of the dielectric layer away from the plastic package. The pins penetrate the dielectric layer and are in contact with the solder joints.

In the chip packaging structure given in this application, the pins embedded in the die penetrate the dielectric layer and contact the solder joints to achieve electrical connection. For example, when the pins and solder joints are both made of copper material, this kind of electrical connection is achieved. The connected structure can be called a Cu-Cu interconnection structure. Compared with some implementations in which pins and solder joints are interconnected through solder joints, this application can avoid the solder connection structure in the process flow. The phenomenon of hollow inside appears due to high temperature. Therefore, the Cu-Cu interconnection structure provided in this application is more reliable and stable. In addition, this application does not require the use of thermal compression bonding (TCB) technology or thermal compression non-conductive film (TCNCF) technology, which is difficult to process, to realize the interconnection of pins and solder joints. , but the photolithography process can be used to bring the pins into contact with the solder joints. Furthermore, this application can also reduce the process difficulty.

In one possible way, along the thickness direction of the dielectric layer, a window is opened in the dielectric layer through the dielectric layer; the orthographic projection of the embedded die on the dielectric layer is located within the edge of the window; the pins are located at the edge of the window inside to make contact with the solder joints.

In the process flow that can be realized, a dielectric layer can be formed on the carrier board first, and then a window can be opened in the dielectric layer to place the pins of the buried die in the window. Finally, the dielectric layer can be connected with the pins located on one side of the dielectric layer. solder joint contact.

In addition, since the orthographic projection of the buried bare chip on the dielectric layer is located within the edge of the window, in this case, a certain installation tolerance can be given to the buried bare chip, that is, a certain offset amount can be given to the buried bare chip, which facilitates the rapid placement of the buried bare chip. The pins of the chip are set inside the window to improve assembly efficiency.

In one possible way, the pins located in the window are wrapped by a protective layer, and the space between the protective layer and the inner wall of the window is filled with a plastic encapsulation body.

The pins here are wrapped in a protective layer, and a plastic seal is filled between the protective layer and the inner wall of the window to improve the reliability and stability of the buried die.

In an implementable manner, the interposer further includes: a first rewiring layer and a second die; the first rewiring layer is formed on a side of the plastic package close to the first die, and the first die and The second die are both disposed on the first redistribution layer.

The chip packaging structure provided in this application includes at least three chips, such as a first die, a second die and a buried die. Both the first die and the second die can be integrated in the first rewiring on the first surface of the layer, and the buried die may be disposed on the second surface of the first redistribution layer, that is, the first die and the second die are located on the same side, and the buried die may be disposed on the first Opposite sides of the redistribution layer, rather than arranging these dies on the same surface of the first redistribution layer. In this way, not only can the chip interconnection integration density be increased, but the size of the entire package structure will not be increased due to the increase in chip integration density. This size can be understood as the size in the direction parallel to the interposer.

Furthermore, in this application, the interconnection between the first die and the second die can be achieved through the first rewiring layer, and the interconnection between the first die or the second die and the peripheral circuit can be achieved through the first rewiring layer. Routing layers, buried die and solder joint implementation.

In an implementable manner, the interposer further includes conductive pillars; the conductive pillars penetrate the plastic package and electrically connect the first rewiring layer and the solder joints.

In this embodiment, the electrical connection path between the first die or the second die and the peripheral circuit can be realized not only by burying the die, but also by conducting conductive pillars. On the basis of achieving increased multi-chip integration density, It can also improve the transmission efficiency of the chip.

In an implementable manner, the buried die includes a substrate and an active layer formed on the substrate. A conductive channel electrically connected to the active layer runs through the substrate, and the conductive channel is electrically connected to the pin; The bottom surface facing away from the active layer is a passive surface, and the active layer is close to the first rewiring layer and is electrically connected to the first rewiring layer.

In an implementable manner, pins are provided on a side of the active layer facing away from the substrate, and the pins are electrically connected to the first rewiring layer.

It can be understood that the buried die can be electrically connected to the first rewiring layer through pins on the active layer.

In an implementable manner, the chip packaging structure further includes a substrate; the substrate is disposed on a side of the interposer away from the first die and the second die, and the solder joints are electrically connected to the substrate.

In the second aspect, this application also provides a chip packaging structure, which also belongs to a multi-chip module (MCM) package.

The chip packaging structure includes: a first bare chip and an interposer; wherein the interposer includes a buried die and a plastic package, as well as a connection layer; the embedded die is wrapped by the plastic package; the first die is arranged on opposite sides of the plastic package One side of the plastic package, and the first die is electrically connected to the buried die, the connection layer is provided on the other side of the opposite sides of the plastic package, and the side of the connection layer facing away from the plastic package is provided with solder joints; the buried die The passive surface of the die is away from the first die, and pins are provided on one side of the passive surface of the buried die; the connection layer includes a first dielectric layer stacked on the plastic package, and the pins and solder joints are located opposite to the first dielectric layer. On both sides; there is a first conductive hole penetrating through the first dielectric layer, and the pin is in contact with the first conductive hole.

In this application, the pins of the buried die are in contact with the conductive holes in the first dielectric layer. In an achievable process flow, after the pins embedded in the die are exposed, a dielectric layer containing conductive holes can be formed so that the pins are in contact with the conductive holes. In some examples, solder joints are then provided on the side of the dielectric layer containing conductive holes away from the buried die, so that the pins pass through the conductive holes and can be electrically connected to the solder joints.

Compared with some implementation methods that use solder joints to interconnect pins and solder joints, this application can avoid the phenomenon that the solder joint structure has hollow inside due to high temperature during the process flow. Therefore, this application provides The resulting interconnection structure is more reliable and stable. In addition, this application does not require the use of thermal compression bonding (TCB) technology or thermal compression non-conductive film (TCNCF) technology, which is difficult to process, to realize the interconnection of pins and solder joints. , instead, the photolithography process can be used to form conductive holes in the dielectric layer so that the pins are in contact with the solder joints. Furthermore, this application can also reduce the process difficulty.

In an implementable manner, the soldering point is provided on a side of the first dielectric layer facing away from the plastic package, and the first conductive hole is in contact with the soldering point.

In an achievable process flow, after the pins of the buried die are exposed, a dielectric layer containing conductive holes can be formed, and then solder joints are set on the side of the dielectric layer away from the buried die so that the pins and the solder joints are in contact with the conductive holes respectively.

In an implementable manner, the connection layer further includes: a multi-layer metal trace formed on the first dielectric layer facing away from the plastic package, and a second dielectric layer spaced between two adjacent layers of metal traces. A second conductive hole for electrically connecting the metal traces penetrates through the two dielectric layers, so that the connection layer forms a second rewiring layer; the solder joint is arranged on the side of the second rewiring layer facing away from the plastic package, and the pin passes through the second rewiring layer. The rewiring layer is electrically connected to the solder joints.

That is, the pins and solder joints are located on opposite sides of the second rewiring layer and are interconnected through the second rewiring layer.

In the multi-chip packaging structure given in this application, similar to the multi-chip packaging structure given above, the first die and the second die located on the same side are arranged on two opposite sides of the first rewiring layer with the buried die. side, rather than arranging these dies all on the same surface of the first redistribution layer. In this way, not only can the chip interconnection integration density be increased, but the size of the entire package structure will not be increased due to the increase in chip integration density.

In an implementable manner, the interposer further includes conductive pillars, the conductive pillars penetrate the plastic package, and the conductive pillars are electrically connected to the solder joints through the second rewiring layer.

The first bare chip or the second bare chip in this embodiment can also be electrically connected to the peripheral circuit through the conductive pillars, and the conductive pillars are electrically connected to the solder joints through the rewiring layer.

In an implementable manner, the buried die includes a substrate and an active layer formed on the substrate, a conductive channel electrically connected to the active layer runs through the substrate, and the conductive channel is electrically connected to the pin; The surface of the substrate facing away from the active layer is a passive surface. The active layer is close to the first rewiring layer and is electrically connected to the first rewiring layer.

In a third aspect, the present application also provides a chip packaging structure, which is also a multi-chip module packaging.

The chip packaging structure may include: a first die and an interposer; wherein the interposer includes a buried die and a plastic package, and the embedded die is wrapped by the plastic package; the first die is disposed on one of the opposite sides of the plastic package. side, and the first bare chip is electrically connected to the buried bare chip; the passive surface of the buried bare chip faces away from the first bare chip, and pins are provided on one side of the passive surface of the buried bare chip; the side of the plastic package facing away from the first bare chip A solder joint is provided on one side; at least part of the pin is exposed outside the plastic package and contacts the solder joint located outside the plastic package.

In the chip packaging structure provided in this application, there is no dielectric layer or wiring layer, but the pins embedded in the die are exposed outside the plastic package to contact the solder joints.

Similarly, when packaging the chip packaging structure given in this application, there is no need to use thermal compression bonding (TCB) technology or thermal compression non-conductive film (thermal compression non-conductive film), which is difficult to process. , TCNCF) technology realizes the interconnection of pins and solder joints, but makes the pins and solder joints contact, improves the reliability of the interconnection structure, and can also reduce process difficulty.

In an implementable manner, the interposer further includes conductive pillars; the conductive pillars penetrate the plastic package and are at least partially exposed outside the plastic package, and are in contact with the solder joints located outside the plastic package.

Since in this embodiment, no dielectric layer or other film layer structure is provided, part of the conductive pillar can be extended outside the plastic package and directly contacted with the solder joint.

In a fourth aspect, this application also provides a packaging method of a chip packaging structure for preparing a chip packaging structure, wherein the packaging method of the chip packaging structure includes:

Form a dielectric layer on the carrier board;

Create a window in the dielectric layer that penetrates the dielectric layer;

A buried bare chip is provided, and the passive surface of the buried bare chip is provided with pins, and the pins are located in the window;

Forming a plastic encapsulation body so that the embedded die is wrapped by the plastic encapsulation body;

Remove the carrier board to expose the pins;

A solder joint is provided on the side of the dielectric layer facing away from the plastic package, so that the pins located in the window are in contact with the solder joint.

Based on the packaging method of the chip packaging structure mentioned above, it can be seen that: a dielectric layer can be set on the carrier board first, and then a window can be opened in the dielectric layer. After setting the buried die and removing the carrier board, the die can be buried. The pins will be exposed through the opening, and then the solder joints will be set so that the pins and solder joints are in contact. That is to say, when performing the step of setting the solder joints, there is no need to use thermal compression bonding (TCB) technology or thermal compression non-conductive film (TCNCF) technology. Instead, the photolithography process can be used. First, from a process perspective, the hot press bonding or hot press non-conductive film process is more difficult than the laser etching process. Second, from the perspective of product performance, it is difficult to use hot press bonding or hot press non-conductive film processes. The obtained first pin is electrically connected to the solder joint through the solder connection structure. The material of the solder connection structure is different from the material of the first pin and the solder joint. In the subsequent high-temperature process of the sealed structure, the solder connection Due to the high temperature, the structure becomes hollow inside, which reduces the reliability and stability of the interconnection structure.

Therefore, when the chip packaging structure is prepared by the packaging method of the present application, it will not only improve the reliability of the interconnection between pins and solder joints, but also reduce the process difficulty of the packaging method.

In one possible way, when a window penetrating the dielectric layer is opened in the dielectric layer, the orthographic projection of the embedded die on the dielectric layer is located within the edge of the window. To facilitate the placement of buried dies.

In one possible way, arranging the embedded bare chip includes: using an adhesive layer to fix the pins of the buried bare chip in the window.

That is, an adhesive layer with a simple process can be used to place the embedded die in the window.

In an implementable manner, after forming the plastic package, the packaging method further includes: forming a first rewiring layer on the plastic package; and arranging a first die and a second die on the first rewiring layer.

The first die and the second die may be interconnected through a first rewiring layer. Furthermore, the first bare chip or the second bare chip may realize signal interconnection with the peripheral circuit by burying the bare chip.

In one possible implementation, before forming the plastic package, the packaging method further includes: arranging conductive pillars on the carrier board, so that the first rewiring layer is electrically connected to the solder joints through the conductive pillars.

With this design, the first bare chip or the second bare chip can also be electrically connected to the peripheral circuit through the conductive pillars.

In a fifth aspect, this application also provides a packaging method of a chip packaging structure for preparing a chip packaging structure, wherein the packaging method of the chip packaging structure includes:

A buried die is provided on the carrier board, and pins are provided on the passive surface of the buried die, and the pins are located above the carrier board;

Remove the carrier board to expose the pins;

A first dielectric layer is formed on one side of the plastic package, and a first conductive hole penetrates the first dielectric layer so that the pins are in contact with the first conductive hole.

In the packaging method of the chip packaging structure given in this application, after the pins of the buried die are exposed, a dielectric layer containing conductive holes can be formed, and the pins are in contact with the conductive holes. In the process flow that can be realized, the photolithography process can be used to form the conductive holes, and there is no need to use hot-press bonding or hot-press non-conductive film processes. Furthermore, there will be no need for the pins to be electrically connected to the solder joints through the solder connection structure. interconnect structure.

In an implementable manner, after the first dielectric layer is formed, the packaging method further includes: arranging solder joints on a side of the first dielectric layer facing away from the plastic package, so that the first conductive holes are connected to the pins and solder joints respectively. touch.

That is, the pins and solder joints are electrically connected through conductive holes penetrating the dielectric layer.

In an implementable manner, after forming the first dielectric layer, the packaging method further includes: forming a multi-layer metal trace on a side of the first dielectric layer facing away from the plastic package, with two adjacent layers of metal traces separated by The second dielectric layer is spaced apart, and a second conductive hole for electrically connecting the metal traces penetrates through the second dielectric layer, so that the structure including the first dielectric layer, the multi-layer metal traces and the second dielectric layer forms a second dielectric layer. Wiring layer; set solder joints on the side of the second rewiring layer facing away from the plastic package, so that the pins are electrically connected to the solder joints through the second rewiring layer.

In this embodiment, the formed second rewiring layer is used to interconnect the pins of the buried die and the solder joints.

In an implementable manner, the packaging method further includes: arranging conductive pillars on the carrier board, so that the conductive pillars are electrically connected to the solder joints through the second rewiring layer.

In one possible way, arranging the embedded die on the carrier board includes: using an adhesive layer to fix the pins of the embedded die above the carrier board.

In a sixth aspect, this application also provides a packaging method of a chip packaging structure for preparing a chip packaging structure, wherein the packaging method of the chip packaging structure includes:

Remove the carrier board to expose the pins;

Set solder joints on one side of the plastic package so that the pins are in contact with the solder joints.

In the packaging method of the chip packaging structure given in this application, the pins of the buried bare chip are exposed. In the process flow that can be realized, the solder joints can be formed so that the solder joints are in direct contact with the pins. There is no need to use hot-press bonding or hot-press non-conductive film processes, and furthermore, there is no interconnection structure in which the pins are electrically connected to the solder joints through the solder connection structure.

In an implementable manner, the packaging method further includes: arranging conductive pillars on the carrier board; when exposing the pins, the conductive pillars are exposed so that the conductive pillars are in contact with the solder joints.

In a seventh aspect, the present application also provides an electronic device, which includes a printed circuit board and a chip packaging structure in any of the above implementations, and the chip packaging structure is disposed on the printed circuit board and connected with the printed circuit board. Circuit board electrical connections.

The electronic device provided by the embodiment of the present application includes the chip packaging structure in any of the above implementations. Therefore, the electronic device provided by the embodiment of the present application and the chip packaging structure of the above technical solution can solve the same technical problem and achieve the same expected effect. .

Description of drawings

Figure 1 is a schematic structural diagram of a chip packaging structure in the prior art;

Figure 2 is a schematic diagram of a partial structure of an electronic device;

Figure 3 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 4 is a schematic structural diagram of an interposer in a chip packaging structure according to an embodiment of the present application;

Figures 5a to 5c are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;

Figure 6 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 7 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 8 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 9 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 10 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 11 is a schematic structural diagram of an interposer in a chip packaging structure according to an embodiment of the present application;

Figure 12 is a top view of a dielectric layer with windows in a chip packaging structure according to an embodiment of the present application;

Figure 13 is a flow chart of a packaging method of a chip packaging structure according to an embodiment of the present application;

Figures 14a to 14h are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;

Figure 15 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 16 is a schematic structural diagram of an interposer in a chip packaging structure according to an embodiment of the present application;

Figure 17 is a flow chart of a packaging method of a chip packaging structure according to an embodiment of the present application;

Figures 18a to 18f are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;

Figure 19 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 20 is a schematic structural diagram of an interposer in a chip packaging structure according to an embodiment of the present application;

Figure 21 is a flow chart of a packaging method of a chip packaging structure according to an embodiment of the present application;

Figures 22a to 22g are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;

Figure 23 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 24 is a schematic structural diagram of an interposer in a chip packaging structure according to an embodiment of the present application;

Figure 25 is a flow chart of a packaging method of a chip packaging structure according to an embodiment of the present application;

26a to 26g are schematic structural diagrams of the corresponding structures after completion of each step in the method for manufacturing the chip packaging structure according to the embodiment of the present application.

Reference signs:

100-PCB;

200-Electrical connection structure;

300-Chip packaging structure, chip packaging structure;

400-radiator;

11-The first die;

12-Second die;

13-The third bare chip, the buried bare chip; 131-substrate; 132-circuit layer; 133-conductive channel; 134, 136-pins; 135-protective layer;

14-Fourth die;

2-Silicon interposer; 21-Wiring layer; 22-TSV;

3-Substrate;

4-intermediate board; 41-first rewiring layer; 42-plastic package; 43-conductive pillar; 44-dielectric layer; 441-window; 442-conductive hole; 45-soldering pad; 46-solder connection structure; 47 -The second rewiring layer; 48-conductive via;

5-solder joint;

6. 811, 812-carrier board;

7. 821, 822-bonding layer;

831, 832-Barrier layer.

Detailed ways

An embodiment of the present application provides an electronic device, which may be a communication device or other electronic device. For example, it can include a server, a data center, or other interconnected communication equipment. For another example, the electronic device may include a mobile phone, a tablet, a smart wearable product (such as a smart watch, a smart bracelet), a virtual reality (VR) device, or augmented reality. AR), or devices such as household appliances. The embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.

As shown in FIG. 2 , various electronic devices such as those described above may include a printed circuit board (PCB) 100 and a chip packaging structure 300 . The chip packaging structure 300 is electrically connected to the PCB 100 through the electrical connection structure 200, so that the chip packaging structure 300 can achieve signal interconnection with other chips or other electronic modules on the PCB 100.

In addition, as shown in FIG. 2 , the electronic device may also include a heat sink 400 . The heat sink 400 covers the chip packaging structure 300 and other electronic modules on the PCB 100 , and is fixedly connected to the PCB 100 . The heat sink 400 here serves as a heat dissipation structure and can dissipate and cool down the chip packaging structure 300 and other electronic modules on the PCB 100 . In addition, the heat sink 400 can also provide physical protection to the chip packaging structure 300 .

In alternative embodiments, the electrical connection structure 200 may include a plurality of solder balls, such as a ball grid array (BGA), or may include a plurality of metal pillars.

With the development of the fourth generation of wireless communications technologies (4G) to the fifth generation of mobile communication technologies (5th generation of wireless communications technologies, 5G), the chip interaction in the chip packaging structure 300 of Figure 2 above The integration density is getting higher and higher, that is, the chip packaging structure 300 is a structure in which multiple dies are packaged together. Such a chip packaging structure can be called a chip packaging structure, or it can also be called a chip packaging structure. It is a multi-chip module (MCM) packaging structure.

In some examples, the chip package structure 300 may be a processor, for example, it may include a dynamic random access memory (dynamic random access memory, DRAM) and a system on chip (SOC); for another example, it may also include a system on a chip. SOC and analog chips, etc., or may also include analog chips and other digital chips, etc.

FIG. 3 shows a schematic structural diagram of a chip packaging structure 300. The chip packaging structure 300 includes a first die 11 and a second die 12. The first die 11 and the second die 12 are disposed on an interposer 4. The interposer 4 may also be called an interposer. ). Furthermore, the interposer 4 includes a third die 13. Since the third die 13 is embedded in the interposer 4, the third die 13 may also be called a buried die, or may be called an embedded die. Therefore, such an interposer board 4 can also be called an EB die Interposer.

Continuing to refer to FIG. 3 , the interposer 4 carrying the first die 11 , the second die 12 and the third die 13 is then disposed on the substrate 3 through solder joints 5 to form a chip packaging structure including at least three chips. . For example, the first die 11 may be a dynamic random access memory DRAM, the second die 12 may be a system on a chip, and the third die 13 may be other digital chips, etc.

The substrate 3 shown in FIG. 3 may be a packaging substrate (substrate), or it may also be a PCB board.

The specific structures that can be implemented by the interposer board 4 will be introduced below with reference to FIGS. 3 and 4 , where FIG. 4 is a schematic structural diagram of the interposer board 4 in FIG. 3 .

Combining Figures 3 and 4 together, the interposer 4 includes a first redistribution layer (RDL) 41. The first redistribution layer 41 has an opposite first surface A1 and a second surface A2, as shown in Figure 3 , the first die 11 and the second die 12 are disposed on the first surface A1 of the first rewiring layer 41, so that the first die 11 and the second die 12 can be realized through the first rewiring layer 41 interconnections between. The third bare chip 13 is disposed on the second surface A2 of the first rewiring layer 41 and is electrically connected to the first rewiring layer 41 . In this case, the first die 11 and the third die 13 can also be interconnected through the first rewiring layer 41 , or the second die 12 and the third die 13 can be implemented through the first rewiring layer 41 Alternatively, the first die 11 and the second die 12 can be interconnected with the third die 13 through the first rewiring layer 41 .

As shown in FIGS. 3 and 4 , since some of the plurality of die are integrated on one side of the first rewiring layer 41 and the other part of the die are integrated on the other side of the first rewiring layer 41 , For example, the first die 11 and the second die 12 are disposed on the first surface A1 of the first rewiring layer 41 , and the third die 13 is disposed on the second surface A2 of the first rewiring layer 41 . Such a design can not only increase the chip integration density of the packaging structure, but also prevent the size of the packaging structure from becoming larger due to the increase in chip integration density. Therefore, the packaging structure shown in Figure 3 can not only increase chip integration density, but also meet the requirements of continuous shrinkage of packaging structure size.

Referring again to Figures 3 and 4, the interposer 4 is electrically connected to the substrate 3 through the solder joints 5. Then, at least one chip among the first die 11, the second die 12 and the third die 13 can pass through the solder joints. 5. Electrically connected to the peripheral circuit provided on the substrate 3.

As shown in FIG. 4 , the third die 13 includes a substrate 131 and a circuit layer 132 formed on the substrate 131 . The circuit layer 132 faces the first rewiring layer 41 and is electrically connected to the first rewiring layer 41 . There is a conductive channel 133 penetrating through the substrate 131. For example, when the substrate 131 is a silicon-based substrate, the conductive channel 133 may be a through silicon via (TSV). A pin 134 is formed on a side of the substrate 131 away from the circuit layer 132 , and the pin 134 is electrically connected to the conductive channel 133 . That is, the third die 13 shown in Figure 4 is an EB die structure with TSV. In an implementation structure, the EB die can be used as a signal transmission path for the first die 11 and the second die 12 to be electrically connected to the peripheral circuit.

In the packaging process that can be realized, when the third die 13 is buried in the interposer 4, it will involve the formation of some interconnection structures, as shown in Figure 5a, Figure 5b and Figure 5c, wherein Figure 5a, Figure 5b and Figure 5c shows the process flow when setting the third die 13 of EB die.

As shown in Figure 5a, a bonding layer 7 is first formed on the carrier board 6, and then a dielectric layer 44 is formed on the bonding layer 7, and a bonding pad 45 is provided on the side of the dielectric layer 44 away from the carrier board 6. For example, the bonding pad 45 can be made of copper material.

See Figure 5b, and then set the third die 13, and connect the pins 134 of the third die 13 to the pad 45 through the solder joint 46.

See Figure 5c, remove the carrier board 6, and then set the solder joint 5 so that the signal of the third bare chip 13 can be electrically connected to the solder joint 5 through the solder joint 46, the pad 45. That is, the interconnection structure between the third chip 13 and the solder point 5 at least includes: the solder connection structure 46 and the soldering pad 45 .

Among them, as shown in Figure 5b, among the optional process methods, when connecting the pin 134 of the third die 13 to the pad 45, thermal compression bonding (thermal compression bonding, TCB) technology or thermal compression is usually used. Thermal compression non conductive film (TCNCF) technology, in turn, will form the solder joint structure shown in Figure 5b between the pin 134 and the pad 45.

The embodiment of the present application also provides some chip packaging structures, as shown in FIG. 6 , which is a schematic structural diagram of another chip packaging structure 300 provided by the embodiment of the present application.

The difference between the chip packaging structure 300 shown in FIG. 6 and the chip packaging structure 300 shown in FIG. 3 is that the structure for interconnecting the third die 13 and the solder joint 5 is different. The following will focus on the structure shown in FIG. 6 The interconnection structure is introduced in detail.

As shown in FIG. 6 , the first die 11 and the second die 12 are arranged on the first rewiring layer 41 through two-dimensional integration. In some implementation structures, multiple die may be stacked on the first die 11 or the second die 12 to form a three-dimensional stacked structure.

In other implementation structures, in order to further improve the chip integration density of the package structure, a fourth die, a fifth die, or more die may also be included. These fourth die and fifth die may be Like the third bare chip 13, it is buried in the interposer 4 as an EB die structure. For example, the third die, the fourth die, and the fifth die are embedded in the interposer 4 in a two-dimensional integrated manner. For example, as shown in FIG. 7 , in the chip packaging structure 300 shown in FIG. 7 , not only the first die 11 , the second die 12 and the third die 13 are shown, but also the fourth die is shown. 14, and the third die 13 and the fourth die 14 are both buried in the interposer 4 to further increase the chip integration density of the package structure.

Continuing to refer to FIGS. 6 and 7 , the third die 13 embedded in the interposer 4 may be an active chip or a passive chip.

When the third die 13 is an active chip, as shown in FIG. 6 , the circuit layer 132 provided on the substrate 131 includes an active layer with active devices such as transistors, so that the buried die 13 is a functional chip. , for example, it can be a memory, etc. When the third die 13 is a passive chip, the circuit layer 132 does not include a circuit structure that can implement the function, that is, the third die 13 can implement the first die 11 and/or the second die 12, Vertical power supply to other modules on base plate 3.

Furthermore, continuing to refer to FIGS. 6 and 7 , the interposer 4 further includes a plastic package 42 , and the embedded die 13 is wrapped by the plastic package 42 to protect the third die 13 .

In addition, the first die 11 and the second die 12 provided on the first rewiring layer 41 can also be wrapped by a plastic package provided on the first surface A1 side of the first rewiring layer 41 to cover the first rewiring layer 41 with a plastic package. The first die 11 and the second die 12 play a protective role.

As shown in Figures 6 and 7, the plastic package 42 wrapping the third die 13, or the plastic package including the first die 11 and the second die 12, can not only play a protective role, but also act as an electromagnetic shielding function to protect these bare chips from interference from external electromagnetic radiation.

In another embodiment, as shown in FIG. 8 , FIG. 8 is a schematic structural diagram of another multi-chip packaging structure 300 according to an embodiment of the present application. In this chip packaging structure, the interposer 4 also includes an electrical connection structure, such as the conductive pillar 43 shown in FIG. 8 . In the example, the conductive pillar 43 may be a copper pillar. One end of the conductive pillar 43 is electrically connected to the first rewiring layer 41 , and the other end is electrically connected to the solder point 5 . The first rewiring layer 41 can be electrically connected to the substrate 3 through the conductive pillar 43 and the solder point 5 . In this way, the signal transmission path through which the first die 11 and the second die 12 are electrically connected to the peripheral circuit can not only pass through the third die 13 but also through the conductive pillar 43. Such an output path can also be called a vertical output path. transmission. By adopting the vertical transmission using the conductive pillars 43 and the third die 13 as shown in FIG. 8 , the signal transmission efficiency of the first die 11 and the second die 12 can be improved.

In some examples, while keeping the size of the package unchanged, the number of conductive pillars 43 can be reduced to dispose the fourth die 14 as shown in FIG. 9 in the area avoided by the conductive pillars 43 . Because after the fourth die 14 is integrated, it will not only increase the integration density, but also take into account the power supply function of the conductive pillars 43 to realize the interconnection between the first die 11 and the second die 12 and peripheral circuits.

Figure 10 is a structural diagram of another chip packaging structure according to an embodiment of the present application. The difference from the embodiment shown in Figure 6 is that in Figure 10, the interposer 4 is used to electrically connect the first bare chip The interconnection structure between 11 and the buried die 13 is a conductive via 48 penetrating through the dielectric layer, for example, it can be a through-silicon TSV.

That is, a film layer structure with silicon through hole TSV can be provided on one side of the plastic package 42 in which the embedded die 13 is embedded, and the first die 11 is formed on the film layer structure, so that the first die 11 The TSV is electrically connected to the buried die 13 through silicon through holes.

In other structures that can be implemented, other bare dies may also be provided on the film structure with conductive vias 48 shown in FIG. 10 , for example, electrically connected to the first die 11 may be provided in a two-dimensional integrated manner. Second die.

Figure 11 shows a structure in which the third bare chip 13 and the solder joint 5 are interconnected in the above-mentioned Figures 6, 7, 8, 9 and 10, and Figure 11 is based on the structure shown in Figure 8. An example is used to illustrate the interconnection structure between the third die 13 and the solder joint 5. Of course, the embodiment shown in FIG. 10 can also be used as an example for explanation.

As shown in FIG. 11 , a dielectric layer 44 is provided on the side of the plastic package 42 facing away from the first rewiring layer 41 , and the solder joints 5 for electrical connection with the substrate 3 are provided on a side of the dielectric layer 44 facing away from the plastic package 42 . side, and the pins 134 of the third die 13 penetrate the dielectric layer 44 and are electrically connected to the solder joints 5 by touching.

That is, the pin 134 is in direct contact with the solder point 5, realizing the interconnection between the pin 134 and the solder point 5. In some structures that can be implemented, pin 134 can be a copper pillar (Cu pillar), and solder point 5 can be a controlled collapse chip connection solder joint (C4). Then, use the interconnection shown in Figure 11 The structure realizes the direct interconnection of Cu and Cu. Compared with the structures shown in Figures 3 and 4 above, at least the solder joint structure formed by thermocompression bonding TCB technology or thermocompression non-conductive film TCNCF technology is omitted.

Continuing to refer to FIG. 11 , FIG. 11 shows one of the implementation ways for the pins 134 of the third die 13 to penetrate the dielectric layer 44 . For example, a penetration can be opened in the dielectric layer 44 along the thickness direction L of the dielectric layer 44 . The pin 134 is disposed in the window 441 of the dielectric layer 44 to contact the solder joint 5 , thereby realizing the electrical connection between the pin 134 and the solder joint 5 .

In order to protect the pins 134 of the third die 13, in some embodiments, as shown in FIG. 11, a protective layer 135 can be provided, and the protective layer 135 is used to wrap the plurality of pins 134 arranged in the array.

The protective layer 135 may include materials such as die attach film (Die Attach Film, DAF), non-conductive adhesive film (Non-Conductive Adhensive Film, NCF).

Continuing to refer to FIG. 11 , since the opening 441 is used to set the third die 13 , for example, the third die 13 has a rectangular structure. Therefore, a rectangular structure as shown in FIG. 12 will be opened in the dielectric layer 44 . Window 441, wherein FIG. 12 shows a top view of the dielectric layer 44 with the window 441.

The long side dimension of the window 441 shown in Figure 12 is d1, and the short side dimension is d2. In some implementation processes, the long-side dimension d1 of the window 441 may be larger than the long-side dimension D1 of the third die 13 shown in FIG. 11 , and the short-side dimension d2 of the window 441 may also be larger than the third die 13 shown in FIG. 11 . The short side size of the die 13 can be understood as: the orthographic projection of the third die 13 on the dielectric layer 44 is located within the boundary of the window 441, or it can be said that the cross-sectional area of the third die 13 is smaller than the window. cross-sectional area. In addition, in other implementation processes, the long-side dimension d1 of the window 441 may be equal to the long-side dimension D1 of the third die 13 shown in FIG. 11 , and the short-side dimension d2 of the window 441 may also be equal to the short-side dimension d2 of the third die 13 shown in FIG. 11 The short side dimension of the third die 13.

In some structures that can be implemented, the third die 13 including the protective layer 134 will be placed on the dielectric layer 44, and the orthographic projection of the third die 13 on the dielectric layer 44 is located at the boundary of the window 441. When inside, there will be a gap S shown in Figure 11 between the protective layer 135 located in the window 441 and the inner wall of the window 441. Then, the gap S can be filled by the plastic package 42 to lift the third die. 13 stability.

This application also provides a method for encapsulating the chip packaging structure 300 shown in Figure 8. For example, Figure 13 is a flow chart of one of the packaging methods of the chip packaging structure 300 provided by this application, Figures 14a to 14h It is a schematic structural diagram of the possible implementation of each step of the process flow shown in Figure 13. Combined with Figure 13, Figure 14a to Figure 14h, the packaging method is as follows:

S11: Form a dielectric layer on the carrier board.

Before forming the dielectric layer on the carrier board, as shown in FIG. 14a , a bonding layer 821 can be formed on the carrier board 811 first, and then a barrier layer 831 can be formed on the bonding layer 821 .

The carrier board 811 can have a variety of structures, for example, it can be a glass plate, a silicon substrate, or other types of substrates.

The bonding layer 821 may be a laser release layer (Laser release layer) or the like.

In some implemented processes, the barrier layer 83 may be a metal layer, such as an aluminum layer, a copper layer, etc.

S12: As shown in FIG. 14b, a window 441 penetrating the dielectric layer 44 is opened in the dielectric layer 44.

S13: As shown in Figure 14c, a third die 13 is provided. The passive surface of the third die 13 is provided with pins 134, and the pins 134 are located in the opening 441.

That is, the substrate of the third die 13 faces the dielectric layer 44 so that the pins 134 located on one side of the substrate are inserted into the openings 441 .

When disposing the third bare chip 13, an adhesive layer can be used to stick the third chip 13 in the opening 441, or other connection layer structures can also be used.

Continuing to see Figure 14c, the pin 134 of the third die 13 is wrapped by a protective layer 135 to protect the pin 134.

When the orthographic projection of the third die 13 on the dielectric layer 44 is located within the boundary of the window 441, when the third die 13 is installed, a certain installation tolerance can be given to the third die 13, so that the third die 13 has The installation offset (shift) improves the assembly efficiency of the third bare chip 13 . Of course, there will be a gap S between the protective layer 135 and the inner wall of the window 441 as shown in FIG. 14c.

S14: As shown in FIG. 14d , a plastic package 42 is formed, so that the third die 13 is wrapped by the plastic package 42 .

Since there is a gap S between the protective layer 135 and the inner wall of the window 441 shown in FIG. 14c, when the plastic package 42 is formed, the gap S between the protective layer 135 and the inner wall of the window 441 can be filled by the plastic package 42.

In addition, before forming the plastic encapsulation body 42, the conductive pillars 43 shown in FIG. 13d can be formed, and part of the conductive pillars 43 can pass through the dielectric layer 44. Then, the plastic package 42 is formed, so that the third die 13 and the conductive pillar 43 are both wrapped by the plastic package 42 .

Continuing to refer to FIG. 14d, in some achievable processes, the conductive pillars 43 can be formed before disposing the third die 13; or, in other achievable processes, after disposing the third die 13, Then conductive pillars 43 are formed.

S15: Remove the carrier board and expose the pins.

14e and 14f, before removing the carrier board 811, the first rewiring layer 41 can be formed on the plastic package 42, so that the third die 13 is electrically connected to the first rewiring layer 41, and the conductive pillars 43 is electrically connected to the first rewiring layer 41 .

As shown in FIG. 14e , pins 136 are provided on one side of the active surface of the third die 13 . Through the interconnection between the pins 136 and the first rewiring layer 41 , the third die 13 and the first rewiring layer are realized. 41 electrical connections. The active surface of the third die 13 is the surface opposite to the passive surface.

The carrier board 811 is then removed, and as shown in FIG. 14f , a grinding process is used to grind the side of the dielectric layer 44 away from the plastic package 42 to expose the pins 134 of the third die 13 located in the window 441 .

When performing the step of removing the carrier board 811, the carrier board 811 may be removed through a debond (DB) process.

As shown in Figure 14e, since a barrier layer 831 is formed between the bonding layer 821 and the dielectric layer 44, then. During debonding, the barrier layer 831 can prevent the debonding process from causing damage to the pins 134 or other devices of the third die 13 , thereby protecting the third die 13 .

S16: Set the solder joints so that the pins located within the opening are in contact with the solder joints.

As shown in Figure 14g, since the pins 134 located in the opening 441 are exposed, after the solder joints 5 are formed, the pins 134 directly contact the solder joints 5 to achieve electrical connection.

When forming the solder joint 5 shown in FIG. 14g, the solder joint 5 can be formed on the side of the dielectric layer 44 away from the plastic package 42 using photolithography technology.

As shown in FIGS. 14f and 14g , before the pins 134 of the third die 13 are exposed, the first rewiring layer 41 may be formed on the carrier board 812 . For example, the bonding layer 822 may be formed on the carrier board 812 first, the barrier layer 832 may be formed on the bonding layer 822, and then the first rewiring layer 41 may be formed on the barrier layer 832.

After setting the solder joints 5 , as shown in FIG. 14 h , the carrier board 812 can be removed to expose the first rewiring layer 44 , and then the first die 11 and the second die 12 are placed on the first rewiring layer 44 .

In some processes that can be implemented, after arranging the first die 11 and the second die 12, a plastic package can be formed, so that the first die 11 and the second die 12 are wrapped by the plastic package.

In addition, the interposer 4 including the first die 11, the second die 12, and the third die 13 embedded therein is placed on the substrate 3, so that the solder joints 5 are fixed on the substrate 3, and the connection with the substrate 3 is realized. interconnection.

Based on the packaging method given above, the interconnection process between the pin 134 of the third die 13 and the solder joint 5 provided in the embodiment of the present application does not use the hot press bonding TCB technology or hot press which is more difficult to process. Non-conductive film TCNCF technology is used, but a photolithography process that is highly compatible with silicon-based processes is used to realize the interconnection between solder point 5 and pin 134. Therefore, as shown in Figure 14g, there will be no connection between solder point 5 and pin 134. A solder connection structure is formed between the pins 134.

Therefore, the interconnection structure shown in Figure 14g is produced using the packaging method of this application. From a process perspective, it can reduce the difficulty of the preparation process and reduce the preparation cost; from a product performance perspective, it can avoid the occurrence of intermetallic compounds in the solder joints of the solder connection structure. (Intermetallic compounds, IMC) voids and other poor reliability problems, that is, the interconnection structure shown in Figure 14g can be produced, which can also improve the reliability of the interconnection structure, thereby improving the reliability of the entire chip packaging structure.

In addition, the embodiment of the present application also provides a chip packaging structure. The chip packaging structure in this embodiment is similar to the above-mentioned chip packaging structure, and can realize direct contact between the pin 134 of the third bare chip 13 and the solder joint 5. The specific structure is shown below.

FIG. 15 is a schematic structural diagram of a chip packaging structure 300 that embodies the direct contact between the pin 134 of the third die 13 and the solder joint 5 according to the embodiment of the present application. In the structure shown in FIG. 15 , compared with the structure shown in FIG. 11 , the dielectric layer 44 is not provided on the side of the plastic package 42 away from the first rewiring layer 44 , and the pins 134 of the third bare chip 13 are also It does not penetrate the dielectric layer. Instead, part of the pin 134 is exposed outside the plastic package 42 and is in direct contact with the solder joint 5 exposed outside the plastic package 42 .

The interconnection structure between the embedded die 13 and the first die 11 in the embodiment shown in FIG. 15 may also adopt the structure shown in FIG. 10 or the interconnection structure shown in FIG. 15 .

The embodiment shown in FIG. 15 is consistent with the embodiment shown in FIGS. 10 and 11 above in that the pins 134 of the third bare chip 13 are in direct contact with the solder joints 5 . For example, when both pin 134 and solder point 5 are made of copper, direct copper-to-copper interconnection is achieved.

Since in this embodiment, no dielectric layer is provided on the side of the plastic package 42 away from the first redistribution layer 41 , then as shown in FIG. 16 , FIG. 16 shows a schematic structural diagram of the interposer in FIG. 15 , part of the conductive pillar 43 is exposed outside the plastic package 42 and contacts the solder joint 5 exposed outside the plastic package 42 .

Continuing to refer to FIG. 16 , the protective layer 135 can be used to wrap the array-disposed pins 134 of the third die 13 , and the plastic package 42 can wrap the protective layer 135 .

For the remaining structures of the interposer 4 shown in Figures 15 and 16, reference can be made to the embodiments shown in Figures 10 and 11. For example, the third bare chip 13 can be an active chip or a passive chip; For another example, at least two EB dies with TSV can be embedded in the plastic package 42.

This application also provides a method for encapsulating the chip packaging structure 300 shown in Figure 15. For example, Figure 17 is a flow chart of one of the packaging methods of the chip packaging structure 300 provided by this application, Figures 18a to 18f It is a schematic structural diagram of the possible implementation of each step of the process flow shown in Figure 17. Combined with Figure 17, Figure 18a to Figure 18f, the packaging method is as follows:

S21: Set a third bare chip on the carrier board. The passive surface of the third bare chip is provided with pins, and the pins are located above the carrier board.

The same as the packaging method shown above, before placing the third die on the carrier board, as shown in Figure 18a, a bonding layer 822 can be formed on the carrier board 812 first, and then a barrier layer 832 can be formed on the bonding layer 822. .

Referring to FIG. 18b again, the third die 13 is disposed on the barrier layer 832.

The arrangement of the third die 13 in this embodiment can be understood in this way. For example, an adhesive layer may be used to bond the protective layer 135 of the third die 13 above the barrier layer 832 .

S22: Form a plastic package so that the third die is wrapped by the plastic package.

Before forming the plastic encapsulation body 42, the conductive pillars 43 shown in FIG. 18b may be formed. Then, the plastic package 42 is formed, so that the third bare chip 13 and the conductive pillar 43 are both wrapped by the plastic package 42 .

S23: Remove the carrier board and expose the pins.

18c and 18d, before removing the carrier board 812, the first rewiring layer 41 can be formed on the plastic package 42, so that the third die 13 is electrically connected to the first rewiring layer 41, and the conductive pillars 43 is electrically connected to the first rewiring layer 41 .

The carrier board 812 is then removed, and as shown in FIG. 18d , a grinding process is used to grind the side of the plastic package 42 away from the first rewiring layer 41 to expose the pins 134 of the third die 13 .

Before using the grinding process to expose the pins 134 of the third die 13 , as shown in FIG. 18d , the first rewiring layer 41 can be formed on the carrier board 812 . For example, the bonding layer 822 may be formed on the carrier board 812 first, the barrier layer 832 may be formed on the bonding layer 822, and then the first rewiring layer 41 may be formed on the barrier layer 832.

S24: Set the solder joints so that the pins are in contact with the solder joints.

As shown in Figure 18e, since the pins 134 of the third bare chip 13 are exposed, after the solder joints 5 are formed, the pins 134 directly contact the solder joints 5 to achieve electrical connection.

Moreover, part of the conductive pillar 43 is exposed from the plastic sealing body 42. Furthermore, after the solder joint is formed, the conductive pillar 43 directly contacts the solder joint 5 to achieve electrical connection.

After setting the solder joints 5 , as shown in FIG. 18 f , the carrier board 812 can be removed so that the first rewiring layer 41 is exposed, and then the first die 11 and the second die 12 are placed on the first rewiring layer 41 .

In some possible processes, after setting the first die 11 and the second die 12, a plastic package can be formed, so that the first die 11 and the second die 12 are wrapped by the plastic package, as shown in Figure 18f. chip packaging structure.

From the multi-chip packaging method shown in Figures 18a to 18f, it can be seen that in this packaging method, when interconnecting the pins 134 of the third bare chip 13 and the solder joints 5, a conventional method can be used. Photolithography technology enables the direct interconnection of pin 134 and solder joint 5 without the need to use hot-press bonding TCB technology or hot-press non-conductive film TCNCF technology, which is more difficult to process. In this way, a solder joint structure will not be formed between the solder joint 5 and the pin 134. Therefore, the interconnection structure of the pin 134 and the solder joint 5 produced by the packaging method of the present application can not only reduce the difficulty of the preparation process and reduce the preparation cost, but also improve the reliability of the interconnection structure, thereby improving the entire chip. The use reliability of the packaging structure.

The above combined with the accompanying drawings respectively provide a variety of chip packaging structures 300 with different structures. Among them, in any chip packaging structure 300, the pins 134 of the third bare chip 13 are in direct contact with the solder joints 5, and there is no need to use solder. The connection structure solder joint serves as the interconnection structure. A variety of different chip packaging structures are also given below. These chip packaging structures do not use the solder connection structure solder joint as the interconnection structure between pin 134 and solder point 5. See below for details.

FIG. 19 is a schematic structural diagram of yet another chip packaging structure 300 according to an embodiment of the present application. The difference between this embodiment and the chip packaging structure 300 shown above is that the structure for interconnecting the third die 13 and the solder joint 5 is different, as shown in Figure 20. Figure 20 shows the pins 134 of the third die 13. interconnection structure with solder point 5.

As shown in FIG. 20 , a dielectric layer 44 is provided on the side of the plastic package 42 away from the first rewiring layer 41 . The solder joints 5 and the pins 134 of the third bare chip 13 are located on opposite sides of the dielectric layer 44 , and in The dielectric layer 44 has a conductive hole 442 penetrating through it. The conductive hole 442 may also be called a through dielectric via (TDV).

Furthermore, as shown in FIG. 20 , the pin 134 located on one side of the dielectric layer 44 is in contact with the conductive hole 442 , and the solder pad 5 located on the other side of the dielectric layer 44 is also in contact with the conductive hole 442 .

In the package shown in FIGS. 19 and 20 , the pins 134 of the third die 13 as the EB die are interconnected with the solder joints 5 through conductive holes 442 penetrating the dielectric layer 44 . In some optional structures, the pin 134, the solder point 4 and the conductive hole 442 can all be made of copper material. Then, the interconnection between the solder point 5 and the pin 134 can also be called a copper-copper interconnection. .

Similar to the embodiment shown above, in the interconnection structure of the pin 134 and the solder joint 5 shown in Figures 19 and 20, the hot press bonding TCB technology or the hot press non-conductive technology, which is difficult to use, is not used. Solder joint structure made of film TCNCF technology.

The dielectric material of the dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, or boron-phosphorus-doped silicon dioxide. One or at least a combination of two.

In some structures that can be implemented, the interconnection structure between the buried die 13 and the first die 11 in the embodiments shown in FIGS. 19 and 20 can also adopt the structure shown in FIG. 10 .

This application also provides a method for encapsulating the chip packaging structure 300 shown in Figure 19. For example, Figure 21 is a flow chart of one of the packaging methods of the chip packaging structure 300 provided by this application, Figures 22a to 22g It is a schematic structural diagram of the possible implementation of each step of the process flow shown in Figure 21. Combined with Figure 21, Figure 22a to Figure 22g, the packaging method is as follows:

S31: Set a third bare chip on the carrier board. The passive surface of the third bare chip is provided with pins, and the pins are located above the carrier board.

The same as the packaging method shown in Figure 17 above, before placing the third die on the carrier board, as shown in Figure 22a, a bonding layer 822 can be formed on the carrier board 812 first, and then a barrier can be formed on the bonding layer 822 Layer 832.

Referring to FIG. 22b again, the third die 13 is disposed on the barrier layer 832. For example, an adhesive layer may be used to bond the protective layer 135 of the third die 13 to the barrier layer 832 .

S32: Form a plastic package so that the third die is wrapped by the plastic package.

Before forming the plastic encapsulation body 42, the conductive pillars 43 shown in FIG. 22b may be formed. Then, the plastic package 42 is formed, so that the third bare chip 13 and the conductive pillar 43 are both wrapped by the plastic package 42 .

S33: Remove the carrier board and expose the pins.

22c and 22d, before removing the carrier board 812, the first rewiring layer 41 can be formed on the plastic package 42, so that the third die 13 is electrically connected to the first rewiring layer 41, and the conductive pillars 43 is electrically connected to the first rewiring layer 41 .

The carrier board 812 is then removed, and as shown in FIG. 22d , a grinding process is used to grind the side of the plastic package 42 away from the first rewiring layer 41 to expose the pins 134 of the third die 13 .

Before using the grinding process to expose the pins 134 of the third die 13, referring to FIG. 22d, one side of the first rewiring layer 41 can be formed on the carrier board 812. For example, the bonding layer 822 may be formed on the carrier board 812 first, the barrier layer 832 may be formed on the bonding layer 822, and then the first rewiring layer 41 may be formed on the barrier layer 832.

S34: Form a dielectric layer, and conductive holes penetrate the dielectric layer so that the pins are in contact with the conductive holes.

As shown in Figure 22e, a dielectric layer 44 can be formed on the side of the plastic package 42 away from the first rewiring layer 41, and a photolithography process is used to form a conductive hole (or dielectric perforation) 442 penetrating the dielectric layer 44 in the dielectric layer 44. , in this case, the pin 134 is in contact with the conductive hole 442.

S35: Set solder joints on the side of the dielectric layer facing away from the plastic package, so that the conductive holes are in contact with the solder joints.

As shown in Figure 22f, photolithography technology can be used to form solder joints 5 on the dielectric layer 44, so that the solder joints 5 contact the conductive holes 442 formed in the dielectric layer 44, that is, as shown in Figure 22f, the third die The pin 134 of 13 is electrically connected to the solder joint 5 through the conductive hole 442 penetrating the dielectric layer 44 .

After setting the solder joints 5 , as shown in FIG. 22 g , the carrier board 812 can be removed to expose the first rewiring layer 41 , and then the first die 11 and the second die 12 are placed on the first rewiring layer 41 .

In some possible processes, after setting the first die 11 and the second die 12, a plastic package can be formed, so that the first die 11 and the second die 12 are wrapped by the plastic package, as shown in Figure 22g. chip packaging structure.

From the multi-chip packaging method shown in Figures 22a to 22g, it can be seen that in this packaging method, when interconnecting the pins 134 of the third bare chip 13 and the solder joints 5, a conventional method can be used. Photolithography technology forms conductive holes in the dielectric layer so that the pin 134 and the solder joint 5 are interconnected through the conductive holes. There is no need to use the hot press bonding TCB technology or the hot press non-conductive film TCNCF technology, which is more difficult to process.

In this way, like the structure shown above, a solder joint structure will not be formed between the solder joint 5 and the pin 134.

Therefore, the interconnection structure of the pin 134 and the solder joint 5 produced by the packaging method of the present application can not only reduce the difficulty of the preparation process and reduce the preparation cost, but also improve the reliability of the interconnection structure.

FIG. 23 is a schematic structural diagram of another chip packaging structure 300 according to the embodiment of the present application. The chip packaging structure 300 shown in Figure 23 is different from the chip packaging structure 300 shown in Figure 19 above in that the structure for realizing the interconnection between the third die 13 and the solder joint 5 is different, as shown in Figure 24. Figure 23 reflects the third The interconnection structure between the pins 134 of the three die 13 and the solder joints 5 .

Specifically, as shown in FIG. 24 , a second rewiring layer 47 is formed on the side of the plastic package 42 away from the first rewiring layer 41 , and the solder joints 5 and the pins 134 of the third bare chip 13 are arranged on the second rewiring layer. The opposite sides of 47 are to use the second rewiring layer 47 to realize the interconnection between the pin 134 and the solder joint 5 .

The second redistribution layer 47 includes multiple layers of metal traces, and two adjacent layers of metal traces are separated by a dielectric layer. In addition, there are conductive holes penetrating the dielectric layer, and the metal traces of different layers are electrically connected through the conductive holes. Wire. As shown in FIG. 20 , the conductive hole of the second rewiring layer 47 close to the pin 134 is in contact with the pin 134 , and the conductive hole of the second rewiring layer 47 close to the solder point 5 is in contact with the solder point 5 .

This application also provides a method for encapsulating the chip packaging structure 300 shown in Figure 23. For example, Figure 25 is a flow chart of one of the packaging methods of the chip packaging structure 300 provided by this application, Figures 26a to 26g It is a schematic structural diagram of the possible implementation of each step of the process flow shown in Figure 25. Combined with Figure 25, Figure 26a to Figure 26g, the packaging method is as follows:

S41: Set a third bare chip on the carrier board. The passive surface of the third bare chip is provided with pins, and the pins are located above the carrier board.

The same as the packaging method shown in Figure 21 above, before placing the third die on the carrier board, as shown in Figure 26a, a bonding layer 822 can be formed on the carrier board 812 first, and then a barrier can be formed on the bonding layer 822 Layer 832.

Referring to FIG. 26b again, the third die 13 is disposed on the barrier layer 832. For example, an adhesive layer may be used to bond the protective layer 135 of the third die 13 to the barrier layer 832 .

S42: Form a plastic package so that the third die is wrapped by the plastic package.

Before forming the plastic encapsulation body 42, the conductive pillars 43 shown in FIG. 26b may be formed. Then, the plastic package 42 is formed, so that the third bare chip 13 and the conductive pillar 43 are both wrapped by the plastic package 42 .

S43: Remove the carrier board to expose the pins.

26c and 26d, before removing the carrier board 812, the first rewiring layer 41 can be formed on the plastic package 42, so that the third die 13 is electrically connected to the first rewiring layer 41, and the conductive pillars 43 is electrically connected to the first rewiring layer 41 .

The carrier board 812 is then removed, and as shown in FIG. 26d , the side of the plastic package 42 away from the first rewiring layer 41 is ground to expose the pins 134 of the third die 13 .

Before using the grinding process to expose the pins 134 of the third die 13, referring to FIG. 26d, one side of the first rewiring layer 41 can be formed on the carrier board 812. For example, the bonding layer 822 may be formed on the carrier board 812 first, the barrier layer 832 may be formed on the bonding layer 822, and then the first rewiring layer 41 may be formed on the barrier layer 832.

S44: Form a second rewiring layer so that the pins are electrically connected to the solder joints through the second rewiring layer.

As shown in FIG. 26e , a photolithography process can be used to form a second rewiring layer 47 on the side of the plastic package 42 away from the first rewiring layer 41 . In this case, the pin 134 can be electrically connected to the second rewiring layer 47 .

S45: Set solder joints on the side of the second rewiring layer facing away from the plastic package, so that the pins are electrically connected to the solder joints through the second rewiring layer.

As shown in FIG. 26f , photolithography technology can be used to form solder joints 5 on the second rewiring layer 47 , so that the solder joints 5 are electrically connected to the second rewiring layer 47 .

After setting the solder joints 5 , as shown in FIG. 26 g , the carrier board 812 can be removed so that the first rewiring layer 41 is exposed, and then the first die 11 and the second die 12 are placed on the first rewiring layer 41 .

In some possible processes, after setting the first die 11 and the second die 12, a plastic package can be formed, so that the first die 11 and the second die 12 are wrapped by the plastic package, as shown in Figure 26g. chip packaging structure.

From the multi-chip packaging method shown in Figures 26a to 26g, it can be seen that in this packaging method, it is the same as the packaging method shown in Figure 21 above. 5 When interconnecting, photolithography technology can be used to form a second rewiring layer, so that the pin 134 and the solder joint 5 are interconnected through the second rewiring layer, without the need to use the difficult thermal compression bonding TCB technology. Or hot pressed non-conductive film TCNCF technology.

In this way, a less reliable solder connection structure solder joint will not be formed between the solder point 5 and the pin 134.

Among the two different packaging methods shown in Figure 21 and Figure 25 above, Figure 21 uses a dielectric layer with conductive holes through it, while Figure 25 uses a rewiring layer with multi-layer metal wiring. From the process From a perspective, the process for interconnecting pins and solder joints is basically the same, and photolithography technology can be used. However, in Figure 21, photolithography technology is used to form conductive holes in a dielectric layer, while in Figure 25, photolithography is used The technology forms multi-layer metal traces, multi-layer dielectric layers and wiring layers with conductive holes.

From the various chip packaging structures given in the above embodiments of the present application, it can be known that when packaging multiple bare chips, in order to interconnect the pins and solder joints of the EB die located in the plastic package , photolithography technology can be used to realize copper-copper interconnection, and does not require some difficult processes, such as hot press bonding TCB technology or hot press non-conductive film TCNCF technology.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A chip packaging structure, which is characterized by including:

first die;

Interposer board, the interposer board includes an embedded die, a plastic package and a dielectric layer, the embedded die is wrapped by the plastic package;

The first die is disposed on one of the opposite sides of the plastic package, and the first die is electrically connected to the buried die, and the dielectric layer is disposed on the opposite sides of the plastic package. the other side of the side;

The passive surface of the buried bare chip faces away from the first bare chip, pins are provided on one side of the passive surface of the buried bare chip, and solder joints are provided on the side of the dielectric layer facing away from the plastic package. , the pin penetrates the dielectric layer and contacts the solder joint.
The chip packaging structure according to claim 1, characterized in that, along the thickness direction of the dielectric layer, a window penetrating the dielectric layer is provided in the dielectric layer;

The orthographic projection of the buried die on the dielectric layer is located within the edge of the window;

The pins are located within the openings to contact the solder joints.
The chip packaging structure according to claim 2, characterized in that:

The pins located in the window are wrapped by a protective layer, and the space between the protective layer and the inner wall of the window is filled with the plastic encapsulation body.
The chip packaging structure according to any one of claims 1-3, characterized in that the interposer further includes:

The first rewiring layer;

second die;

The first rewiring layer is formed on a side of the plastic package close to the first die, and both the first die and the second die are disposed on the first rewiring layer. superior.
The chip packaging structure according to claim 4, wherein the interposer further includes: conductive pillars;

The conductive pillar penetrates the plastic package and electrically connects the first rewiring layer and the solder joint.
The chip packaging structure according to claim 4 or 5, characterized in that the buried die includes a substrate and an active layer formed on the substrate, and the substrate is penetrated by a layer connected to the active layer. A conductive channel that is electrically connected to each other, and the conductive channel is electrically connected to the pin;

The surface of the substrate facing away from the active layer is the passive surface. The active layer is close to the first rewiring layer and is electrically connected to the first rewiring layer.
The chip packaging structure according to any one of claims 1-6, characterized in that the chip packaging structure further includes a substrate;

The substrate is disposed on a side of the interposer away from the first die, and the solder joints are electrically connected to the substrate.
A packaging method for a chip packaging structure, which is characterized by including:

Form a dielectric layer on the carrier board;

establishing a window in the dielectric layer that penetrates the dielectric layer;

An embedded die is provided, the passive surface of the embedded die is provided with pins, and the pins are located in the window;

Forming a plastic package such that the embedded die is wrapped by the plastic package;

Remove the carrier board to expose the pins;

A solder joint is provided on a side of the dielectric layer facing away from the plastic package, so that the pins located in the opening are in contact with the solder joint.
The packaging method of a chip packaging structure according to claim 8, characterized in that when opening a window penetrating the dielectric layer in the dielectric layer, the orthographic projection of the buried die on the dielectric layer Located within the edge of said fenestration.
The packaging method of a chip packaging structure according to claim 8 or 9, characterized in that arranging the buried die includes:

An adhesive layer is used to fix the pins of the embedded bare chip in the window.
The packaging method of a chip packaging structure according to any one of claims 8 to 10, characterized in that after forming the plastic packaging body, the packaging method further includes:

forming a first rewiring layer on the plastic package;

A first die and a second die are disposed on the first rewiring layer.
A chip packaging structure, which is characterized by including:

first die;

An interposer board, the interposer board includes an embedded die and a plastic package, and a connection layer, the embedded die is wrapped by the plastic package;

The first bare chip is disposed on one of the opposite sides of the plastic package body, and the first bare chip is electrically connected to the buried die chip, and the connection layer is disposed on the opposite two sides of the plastic package body. On the other side of the side, the side of the connecting layer facing away from the plastic package is provided with welding points;

The passive surface of the buried bare chip faces away from the first bare chip, and pins are provided on one side of the passive surface of the buried bare chip;

The connection layer includes a first dielectric layer stacked on the plastic package, and the pins and solder joints are located on opposite sides of the first dielectric layer;

A first conductive hole penetrates the first dielectric layer, and the pin is in contact with the first conductive hole.
The chip packaging structure according to claim 12, wherein the soldering point is provided on a side of the first dielectric layer facing away from the plastic package, and the first conductive hole is in contact with the soldering point.
The chip packaging structure according to claim 12, wherein the connection layer further includes: a multi-layer metal trace formed on the first dielectric layer facing away from the plastic package body, and a multi-layer metal trace spaced between two adjacent layers. The second dielectric layer between the metal traces has a second conductive hole that electrically connects the metal traces through the second dielectric layer, so that the connection layer forms a second rewiring layer;

The soldering point is disposed on a side of the second rewiring layer facing away from the plastic package, and the pins are electrically connected to the soldering point through the second rewiring layer.
The chip packaging structure according to any one of claims 12-14, wherein the interposer further includes:

The first rewiring layer;

second die;

The first rewiring layer is formed on a side of the plastic package close to the first die, and both the first die and the second die are disposed on the first rewiring layer. superior.
The chip packaging structure according to claim 15, wherein the interposer further includes: conductive pillars;

The conductive pillar penetrates the plastic package body, and the conductive pillar is electrically connected to the solder joint.
The chip packaging structure according to claim 15 or 16, characterized in that the buried die includes a substrate and an active layer formed on the substrate, and the substrate is penetrating with the active layer. a conductive channel electrically connected to each other, and the conductive channel is electrically connected to the pin;

The surface of the substrate facing away from the active layer is the passive surface. The active layer is close to the first rewiring layer and is electrically connected to the first rewiring layer.
The chip packaging structure according to any one of claims 12-17, wherein the chip packaging structure further includes a substrate;

The substrate is disposed on a side of the interposer away from the first die, and the solder joints are electrically connected to the substrate.
A packaging method for a chip packaging structure, which is characterized by including:

An embedded bare chip is provided on the carrier board, and the passive surface of the buried bare chip is provided with pins, and the pins are located above the carrier board;

Forming a plastic encapsulation body so that the embedded die is wrapped by the plastic encapsulation body;

Remove the carrier board to expose the pins;

A first dielectric layer is formed on one side of the plastic package, and a first conductive hole penetrates the first dielectric layer so that the pins are in contact with the first conductive hole.
The packaging method of a chip packaging structure according to claim 19, characterized in that:

After forming the first dielectric layer, the packaging method further includes:

Solder points are provided on a side of the first dielectric layer facing away from the plastic package, so that the first conductive holes are in contact with the pins and the solder points respectively.
The packaging method of a chip packaging structure according to claim 19, characterized in that:

After forming the first dielectric layer, the packaging method further includes:

Multiple layers of metal traces are formed on the side of the first dielectric layer facing away from the plastic package. Two adjacent layers of metal traces are separated by a second dielectric layer. A second conductive hole is passed through and electrically connected to the metal trace, so that the structure including the first dielectric layer, the multi-layer metal trace and the second dielectric layer forms a second redistribution layer;

A soldering point is provided on a side of the second rewiring layer facing away from the plastic package, so that the pins are electrically connected to the soldering point through the second rewiring layer.
The packaging method of a chip packaging structure according to claim 21, characterized in that the packaging method further includes:

Conductive pillars are disposed on the carrier board so that the conductive pillars are electrically connected to the solder joints through the second rewiring layer.
The packaging method of a chip packaging structure according to any one of claims 19 to 22, characterized in that arranging the buried die on the carrier board includes:

An adhesive layer is used to fix the pins of the embedded bare chip above the carrier board.
The packaging method of a chip packaging structure according to any one of claims 19 to 23, characterized in that after forming the plastic package body, the packaging method further includes:

forming a first rewiring layer on the plastic package;

A first die and a second die are disposed on the first rewiring layer.
A chip packaging structure, which is characterized by including:

first die;

An interposer board, the interposer board includes an embedded die and a plastic package, and the embedded die is wrapped by the plastic package;

The first die is disposed on one of the opposite sides of the plastic package, and the first die is electrically connected to the embedded die;

The passive surface of the buried bare chip faces away from the first bare chip, and pins are provided on one side of the passive surface of the buried bare chip;

A solder joint is provided on a side of the plastic package away from the first bare chip;

At least part of the pin is exposed outside the plastic package and contacts the solder joint located outside the plastic package.
The chip packaging structure according to claim 25, wherein the interposer further includes: conductive pillars;

The conductive pillar penetrates the plastic package body and is at least partially exposed outside the plastic package body, and is in contact with the solder joint located outside the plastic package body.
The chip packaging structure according to claim 25 or 26, wherein the interposer further includes:

The first rewiring layer;

second die;

The first rewiring layer is formed on a side of the plastic package close to the first die, and both the first die and the second die are disposed on the first rewiring layer. superior.
The chip packaging structure according to claim 27, wherein the buried die includes a substrate and an active layer formed on the substrate, and an electrical connection with the active layer is penetrated through the substrate. A connected conductive channel, and the conductive channel is electrically connected to the pin;

The surface of the substrate facing away from the active layer is the passive surface. The active layer is close to the first rewiring layer and is electrically connected to the first rewiring layer.
The chip packaging structure according to any one of claims 25-28, wherein the chip packaging structure further includes a substrate;

The substrate is disposed on a side of the interposer away from the first die, and the solder joints are electrically connected to the substrate.
A packaging method for a chip packaging structure, which is characterized by including:

An embedded bare chip is provided on the carrier board, and the passive surface of the buried bare chip is provided with pins, and the pins are located above the carrier board;

Forming a plastic package such that the embedded die is wrapped by the plastic package;

Remove the carrier board to expose the pins;

Welding points are provided on one side of the plastic package so that the pins are in contact with the welding points.
The packaging method of a chip packaging structure according to claim 30, characterized in that the packaging method further includes:

Conductive pillars are provided on the carrier board;

When the pins are exposed, the conductive pillars are exposed, so that the conductive pillars are in contact with the solder joints.
The packaging method of a chip packaging structure according to claim 30 or 31, characterized in that arranging the buried die on the carrier board includes:

An adhesive layer is used to fix the pins of the embedded bare chip above the carrier board.
The packaging method of a chip packaging structure according to any one of claims 30 to 32, wherein after forming the plastic package body, the packaging method further includes:

forming a first rewiring layer on the plastic package;

A first die and a second die are disposed on the first rewiring layer.
An electronic device, characterized by including:

circuit board;

The chip packaging structure as described in any one of claims 1 to 7, 12 to 18, and 25 to 29, or any one of claims 8 to 11, 19 to 24, and 30 to 33. The chip packaging structure obtained by the packaging method of the chip packaging structure described in one item;

Wherein, the chip packaging structure is provided on the circuit board.