WO2024008015A1 - Insulated gate bipolar transistor - Google Patents

Insulated gate bipolar transistor Download PDF

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Publication number
WO2024008015A1
WO2024008015A1 PCT/CN2023/105186 CN2023105186W WO2024008015A1 WO 2024008015 A1 WO2024008015 A1 WO 2024008015A1 CN 2023105186 W CN2023105186 W CN 2023105186W WO 2024008015 A1 WO2024008015 A1 WO 2024008015A1
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Prior art keywords
short
circuit
projection
region
unit
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PCT/CN2023/105186
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French (fr)
Chinese (zh)
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祁金伟
张耀辉
卢烁今
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苏州华太电子技术股份有限公司
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Publication of WO2024008015A1 publication Critical patent/WO2024008015A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to an insulated gate bipolar transistor.
  • the insulated gate bipolar transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar triode (BJT) and an insulated gate field effect transistor (MOS). It is very suitable for applications with DC voltages of 600V and The above converter systems include AC motors, frequency converters, switching power supplies, lighting circuits, traction and other fields.
  • IGBT In many applications, IGBT requires a diode in anti-parallel to achieve freewheeling.
  • Reverse conduction insulated gate bipolar transistor (RC-IGBT) integrates IGBT and diode on the same chip, so that the device has both forward and reverse conduction capabilities, and can improve the integration of the device and save manufacturing costs.
  • RC-IGBT Reverse conduction insulated gate bipolar transistor
  • the conduction mode will undergo a conversion process from single electron conduction to bipolar conduction.
  • the RC-IGBT switches between two conductive modes, the current will continue to increase while the voltage will decrease. This phenomenon is called negative resistance. This phenomenon will cause the device to see uneven current distribution, resulting in some Devices are burned out due to excessive current, and some devices are difficult to start working due to too small current.
  • the main purpose of the present disclosure is to provide an insulated gate bipolar transistor to solve the problem of uneven current distribution in the prior art.
  • an insulated gate bipolar transistor includes: an epitaxial layer; a drift region formed in the epitaxial layer, and the drift region has a relative third a surface and a second surface, and the drift region has a first doping type; a plurality of super junctions are formed in the drift region and are spaced along the first direction, and each super junction extends along the second direction and the third direction; One direction is parallel to the first surface, the second direction is the direction in which the first surface points to the second surface, the third direction is parallel to the first surface and different from the first direction, the super junction has a second doping type; the collector region, Formed on the second surface in the epitaxial layer, the collector region has a second doping type; a plurality of short-circuit regions are formed on the second surface and spaced along the third direction, and the projection of each super junction on the second surface It partially overlaps with the projection of at least one short-circuit region on
  • the plurality of super junction units includes a plurality of super junction units, each super junction unit includes a plurality of super junctions, and the projection of each super junction unit on the second surface partially overlaps with the projection of the plurality of short-circuit regions on the second surface.
  • the super junction unit includes a first super junction unit and a second super junction unit, the first super junction unit and the second super junction unit are alternately arranged along the first direction, and the number of super junctions in the first super junction unit is less than that of the first super junction unit.
  • the number of super junctions in the two super junction units, the first super junction unit has a first projection on the second surface, the second super junction unit has a second projection on the second surface, the first projection and the second projection are the same number
  • the projections of the short-circuit areas on the second surface partially overlap.
  • the plurality of short-circuit areas include a first short-circuit area unit and a second short-circuit area unit, the number of short-circuit areas in the first short-circuit area unit is greater than the number of short-circuit areas in the second short-circuit area unit, and the first short-circuit area unit is in the There is a third projection on one surface, the second short-circuit area unit has a fourth projection on the first surface, the first projection and the third projection partially overlap, and the second projection and the fourth projection partially overlap.
  • adjacent short-circuit areas in the first short-circuit area unit have the same first spacing
  • adjacent short-circuit areas in the second short-circuit area unit have the same second spacing
  • the first spacing is equal to the first spacing. Two intervals.
  • each third projection overlaps after extending along the first direction, and each third projection does not overlap with the fourth projection after extending along the first direction.
  • each first projection has a first area respectively located on both sides of the third projection
  • each second projection has a plurality of second areas located between adjacent fourth projections, and each first area The area is equal to that of each second region; in the first direction, the first region does not overlap with the second region after extending.
  • the projected areas of each super junction on the first surface are equal, and the projected areas of each short-circuit region on the first surface are equal.
  • adjacent super junctions are arranged at equal intervals along the first direction.
  • the first direction is perpendicular to the third direction.
  • an insulated gate bipolar transistor includes: an epitaxial layer; a drift region formed in the epitaxial layer, the drift region has an opposite first surface and a second surface, and the drift region has A first doping type; a plurality of super junctions formed in the drift region and spaced along a first direction, each super junction extending along a second direction and a third direction, the first direction being parallel to the first surface, and the second direction is the direction in which the first surface points to the second surface and is perpendicular to the second direction.
  • the third direction is parallel to the first surface and different from the first direction.
  • the super junction has a second doping type; the collector region is formed in On the second surface of the epitaxial layer, the collector region has a second doping type; a plurality of short-circuit regions are formed on the second surface and spaced along the third direction, and the projection of each super junction on the second surface is consistent with at least The projection of a short-circuit region on the second surface partially overlaps, the short-circuit region has a first doping type, and the doping concentration of the short-circuit region is greater than the doping concentration of the drift region.
  • the self-bias effect formed by the initial electron flow is very significant, thus causing unevenness.
  • the area in the short-circuit area will first enter the bipolar conduction mode and produce a clamping effect.
  • the lateral component of the electron flow in the bipolar conduction area also increases, which will continuously trigger the surrounding bipolar conduction in the short-circuit region, thereby ensuring that the bipolar current never flows from the
  • the rapid and smooth transition from the area with short-circuit area to the short-circuit area makes the current in the device evenly distributed and the rebound phenomenon is greatly reduced, thereby improving the stability and reliability of the device's operation.
  • Figure 1 shows a schematic cross-sectional structural diagram of an embodiment of an insulated gate bipolar transistor according to the present disclosure
  • Figure 2 shows a schematic cross-sectional view of Figure 1 with a short-circuit area
  • Figure 3 shows a cross-sectional schematic diagram of the current in the short circuit region shown in Figure 2;
  • FIG. 4 shows a schematic cross-sectional view of FIG. 1 with the guide IGBT region.
  • the above-mentioned drawings include the following reference signs: 1. Collection area; 2. Drift area; 3. Super junction; 4. Epitaxial layer; 5. Gate oxide layer; 6. Gate; 7. Doped well; 8. Emitter area; 9. Dielectric layer; 10. Emitter metal; 11. Collector; 12. Collector metal; 13. Short circuit area; 14. First super junction unit; 15. Second super junction unit; 16. The first short-circuit area unit; 17. The second short-circuit area unit; 18. The first area; 19. The second area.
  • the transistor includes: an epitaxial layer 4; a drift region 2, which is formed in the epitaxial layer 4; the drift region 2 has an opposite first surface and a second surface, and the drift region 2 has a first doping type; a plurality of super junctions 3 are formed in the drift region 2 and are spaced apart along the first direction A, and each super junction 3 extends along the second direction B and the third direction C.
  • the second direction B is the direction from the first surface to the second surface, and the first direction A is parallel to the A surface, a third direction C is parallel to the first surface and different from the first direction A, the super junction 3 has a second doping type;
  • a collector region 1 is formed on a second surface in the epitaxial layer 4, the collector region 1 has a second doping type;
  • a plurality of short-circuit regions 13 are formed on the second surface and are spaced along the third direction C, and the projection of each super junction on the second surface is consistent with at least one short-circuit region 13 on the second surface The projections overlap, and the short-circuit region 13 has the first doping type, and the doping concentration of the short-circuit region 13 is greater than the doping concentration of the drift region 2 .
  • a plurality of short-circuit regions 13 are provided at intervals on the second surface of the drift region 2, so that in the regions where the short-circuit regions 13 are not uniformly present in the above-mentioned device, the initial electron flow is formed
  • the self-bias effect is very significant, so that the area with uneven short-circuit area 13 will first enter the bipolar conduction mode and produce a clamping effect. Then as the current increases, the electron flow in the bipolar conduction area will decrease.
  • the lateral component also increases, which will continuously trigger the bipolar conduction of the surrounding short-circuit area 13, thereby ensuring a fast and smooth transition of the bipolar current from the area with uneven short-circuit area 13 to the short-circuit area 13 when the device is turned on. , so that the current in the device is evenly distributed, and the rebound phenomenon is greatly reduced, thereby improving the stability and reliability of the device's operation.
  • the above device also includes an epitaxial layer 4 , a gate oxide layer 5 , at least one gate 6 , at least one doped well 7 , at least one emitter region 8 , at least one dielectric layer 9 and an emitter metal 10 .
  • the epitaxial layer 4 is disposed on the first surface of the above-mentioned drift region 2, and the doping well 7 is located on a side of the above-mentioned epitaxial layer 4 away from the drift region 2.
  • the above-mentioned doping well 7 has a second doping type, and the above-mentioned doping well 7 It also has a first side away from the epitaxial layer 4 and a second side close to the epitaxial layer 4.
  • the gate 6 extends from the first side to the second side into the epitaxial layer 4, and the gate oxide layer 5 is disposed on the gate electrode 6. around, the gate 6, the epitaxial layer 4 and the doped well 7 are electrically isolated.
  • the emitter region 8 is disposed on the side of the doped well 7 away from the epitaxial layer 4 and surrounds the gate 6.
  • the dielectric layer 9 is disposed on the third On one side, the dielectric layer 9 corresponds to the gate electrode 6 one-to-one and completely covers the gate electrode 6.
  • the emitter metal 10 is located on the first side and is in contact with the emitter region 8.
  • the collector electrode 11 is located on the side of the collector region 1 away from the drift region 2. side, and the doping type of the collector 11 is the same as that of the collector region 1, the doping concentration of the collector 11 is greater than that of the collector region 1, and the collector metal 12 is located on one side of the collector 11 and the short-circuit region 13.
  • the material of the epitaxial layer 4 is germanium (Ge). Since the lattice constant of Ge (5.646A) and the lattice constant of Si (5.431A) among Group IV elements are minimally different, this makes SiGe and Si processes are easy to integrate, and due to the mismatch of lattice constants between Si and SiGe, the Si single crystal layer is subject to tensile stress by the underlying SiGe layer, which increases the mobility of electrons, thereby increasing the operating saturation current of the device and response speed and improve device reliability.
  • germanium germanium
  • multiple super junction units include multiple super junction units, each super junction unit includes multiple super junctions, and the projection of each super junction unit on the second surface is consistent with the plurality of super junction units.
  • the projections of the short-circuit areas 13 on the second surface partially overlap.
  • the plurality of super junctions are spaced apart along the first direction A, and in the first direction A, according to the overlapping relationship between the short circuit region 13 and the super junction, when the short circuit region 13 and the plurality of super junctions are in When the projections on the second surface overlap, the plurality of super junctions that overlap with the short-circuit area 13 are divided into one super junction unit.
  • the hole storage in the area of the super junction close to the short-circuit region 13 can be preferentially entered into the short-circuit region. 13, as shown in Figure 3, and in the area where the short-circuit area 13 does not exist, the self-bias effect formed by the initial electron flow is significant, so that the bipolar conduction mode is preferentially entered in the area where the short-circuit area 13 does not exist, and as the The increase in current continuously triggers bipolar conduction in the area around the short-circuit area 13, thereby reducing the rebound phenomenon.
  • the super junction unit includes a first super junction unit 14 and a second super junction unit 15.
  • the first super junction unit 14 and the second super junction unit 15 are alternately arranged along the first direction A.
  • the first super junction unit 14 and the second super junction unit 15 are alternately arranged along the first direction A.
  • the number of super junctions in the super junction unit 14 is less than the number of super junctions in the second super junction unit 15.
  • the first super junction unit 14 has a first projection on the second surface and the second super junction unit 15 has a first projection on the second surface.
  • the second projection, the first projection and the second projection partially overlap with the same number of projections of the short-circuit areas 13 on the second surface.
  • the first super junction unit 14 includes two adjacent super junctions, and the two adjacent super junctions have overlapping projections with the short-circuit region 13 on the second surface
  • the second super junction unit 15 includes four adjacent super junctions, and the four adjacent super junctions all have overlapping projections with the short circuit region 13 on the second surface
  • the first super junction unit 14 is arranged adjacent to the second super junction unit 15.
  • the two super junctions are arranged to have overlapping projections with the short circuit region 13 on the second surface, that is, the first super junction units 14 and the second super junction units 15 are alternately arranged along the first direction A.
  • the plurality of short-circuit areas 13 include a first short-circuit area unit 16 and a second short-circuit area unit 17 .
  • the number of short-circuit areas 13 in the first short-circuit area unit 16 is greater than the number of short-circuit areas 13 in the second short-circuit area unit 17 .
  • the number of areas 13, the first short-circuit area unit 16 has a third projection on the first surface, the second short-circuit area unit 17 has a fourth projection on the first surface, the first projection and the third projection partially overlap, the second projection Partially overlaps with the fourth projection.
  • Each of the above-mentioned short-circuit area units includes a plurality of short-circuit areas 13.
  • the above-mentioned first short-circuit area unit 16 includes two adjacent super junctions at the first
  • the projections of the multiple short-circuit areas 13 overlapping on the two surfaces are regarded as the third projection.
  • the multiple short-circuit areas 13 of the above-mentioned second short-circuit unit overlap with the projections of the four adjacent super junctions on the second surface, and the projections are regarded as the third projection. Projection as the fourth projection.
  • the number of short-circuit areas 13 passing through the first short-circuit area unit 16 is greater than the number of short-circuit areas 13 in the second short-circuit area unit 17
  • the number of holes stored in each super junction near the short-circuit region 13 in the device is relatively uniformly distributed within the device body.
  • adjacent short-circuit areas 13 in the first short-circuit area unit 16 have the same first spacing
  • adjacent short-circuit areas 13 in the second short-circuit area unit 17 have the same first spacing.
  • the same second spacing the first spacing is equal to the second spacing.
  • the spacing between two adjacent short-circuit regions 13 in the third direction C is used as the first spacing
  • the spacing between two adjacent short-circuit regions 13 in the third direction C is set to be equal, so that When the device is turned on, the bipolar current can smoothly transition in the third direction C.
  • the distance between two adjacent short-circuit areas 13 in the first direction A is used as the second distance.
  • the spacing between two adjacent short-circuit areas 13 is equal, so that the bipolar current can smoothly transition in the first direction A during the device turn-on process.
  • each third projection extends along the first direction A and then overlaps, and each third projection does not overlap with the fourth projection after extending along the first direction A.
  • the third projection is that the first short-circuit area unit 16 is in the second surface
  • the fourth projection is the projection of the second short-circuit area unit 17 on the second surface.
  • each first projection in the third direction C, has a first area 18 located on both sides of the third projection, and each second projection has a second area 19 located between adjacent fourth projections. ; In the first direction A, the first region 18 does not overlap with the second region 19 after extending. As shown in FIG.
  • the areas on both sides of the projected overlapping area of the first super junction unit 14 and the first short-circuit area unit 16 are respectively regarded as the first areas 18 , and the areas located on the adjacent second super junction unit are
  • the area between 15 and the projected overlapping area of the second short-circuit unit is divided into a plurality of second areas 19 with the same area as the first area 18, and in the above-mentioned first direction A, the area between the first area 18 and the second short-circuit unit
  • the projections are alternately arranged, and the projections of the second area 19 and the first short-circuit unit are arranged alternately. Therefore, in the above-mentioned first direction A, the first area 18 does not overlap with the second area 19 after extending.
  • the above-mentioned first region 18 and the second region 19 serve as the guide region in the device. Since there is no short-circuit region 13 in the guide region, the self-bias formed by the initial electron flow in the guide region The voltage effect is very significant, so this area will enter the bipolar conduction mode first and produce a clamping effect. As the current increases, the lateral component of the electron flow in the bipolar conduction area also increases, and there will be The bipolar conduction in the surrounding guide area is continuously triggered, thereby reducing the rebound phenomenon and allowing the bipolar conduction range to quickly expand to the entire area of the device.
  • the above-mentioned guide area includes different shapes such as rectangle and cross, and its size, quantity, shape, area, etc. can include different designs.
  • the device is divided into equal parts according to a rectangular shape to ensure that the bipolar current can quickly and smoothly transition from the leading area to the rest of the device when the device is turned on.
  • the projected areas of each super junction on the first surface are equal, and the projected areas of each short-circuit region 13 on the first surface are equal, so that the current flow in the device can be evenly distributed, and thus the current flow in the device can be evenly distributed. Laterally, the device is promoted into full bipolar conduction.
  • adjacent super junctions are arranged at equal intervals along the first direction A.
  • the super junction structures arranged at equal intervals can reduce the conductance modulation effect of each part of the device to the same extent, thereby greatly improving the current tailing phenomenon of the device.
  • the first direction A is perpendicular to the third direction C.
  • the area around the multiple short-circuit areas 13 in the device is equivalent to a large area of guide areas evenly distributed around the device, which can be more conducive to weakening Rebound, effectively improving the problem of uneven current distribution.
  • the first super junction unit 14 is composed of two super junctions 3
  • the second super junction unit 15 is composed of four super junctions 3
  • the first super junction unit 14 and the second super junction unit 15 are composed of four super junctions 3 .
  • the super junction units 15 are alternately arranged along the first direction A
  • the first short circuit area unit 16 is composed of four short circuit areas 13
  • the second short circuit area unit 17 is composed of two short circuit areas 13
  • the first super junction unit 14 has a second short circuit area unit 13.
  • the first projection on the surface, the first short-circuit area unit 16 has a third projection on the second surface, and the first projection has areas located on both sides of the third projection along the third direction C, that is, located at the four corners in Figure 4 of four first regions 18, the second superjunction unit 15 has a second projection on the second surface, and the second short-circuit area unit 17 has The fourth projection on the second surface, the second projection has an area between the two third projections along the third direction C, that is, the four second areas 19 located in the middle in Figure 4, the first area 18 and the The two regions 19 have equal areas, and in the first direction A, the first region 18 does not overlap with the second region 19 after extending.

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Abstract

Provided in the present disclosure is an insulated gate bipolar transistor. The transistor comprises: an epitaxial layer; a drift region formed in the epitaxial layer, the drift region having a first doping type; a plurality of super junctions formed in the drift region and arranged at intervals along a first direction, each super junction extending in a second direction and a third direction, the first direction being parallel to a first surface, the second direction being a direction from the first surface of the drift region to a second surface, the third direction being parallel to the first surface and being different from the first direction, and the super junction having a second doping type; a collector region formed on a second surface in the epitaxial layer, the collector region having the second doping type; and a plurality of shorting regions formed on the second surface and arranged at intervals along the third direction, the projection of each super junction on the second surface partially overlapping with the projection of the at least one shorting region on the second surface, the shorting region having the first doping type, and the doping concentration of the shorting region being greater than the doping concentration of the drift region. The device has high working stability and reliability.

Description

绝缘栅双极型晶体管Insulated gate bipolar transistor
相关申请的交叉引用Cross-references to related applications
本申请要求于2022年07月04日提交中国专利局，申请号为202210780048.3，申请名称为“绝缘栅双极型晶体管”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to the Chinese patent application filed with the China Patent Office on July 4, 2022, with the application number 202210780048.3 and the application name "Insulated Gate Bipolar Transistor", the entire content of which is incorporated into this application by reference.
技术领域Technical field
本公开涉及半导体技术领域，具体而言，涉及一种绝缘栅双极型晶体管。The present disclosure relates to the field of semiconductor technology, and in particular, to an insulated gate bipolar transistor.
背景技术Background technique
绝缘栅双极型晶体管(IGBT)是由双极型三极管(BJT)和绝缘栅型场效应管(MOS)组成的复合全控型电压驱动式功率半导体器件，非常适合应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路以及牵引牵动等领域。The insulated gate bipolar transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar triode (BJT) and an insulated gate field effect transistor (MOS). It is very suitable for applications with DC voltages of 600V and The above converter systems include AC motors, frequency converters, switching power supplies, lighting circuits, traction and other fields.
在很多应用场合，IGBT需要反并联一个二极管来实现续流。逆导型绝缘栅双极型晶体管(RC-IGBT)将IGBT和二极管集成在同一块芯片上，从而使得器件兼备正向导通能力和反向导通能力，并且可以提高器件的集成度，节约制造成本。然而，RC-IGBT器件在正向导通过程中，其导电模式会存在一个由单电子导电向双极型导电转换的过程。当RC-IGBT在两种导电模式之间转换时，会出现电流持续增长而电压反而下降的现象，这种现象称为负阻现象，这种现象会使器件见电流分配不均匀，从而导致一些器件因电流过大而烧毁，一些器件因电流过小而难以开启工作In many applications, IGBT requires a diode in anti-parallel to achieve freewheeling. Reverse conduction insulated gate bipolar transistor (RC-IGBT) integrates IGBT and diode on the same chip, so that the device has both forward and reverse conduction capabilities, and can improve the integration of the device and save manufacturing costs. . However, during the forward conduction process of the RC-IGBT device, the conduction mode will undergo a conversion process from single electron conduction to bipolar conduction. When the RC-IGBT switches between two conductive modes, the current will continue to increase while the voltage will decrease. This phenomenon is called negative resistance. This phenomenon will cause the device to see uneven current distribution, resulting in some Devices are burned out due to excessive current, and some devices are difficult to start working due to too small current.
发明内容Contents of the invention
本公开的主要目的在于提供一种绝缘栅双极型晶体管，以解决现有技术中电流分配不均匀的问题。The main purpose of the present disclosure is to provide an insulated gate bipolar transistor to solve the problem of uneven current distribution in the prior art.
为了实现上述目的，根据本公开的一个方面，提供了一种绝缘栅双极型晶体管，该绝缘栅双极型晶体管包括：外延层；漂移区，形成于外延层中，漂移区具有相对的第一表面和第二表面，且漂移区具有第一掺杂类型；多个超级结，形成于漂移区中并沿第一方向间隔设置，各超级结均沿第二方向和第三方向延伸，第一方向平行于第一表面，第二方向为第一表面指向第二表面的方向，第三方向平行于第一表面且不同于第一方向，超级结具有第二掺杂类型；集电区，形成于外延层中的第二表面上，集电区具有第二掺杂类型；多个短路区，形成于第二表面上并沿第三方向间隔设置，各超级结在第二表面上的投影与至少一个短路区在第二表面上的投影部分重叠，且短路区具有第一掺杂类型，短路区的掺杂浓度大于漂移区的掺杂浓度。 In order to achieve the above object, according to one aspect of the present disclosure, an insulated gate bipolar transistor is provided. The insulated gate bipolar transistor includes: an epitaxial layer; a drift region formed in the epitaxial layer, and the drift region has a relative third a surface and a second surface, and the drift region has a first doping type; a plurality of super junctions are formed in the drift region and are spaced along the first direction, and each super junction extends along the second direction and the third direction; One direction is parallel to the first surface, the second direction is the direction in which the first surface points to the second surface, the third direction is parallel to the first surface and different from the first direction, the super junction has a second doping type; the collector region, Formed on the second surface in the epitaxial layer, the collector region has a second doping type; a plurality of short-circuit regions are formed on the second surface and spaced along the third direction, and the projection of each super junction on the second surface It partially overlaps with the projection of at least one short-circuit region on the second surface, and the short-circuit region has a first doping type, and the doping concentration of the short-circuit region is greater than the doping concentration of the drift region.
可选地，多个超级结包括多个超级结单元，各超级结单元包括多个超级结，各超级结单元在第二表面上的投影与多个短路区在第二表面上的投影部分重叠。Optionally, the plurality of super junction units includes a plurality of super junction units, each super junction unit includes a plurality of super junctions, and the projection of each super junction unit on the second surface partially overlaps with the projection of the plurality of short-circuit regions on the second surface. .
可选地，超级结单元包括第一超级结单元和第二超级结单元，第一超级结单元和第二超级结单元沿第一方向交替设置，第一超级结单元中超级结的数量小于第二超级结单元中超级结的数量，第一超级结单元在第二表面上具有第一投影，第二超级结单元在第二表面上具有第二投影，第一投影和第二投影与相同数量的短路区在第二表面上的投影部分重叠。Optionally, the super junction unit includes a first super junction unit and a second super junction unit, the first super junction unit and the second super junction unit are alternately arranged along the first direction, and the number of super junctions in the first super junction unit is less than that of the first super junction unit. The number of super junctions in the two super junction units, the first super junction unit has a first projection on the second surface, the second super junction unit has a second projection on the second surface, the first projection and the second projection are the same number The projections of the short-circuit areas on the second surface partially overlap.
可选地，多个短路区包括第一短路区单元和第二短路区单元，第一短路区单元中短路区的数量大于第二短路区单元中短路区的数量，第一短路区单元在第一表面上具有第三投影，第二短路区单元在第一表面上具有第四投影，第一投影和第三投影部分重叠，第二投影和第四投影部分重叠。Optionally, the plurality of short-circuit areas include a first short-circuit area unit and a second short-circuit area unit, the number of short-circuit areas in the first short-circuit area unit is greater than the number of short-circuit areas in the second short-circuit area unit, and the first short-circuit area unit is in the There is a third projection on one surface, the second short-circuit area unit has a fourth projection on the first surface, the first projection and the third projection partially overlap, and the second projection and the fourth projection partially overlap.
可选地，在第三方向上，第一短路区单元中的相邻短路区具有相同的第一间距，第二短路区单元中的相邻短路区具有相同的第二间距，第一间距等于第二间距。Optionally, in the third direction, adjacent short-circuit areas in the first short-circuit area unit have the same first spacing, and adjacent short-circuit areas in the second short-circuit area unit have the same second spacing, and the first spacing is equal to the first spacing. Two intervals.
可选地，各第三投影沿第一方向延伸后重叠，且各第三投影沿第一方向延伸后与第四投影不重叠。Optionally, each third projection overlaps after extending along the first direction, and each third projection does not overlap with the fourth projection after extending along the first direction.
可选地，在第三方向上，各第一投影具有分别位于第三投影两侧的第一区域，各第二投影具有位于相邻第四投影之间的多个第二区域，各第一区域与各第二区域面积相等；在第一方向上，第一区域延伸后与第二区域不重叠。Optionally, in the third direction, each first projection has a first area respectively located on both sides of the third projection, each second projection has a plurality of second areas located between adjacent fourth projections, and each first area The area is equal to that of each second region; in the first direction, the first region does not overlap with the second region after extending.
可选地，各超级结在第一表面上的投影面积相等，且各短路区在第一表面上的投影面积相等。Optionally, the projected areas of each super junction on the first surface are equal, and the projected areas of each short-circuit region on the first surface are equal.
可选地，相邻超级结沿第一方向等间距设置。Optionally, adjacent super junctions are arranged at equal intervals along the first direction.
可选地，第一方向与第三方向垂直。Optionally, the first direction is perpendicular to the third direction.
应用本公开的技术方案，提供一种绝缘栅双极型晶体管，该晶体管包括：外延层；漂移区，形成于外延层中，漂移区具有相对的第一表面和第二表面，且漂移区具有第一掺杂类型；多个超级结，形成于漂移区中并沿第一方向间隔设置，各超级结均沿第二方向和第三方向延伸，第一方向平行于第一表面，第二方向为第一表面指向第二表面的方向，且垂直于第二方向的方向，第三方向平行于第一表面且不同于第一方向，超级结具有第二掺杂类型；集电区，形成于外延层中的第二表面上，集电区具有第二掺杂类型；多个短路区，形成于第二表面上并沿第三方向间隔设置，各超级结在第二表面上的投影与至少一个短路区在第二表面上的投影部分重叠，且短路区具有第一掺杂类型，短路区的掺杂浓度大于漂移区的掺杂浓度。通过在上述绝缘栅双极型晶体管中设置间隔设置了多个短路区，从而在上述器件中不均有短路区的区域中，初始电子流形成的自偏压效应非常显著，因而使得不均有短路区的区域将先进入双极型导通模式，并产生钳位效应，继而随着电流的增大，双极型导通区电子流的横向分量也随之增大，就会不断触发周围短路区的双极型导通，从而确保在器件导通时双极电流从不 均有短路区的区域到短路区的快速平稳过渡，使得器件中的电流分配均匀，回跳现象被大大减弱，进而提高器件工作的稳定性和可靠性。Applying the technical solution of the present disclosure, an insulated gate bipolar transistor is provided. The transistor includes: an epitaxial layer; a drift region formed in the epitaxial layer, the drift region has an opposite first surface and a second surface, and the drift region has A first doping type; a plurality of super junctions formed in the drift region and spaced along a first direction, each super junction extending along a second direction and a third direction, the first direction being parallel to the first surface, and the second direction is the direction in which the first surface points to the second surface and is perpendicular to the second direction. The third direction is parallel to the first surface and different from the first direction. The super junction has a second doping type; the collector region is formed in On the second surface of the epitaxial layer, the collector region has a second doping type; a plurality of short-circuit regions are formed on the second surface and spaced along the third direction, and the projection of each super junction on the second surface is consistent with at least The projection of a short-circuit region on the second surface partially overlaps, the short-circuit region has a first doping type, and the doping concentration of the short-circuit region is greater than the doping concentration of the drift region. By arranging a plurality of short-circuit regions at intervals in the above-mentioned insulated gate bipolar transistor, in the region where there are uneven short-circuit regions in the above-mentioned device, the self-bias effect formed by the initial electron flow is very significant, thus causing unevenness. The area in the short-circuit area will first enter the bipolar conduction mode and produce a clamping effect. Then as the current increases, the lateral component of the electron flow in the bipolar conduction area also increases, which will continuously trigger the surrounding bipolar conduction in the short-circuit region, thereby ensuring that the bipolar current never flows from the The rapid and smooth transition from the area with short-circuit area to the short-circuit area makes the current in the device evenly distributed and the rebound phenomenon is greatly reduced, thereby improving the stability and reliability of the device's operation.
附图说明Description of the drawings
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：The description drawings that form a part of the present disclosure are used to provide a further understanding of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the attached picture:
图1示出了根据本公开的一种绝缘栅双极型晶体管的实施例的剖面结构示意图；Figure 1 shows a schematic cross-sectional structural diagram of an embodiment of an insulated gate bipolar transistor according to the present disclosure;
图2示出了图1中具有短路区的截面示意图；Figure 2 shows a schematic cross-sectional view of Figure 1 with a short-circuit area;
图3示出了图2所示的短路区电流的截面示意图；Figure 3 shows a cross-sectional schematic diagram of the current in the short circuit region shown in Figure 2;
图4示出了图1中具有引导IGBT区的截面示意图。FIG. 4 shows a schematic cross-sectional view of FIG. 1 with the guide IGBT region.
其中，上述附图包括以下附图标记：
1、集电区；2、漂移区；3、超级结；4、外延层；5、栅氧化层；6、栅极；7、掺杂阱；
8、发射区；9、介质层；10、发射极金属；11、集电极；12、集电极金属；13、短路区；14、第一超级结单元；15、第二超级结单元；16、第一短路区单元；17、第二短路区单元；18、第一区域；19、第二区域。Among them, the above-mentioned drawings include the following reference signs:
1. Collection area; 2. Drift area; 3. Super junction; 4. Epitaxial layer; 5. Gate oxide layer; 6. Gate; 7. Doped well;
8. Emitter area; 9. Dielectric layer; 10. Emitter metal; 11. Collector; 12. Collector metal; 13. Short circuit area; 14. First super junction unit; 15. Second super junction unit; 16. The first short-circuit area unit; 17. The second short-circuit area unit; 18. The first area; 19. The second area.
具体实施方式Detailed ways
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other. The present disclosure will be described in detail below in conjunction with embodiments with reference to the accompanying drawings.
为了使本技术领域的人员更好地理解本公开方案，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分的实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。In order to enable those skilled in the art to better understand the present disclosure, the following will clearly and completely describe the technical solutions in the present disclosure embodiments in conjunction with the accompanying drawings. Obviously, the described embodiments are only These are part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts should fall within the scope of protection of this disclosure.
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。It should be noted that the terms "first", "second", etc. in the description and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that data so used may be interchanged where appropriate for the embodiments of the disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.
本申请提出了一种绝缘栅双极型晶体管，如图1所示，该晶体管包括：外延层4；漂移区2，形成于外延层4中，漂移区2具有相对的第一表面和第二表面，且漂移区2具有第一掺杂类型；多个超级结3，形成于漂移区2中并沿第一方向A间隔设置，各超级结3均沿第二方向B和第三方向C延伸，第二方向B为第一表面指向第二表面的方向，第一方向A平行于第 一表面，第三方向C平行于第一表面且不同于第一方向A，超级结3具有第二掺杂类型；集电区1，形成于外延层4中的第二表面上，集电区1具有第二掺杂类型；多个短路区13，形成于第二表面上并沿第三方向C间隔设置，各超级结在第二表面上的投影与至少一个短路区13在第二表面上的投影部分重叠，且短路区13具有第一掺杂类型，短路区13的掺杂浓度大于漂移区2的掺杂浓度。This application proposes an insulated gate bipolar transistor, as shown in Figure 1. The transistor includes: an epitaxial layer 4; a drift region 2, which is formed in the epitaxial layer 4; the drift region 2 has an opposite first surface and a second surface, and the drift region 2 has a first doping type; a plurality of super junctions 3 are formed in the drift region 2 and are spaced apart along the first direction A, and each super junction 3 extends along the second direction B and the third direction C. , the second direction B is the direction from the first surface to the second surface, and the first direction A is parallel to the A surface, a third direction C is parallel to the first surface and different from the first direction A, the super junction 3 has a second doping type; a collector region 1 is formed on a second surface in the epitaxial layer 4, the collector region 1 has a second doping type; a plurality of short-circuit regions 13 are formed on the second surface and are spaced along the third direction C, and the projection of each super junction on the second surface is consistent with at least one short-circuit region 13 on the second surface The projections overlap, and the short-circuit region 13 has the first doping type, and the doping concentration of the short-circuit region 13 is greater than the doping concentration of the drift region 2 .
上述绝缘栅双极型晶体管器件中，通过在漂移区2的第二表面上设置间隔设置了多个短路区13，从而在上述器件中不均有短路区13的区域中，初始电子流形成的自偏压效应非常显著，因而使得不均有短路区13的区域将先进入双极型导通模式，并产生钳位效应，继而随着电流的增大，双极型导通区电子流的横向分量也随之增大，就会不断触发周围短路区13的双极型导通，从而确保在器件导通时双极电流从不均有短路区13的区域到短路区13的快速平稳过渡，使得器件中的电流分配均匀，回跳现象被大大减弱，进而提高器件工作的稳定性和可靠性。In the above-mentioned insulated gate bipolar transistor device, a plurality of short-circuit regions 13 are provided at intervals on the second surface of the drift region 2, so that in the regions where the short-circuit regions 13 are not uniformly present in the above-mentioned device, the initial electron flow is formed The self-bias effect is very significant, so that the area with uneven short-circuit area 13 will first enter the bipolar conduction mode and produce a clamping effect. Then as the current increases, the electron flow in the bipolar conduction area will decrease. The lateral component also increases, which will continuously trigger the bipolar conduction of the surrounding short-circuit area 13, thereby ensuring a fast and smooth transition of the bipolar current from the area with uneven short-circuit area 13 to the short-circuit area 13 when the device is turned on. , so that the current in the device is evenly distributed, and the rebound phenomenon is greatly reduced, thereby improving the stability and reliability of the device's operation.
如图1所示，上述器件还包括外延层4、栅氧化层5、至少一个栅极6、至少一个掺杂阱7、至少一个发射区8、至少一个介质层9以及发射极金属10。其中，外延层4设置于上述漂移区2的第一表面，掺杂阱7位于上述外延层4远离漂移区2的一侧，上述掺杂阱7具有第二掺杂类型，上述掺杂阱7还具有远离外延层4的第一侧和靠近外延层4的第二侧，栅极6自第一侧指向第二侧的方向延伸至外延层4中，栅氧化层5设置于栅极6的周围，使栅极6、外延层4以及掺杂阱7电性隔离，发射区8设置在掺杂阱7远离外延层4的一侧，并环绕在栅极6周围，介质层9设置于第一侧，介质层9与栅极6一一对应且完全掩盖栅极6，发射极金属10位于第一侧，并与发射区8接触，集电极11位于集电区1远离漂移区2的一侧，且集电极11与集电区1的掺杂类型一样，集电极11的掺杂浓度大于集电区1的掺杂浓度，集电极金属12位于集电极11和短路区13的一侧。As shown in FIG. 1 , the above device also includes an epitaxial layer 4 , a gate oxide layer 5 , at least one gate 6 , at least one doped well 7 , at least one emitter region 8 , at least one dielectric layer 9 and an emitter metal 10 . Wherein, the epitaxial layer 4 is disposed on the first surface of the above-mentioned drift region 2, and the doping well 7 is located on a side of the above-mentioned epitaxial layer 4 away from the drift region 2. The above-mentioned doping well 7 has a second doping type, and the above-mentioned doping well 7 It also has a first side away from the epitaxial layer 4 and a second side close to the epitaxial layer 4. The gate 6 extends from the first side to the second side into the epitaxial layer 4, and the gate oxide layer 5 is disposed on the gate electrode 6. around, the gate 6, the epitaxial layer 4 and the doped well 7 are electrically isolated. The emitter region 8 is disposed on the side of the doped well 7 away from the epitaxial layer 4 and surrounds the gate 6. The dielectric layer 9 is disposed on the third On one side, the dielectric layer 9 corresponds to the gate electrode 6 one-to-one and completely covers the gate electrode 6. The emitter metal 10 is located on the first side and is in contact with the emitter region 8. The collector electrode 11 is located on the side of the collector region 1 away from the drift region 2. side, and the doping type of the collector 11 is the same as that of the collector region 1, the doping concentration of the collector 11 is greater than that of the collector region 1, and the collector metal 12 is located on one side of the collector 11 and the short-circuit region 13.
在一些可选的实施方式中，上述外延层4的材料为锗(Ge)，由于IV族元素中Ge的晶格常数(5.646A)与Si的晶格常数(5.431A)差别最小，这使得SiGe与Si工艺易集成，且由于Si与SiGe晶格常数失配而导致Si单晶层受到下面SiGe层的拉伸应力而使得电子的迁移率得到增大，从而增大器件的工作饱和电流以及响应速度，提高器件的可靠性。In some optional embodiments, the material of the epitaxial layer 4 is germanium (Ge). Since the lattice constant of Ge (5.646A) and the lattice constant of Si (5.431A) among Group IV elements are minimally different, this makes SiGe and Si processes are easy to integrate, and due to the mismatch of lattice constants between Si and SiGe, the Si single crystal layer is subject to tensile stress by the underlying SiGe layer, which increases the mobility of electrons, thereby increasing the operating saturation current of the device and response speed and improve device reliability.
如图2所示，在一些可选的实施方式中，多个超级结包括多个超级结单元，各超级结单元包括多个超级结，各超级结单元在第二表面上的投影与多个短路区13在第二表面上的投影部分重叠。其中，上述多个超级结为沿着第一方向A间隔设置，且在上述第一方向A上，根据短路区13与超级结之间的重叠关系，当短路区13与上述多个超级结在第二表面上的投影有重叠时，则将与上述短路区13有重叠的多个超级结划分为一个超级结单元。As shown in Figure 2, in some optional implementations, multiple super junction units include multiple super junction units, each super junction unit includes multiple super junctions, and the projection of each super junction unit on the second surface is consistent with the plurality of super junction units. The projections of the short-circuit areas 13 on the second surface partially overlap. Wherein, the plurality of super junctions are spaced apart along the first direction A, and in the first direction A, according to the overlapping relationship between the short circuit region 13 and the super junction, when the short circuit region 13 and the plurality of super junctions are in When the projections on the second surface overlap, the plurality of super junctions that overlap with the short-circuit area 13 are divided into one super junction unit.
上述实施方式中，通过设置超级结单元在第二表面上的投影与多个短路区13在第二表面上的投影部分重叠，能够使得超级结靠近短路区13区域的空穴存储优先进入短路区13，如图3所示，而在不存在短路区13的区域，初始电子流形成的自偏压效应显著，使得在不存在短路区13的区域中优先进入双极导通模式，并随着电流的增大，不断触发短路区13周围的区域双极导通，从而减少回跳现象。 In the above embodiments, by arranging the projection of the super junction unit on the second surface to partially overlap with the projection of the plurality of short-circuit regions 13 on the second surface, the hole storage in the area of the super junction close to the short-circuit region 13 can be preferentially entered into the short-circuit region. 13, as shown in Figure 3, and in the area where the short-circuit area 13 does not exist, the self-bias effect formed by the initial electron flow is significant, so that the bipolar conduction mode is preferentially entered in the area where the short-circuit area 13 does not exist, and as the The increase in current continuously triggers bipolar conduction in the area around the short-circuit area 13, thereby reducing the rebound phenomenon.
在一些可选的实施方式中，超级结单元包括第一超级结单元14和第二超级结单元15，第一超级结单元14和第二超级结单元15沿第一方向A交替设置，第一超级结单元14中超级结的数量小于第二超级结单元15中超级结的数量，第一超级结单元14在第二表面上具有第一投影，第二超级结单元15在第二表面上具有第二投影，第一投影和第二投影与相同数量的短路区13在第二表面上的投影部分重叠。In some optional embodiments, the super junction unit includes a first super junction unit 14 and a second super junction unit 15. The first super junction unit 14 and the second super junction unit 15 are alternately arranged along the first direction A. The first super junction unit 14 and the second super junction unit 15 are alternately arranged along the first direction A. The number of super junctions in the super junction unit 14 is less than the number of super junctions in the second super junction unit 15. The first super junction unit 14 has a first projection on the second surface and the second super junction unit 15 has a first projection on the second surface. The second projection, the first projection and the second projection partially overlap with the same number of projections of the short-circuit areas 13 on the second surface.
示例性的，如图2所示，上述第一超级结单元14包括相邻的两个超级结，且上述相邻设置的两个超级结均与短路区13在第二表面上具有重叠投影，在沿着上述第一方向A上，第二超级结单元15包括相邻的四个超级结，且上述四个相邻的四个超级结均与短路区13在第二表面上具有重叠投影，第一超级结单元14与第二超级结单元15相邻设置，在第二超级结单元15远离第一超级结单元14的一侧，还具有相邻设置的两个超级结，且该相邻设置的了两个超级结均与短路区13在第二表面上具有重叠投影，即第一超级结单元14和第二超级结单元15沿第一方向A交替设置。For example, as shown in Figure 2, the first super junction unit 14 includes two adjacent super junctions, and the two adjacent super junctions have overlapping projections with the short-circuit region 13 on the second surface, Along the first direction A, the second super junction unit 15 includes four adjacent super junctions, and the four adjacent super junctions all have overlapping projections with the short circuit region 13 on the second surface, The first super junction unit 14 is arranged adjacent to the second super junction unit 15. On the side of the second super junction unit 15 away from the first super junction unit 14, there are two adjacent super junctions, and the adjacent super junction units 14 are arranged adjacent to each other. The two super junctions are arranged to have overlapping projections with the short circuit region 13 on the second surface, that is, the first super junction units 14 and the second super junction units 15 are alternately arranged along the first direction A.
上述实施方式中，为了使得器件在第一方向A上和第三方向C上具有均匀的电流流量，通过设置第一超级结单元14中超级结的数量小于第二超级结单元15中超级结的数量，从而使得位于器件中各超级结靠近短路区13区域中的空穴存储相对均匀的分布于器件体内。In the above embodiment, in order to ensure that the device has a uniform current flow in the first direction A and the third direction C, by setting the number of super junctions in the first super junction unit 14 to be smaller than the number of super junctions in the second super junction unit 15 quantity, so that the hole storage located in the region of each super junction near the short-circuit region 13 in the device is relatively evenly distributed within the device body.
在一些可选的实施方式中，多个短路区13包括第一短路区单元16和第二短路区单元17，第一短路区单元16中短路区13的数量大于第二短路区单元17中短路区13的数量，第一短路区单元16在第一表面上具有第三投影，第二短路区单元17在第一表面上具有第四投影，第一投影和第三投影部分重叠，第二投影和第四投影部分重叠。In some optional embodiments, the plurality of short-circuit areas 13 include a first short-circuit area unit 16 and a second short-circuit area unit 17 . The number of short-circuit areas 13 in the first short-circuit area unit 16 is greater than the number of short-circuit areas 13 in the second short-circuit area unit 17 . The number of areas 13, the first short-circuit area unit 16 has a third projection on the first surface, the second short-circuit area unit 17 has a fourth projection on the first surface, the first projection and the third projection partially overlap, the second projection Partially overlaps with the fourth projection.
其中，上述每个短路区单元包括多个短路区13，示例性的，如图2所示，在上述第一方向A上，上述第一短路区单元16包括与相邻两个超级结在第二表面上的投影重叠的多个短路区13，将该投影作为第三投影，上述第二短路单元的多个短路区13与相邻四个超级结在第二表面上的投影重叠，将该投影作为第四投影。Each of the above-mentioned short-circuit area units includes a plurality of short-circuit areas 13. For example, as shown in FIG. 2, in the above-mentioned first direction A, the above-mentioned first short-circuit area unit 16 includes two adjacent super junctions at the first The projections of the multiple short-circuit areas 13 overlapping on the two surfaces are regarded as the third projection. The multiple short-circuit areas 13 of the above-mentioned second short-circuit unit overlap with the projections of the four adjacent super junctions on the second surface, and the projections are regarded as the third projection. Projection as the fourth projection.
上述实施方式中，为了使得器件在第一方向A上和第三方向C上具有均匀的电流流量，通过第一短路区单元16中短路区13的数量大于第二短路区单元17中短路区13的数量，从而使得位于器件中各超级结靠近短路区13区域中的空穴存储相对均匀的分布于器件体内。In the above embodiment, in order to allow the device to have a uniform current flow in the first direction A and the third direction C, the number of short-circuit areas 13 passing through the first short-circuit area unit 16 is greater than the number of short-circuit areas 13 in the second short-circuit area unit 17 The number of holes stored in each super junction near the short-circuit region 13 in the device is relatively uniformly distributed within the device body.
在一些可选的实施方式中，在第三方向C上，第一短路区单元16中的相邻短路区13具有相同的第一间距，第二短路区单元17中的相邻短路区13具有相同的第二间距，第一间距等于第二间距。上述实施方式中，将在第三方向C上相邻两个短路区13之间的间距作为第一间距，通过设置在第三方向C上相邻两个短路区13之间的间距相等，使得在器件开通时，双极电流在第三方向C上能够平稳过渡，将在第一方向A上相邻两个短路区13之间的间距作为第二间距，通过设置在第一方向A上相邻两个短路区13之间的间距相等，使得在器件开通过程中，双极电流在第一方向A上能够平稳过渡。In some optional implementations, in the third direction C, adjacent short-circuit areas 13 in the first short-circuit area unit 16 have the same first spacing, and adjacent short-circuit areas 13 in the second short-circuit area unit 17 have the same first spacing. The same second spacing, the first spacing is equal to the second spacing. In the above embodiment, the spacing between two adjacent short-circuit regions 13 in the third direction C is used as the first spacing, and the spacing between two adjacent short-circuit regions 13 in the third direction C is set to be equal, so that When the device is turned on, the bipolar current can smoothly transition in the third direction C. The distance between two adjacent short-circuit areas 13 in the first direction A is used as the second distance. By setting the phase in the first direction A, The spacing between two adjacent short-circuit areas 13 is equal, so that the bipolar current can smoothly transition in the first direction A during the device turn-on process.
在一些可选的实施方式中，各第三投影沿第一方向A延伸后重叠，且各第三投影沿第一方向A延伸后与第四投影不重叠。上述实施方式中，第三投影为第一短路区单元16在第二表 面上的投影，第四投影为第二短路区单元17在第二表面上的投影，当沿着上述第一方向A延伸时，上述第三投影与第四投影不重叠，从而使得器件中的短路区13能够呈现出正交型分布，进而有利于双极导通区内电子流在横向分量增大的情况下，触发短路区13周围区域的双极导通，减少器件中电流分配不均的问题，改善回跳现象。In some optional implementations, each third projection extends along the first direction A and then overlaps, and each third projection does not overlap with the fourth projection after extending along the first direction A. In the above embodiment, the third projection is that the first short-circuit area unit 16 is in the second surface The fourth projection is the projection of the second short-circuit area unit 17 on the second surface. When extending along the first direction A, the third projection and the fourth projection do not overlap, so that the The short-circuit area 13 can present an orthogonal distribution, which is conducive to triggering bipolar conduction in the area around the short-circuit area 13 when the lateral component of the electron flow in the bipolar conduction area increases, reducing uneven current distribution in the device. problem and improve the rebound phenomenon.
在一些可选的实施中，在第三方向C上，各第一投影具有位于第三投影两侧的第一区域18，各第二投影具有位于相邻第四投影之间的第二区域19；在第一方向A上，第一区域18延伸后与第二区域19不重叠。如图4所示，上述实施方式中，将位于第一超级结单元14与第一短路区单元16的投影重叠区域两侧的区域分别作为第一区域18，将位于相邻第二超级结单元15与第二短路单元的投影重叠区域之间的区域分为多个与第一区域18面积相同的第二区域19，且在上述第一方向A上，第一区域18与第二短路单元的投影交替设置，第二区域19与第一短路单元的投影交替设置，因而在上述第一方向A上，第一区域18延伸后与第二区域19不重叠。In some optional implementations, in the third direction C, each first projection has a first area 18 located on both sides of the third projection, and each second projection has a second area 19 located between adjacent fourth projections. ; In the first direction A, the first region 18 does not overlap with the second region 19 after extending. As shown in FIG. 4 , in the above embodiment, the areas on both sides of the projected overlapping area of the first super junction unit 14 and the first short-circuit area unit 16 are respectively regarded as the first areas 18 , and the areas located on the adjacent second super junction unit are The area between 15 and the projected overlapping area of the second short-circuit unit is divided into a plurality of second areas 19 with the same area as the first area 18, and in the above-mentioned first direction A, the area between the first area 18 and the second short-circuit unit The projections are alternately arranged, and the projections of the second area 19 and the first short-circuit unit are arranged alternately. Therefore, in the above-mentioned first direction A, the first area 18 does not overlap with the second area 19 after extending.
通过上述实施方式中的设置方式，使得上述第一区域18和第二区域19作为器件中的引导区，由于引导区中不存在短路区13，使得在引导区中的初始电子流形成的自偏压效应非常显著，因而该区域将最先进入双极导通模式并产生钳位效应，随着电流的增大，双极导通区内的电子流的横向分量也随之增大，就会不断触发周围引导区双极导通，从而减少回跳现象，使得双极导通范围快速扩大到器件的整个面积。Through the arrangement in the above embodiment, the above-mentioned first region 18 and the second region 19 serve as the guide region in the device. Since there is no short-circuit region 13 in the guide region, the self-bias formed by the initial electron flow in the guide region The voltage effect is very significant, so this area will enter the bipolar conduction mode first and produce a clamping effect. As the current increases, the lateral component of the electron flow in the bipolar conduction area also increases, and there will be The bipolar conduction in the surrounding guide area is continuously triggered, thereby reducing the rebound phenomenon and allowing the bipolar conduction range to quickly expand to the entire area of the device.
其中，上述引导区包括矩形、十字型等不同形状，其大小、数量、形状以及面积等可以包括不同的设计。示例性的，如图4所示，按照矩形的形状，将器件等分，以确保器件在开通时双极电流能够从引导区到器件的其余位置的快速平稳过渡。Wherein, the above-mentioned guide area includes different shapes such as rectangle and cross, and its size, quantity, shape, area, etc. can include different designs. For example, as shown in Figure 4, the device is divided into equal parts according to a rectangular shape to ensure that the bipolar current can quickly and smoothly transition from the leading area to the rest of the device when the device is turned on.
在一些可选的实施方式中，各超级结在第一表面上的投影面积相等，且各短路区13在第一表面上的投影面积相等，从而使得器件中的电流流量能够均匀的分布，进而横向促进器件进入全面性的双极导通。In some optional implementations, the projected areas of each super junction on the first surface are equal, and the projected areas of each short-circuit region 13 on the first surface are equal, so that the current flow in the device can be evenly distributed, and thus the current flow in the device can be evenly distributed. Laterally, the device is promoted into full bipolar conduction.
在一些可选的实施方式中，相邻超级结沿第一方向A等间距设置。上述实施方式中，等间距设置的超级结结构能够同等程度的降低器件各部分的电导调制效应，进而大大改善器件的电流拖尾现象。In some optional implementations, adjacent super junctions are arranged at equal intervals along the first direction A. In the above embodiments, the super junction structures arranged at equal intervals can reduce the conductance modulation effect of each part of the device to the same extent, thereby greatly improving the current tailing phenomenon of the device.
在一些可选的实施方式中，第一方向A与第三方向C垂直。上述实施方式中，由于第一方向A和第三方向C垂直，则位于器件中的多个短路区13周围的区域相当于均匀分布在器件四周的很大面积的引导区，能够更有利于减弱回跳，有效改善电流分配不均的问题。In some optional implementations, the first direction A is perpendicular to the third direction C. In the above embodiment, since the first direction A and the third direction C are perpendicular, the area around the multiple short-circuit areas 13 in the device is equivalent to a large area of guide areas evenly distributed around the device, which can be more conducive to weakening Rebound, effectively improving the problem of uneven current distribution.
示例性的，如图2至图4所示，第一超级结单元14由两个超级结3组成，第二超级结单元15由四个超级结3组成，第一超级结单元14与第二超级结单元15沿第一方向A交替设置，第一短路区单元16由四个短路区13组成，第二短路区单元17由两个短路区13组成，第一超级结单元14具有在第二表面上的第一投影，第一短路区单元16具有在第二表面上的第三投影，第一投影中具有沿第三方向C位于第三投影两侧的区域，即图4中位于四角处的四个第一区域18，第二超级结单元15具有在第二表面上的第二投影，第二短路区单元17具有在 第二表面上的第四投影，第二投影中具有沿第三方向C位于两个第三投影之间的区域，即图4中位于中部的四个第二区域19，第一区域18与第二区域19面积相等，且在第一方向A上，第一区域18延伸后与第二区域19不重叠。For example, as shown in FIGS. 2 to 4 , the first super junction unit 14 is composed of two super junctions 3 , the second super junction unit 15 is composed of four super junctions 3 , and the first super junction unit 14 and the second super junction unit 15 are composed of four super junctions 3 . The super junction units 15 are alternately arranged along the first direction A, the first short circuit area unit 16 is composed of four short circuit areas 13, the second short circuit area unit 17 is composed of two short circuit areas 13, and the first super junction unit 14 has a second short circuit area unit 13. The first projection on the surface, the first short-circuit area unit 16 has a third projection on the second surface, and the first projection has areas located on both sides of the third projection along the third direction C, that is, located at the four corners in Figure 4 of four first regions 18, the second superjunction unit 15 has a second projection on the second surface, and the second short-circuit area unit 17 has The fourth projection on the second surface, the second projection has an area between the two third projections along the third direction C, that is, the four second areas 19 located in the middle in Figure 4, the first area 18 and the The two regions 19 have equal areas, and in the first direction A, the first region 18 does not overlap with the second region 19 after extending.
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。 The above descriptions are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this disclosure shall be included in the protection scope of this disclosure.

Claims (10)

  1. 一种绝缘栅双极型晶体管，包括：An insulated gate bipolar transistor, including:
    外延层；epitaxial layer;
    漂移区，形成于所述外延层中，所述漂移区具有相对的第一表面和第二表面，且所述漂移区具有第一掺杂类型；a drift region formed in the epitaxial layer, the drift region having opposite first and second surfaces, and the drift region having a first doping type;
    多个超级结，形成于所述漂移区中并沿第一方向间隔设置，各所述超级结均沿第二方向和第三方向延伸，所述第一方向平行于所述第一表面，所述第二方向为所述第一表面指向所述第二表面的方向，所述第三方向平行于所述第一表面且不同于所述第一方向，所述超级结具有第二掺杂类型；A plurality of super junctions are formed in the drift region and are spaced apart along the first direction. Each of the super junctions extends along the second direction and the third direction. The first direction is parallel to the first surface, so The second direction is a direction in which the first surface points to the second surface, the third direction is parallel to the first surface and different from the first direction, and the super junction has a second doping type. ;
    集电区，形成于所述外延层中的第二表面上，所述集电区具有所述第二掺杂类型；a collector region formed on the second surface in the epitaxial layer, the collector region having the second doping type;
    多个短路区，形成于所述第二表面上并沿所述第三方向间隔设置，各所述超级结在所述第二表面上的投影与至少一个所述短路区在所述第二表面上的投影部分重叠，且所述短路区具有所述第一掺杂类型，所述短路区的掺杂浓度大于所述漂移区的掺杂浓度。A plurality of short-circuit regions are formed on the second surface and are spaced apart along the third direction. The projection of each super junction on the second surface is consistent with at least one of the short-circuit regions on the second surface. The projections above partially overlap, and the short-circuit region has the first doping type, and the doping concentration of the short-circuit region is greater than the doping concentration of the drift region.
  2. 根据权利要求1所述的绝缘栅双极型晶体管，其中，所述多个超级结包括多个超级结单元，各所述超级结单元包括多个所述超级结，各所述超级结单元在所述第二表面上的投影与多个所述短路区在所述第二表面上的投影部分重叠。The insulated gate bipolar transistor according to claim 1, wherein the plurality of super junction units includes a plurality of super junction units, each of the super junction units includes a plurality of the super junction units, and each of the super junction units is in The projection on the second surface partially overlaps with the projections of the plurality of short-circuit areas on the second surface.
  3. 根据权利要求2所述的绝缘栅双极型晶体管，其中，所述超级结单元包括第一超级结单元和第二超级结单元，所述第一超级结单元和所述第二超级结单元沿所述第一方向交替设置，所述第一超级结单元中所述超级结的数量小于所述第二超级结单元中所述超级结的数量，所述第一超级结单元在所述第二表面上具有第一投影，所述第二超级结单元在所述第二表面上具有第二投影，所述第一投影和所述第二投影与相同数量的所述短路区在所述第二表面上的投影部分重叠。The insulated gate bipolar transistor according to claim 2, wherein the super junction unit includes a first super junction unit and a second super junction unit, the first super junction unit and the second super junction unit extend along The first directions are alternately arranged, the number of super knots in the first super knot unit is smaller than the number of super knots in the second super knot unit, and the first super knot unit is in the second super knot unit. There is a first projection on the surface, the second super junction unit has a second projection on the second surface, the first projection and the second projection have the same number of short-circuit areas on the second surface. The projections on the surface partially overlap.
  4. 根据权利要求3所述的绝缘栅双极型晶体管，其中，所述多个短路区包括第一短路区单元和第二短路区单元，所述第一短路区单元中所述短路区的数量大于所述第二短路区单元中所述短路区的数量，所述第一短路区单元在所述第一表面上具有第三投影，所述第二短路区单元在所述第一表面上具有第四投影，所述第一投影和所述第三投影部分重叠，所述第二投影和所述第四投影部分重叠。The insulated gate bipolar transistor according to claim 3, wherein the plurality of short-circuit regions include a first short-circuit region unit and a second short-circuit region unit, and the number of the short-circuit regions in the first short-circuit region unit is greater than The number of the short-circuit areas in the second short-circuit area unit, the first short-circuit area unit has a third projection on the first surface, and the second short-circuit area unit has a third projection on the first surface. Four projections, the first projection and the third projection partially overlap, and the second projection and the fourth projection partially overlap.
  5. 根据权利要求4所述的绝缘栅双极型晶体管，其中，在所述第三方向上，所述第一短路区单元中的相邻所述短路区具有相同的第一间距，所述第二短路区单元中的相邻所述短路区具有相同的第二间距，所述第一间距等于所述第二间距。The insulated gate bipolar transistor according to claim 4, wherein in the third direction, adjacent short-circuit regions in the first short-circuit region unit have the same first spacing, and the second short-circuit region Adjacent short-circuit regions in a region unit have the same second spacing, and the first spacing is equal to the second spacing.
  6. 根据权利要求4所述的绝缘栅双极型晶体管，其中，各所述第三投影沿所述第一方向延伸后重叠，且各所述第三投影沿所述第一方向延伸后与所述第四投影不重叠。The insulated gate bipolar transistor according to claim 4, wherein each of the third projections extends along the first direction and then overlaps, and each of the third projections extends along the first direction and overlaps with the The fourth projection does not overlap.
  7. 根据权利要求6所述的绝缘栅双极型晶体管，其中， The insulated gate bipolar transistor according to claim 6, wherein
    在所述第三方向上，各所述第一投影具有分别位于所述第三投影两侧的第一区域，各所述第二投影具有位于相邻第四投影之间的多个第二区域，各所述第一区域与各所述第二区域面积相等；In the third direction, each of the first projections has a first area respectively located on both sides of the third projection, and each of the second projections has a plurality of second areas located between adjacent fourth projections, The area of each first region is equal to that of each second region;
    在所述第一方向上，所述第一区域延伸后与所述第二区域不重叠。In the first direction, the first region does not overlap with the second region after extending.
  8. 根据权利要求1至7中任一项所述的绝缘栅双极型晶体管，其中，各所述超级结在所述第一表面上的投影面积相等，且各所述短路区在所述第一表面上的投影面积相等。The insulated gate bipolar transistor according to any one of claims 1 to 7, wherein the projected areas of each super junction on the first surface are equal, and each of the short-circuit regions is on the first surface. The projected areas on the surface are equal.
  9. 根据权利要求1至7中任一项所述的绝缘栅双极型晶体管，其中，相邻所述超级结沿所述第一方向等间距设置。The insulated gate bipolar transistor according to any one of claims 1 to 7, wherein adjacent super junctions are arranged at equal intervals along the first direction.
  10. 根据权利要求1至7中任一项所述的绝缘栅双极型晶体管，其中，所述第一方向与所述第三方向垂直。 The insulated gate bipolar transistor according to any one of claims 1 to 7, wherein the first direction is perpendicular to the third direction.
PCT/CN2023/105186 2022-07-04 2023-06-30 Insulated gate bipolar transistor WO2024008015A1 (en)

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CN107464842A (en) * 2017-08-03 2017-12-12 电子科技大学 A kind of superjunction with colelctor electrode groove is against conductivity type IGBT
CN109449202A (en) * 2018-10-30 2019-03-08 广州工商学院 One kind is inverse to lead bipolar junction transistor
CN109888005A (en) * 2019-01-22 2019-06-14 上海华虹宏力半导体制造有限公司 Inverse conductivity type superjunction IGBT device and its manufacturing method
CN115132825A (en) * 2022-07-04 2022-09-30 深圳市千屹芯科技有限公司 Insulated gate bipolar transistor

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CN107464842A (en) * 2017-08-03 2017-12-12 电子科技大学 A kind of superjunction with colelctor electrode groove is against conductivity type IGBT
CN109449202A (en) * 2018-10-30 2019-03-08 广州工商学院 One kind is inverse to lead bipolar junction transistor
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