WO2024007586A1 - 一种三层堆叠结构晶圆的制备方法及应用 - Google Patents

一种三层堆叠结构晶圆的制备方法及应用 Download PDF

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Publication number
WO2024007586A1
WO2024007586A1 PCT/CN2023/075464 CN2023075464W WO2024007586A1 WO 2024007586 A1 WO2024007586 A1 WO 2024007586A1 CN 2023075464 W CN2023075464 W CN 2023075464W WO 2024007586 A1 WO2024007586 A1 WO 2024007586A1
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layer
wafer
photoelectric conversion
optical waveguide
stacked structure
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PCT/CN2023/075464
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English (en)
French (fr)
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赵子强
单子豪
周武平
黄锦熙
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杭州视光半导体科技有限公司
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Publication of WO2024007586A1 publication Critical patent/WO2024007586A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/11—Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention belongs to the field of semiconductor technology and materials, and particularly relates to a preparation method and application of a three-layer stacked structure wafer based on heterogeneous integration. Based on the wafer, semiconductors containing passive/active optoelectronic devices with multiple functions can be prepared. Wafer platform, which can be used for applications such as free space/link space communication, free space/link sensing and biomedical sensing in a wide wavelength range.
  • these PICs must operate on a predetermined channel wavelength plan, since optical signals of different wavelengths are typically provided from multiple remote and discrete transmitters.
  • the traditional PIC process was first based on planar light wave circuits.
  • This type of platform mainly uses ion implantation or diffusion to selectively dope glass wafers (such as quartz, oxides, nonlinear crystals, etc.) to form a mutation area of refractive index to form a light field localization. domain mode.
  • the advantage of this type of platform lies in extremely low light wave transmission loss.
  • the refractive index change (core layer/substrate refractive index contrast) in its waveguide area generally does not exceed 5%, which makes the chip size generally at the cm level.
  • gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), and indium gallium arsenide phosphide (InGaAsP) can be used for 850nm, 1300nm, and 1550nm PICs. Its semiconductor bandgap can be fine-tuned by introducing recipe control or external doping. Furthermore, indium (In), Other tertiary and ternary semiconductor materials such as gallium (Ga), aluminum (Al), arsenic (As) and phosphorus (P) are used in PICs across the visible and near-UV regions. Devices with different functions are often made from different but compatible semiconductor materials. Although through targeted design some structures can provide light amplification and photodetection with reverse bias polarity, the choice of substrate and waveguide design still remains. It has a profound impact on both the design and manufacturing of PIC.
  • Ion-cut technology generally refers to the use of high-energy, large-injection ion (such as H + , H 2 + , He, etc.) beams to bombard the interior of the material through electromagnetic coil acceleration to form a defect-enriched layer.
  • ions in the defect-enriched layer will spontaneously aggregate into gas molecules and be stored in the lattice defects caused by ion bombardment.
  • the stress generated inside them will cause the material to The lattice defects in the film further expand to form a scaly splitting phenomenon.
  • a wide range of semiconductor material thin films can be prepared. The advantage of this method is that the film thickness is controllable, but the annealing process can easily introduce additional thermal stress and cause wafer cracks.
  • Direct wafer bonding refers to the process of contacting and bonding two separate wafer surfaces without any intermediate adhesive or external force.
  • Direct wafer bonding currently has a variety of applications in the microelectronics industry. Examples of semiconductor process applications include substrate engineering, fabrication of integrated circuits, packaging and encapsulation of micro-electromechanical-systems (MEMS), and many processed parts of pure microelectronic components. Stacking of layers (3D integration).
  • MEMS micro-electromechanical-systems
  • Stacking of layers (3D integration).
  • the advantage is that it directly utilizes dangling bonds on the interface of semiconductor materials (typically Si-Si bonding), thus facilitating the formation of a vertical semiconductor junction structure.
  • the disadvantage of direct bonding is its stringent requirements on the surface state of the wafer. Generally, the surface wafer roughness (roughness mean square, RMS) is required to be less than 0.5nm.
  • Adhesive bonding refers to the formation of a dielectric layer on the surface of the wafer to be bonded by spin coating, deposition, sputtering, evaporation or growth.
  • the bonding between wafers is achieved through the molecular force of the materials in the dielectric layer. combine.
  • This type of bonding method can make the interface between the bonded wafer combinations have good electrical insulation.
  • its disadvantage is that defects at the dielectric layer interface can easily lead to device failure.
  • an improved PIC preparation process is based on compound semiconductor wafers (III-V Optoelectronic interconnections between binary, ternary and quaternary alloys of groups II-VI and their quantum structures) and semiconductors on insulating layers.
  • the preparation method can be based on direct or adhesive bonding, and quantum structures can be introduced to achieve the functions of optical gain and light signal detection.
  • wafers with different forbidden band gaps need to be introduced, so the bonding process between compound semiconductor wafers of various structures and semiconductors on the insulating layer needs to be considered.
  • One way is to fine-tune the forbidden band gap by perturbing the quantum structure (such as quantum well intermixing).
  • damage to the quantum structure will also reduce the reliability of the device.
  • the compound semiconductor wafer can also be pre-divided and bonded to the semiconductor on the insulating layer one by one.
  • a large amount of wafer area must be sacrificed in actual production to ensure the bonding area.
  • Independence, which at the same time easily introduces too low yield rates.
  • optical crystals on the insulating layer can also be used in the PIC preparation process.
  • LNOI lithium niobate on the insulating layer, LNOI, etc.
  • its preparation method is similar to that of SOI.
  • the optical signal modulation of LNOI relies on the electro-optical effect of lithium niobate crystal, so the design of its driving circuit can be greatly simplified.
  • the etching of lithium niobate will introduce additional metal ions, so it cannot be improved on the basis of existing CMOS.
  • dry etching of lithium niobate is difficult to achieve a smooth and flat waveguide interface, its high-density and high-precision PIC integration is still difficult to achieve.
  • the purpose of the present disclosure is to provide a preparation method and application of a three-layer stacked structure wafer. Based on this wafer, a semiconductor wafer containing multiple functional passive/active optoelectronic devices can be prepared. platform.
  • the object of the present invention is achieved through the following technical solution: a method for preparing a three-layer stacked structure wafer.
  • the three-layer stacked structure wafer is composed of a substrate wafer, an intermediate layer wafer and a top layer wafer/slice. formed by stacking;
  • the substrate wafer has a signal modulation layer, the middle layer wafer has an optical waveguide layer, and the top wafer/slice has a photoelectric conversion layer;
  • the substrate wafer and the intermediate layer wafer are combined and thinned to obtain the optical waveguide wafer;
  • the optical waveguide wafer is combined with the top wafer/slice and thinned to obtain the final three-layer stacked structure wafer.
  • the signal modulation layer, optical waveguide layer, and photoelectric conversion layer are mutually heterogeneous materials, specifically:
  • the signal modulation layer contains one or more material systems that can be used as modulators;
  • the optical waveguide layer includes one or more of the following: III-V semiconductor materials, II-VI semiconductor materials, IV semiconductor materials, nitride or oxide materials, lead salt materials, quartz, nonlinear Crystals and optical glasses;
  • the photoelectric conversion layer includes one or more of the following: III-V semiconductor materials and one- or multi-component alloys thereof, II-VI semiconductor materials and one-component or multi-component alloys thereof, Group IV semiconductor materials and one-component or multi-component alloys thereof , and quantum structures based on the above material systems.
  • the signal modulation layer is on the top layer of the substrate wafer;
  • the optical waveguide layer is on the top layer of the intermediate layer wafer;
  • the top layer of the substrate wafer and the intermediate layer wafer is pre-processed with surface dangling bonds, and then combined.
  • the intermediate layer wafer combined with the substrate wafer is thinned to retain the optical guide. Wave layer and post-processing to obtain optical waveguide wafer.
  • the photoelectric conversion layer is on the top layer of the top wafer/slice; the photoelectric conversion layer has the conversion between photoelectric signals and/or the gain function of the optical signal;
  • the top layer of the optical waveguide wafer is first pattern-defined and etched to form a flat dielectric layer, and then the surface of the dielectric layer is pre-treated with dangling bonds, and then combined with the top wafer/slice to form a flat dielectric layer.
  • the top wafer/slice combined with the optical waveguide wafer is thinned to retain the photoelectric conversion layer to obtain the final three-layer stacked structure wafer.
  • pattern definition and etching are performed on the top layer of the three-layer stacked structure wafer, a protective layer is formed on the top layer of the etched three-layer stacked structure wafer, and metal electrodes are formed and packaged.
  • the photoelectric conversion layer is formed by stacking an N-type contact layer, a quantum structure layer, and a P-type contact layer in sequence. At this time, the electric field of the PN junction or PIN junction is directed perpendicular to the top surface. By adjusting the thickness and composition of the quantum structure layer It can make the photoelectric conversion layer have the functions of generating, amplifying and receiving optical signals at the same time. Energy; Alternatively, the photoelectric conversion layer is stacked by a mode matching layer and a quantum structure layer, where P-type contact and N-type contact need to be formed in the mode matching layer. At this time, the electric field of the PN junction or PIN junction is directed parallel to the top surface. , by jointly adjusting the thickness and composition of the mode matching layer and the quantum structure layer, the photoelectric conversion layer can simultaneously have the functions of generating, amplifying and receiving optical signals.
  • the material of the photoelectric conversion layer is III-V compound semiconductor and its quantum structure, and the thickness is 0.1-1.5 microns;
  • the material of the optical waveguide layer is silicon, and the thickness is 0.2-0.5 microns;
  • the material of the signal modulation layer is lithium niobate, and the thickness is 0.1-10 microns;
  • the carrier layer of the three-layer stacked structure wafer is a single crystal silicon layer, or a combination of a single crystal silicon layer and a silicon oxide layer, with a thickness of 325-825 microns.
  • the three-layer stacked structure wafer prepared by the present invention can realize modulator/transmitter/amplifier/receiver functions based on the combination of signal modulation layer, optical waveguide layer and photoelectric conversion layer.
  • the implementation carrier is a signal modulation layer, and in the TM mode of electric field distribution, phase modulation is achieved through the electro-optical effect. Its good modulation linearity can greatly simplify the design and power consumption of peripheral drive circuits, and is also suitable for large-scale array integration.
  • the implementation carrier is a photoelectric conversion layer, and the transmitter/amplifier/receiver functions are realized by regulating the electric field distribution in the super-mode waveguide with a three-layer stacked structure.
  • the material layer structure in the photoelectric conversion layer and the quantum structure it contains can be optimized to make it suitable for large-scale photoelectric signal processing.
  • the beneficial effects of the present invention are: by integrating three heterogeneous materials on the same wafer, the present invention can effectively avoid the high insertion loss and high processing difficulty that are easily produced by traditional methods when using optical waveguide layers for signal modulation. Inherent defects. By transferring signal modulation and photoelectric conversion to corresponding layers for processing, the material properties of each layer can be fully utilized to achieve high-performance, highly integrated integrated optoelectronic device chips.
  • Figure 1 is a flow chart of a method for preparing a three-layer stacked structure wafer in an embodiment provided by the present disclosure
  • Figure 2(a) is a structural diagram of the first alternative W00-a of the three-layer stacked structure wafer in the embodiment provided by the present disclosure
  • Figure 2(b) is the third alternative W00-a of the three-layer stacked structure wafer in the embodiment provided by the present disclosure.
  • Figure 3(a) is a layer structure diagram of the intermediate layer wafer W02 in an embodiment provided by the present disclosure
  • Figure 3(b) is a layer structure diagram of the substrate wafer W01 in an embodiment provided by the present disclosure
  • Figure 3(c) ) is a layer structure diagram of the intermediate layer wafer W02 after plasma surface activation treatment in the embodiment provided by the present disclosure
  • Figure 3(d) is a layer structure diagram of the substrate wafer W01 after plasma surface activation treatment in the embodiment provided by the present disclosure. layer structure diagram;
  • Figure 4(a) is a layer structure diagram of the optical waveguide wafer W41 after step S04 in the embodiment provided by the present disclosure
  • Figure 4(b) is the layer structure diagram of the optical waveguide wafer W41 after step S05 in the embodiment provided by the present disclosure.
  • Figure 4(c) is the layer structure diagram of the optical waveguide wafer W41 after step S06 in the embodiment provided by the disclosure;
  • Figure 4(d) is the optical waveguide wafer W41 in the embodiment provided by the disclosure.
  • Circle W41 is processed in step S06 and filled with the layer structure diagram of the dielectric layer;
  • Figure 5 is a layer structure diagram of the top wafer/slice first alternative W03-a and the top wafer/slice second alternative W03-b in the embodiment provided by the present disclosure
  • Figures 6(a1) and 6(a2) are respectively the wafer front top view and layer structure diagram of the first alternative W00-a of the three-layer stacked structure wafer in the embodiment provided by the present disclosure
  • Figure 6(b1) and Figure 6(b2) is respectively a wafer front plan view and a layer structure diagram of the second alternative W00-b of the three-layer stacked structure wafer in the embodiment provided by the present disclosure
  • Figure 7(a) is a layer structure diagram of the optical waveguide wafer W41 in the embodiment provided by the present disclosure after being combined with the top wafer/slice W03 after step S08;
  • Figure 7(b) is a view of the optical waveguide wafer W41 in the embodiment provided by the present disclosure.
  • the layer structure diagram after the waveguide wafer W41 is processed in step S09 and combined with the top wafer/slice W03;
  • Figure 7(c) is the optical waveguide wafer W41 processed in step S10 and combined with the top wafer/slice in an embodiment provided by the present disclosure.
  • Figure 7(d) is a layer structure diagram of the optical waveguide wafer W41 in the embodiment provided by the present disclosure after being processed in step S10 and combined with the top wafer/slice W03 and introducing the protective layer I02;
  • Figure 8(a) is a schematic structural diagram of a modulator based on the optical waveguide layer L02 and the signal modulation layer L03 in the embodiment provided by the present disclosure
  • Figure 8(b) is a schematic diagram of the modulator based on the signal modulation layer L03, L03, and the signal modulation layer L03 in the embodiment provided by the present disclosure.
  • the material system includes three layer structures with different purposes, namely the signal modulation layer L03 , optical waveguide layer L02 and photoelectric conversion layer L01.
  • the signal modulation layer L03 includes one or more material systems that can be used as modulators.
  • the optical waveguide layer L02 includes one or more of the following: III-V semiconductor materials, II-VI semiconductor materials, IV semiconductor materials, nitride or oxide materials, lead salt materials, Quartz, nonlinear crystal and optical glass, etc.
  • the photoelectric conversion layer L01 includes one or more of the following: III-V semiconductor materials and their one-element or multi-element alloys, II-VI group semiconductor materials and their one-element or multi-element alloys, group IV semiconductor materials and their one-element or multi-element alloys, and quantum structures based on the above material systems.
  • the material system of the signal modulation layer L03 is selected as lithium niobate crystal.
  • the material system of the optical waveguide layer L02 is selected from silicon.
  • the material system of the photoelectric conversion layer L01 is selected as III-V compound semiconductor and its quantum structure.
  • Figure 1 is a flow chart of a method for preparing a three-layer stacked wafer according to an embodiment of the present application. The method includes the following steps:
  • solution W00-a includes: photoelectric conversion layer L01, optical waveguide layer L02, signal modulation layer L03, substrate insulating layer L04 and substrate structural layer L05.
  • solution W00-b includes: a photoelectric conversion layer L01, an optical waveguide layer L02, and a signal modulation layer L03.
  • the layer structure structure needs to consider the thermal budget of the wafer in the production process line.
  • the coefficient of thermal expansion (CTE) and the coefficient of thermal conductivity (CTC) between each layer need to be carefully considered.
  • thermal expansion coefficients and thermal conductivity coefficients of each layer material are as shown in Table 1:
  • the CTE contrast between its CTE and the functional material silicon of the optical waveguide layer L02 can reach 288%-554%, which will result in the layer structure stacking process.
  • the rapid failure of the thermal budget eventually causes the wafer to be scrapped.
  • the thermal stress caused by the CTE difference can be compensated by transferring the material of the signal modulation layer L03 to a material system with a thermal expansion coefficient similar to that of the optical waveguide layer L02.
  • the signal modulation layer L03, the substrate insulation layer L04 and the substrate structure layer L05 constitute the substrate wafer W01, as shown in Figure 3(b). Further, the substrate insulating layer L04 and the substrate structural layer L05 together constitute the bearing layer L41. In some special cases, the substrate insulating layer L04 and the substrate structural layer L05 may be made of the same material. In particular, for the substrate wafer W01 composed of lithium niobate, its specific implementation method has been described in detail in other disclosures, so the preparation method of the substrate wafer W01 will not be described again in this disclosure.
  • a substrate wafer W01 is provided, in which the signal modulation layer L03 has been integrated on the substrate wafer W01.
  • the substrate wafer W01 selected in the embodiment is available in a size of 2-6 inches.
  • This disclosure does not specify the specific size of the substrate wafer W01, but it should be understood that without violating the central idea of the disclosure, the size of the substrate wafer W01 can be freely enlarged or reduced according to specific application scenarios and actual conditions of production equipment.
  • the interlayer wafer W02 may be a multi-layer wafer structure with an optical waveguide layer L02 having a given thickness on top.
  • the intermediate layer wafer W02 may be a single-layer wafer structure independently composed of the optical waveguide layer L02 material.
  • joining refers to wafers/wafer slices, wafers/wafers, wafer slices/wafer slices through layers The process of achieving layer structure integration through structural media or dangling bond/covalent bond structures.
  • a direct bonding method can be used to realize the bonding between the intermediate layer wafer W02 and the substrate wafer W01 by utilizing the top molecular hydrophobic/hydrophilic layer structure of the two.
  • the plasma activation bonding method includes surface activation using oxygen or inert gas (such as nitrogen, argon and other common semiconductor process gases) plasma, surface cleaning using deionized water, subsequent preliminary bonding, and finally Heat treatment to bond the two wafers.
  • Plasma-activated bonding relies on oxygen bonding and van der Waals forces in the hydroxyl groups to achieve preliminary bonding prior to thermal treatment.
  • heat treatment water molecules are removed in a condensation reaction, forming covalent bonds between the front sides of the wafer to achieve a stable bond.
  • the interlayer wafer W02 needs to be pre-processed as follows:
  • the wafer needs to be cleaned for 1-10 minutes using common semiconductor cleaning processes, including but not limited to plasma cleaning, infiltration or ultrasonic infiltration of deionized water, RCA, SC1 ⁇ SC2 or organic solvents to clean the wafer. ;
  • the top surface of the intermediate layer wafer W02 needs to be subjected to plasma activation treatment.
  • the intermediate layer wafer W02 needs to be preprocessed as follows:
  • the intermediate layer wafer W02 since the intermediate layer wafer W02 has a single-layer structure, its thickness generally needs to be greater than several hundred microns to ensure mechanical strength, and the larger the wafer size, the higher the thickness required.
  • the single-layer wafer structure in this embodiment is a single-crystal silicon wafer.
  • thin film transfer of large-sized single crystal silicon is difficult to achieve through multi-layer structures.
  • this is because the price of silicon single crystal itself is low, and on the other hand, it is Forming silicon films inevitably requires long wet/dry etching, which also introduces the risk of wafer cracking.
  • the thickness of the defect-enriched layer X01 needs to be 30-80% greater than the specified optical waveguide layer L02 to ensure the lattice quality of the optical waveguide layer L02.
  • the top surface of the intermediate layer wafer W02 processed by the ion scissors is subjected to plasma activation treatment.
  • the hydrophilicity and hydrophobicity of the interface B01 after plasma activation must be consistent with the substrate wafer W01.
  • the substrate wafer W01 is pre-processed as follows:
  • the wafer needs to be cleaned for 1-10 minutes using common semiconductor cleaning processes, including but not limited to plasma cleaning, infiltration or ultrasonic infiltration of deionized water, RCA, SC1 ⁇ SC2 or organic solvents to clean the wafer. ;
  • the top surface of the wafer needs to be subjected to plasma activation treatment.
  • the hydrophilicity and hydrophobicity of the interface B01 after plasma activation must be consistent with that of the middle layer wafer W02.
  • the intermediate layer wafer W02 and the substrate wafer W01 that have undergone the top surface treatment are subjected to an alignment bonding operation in a specific atmosphere.
  • the atmosphere includes vacuum, nitrogen, argon and other inert gas atmospheres. After bonding is completed, it is annealed in the same atmosphere to strengthen the covalent bonding force between the two wafers.
  • the thinning is achieved by performing high-temperature annealing on a combination of the ion scissor-treated interlayer wafer W02 and the substrate wafer W01 in S03.
  • the unrepaired optical waveguide wafer W41 is obtained after the thinning process.
  • S05 Improve the lattice quality and surface flatness of the optical waveguide layer L02 semiconductor film through chemical and mechanical polishing (CMP) and annealing.
  • CMP chemical and mechanical polishing
  • the surface of the optical waveguide wafer W41 is ground in the order of a hard grinding disc and a soft grinding disc.
  • the defect-enriched layer X01 is removed, and the optical waveguide layer L02 is allowed to reach a specified thickness.
  • the final structure of the optical waveguide wafer W41 after thinning and annealing treatment is as shown in Figure 4(b).
  • the optical waveguide layer L02 can be pattern-defined to form the necessary optical structure.
  • the optical structure can be used as part or one or more of a transmitter, a modulator, a receiver, and a waveguide.
  • the etched portion may include a fully etched portion P01 and a partially etched portion P02, as shown in Figure 4(c).
  • the pattern-defined optical waveguide wafer W41 can be directly used for re-bonding.
  • the dielectric layer I01 carrying the photoelectric conversion layer L01. can also be filled by deposition, sputtering or evaporation as the dielectric layer I01 carrying the photoelectric conversion layer L01.
  • other materials such as silicon oxide
  • the bonding strength is higher and high-density optoelectronic devices can be integrated.
  • the dielectric layer I01 will inevitably form step-like undulations during the formation process, which is very unfavorable for the subsequent re-bonding process.
  • the dielectric layer I01 can be planarized by introducing a second CMP, as shown in Figure 4(d). It should be noted that in this process, each parameter of the CMP needs to be carefully controlled to ensure that the defined pattern on the original optical waveguide layer L02 will not be destroyed during the planarization process.
  • this embodiment provides two alternative layer structure schemes for the top wafer/slice W03: the first alternative scheme W03-a for the top wafer/slice and the second alternative scheme W03-a for the top wafer/slice. options W03-b.
  • the top wafer/slice first alternative W03-a includes: N-type contact layer L015, quantum structure layer L014, P-type contact layer L013, sacrificial layer L012 and sacrificial layer substrate L011.
  • the N-type contact layer L015, the quantum structure layer L014 and the P-type contact layer L013 constitute the photoelectric conversion layer L01.
  • the top wafer/slice second alternative W03-b includes: a mode matching layer L016, a quantum structure layer L014, a sacrificial layer L012, and a sacrificial layer substrate L011.
  • the mode matching layer L016 and the quantum structure layer L014 constitute the photoelectric conversion layer L01.
  • the P-type contact layer L013 and the N-type contact layer L015 can be embedded in the mode matching layer L016 through diffusion/ion implantation in the back-end process.
  • the sacrificial layer substrate L011 can be selected as InP
  • the sacrificial layer L012 can be selected as InGaAsP
  • the quantum structure layer L014 can be selected as a multi-quantum well (MQW) structure based on InGaAsP.
  • MQW multi-quantum well
  • the optical waveguide wafer W41 needs to be pre-processed as follows:
  • the wafer needs to be cleaned for 1-10 minutes using common semiconductor cleaning processes, including but not limited to plasma cleaning, infiltration or ultrasonic infiltration of deionized water, RCA, SC1 ⁇ SC2 or organic solvents to clean the wafer. ;
  • the top surface of the wafer needs to be subjected to plasma activation treatment. After plasma activation, it must be ensured that the hydrophilicity and hydrophobicity of the top layer interface must be consistent with the top layer wafer/slice W03.
  • the top wafer/slice W03 needs to be pre-processed as follows:
  • the wafer needs to be cleaned for 1-10 minutes using common semiconductor cleaning processes, including but not limited to plasma cleaning, infiltration or ultrasonic infiltration of deionized water, RCA, SC1 ⁇ SC2 or organic solvents to clean the wafer. ;
  • the top surface of the wafer needs to be subjected to plasma activation treatment. After plasma activation, it is necessary to ensure that the hydrophilicity and hydrophobicity of the top layer interface must be consistent with the optical waveguide wafer W41.
  • the top surface-treated optical waveguide wafer W41 and the top wafer/slice W03 are subjected to an alignment bonding operation in a specific atmosphere.
  • the atmosphere includes vacuum, nitrogen, argon and other inert gas atmospheres.
  • annealing is performed in the same atmosphere to strengthen the covalent bonding force between the two wafers.
  • the bonded wafer layer structure is shown in Figure 7(a).
  • the maximum wafer size of Group III-V compound semiconductors that can be achieved as of the date of this disclosure is 2-6 inches. Therefore, when performing step S08, the bonding plan should be flexibly adjusted in a timely manner according to the wafer size.
  • FIG. 6(a1) and FIG. 6(a2) respectively represent the front-view structure and layer structure of the first alternative W00-a of the final three-layer stacked structure wafer obtained after step S08.
  • the dielectric layer I01 is omitted to highlight the stacking of the top wafer/slice W03 on the optical waveguide wafer W41.
  • the optical waveguide layer L02 has integrated an optical device structure.
  • the top wafer/slice W03 can be bonded to a designated position on the optical waveguide wafer W41 through micro-nano structure transfer.
  • the advantage is that the optical device functional areas in the final three-layer stacked structure wafer W00 can be flexibly arranged, and the quantum structure inside the quantum structure layer L012 in the top wafer/slice W03 can be flexibly adjusted.
  • the disadvantage of this solution is that it requires extremely high alignment accuracy and high consistency of bonding strength during the bonding process.
  • Figure 6 (b1) and Figure 6 (b2) respectively represent the front top view structure and layer structure of the second alternative W00-b of the final three-layer stacked structure wafer obtained after step S08.
  • This solution uses wafer/wafer combination. It should be noted that in this scheme, the dielectric layer I01 is omitted to highlight the stacking of the top wafer/slice W03 on the optical waveguide wafer W41. It should be noted that in this schematic diagram, the optical waveguide layer L02 has integrated an optical device structure. It should be noted that although this solution compromises the wafer size, it should be understood that the specific size of the top wafer in the three-layer stacked structure wafer W00 used in the present disclosure is not limited to the aforementioned size limitations.
  • the sacrificial layer substrate L011 and the sacrificial layer L012 can be removed by wet etching, and the resulting three-layer stacked structure wafer W00 is shown in Figure 7(b).
  • the etching method may include full etching or partial etching. These two methods are represented by the photoelectric conversion layer etching part P03. Then a protective layer I02 is formed on the etched photoelectric conversion layer L01;
  • the photoelectric conversion layer L01 can be pattern transferred by dry etching, and the schematic diagram is shown in Figure 7(c).
  • the pattern-defined P-type contact layer L013 and quantum structure layer L012 can be removed by dry etching, leaving the N-type contact layer L011 for subsequent electrode definition. .
  • the pattern-defined pattern matching layer L016 and quantum structure layer L012 can be removed by dry etching, and a P/N doped region can be additionally defined to achieve Lateral PN/PIN junction semiconductor structure.
  • the protective layer I02 (such as silicon oxide) is filled on the pattern-defined three-layer stacked structure wafer W00 by deposition, sputtering or evaporation, and the filled layer structure is as shown in Figure 7(d) Show.
  • a cavity structure that allows the metal electrode to have good contact with the designated functional area is formed.
  • the formation of the metal electrode can be achieved by deposition, sputtering, evaporation or electroplating, and its pattern definition can be formed by stripping or etching.
  • this example demonstrates a method based on optical waveguide layer L02 and signal Modulator structure constructed by modulation layer L03.
  • the optical signal passes through the first waveguide WG1-1 composed of the optical waveguide layer L02 and the signal modulation layer L03 (optionally, the width of the waveguide is 0.55 microns in this example) and passes through the first super-mode transition waveguide of the modulation layer.
  • SWG1-1 is input to the modulation layer supermode waveguide SWG2 (optionally, the width of this supermode waveguide is 0.35 microns in this example).
  • the optical signal can be modulated in phase by the electric field applied on the signal modulation layer L03 through the linear electro-optical effect of lithium niobate selected for the signal modulation layer L03 in this example.
  • the modulated optical signal is output to the second waveguide WG1-2 through the second supermode transition waveguide SWG1-2 of the modulation layer.
  • the cross-sectional electric field distribution in the first waveguide WG1-1 and the second waveguide WG1-2 is demonstrated by the optical waveguide mode M01, and the displayed mode type is TE00.
  • the first waveguide WG1-1 and the second waveguide WG1-2 can also form in other areas such as S-shaped, L-shaped or U-shaped curved waveguides, N ⁇ N port directional couplers, Y-shaped branches, M ⁇ N Passive optical structures such as port MMI and M ⁇ N star couplers.
  • the first waveguide WG1-1 and the second waveguide WG1-2 are strip waveguide (channel waveguide) structures. Generally, it can also form a rib waveguide, a slot waveguide, and an optical waveguide based on a Bragg grating structure, a superlattice structure or a photonic crystal.
  • the optical waveguide layer L02 part of the modulation layer supermode waveguide SWG2 in this example has a strip waveguide structure.
  • ridge waveguides, groove waveguides, and optical waveguides based on Bragg grating structures, superlattice structures, or photonic crystals can also be constructed.
  • the cross-sectional electric field distribution in the modulation layer supermode waveguide SWG2 is demonstrated by the signal modulation layer mode M02, and the displayed mode type is TM00. Since the intensity of the applied electric field is highest at the interface between the optical waveguide layer L02 and the signal modulation layer L03, the cross-sectional electric field distribution center in the modulation layer supermode waveguide SWG2 should be fine-tuned to the interface as much as possible. In this example, by reducing the width of the waveguide structure of the optical waveguide layer L02 in the modulation layer supermode waveguide SWG2, the generation of the TE mode can be limited.
  • this example demonstrates a transmitter/amplifier/receiver structure based on the signal modulation layer L03, the optical waveguide layer L02 and the photoelectric conversion layer L01.
  • the implementation of this example can be achieved by carefully designing the thickness of the photoelectric conversion layer L01 and the width of the optical waveguide formed by the optical waveguide layer L02. Its electric field distribution can be demonstrated by the three-layer stacked structure waveguide mode M03. It should be noted that other waveguide structures such as slot waveguides and photonic crystal waveguides can also achieve similar effects. Under the premise of not violating the central idea of the present disclosure, it will be considered that such changes can still be attributed to the effect demonstrated by this example.
  • the optical signal passes through the first waveguide WG1-1 composed of the optical waveguide layer L02 and the signal modulation layer L03 (optionally, the width of the waveguide is 0.55 microns in this example), passes through the signal modulation layer L03, the optical waveguide
  • the first supermode transition waveguide SWG3-1 of the photoelectric conversion layer composed of layer L02 and the photoelectric conversion layer L01 is input to the photoelectric conversion layer supermode waveguide SWG4 (optionally, in this example, the optical waveguide layer L02 part of the supermode waveguide
  • the width is 0.35 microns
  • the optical signal mode transitions the waveguide mode center intensity through the first supermode transition waveguide SWG3-1 of the photoelectric conversion layer to the quantum of the photoelectric conversion layer L01 in the photoelectric conversion layer supermode waveguide SWG4.
  • Structural layer L012 to maximize amplification efficiency.
  • the amplified optical signal is output to the second waveguide WG1-2 through the second supermode transition waveguide SWG3-2 of the photoelectric conversion layer.
  • a resonant cavity structure needs to be formed on or outside the first waveguide WG1-1 and the second waveguide WG1-2, and the implementation method is also defined in the term "transmitter”.
  • the optical signal mode transitions the waveguide mode center intensity through the first super-mode transition waveguide SWG3-1 of the photoelectric conversion layer to the quantum structure layer L012 of the photoelectric conversion layer L01 in the photoelectric conversion layer super-mode waveguide SWG4.
  • the optical signal generated by the resonant cavity selection is output to the second waveguide WG1-2 through the second super-mode transition waveguide SWG3-2 of the photoelectric conversion layer.
  • the optical signal mode transitions the waveguide mode center intensity through the first supermode transition waveguide SWG3-1 of the photoelectric conversion layer to the photoelectric conversion layer L01 in the photoelectric conversion layer supermode waveguide SWG4.
  • Quantum structure layer L012 to improve light energy-electric energy efficiency as much as possible. Since the receiver is a type of terminal device, no photoelectric conversion is required in this example.
  • the structures described in this example are all single-segment linear gradient structures.
  • the gradient structure can include the following changes: a combination with a multi-segment linear gradient structure, a combination with a single or multi-segment non-linear gradient structure, a combination with a multi-segment linear/non-linear gradient structure, a combination with a single or multi-segment grating structure and a set containing the above combinations having a reflex-inhibiting effect.

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Abstract

本发明公开了一种三层堆叠结构晶圆的制备方法及其应用。该三层堆叠结构晶圆可在晶圆层面集成信号调制层、光学导波层及光电转换层的三层堆叠结构。本发明通过在同一晶圆上集成三种异质材料的方法，可以有效规避传统方法在利用光学导波层进行信号调制时易产生的高插损和高加工难度的固有缺陷。通过将信号调制和光电转换分别转移至对应层进行处理，可充分利用各层材料特性以实现低调制插损且高光学增益的有源/无源集成光电器件芯片。

Description

一种三层堆叠结构晶圆的制备方法及应用 技术领域
本发明属于半导体工艺与材料领域，特别涉及一种基于异质集成的三层堆叠结构晶圆的制备方法及应用，基于该晶圆可制备包含多种功能的无源/有源光电器件的半导体晶圆平台，该平台可用于宽波长范围内的自由空间/链路空间通信，自由空间/链路传感与生物医疗感知等应用。
背景技术
摩尔定律自1965年被提出以来经历了几十年的发展，其受限于光学衍射极限以及现有半导体加工工艺与备选材料的趋势愈发明显。硅基光子集成电路(photonic integrated circuits，PIC)自二十一世纪初期以来迅猛发展，其中心思想在于将传统光学分立器件通过片上集成的方式构建为如同微电子芯片(microelectronic chips)一般的微系统以实现不同光功能的单片集合功效。特别地，利用互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺链及其变种工艺链实现PIC芯片的制备技术在近年来成为了主流。得益于精细线宽制程的帮助，PIC被主要应用在通信、传感以及近年开始兴起的模拟运算领域。
特别地，这些PIC必须操作在预定信道波长规划上，因为不同的波长光信号通常是从多个远程且分立的发射机提供的。传统PIC制程最早基于平面光波电路，该类平台主要利用离子注入或者扩散的方式选择掺杂玻璃晶圆(如石英、氧化物、非线性晶体等)来构成折射率的突变区域以形成光场局域模式。该类平台的优势在于极低的光波传输损耗，然而其导波区域折射率变化(芯层/衬底折射率对比度)一般不超过5％，这使得芯片尺寸一般在cm级别。
备选地，可以采用砷化镓(GaAs)、砷化铝镓(AlGaAs)和磷化铟镓砷(InGaAsP)来用于850nm、1300nm和1550nm PIC。其半导体带隙可通过引入配方控制或者外部掺杂的手段进行微调。进一步地，可以通过开发采用铟(In)、 镓(Ga)、铝(Al)、砷(As)和磷(P)的其他第三和三元半导体材料来跨可见和近紫外区采用PIC。功能不同的器件通常由不同的、但兼容的半导体材料制成，尽管通过有针对性的设计一些结构可以提供具有反向偏置极性的光放大和光电检测，衬底和波导设计的选择依然对PIC的设计和制造两者有着深远的影响。
离子剪刀(ion-cut)技术泛指利用高能量、大注入量的离子(如H+、H2 +，He等)束，通过电磁线圈加速的方式轰击至材料内部以构成缺陷富集层。在适当的退火条件下，缺陷富集层中的离子会自发聚集成为气体分子并贮存在由离子轰击造成的晶格缺陷当中，当聚集的气体分子达到一定数量时其内部产生的应力会使得材料中的晶格缺陷进一步扩大从而形成鳞片状的剥离(splitting)现象。通过将离子轰击后的半导体材料转移至给定衬底结构(一般地，多采用晶圆键合(wafer bonding)技术)，可以实现大范围的半导体材料薄膜制备。该方法的优点在于其薄膜厚度可控，但其退火过程容易引入额外的热应力从而造成晶圆破裂。
直接晶圆键合是指在没有任何中间黏着剂或外力的情况下将两个分离的晶圆表面接触并键合的过程。目前直接晶圆键合在微电子产业里拥有多种应用。半导体过程应用的实例包括衬底工程(substrate engineering)、集成电路制造(fabrication of integrated circuits)、微机电系统(micro-electromechanical-systems，MEMS)的包装和封装以及纯微电子组件的许多加工过的层的堆叠(3D integration)。其优点在于直接利用了半导体材料(典型的如Si-Si键合)界面上的悬挂键，因而便于形成垂直方向上的半导体结(junciton)结构。然而，直接键合的缺点在于其对与晶圆表面态的严苛要求。一般地，要求表面晶圆粗糙度(roughness mean square，RMS)小于0.5nm。
粘合剂键合指在待键合的晶圆表面通过旋涂、沉积、溅射、蒸镀或生长等方式形成介质层，晶圆之间的结合则通过介质层中材料的分子力进行键合。该类键合方式可使得键合晶圆组合之间的界面具有良好的电绝缘性，然而其缺点在于介质层界面缺陷易导致器件失效。
进一步地，一种经过改善的PIC制备工艺则基于化合物半导体晶圆(III-V 族以及II-VI族二元、三元及四元合金及其量子结构)与绝缘层上半导体之间的光电互联。其制备方法可基于直接或者粘合剂键合，同时可引入量子结构实现光学增益与光信号探测的功能。然而，在实现信号调制模块时需要引入不同禁带带隙的晶圆，因而需要考虑多种结构的化合物半导体晶圆与绝缘层上半导体之间的键合工艺。一种方式可通过对量子结构进行微扰(如quantum well intermixing)实现对禁带带隙的微调，然而对量子结构的破坏亦会使得器件可靠性降低。也可通过将化合物半导体晶圆预先进行分割并逐个键合至绝缘层上半导体，然而为了保证各部分功能区域之间互不干扰，在实际生产中必须牺牲大量晶圆面积来保证键合区域的独立性，这同时又容易引入过低的良率。
进一步地，绝缘层上光学晶体(如绝缘层上铌酸锂，LNOI等)亦可用于PIC制备工艺。以LNOI为例，其制备方法与SOI相似，相比较于SOI的非线性信号调制机制而言，LNOI的光学信号调制依赖于铌酸锂晶体的电光效应，因此可大幅简化其驱动电路的设计。然而，铌酸锂的刻蚀会引入额外金属离子，因此无法在现有CMOS基础上进行改进。同时，由于铌酸锂的干法刻蚀难以实现光滑平整的波导界面，因此其大密度高精度的PIC集成依旧难以实现。
综上，为了解决现有各类PIC集成工艺中的短板效应，亟需寻找一种足够优秀的折衷方案用以实现高密度、低能耗、较低加工难度的PIC材料平台。
发明内容
鉴于上述现有技术的缺点，本公开的目的在于提供一种三层堆叠结构晶圆的制备方法及应用，基于该晶圆可制备包含多种功能的无源/有源光电器件的半导体晶圆平台。
本发明的目的是通过以下技术方案实现的：一种三层堆叠结构晶圆的制备方法，所述三层堆叠结构晶圆由衬底晶圆、中间层晶圆和顶层晶圆/切片经过两次堆叠而成；
所述衬底晶圆具有信号调制层，所述中间层晶圆具有光学导波层，所述顶层晶圆/切片具有光电转换层；
第一次堆叠，将衬底晶圆与中间层晶圆结合并减薄得到光学波导晶圆；
第二次堆叠，将光学波导晶圆与顶层晶圆/切片结合并减薄得到最终的三层堆叠结构晶圆。
进一步地，所述信号调制层、光学导波层、光电转换层两两之间互为异质材料，具体地：
所述信号调制层包含有可作为调制器使用的材料体系中的一种或多种；
所述光学导波层包含以下的一种或多种：III-V族半导体材料、II-VI族半导体材料、IV族半导体材料、氮化物或氧化物材料、铅盐类材料、石英、非线性晶体以及光学玻璃；
所述光电转换层包含以下的一种或多种：III-V族半导体材料及其一元或多元合金、II-VI族半导体材料及其一元或多元合金，IV族半导体材料及其一元或多元合金、以及基于上述材料体系实现的量子结构。
进一步地，所述信号调制层在衬底晶圆的顶层；所述光学导波层在中间层晶圆的顶层；
第一次堆叠过程中，对衬底晶圆和中间层晶圆的顶层进行表面悬挂键预处理，之后进行结合，将与衬底晶圆结合后的中间层晶圆进行减薄，保留光学导波层并进行后处理，得到光学波导晶圆。
进一步地，所述光电转换层在顶层晶圆/切片的顶层；所述光电转换层具有对光电信号间的转换和/或光信号的增益功能；
第二次堆叠过程中，首先对光学波导晶圆的顶层进行图案定义与刻蚀，形成平坦的介质层，再对介质层表面进行悬挂键预处理，之后与顶层晶圆/切片进行结合，将与光学波导晶圆结合后的顶层晶圆/切片进行减薄，保留光电转换层，得到最终的三层堆叠结构晶圆。
进一步地，在三层堆叠结构晶圆的顶层进行图案定义与刻蚀，在刻蚀后的三层堆叠结构晶圆的顶层形成保护层，并进行金属电极形成与封装。
进一步地，所述光电转换层由N型接触层、量子结构层、P型接触层依次堆叠形成，此时PN结或PIN结的电场指向垂直于顶层表面，通过调整量子结构层的厚度及组分，能够使光电转换层同时具有对光信号的产生、放大及接收功 能；或者，所述光电转换层由模式匹配层和量子结构层堆叠而成，其中模式匹配层中需要形成P型接触和N型接触，此时PN结或PIN结的电场指向平行于顶层表面，通过共同调整模式匹配层和量子结构层的厚度及组分，能够使光电转换层同时具有对光信号的产生、放大及接收功能。
进一步地，所述光电转换层的材料为III-V族化合物半导体及其量子结构，厚度为0.1-1.5微米；
所述光学导波层的材料为硅，厚度为0.2-0.5微米；
所述信号调制层的材料为铌酸锂，厚度为0.1-10微米；
所述三层堆叠结构晶圆的承载层为单晶硅层，或者单晶硅层与氧化硅层的结合，厚度为325-825微米。
本发明制备的三层堆叠结构晶圆，可基于信号调制层、光学导波层及光电转换层之间的组合实现调制器/发射器/放大器/接收器功能。
对于本公开演示的调制器而言，实现载体为信号调制层，在电场分布的TM模式下，通过电光效应实现相位调制。其良好的调制线性度可以大幅简化外围驱动电路的设计与功耗，同时适用于大规模阵列集成。
对于本公开演示的发射器/放大器/接收器而言，实现载体为光电转换层，通过对三层堆叠结构的超模式波导中电场分布的调控，实现发射器/放大器/接收器功能。可通过优化光电转换层中的材料层结构及其包含的量子结构，使其适用于大规模光电信号处理。
本发明的有益效果是：本发明通过在同一晶圆上集成三种异质材料的方法，可以有效规避传统方法在利用光学导波层进行信号调制时易产生的高插损和高加工难度的固有缺陷。通过将信号调制和光电转换分别转移至对应层进行处理，可充分利用各层材料特性以实现高性能、高集成度的集成光电器件芯片。
附图说明
图1是本公开提供的实施例中三层堆叠结构晶圆的制备方法流程图；
图2(a)是本公开提供的实施例中三层堆叠结构晶圆第一备选方案W00-a结构图；图2(b)是本公开提供的实施例中三层堆叠结构晶圆第二备选方案 W00-b结构图；
图3(a)是本公开提供的实施例中中间层晶圆W02的层结构图；图3(b)是本公开提供的实施例中衬底晶圆W01的层结构图；图3(c)是本公开提供的实施例中中间层晶圆W02经过等离子表面活化处理后的层结构图；图3(d)是本公开提供的实施例中衬底晶圆W01经过等离子表面活化处理后的层结构图；
图4(a)是本公开提供的实施例中光学波导晶圆W41经过步骤S04处理后的层结构图；图4(b)是本公开提供的实施例中光学波导晶圆W41经过步骤S05处理后的层结构图；图4(c)是本公开提供的实施例中光学波导晶圆W41经过步骤S06处理后的层结构图；图4(d)是本公开提供的实施例中光学波导晶圆W41经过步骤S06处理并填充介质层的层结构图；
图5是本公开提供的实施例中顶层晶圆/切片第一备选方案W03-a和顶层晶圆/切片第二备选方案W03-b的层结构图；
图6(a1)和图6(a2)分别是本公开提供的实施例中三层堆叠结构晶圆第一备选方案W00-a的晶圆正面俯视图和层结构图；图6(b1)和图6(b2)分别是本公开提供的实施例中三层堆叠结构晶圆第二备选方案W00-b的晶圆正面俯视图和层结构图；
图7(a)是本公开提供的实施例中光学波导晶圆W41经过步骤S08处理与顶层晶圆/切片W03结合后的层结构图；图7(b)是本公开提供的实施例中光学波导晶圆W41经过步骤S09处理与顶层晶圆/切片W03结合后的层结构图；图7(c)是本公开提供的实施例中光学波导晶圆W41经过步骤S10处理与顶层晶圆/切片W03结合后的层结构图；图7(d)是本公开提供的实施例中光学波导晶圆W41经过步骤S10处理与顶层晶圆/切片W03结合并引入保护层I02的层结构图；
图8(a)是本公开提供的实施例中基于光学导波层L02和信号调制层L03构造的调制器结构示意图；图8(b)是本公开提供的实施例中基于信号调制层L03、光学导波层L02和光电转换层L01构造的发射器/放大器/接收器结构示意图；
标记符号说明：光电转换层L01；光学导波层L02；信号调制层L03；衬底绝缘层L04；衬底结构层L05；N型接触层L011；量子结构层L012；P型接触层L013；牺牲层L014；牺牲层衬底L015；模式匹配层L016；承载层L41；三层堆叠结构晶圆W00；三层堆叠结构晶圆第一备选方案W00-a；三层堆叠结构晶圆第二备选方案W00-b；衬底晶圆W01；中间层晶圆W02；顶层晶圆/切片W03；顶层晶圆/切片第一备选方案W03-a；顶层晶圆/切片第二备选方案W03-b；光学波导晶圆W41；界面B01；介质层I01；保护层I02；缺陷富集层X01；光学波导模式M01；信号调制层模式M02；三层堆叠结构波导模式M03；第一波导WG1-1；第二波导WG1-2；调制层第一超模式过渡波导SWG1-1；调制层第二超模式过渡波导SWG1-2；调制层超模式波导SWG2；光电转换层第一超模式过渡波导SWG3-1；光电转换层第二超模式过渡波导SWG3-2；光电转换层超模式波导SWG4；完全刻蚀部分P01、部分刻蚀部分P02、光电转换层刻蚀部分P03。
具体实施方式
虽然讨论了具体配置和布置，但是应当理解，这仅仅是为示例目的。本领域技术人员将认识到，能够使用其它配置和布置，而不脱离本公开的精神和范围。对本领域技术人员将明显的是，也能够将本公开采用于各种其它应用中。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
下面介绍本公开的实施例，在该实施例中，将介绍一种基于异质材料集成的三层堆叠结构晶圆的制备方法，材料体系包括三种不同目的的层结构，即信号调制层L03、光学导波层L02及光电转换层L01。
在实施例中，信号调制层L03包含有可作为调制器使用的材料体系中的一种或多种。
在实施例中，光学导波层L02包含以下的一种或多种：III-V族半导体材料、II-VI族半导体材料、IV族半导体材料、氮化物或氧化物材料、铅盐类材料、石英、非线性晶体以及光学玻璃等。
在实施例中，光电转换层L01包含以下的一种或多种：III-V族半导体材料 及其一元或多元合金、II-VI族半导体材料及其一元或多元合金，IV族半导体材料及其一元或多元合金、以及基于上述材料体系实现的量子结构。
优选地，在实施例中信号调制层L03材料体系选为铌酸锂晶体。
优选地，在实施例中光学导波层L02材料体系选为硅。
优选地，在实施例中光电转换层L01材料体系选为III-V族化合物半导体及其量子结构。
请参阅图1，图1为本申请实施例提供的一种三层堆叠结构晶圆的制备方法流程图，该方法包括如下步骤：
S00：开始。一般地，在该阶段同时应确定在实施例中的层组合及其附属层结构所形成的最终三层堆叠结构晶圆W00。如图2(a)和图2(b)所示，本公开提供了两种三层堆叠结构晶圆的备选方案，即三层堆叠结构晶圆第一备选方案W00-a和三层堆叠结构晶圆第二备选方案W00-b。
具体地，方案W00-a包含：光电转换层L01、光学导波层L02、信号调制层L03、衬底绝缘层L04及衬底结构层L05。
具体地，方案W00-b包含：光电转换层L01、光学导波层L02及信号调制层L03。
具体地，由于层结构构造需考虑晶圆在生产工艺线中的热预算(thermal budget)。在进行层材料选择与匹配过程当中，需仔细考虑各层之间的热膨胀系数(coefficient of thermal expansion，CTE)以及其导热系数(coefficient of thermal conductivity，CTC)。
具体地，在实施例所提供的所有备选方案中，各个层材料的热膨胀系数及导热系数如表1所示：
表1

具体地，由于铌酸锂作为信号调制层L03的功能材料，其CTE与光学导波层L02的功能材料硅之间的CTE对比度可达到288％-554％，这将导致在层结构堆叠过程当中热预算的快速失效，最终使得晶圆报废。
具体地，在晶圆处理过程当中，随着层结构的增加，其各层之间的热膨胀系数的差异将使得晶圆不可避免地引入额外的热应力。过高的热应力不仅会造成器件可靠性降低，也会大幅增加在生产过程当中晶圆因热应力累加而产生崩裂的可能性，这对于保障最终晶圆结构的良率而言十分关键。为防止在晶圆加工流程中热预算的快速消耗，需对各层结构的厚度进行仔细调整与优化。在实施例中，可采取将信号调制层L03材料转移至与光学导波层L02热膨胀系数近似的材料体系的方式来补偿CTE差异带来的热应力。需要注意的是，本实施例中所示各层参数可根据具体应用场景及需求灵活变化，应明确在充分理解该本实施例的基础上工程人员可对各参数进行具体优化调整，此类变化亦包含在该公开保护范围之内。
进一步地，在实施例中经优选后的层厚度方案如表2所示：
表2

进一步地，所述信号调制层L03、衬底绝缘层L04及衬底结构层L05组成衬底晶圆W01，如图3(b)所示。进一步地，衬底绝缘层L04及衬底结构层L05共同构成承载层L41，在某些特殊情况下，衬底绝缘层L04及衬底结构层L05可以为同一种材料。特别地，对于由铌酸锂构成的衬底晶圆W01，其具体实现方法已在其他公开中详细阐述，因而在本公开中对于衬底晶圆W01的制备方法不再赘述。
S01：提供衬底晶圆W01，其中信号调制层L03已经集成在衬底晶圆W01上。
补充地，截至本公开申请之日，实施例所选用的衬底晶圆W01其可提供尺寸为2-6英寸。本公开并未指定衬底晶圆W01的具体尺寸，但应明白在不违背本公开中心思想的基础上，衬底晶圆W01的尺寸可依据具体应用场景与生产设备实际情况自由放大或缩小。
S02：提供中间层晶圆W02。
特别地，中间层晶圆W02可以是顶层为具有给定厚度的光学导波层L02的多层晶圆结构。
特别地，中间层晶圆W02可以是由光学导波层L02材料独立构成的单层晶圆结构。
S03：在对中间层晶圆W02与衬底晶圆W01的顶层表面进行预处理之后，将中间层晶圆W02与衬底晶圆W01结合。
进一步地，遍及本全文上下的术语结构的“结合”、“键合”、“粘合”指代晶圆/晶圆切片、晶圆/晶圆、晶圆切片/晶圆切片之间通过层结构介质或悬挂键/共价键结构实现层结构一体化的过程。
优选地，对实施例而言，可采用直接键合的方式，利用中间层晶圆W02与衬底晶圆W01的顶层分子疏水/亲水层结构实现二者之间的结合。
进一步地，直接键合具有差异较大的热膨胀系数的加工过的晶圆或一般晶圆需要低温键合过程以克服晶圆翘曲，同时对于典型硅晶圆键合而言其温度冗余并不能够满足其与异种材料键合的晶圆膨胀/翘曲匹配，热膨胀系数失配将导致晶圆去键合(debonding)。为尽量提高热预算，一种成熟工艺采用将晶圆放置于离子腔室内进行表面态活性化的方法来提高键合强度。该方法优势在于通过等离子轰击形成表面分子悬挂键，从而在后续低温(一般地，该温度小于或等于200℃)或者室温条件下的贴合状态中实现等同于高温处理后的晶圆键合强度。
具体地，等离子体活化键合方法包含使用氧气或惰性气体(如氮气、氩气等常见半导体工艺气体)等离子体的表面活化、使用去离子水的表面清洁、随后的初步键合、以及最后的热处理以键合两个晶圆。等离子体活化键合依赖于羟基中的氧键合和范德华力，以在热处理之前实现初步键合。在热处理期间，在缩合反应(condensation reaction)中去除水分子，在晶圆的正面之间形成共价键，以实现稳定的键合。
备选地，当中间层晶圆W02存在多层结构时，需对中间层晶圆W02进行如下预处理：
1.需用常用半导体清洗工艺对晶圆进行1-10分钟的清洗，包括但不限于等离子清洗、采用浸润或超声波下浸润的去离子水、RCA、SC1\SC2或有机溶剂对晶圆进行清洗；
2.需对中间层晶圆W02的顶层表面进行等离子活化处理。
优选地，当中间层晶圆W02为单层结构时，需对中间层晶圆W02进行如下预处理：
1.如图3(a)所示，由于中间层晶圆W02为单层结构，为保证机械强度其厚度一般需大于数百微米，且晶圆尺寸越大所需要的厚度越高。优选地，在本实施例中的单层晶圆结构为单晶硅晶圆。一般地，大尺寸单晶硅的薄膜转移很难通过多层结构实现。这一方面是因为硅单晶本身的价格低廉，另一方面是为 形成硅薄膜不可避免地需要长时间的湿法/干法刻蚀，这同样会引入晶圆崩裂的风险。优选地，我们采用离子剪刀技术来引入光学导波层L02，该技术的具体实验已由其他公开详细阐述，在本公开中不做赘述。因此，在本步骤中，需确定离子剪刀引入缺陷富集层X01的位置。一般地，缺陷富集层X01的厚度需比指定的光学导波层L02多30-80％，以保证光学导波层L02的晶格质量。
2.如图3(c)所示，对经过离子剪刀处理的中间层晶圆W02的顶层表面进行等离子活化处理，等离子活化后的界面B01的亲疏水性需与衬底晶圆W01保持一致。
优选地，对衬底晶圆W01进行如下预处理：
1.需用常用半导体清洗工艺对晶圆进行1-10分钟的清洗，包括但不限于等离子清洗、采用浸润或超声波下浸润的去离子水、RCA、SC1\SC2或有机溶剂对晶圆进行清洗；
2.如图3(d)所示，需对晶圆的顶层表面进行等离子活化处理，等离子活化后的界面B01的亲疏水性需与中间层晶圆W02保持一致。
进一步地，将经过顶层表面处理的中间层晶圆W02和衬底晶圆W01在特定氛围中进行对准键合操作。特别地，该氛围包括真空、氮气、氩气以及其他惰性气体氛围。在键合完成后，在相同氛围内经退火处理以加固两晶圆之间的共价键结合力。
S04：将与衬底晶圆W01结合后的中间层晶圆W02进行减薄处理，得到未经修复的光学波导晶圆W41。
优选地，减薄由对S03中经离子剪刀处理过的中间层晶圆W02与衬底晶圆W01的结合体进行高温退火实现。如图4(a)所示，减薄处理后得到未经修复的光学波导晶圆W41。
S05：通过化学机械研磨(chemical and mechanical polishing，CMP)与退火(annealing)提升光学导波层L02半导体薄膜晶格质量与表面平坦度。
具体地，由离子剪刀技术制备而成的半导体薄膜表面粗糙度极高(典型值为RMS＝10～30nm)，并不适合光学波导或集成电路的制备。因而必须采用合适 的研磨方式来对表面平整度进行修复。
具体地，通过采用含有氧化硅、氧化铝、金刚石等纳米颗粒材料的非中性悬浮液作为研磨液材料，以硬质研磨盘、软质研磨盘的顺序对光学波导晶圆W41表面进行研磨以除去缺陷富集层X01，并使得光学导波层L02到达指定厚度。
进一步地，由于离子剪刀技术会在远离缺陷富集层X01的位置形成少量轰击造成的缺陷，在完成化学机械研磨步骤后仍需通过退火的方式以修复晶圆中的晶格缺陷。这部分内容已在其他公开中详细阐述，故本公开不做赘述。
优选地，经减薄和退火处理后的光学波导晶圆W41的最终结构如图4(b)所示。
需特别注意地是，如无特殊说明，预处理后的键合界面B01将在后文省略。
S06：对光学导波层L02半导体薄膜进行图案定义与刻蚀并为下一次键合做预处理。
具体地，通过干法刻蚀的方式，可对光学导波层L02进行图案定义以形成必要的光学结构。该光学结构可作为发射器、调制器、接收器以及波导的一部分或一个与多个整体。刻蚀部分可包括完全刻蚀部分P01以及部分刻蚀部分P02，如图4(c)所示。
进一步地，图案定义后的光学波导晶圆W41可直接用于再次键合。
优选地，在刻蚀结束后，亦可选择通过沉积、溅射或蒸镀的方式填充其他材料(如氧化硅)作为承载光电转换层L01的介质层I01。其优点在于键合强度更高，可集成高密度的光电器件。然而，介质层I01在形成过程中会不可避免地形成台阶状起伏，这十分不利于后续再次键合的过程。
优选地，可通过引入第二次CMP的方式将介质层I01平坦化，如图4(d)所示。须注意的是在本过程中，需精细控制CMP的各参数以保证在平坦化过程中不会破坏原有的光学导波层L02上已被定义的图案。
S07：提供顶层晶圆/切片W03。
进一步地，如图5所示，本实施例提供两种备选顶层晶圆/切片W03的层结构方案：顶层晶圆/切片第一备选方案W03-a和顶层晶圆/切片第二备选方案 W03-b。
具体地，顶层晶圆/切片第一备选方案W03-a包含：N型接触层L015、量子结构层L014、P型接触层L013、牺牲层L012和牺牲层衬底L011。其中，N型接触层L015、量子结构层L014和P型接触层L013构成光电转换层L01。
具体地，顶层晶圆/切片第二备选方案W03-b包含：模式匹配层L016、量子结构层L014、牺牲层L012和牺牲层衬底L011。其中，模式匹配层L016和量子结构层L014构成光电转换层L01。特别地，P型接触层L013和N型接触层L015可在后端工艺中通过扩散/离子注入的方式嵌入模式匹配层L016中。
其中，牺牲层衬底L011可选为InP，牺牲层L012可选为InGaAsP，量子结构层L014可选为基于InGaAsP的多层量子阱(multi-quantum well，MQW)结构。
S08：将光学波导晶圆W41与顶层晶圆/切片W03结合。
进一步地，为保证光学波导晶圆W41与顶层晶圆/切片W03之间的电气良绝缘性，需保证光学波导晶圆W41上的介质层仍包裹住光学导波层L02所构成的光学器件结构。
优选地，对光学波导晶圆W41需进行如下预处理：
1.需用常用半导体清洗工艺对晶圆进行1-10分钟的清洗，包括但不限于等离子清洗、采用浸润或超声波下浸润的去离子水、RCA、SC1\SC2或有机溶剂对晶圆进行清洗；
2.需对晶圆的顶层表面进行等离子活化处理，等离子活化后需保证顶层界面亲疏水性需与顶层晶圆/切片W03保持一致。
优选地，对顶层晶圆/切片W03需进行如下预处理：
1.需用常用半导体清洗工艺对晶圆进行1-10分钟的清洗，包括但不限于等离子清洗、采用浸润或超声波下浸润的去离子水、RCA、SC1\SC2或有机溶剂对晶圆进行清洗；
2.需对晶圆的顶层表面进行等离子活化处理，等离子活化后需保证顶层界面亲疏水性需与光学波导晶圆W41保持一致。
进一步地，将经过顶层表面处理的光学波导晶圆W41和顶层晶圆/切片W03在特定氛围中进行对准键合操作。特别地，该氛围包括真空、氮气、氩气以及其他惰性气体氛围。在键合完成后，在相同氛围内经退火处理以加固两晶圆之间的共价键结合力，键合后的晶圆层结构如图7(a)所示。
特别地，对于III-V族化合物半导体而言，受限于其晶体生长方法，截至本公开发表之日所能实现的最大三五组化合物半导体的晶圆尺寸为2-6英寸。因此在执行步骤S08时，应灵活依据晶圆大小适时调整结合方案。
具体地，图6(a1)及图6(a2)分别表示步骤S08处理后得到的最终三层堆叠结构晶圆第一备选方案W00-a正面俯视结构和层结构。需明确，在本方案中，介质层I01被省略以凸显顶层晶圆/切片W03在光学波导晶圆W41上的堆叠方式。需明确，在该示意图中，光学导波层L02已集成了光学器件结构。在本方案中，顶层晶圆/切片W03可通过微纳结构转印的方式被结合至光学波导晶圆W41上指定位置。其优点在于可以灵活布置最终三层堆叠结构晶圆W00中的光学器件功能区，并且可以灵活调整顶层晶圆/切片W03中量子结构层L012内部的量子结构。然而对于该方案而言，其弊端在于需在结合过程中保证极高的对准精度以及高一致性的键合强度的要求十分苛刻。
优选地，图6(b1)及图6(b2)分别表示步骤S08处理后得到的最终三层堆叠结构晶圆第二备选方案W00-b的正面俯视结构和层结构。该方案采用晶圆/晶圆结合。需明确，在本方案中，介质层I01被省略以凸显顶层晶圆/切片W03在光学波导晶圆W41上的堆叠方式。需明确，在该示意图中，光学导波层L02已集成了光学器件结构。需明确，此方案虽在晶圆尺寸上做出了妥协，但应理解在本公开中所采用三层堆叠结构晶圆W00中的顶层晶圆的具体尺寸并不局限于前述尺寸限制。
S09：将与光学波导晶圆W41结合后的顶层晶圆/切片W03进行减薄处理，得到三层堆叠结构晶圆W00。
具体地，可通过湿法刻蚀的方式除去牺牲层衬底L011及牺牲层L012，所得到的三层堆叠结构晶圆W00如图7(b)所示。
S10：对光电转换层L01半导体薄膜进行图案定义与刻蚀。根据具体实施例要求，其刻蚀方法可包括全部刻蚀或部分刻蚀，这两种方式由光电转换层刻蚀部分P03表示。随后在刻蚀后的光电转换层L01上形成保护层I02；
具体地，可通过干法刻蚀的方式对光电转换层L01进行图案转移，其示意图为图7(c)。
优选地，对于备选方案W03-a而言，可通过干法刻蚀的方式将经过图案定义的P型接触层L013和量子结构层L012移除，保留N型接触层L011用于后续电极定义。
备选地，对于备选方案W03-b而言，可通过干法刻蚀的方式将经过图案定义的模式匹配层L016和量子结构层L012移除，并额外定义P/N掺杂区域以实现横向PN/PIN结半导体结构。
优选地，在经图案定义后的三层堆叠结构晶圆W00上通过沉积、溅射或蒸镀的方式填充保护层I02(如氧化硅)，其填充后的层结构如图7(d)所示。
S11：对三层堆叠结构晶圆W00执行后端金属电极成型工艺与封装。
具体地，通过在保护层I02与介质层I01上进行图案定义与干法/湿法刻蚀的方式，形成可让金属电极与指定功能区域具有良接触的空腔结构。
具体地，金属电极的形成可通过沉积、溅射、蒸镀或电镀实现，其图案定义可通过剥离或刻蚀形成。
应了解，在形成金属电极过程中，工程人员可根据实际场景与具体指标灵活布置金属电极的大小、材料及其附属集成电路(如在光学导波层中增加掺杂步骤以实现电阻、电容、电感、场效应晶体管、双极性晶体管等电学器件。)。在不违背本公开的中心思想的前提下，以上变动均可认为包含在该实施例的演示范围内。
S12：结束流程。
在图8(a)和图8(b)所演示的实例当中，介绍了基于三层堆叠结构晶圆W00可实现的光电器件类型及其具体实现方法。
具体地，如图8(a)所示，该实例演示了一种基于光学导波层L02和信号 调制层L03构造的调制器结构。
具体地，光信号经由光学导波层L02和信号调制层L03构成的第一波导WG1-1(可选地，在本实例中该波导的宽度为0.55微米)经由调制层第一超模式过渡波导SWG1-1输入至调制层超模式波导SWG2(可选地，在本实例中该超模式波导的宽度为0.35微米)。在调制层超模式波导SWG2中，光信号可由印加在信号调制层L03上的电场经由本实例中信号调制层L03所选用铌酸锂的线性电光效应进行相位信号的调制。经过调制的光信号通过调制层第二超模式过渡波导SWG1-2输出至第二波导WG1-2。
具体地，第一波导WG1-1与第二波导WG1-2中的截面电场分布由光学波导模式M01所演示，所展示的模式类型为TE00。
一般地，第一波导WG1-1与第二波导WG1-2亦可在其他区域中构成诸如S型、L型或U型弯曲波导、N×N端口方向耦合器、Y型分支、M×N端口MMI以及M×N星型耦合器等无源光学结构。
本实例中的第一波导WG1-1与第二波导WG1-2为条形波导(channel waveguide)结构。一般地、亦可构成脊型波导(rib waveguide)、槽波导(slot waveguide)以及基于布拉格光栅结构、超晶格结构或光子晶体实现的光波导。
本实例中的调制层超模式波导SWG2的光学导波层L02部分为条形波导结构。一般地、亦可构成脊型波导、槽波导以及基于布拉格光栅结构、超晶格结构或光子晶体实现的光波导。
具体地，在条形波导的结构下，调制层超模式波导SWG2中的截面电场分布由信号调制层模式M02所演示，所展示的模式类型为TM00。由于外加电场在光学导波层L02和信号调制层L03的界面处强度最高，因此应尽可能将调制层超模式波导SWG2中的截面电场分布中心微调至界面处。在本实例中，通过缩小调制层超模式波导SWG2中光学导波层L02部分波导结构的宽度，可限制TE模式的产生。需注意，其他波导结构例如槽波导和光子晶体波导等亦可以实现类似效果。在不违反本公开中心思想的前提下，将认为这类改变仍可归于该实例演示的效果之内。
具体地，如图8(b)所示，该实例演示了一种基于信号调制层L03、光学导波层L02和光电转换层L01构造的发射器/放大器/接收器结构。
进一步地，该实例的实施可通过精细设计光电转换层L01厚度以及光学导波层L02所构成的光学波导宽度来实现。其电场分布可由三层堆叠结构波导模式M03所演示。需注意，其他波导结构例如槽波导和光子晶体波导等亦可以实现类似效果。在不违反本公开中心思想的前提下，将认为这类改变仍可归于该实例演示的效果之内。
具体地，光信号经由光学导波层L02和信号调制层L03构成的第一波导WG1-1(可选地，在本实例中该波导的宽度为0.55微米)经由信号调制层L03、光学导波层L02和光电转换层L01构成的光电转换层第一超模式过渡波导SWG3-1输入至光电转换层超模式波导SWG4(可选地，在本实例中该超模式波导中光学导波层L02部分的宽度为0.35微米)依据其应用进行相应处理：
作为放大器，在光电转换层超模式波导SWG4中，光信号模式通过光电转换层第一超模式过渡波导SWG3-1将波导模式中心强度过渡至光电转换层超模式波导SWG4中光电转换层L01的量子结构层L012以尽可能提高放大效率。经过放大的光信号通过光电转换层第二超模式过渡波导SWG3-2输出至第二波导WG1-2。
作为发射器，需在第一波导WG1-1和第二波导WG1-2上或之外形成谐振腔结构，其实现方法在术语“发射器”中亦做出了定义。在光电转换层超模式波导SWG4中，光信号模式通过光电转换层第一超模式过渡波导SWG3-1将波导模式中心强度过渡至光电转换层超模式波导SWG4中光电转换层L01的量子结构层L012以尽可能提高电能-光能转换效率。经过谐振腔选择产生的光信号通过光电转换层第二超模式过渡波导SWG3-2输出至第二波导WG1-2。
作为接收器，在光电转换层超模式波导SWG4中，光信号模式通过光电转换层第一超模式过渡波导SWG3-1将波导模式中心强度过渡至光电转换层超模式波导SWG4中光电转换层L01的量子结构层L012以尽可能提高光能-电能效率。由于接收器属于终端(terminal)器件的一种，故在此实例中无需光电转换 层第二超模式过渡波导SWG3-2及第二波导WG1-2。
特别地，对于调制层第一超模式过渡波导SWG1-1、调制层第二超模式过渡波导SWG1-2、光电转换层第一超模式过渡波导SWG3-1及光电转换层第二超模式过渡波导SWG3-2而言，本实例中所述结构均为单段线性渐变结构。需注意该渐变结构可包含以下变动：具有多段线性渐变结构的组合、具有单段或多段非线性渐变结构的组合、具有多段线性/非线性渐变结构的组合、具有单段或多段光栅结构的组合及包含具有抑制反射作用的上述组合的集合。
发明内容和摘要部分可以阐述由发明人(一个或多个)设想的本公开的一个或多个但不是全部示范性实施例，并且从而不是意在以任何方式限制本公开和所附权利要求。
本公开的广度和范围不应受到任何上述示范性实施例的限制，而仅仅应当被根据以下权利要求及其等同物限定。

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  1. 一种三层堆叠结构晶圆的制备方法，其特征在于，所述三层堆叠结构晶圆由衬底晶圆、中间层晶圆和顶层晶圆/切片经过两次堆叠而成；
    所述衬底晶圆具有信号调制层，所述中间层晶圆具有光学导波层，所述顶层晶圆/切片具有光电转换层；
    第一次堆叠，将衬底晶圆与中间层晶圆结合并减薄得到光学波导晶圆；
    第二次堆叠，将光学波导晶圆与顶层晶圆/切片结合并减薄得到最终的三层堆叠结构晶圆。
  2. 根据权利要求1所述的方法，其特征在于，所述信号调制层、光学导波层、光电转换层两两之间互为异质材料。
  3. 根据权利要求1所述的方法，其特征在于，所述信号调制层在衬底晶圆的顶层；所述光学导波层在中间层晶圆的顶层；
    第一次堆叠过程中，对衬底晶圆和中间层晶圆的顶层进行表面悬挂键预处理，之后进行结合，将与衬底晶圆结合后的中间层晶圆进行减薄，保留光学导波层并进行后处理，得到光学波导晶圆。
  4. 根据权利要求1所述的方法，其特征在于，所述光电转换层在顶层晶圆/切片的顶层；所述光电转换层具有对光电信号间的转换和/或光信号的增益功能；
    第二次堆叠过程中，首先对光学波导晶圆的顶层进行图案定义与刻蚀，形成平坦的介质层，再对介质层表面进行悬挂键预处理，之后与顶层晶圆/切片进行结合，将与光学波导晶圆结合后的顶层晶圆/切片进行减薄，保留光电转换层，得到最终的三层堆叠结构晶圆。
  5. 根据权利要求1所述的方法，其特征在于，在三层堆叠结构晶圆的顶层进行图案定义与刻蚀，在刻蚀后的三层堆叠结构晶圆的顶层形成保护层，并进行金属电极形成与封装。
  6. 根据权利要求1所述的方法，其特征在于，所述光电转换层由N型接触层、量子结构层、P型接触层依次堆叠形成，此时PN结或PIN结的电场指向垂 直于顶层表面，通过调整量子结构层的厚度及组分，能够使光电转换层同时具有对光信号的产生、放大及接收功能；
    或者，所述光电转换层由模式匹配层和量子结构层堆叠而成，其中模式匹配层中需要形成P型接触和N型接触，此时PN结或PIN结的电场指向平行于顶层表面，通过共同调整模式匹配层和量子结构层的厚度及组分，能够使光电转换层同时具有对光信号的产生、放大及接收功能。
  7. 根据权利要求1所述的方法，其特征在于，所述光电转换层的材料为III-V族化合物半导体及其量子结构，厚度为0.1-1.5微米；
    所述光学导波层的材料为硅，厚度为0.2-0.5微米；
    所述信号调制层的材料为铌酸锂，厚度为0.1-10微米；
    所述三层堆叠结构晶圆的承载层为单晶硅层，或者单晶硅层与氧化硅层的结合，厚度为325-825微米。
  8. 一种权利要求1-7中任一项所述方法制备的三层堆叠结构晶圆的应用，其特征在于，基于信号调制层、光学导波层及光电转换层之间的组合实现调制器/发射器/放大器/接收器功能。
  9. 根据权利要求8所述的应用，其特征在于，对于调制器功能，实现载体为信号调制层，在电场分布的TM模式下，通过电光效应实现相位调制。
  10. 根据权利要求8所述的应用，其特征在于，对于发射器/放大器/接收器功能，实现载体为光电转换层，通过对三层堆叠结构的超模式波导中电场分布的调控，实现发射器/放大器/接收器功能。
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