WO2024001338A1 - 一种数据传输方法、系统、装置及存储介质 - Google Patents

一种数据传输方法、系统、装置及存储介质 Download PDF

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Publication number
WO2024001338A1
WO2024001338A1 PCT/CN2023/083570 CN2023083570W WO2024001338A1 WO 2024001338 A1 WO2024001338 A1 WO 2024001338A1 CN 2023083570 W CN2023083570 W CN 2023083570W WO 2024001338 A1 WO2024001338 A1 WO 2024001338A1
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WIPO (PCT)
Prior art keywords
nvmessd
data
storage array
address
array card
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PCT/CN2023/083570
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English (en)
French (fr)
Inventor
李幸远
王江
孙华锦
李树青
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苏州元脑智能科技有限公司
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Publication of WO2024001338A1 publication Critical patent/WO2024001338A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the field of data transmission, and in particular, to a data transmission method, system, device and storage medium.
  • RAID Redundant Arrays of Independent Disks, Disk Array
  • the hard disk It needs to be connected to the RAID controller through the PCIe (Peripheral component interconnect express, high-speed serial computer expansion bus standard) bus.
  • the control module in the RAID controller cannot control the direct transmission of data between the NVMe hard disk and the host. It needs to be connected first. Buffering is performed through its own RAID DRAM (Dynamic Random Access Memory, dynamic random access memory).
  • RAID DRAM Dynamic Random Access Memory, dynamic random access memory
  • the purpose of this application is to provide a data transmission method, system, device and storage medium that does not require a storage array card to perform intermediate data transmission instruction processing, and does not require a storage array card to perform an intermediate data movement process.
  • the data can be directly transferred between the host and Transmission between NVMeSSDs improves the efficiency of data transmission and reduces the performance requirements of storage array cards.
  • the data transmission device includes a host, a storage array card and an NVMeSSD connected in sequence. Between the host and the storage array card and the storage array The card and NVMeSSD are connected through the PCIe bus; the storage array card includes address mapping logic. NVMeSSD maps its own control address space to the storage array card through the address mapping logic of the storage array card. The mapped control address space is the hard disk control mapping address. ;Methods include:
  • the mapped storage address space is the host storage mapping address;
  • the storage array card also includes interrupt mapping logic
  • the mapped interrupt signal address space is the host interrupt signal mapping address
  • NVMeSSD After sending data transfer instructions to NVMeSSD through the hard disk control mapping address in the storage array card, so that NVMeSSD performs data transmission based on the data transfer instructions and the host storage mapping address in the storage array card, it also includes:
  • the interrupt signal is processed after the NVMeSSD writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the NVMeSSD before sending a data transfer instruction to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transfer based on the data transfer instruction and the host storage mapping address in the storage array card, it also includes:
  • the interrupt signal is processed, including:
  • the interrupt signal is processed when the NVMeSSD enables the I/O queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the I/O queue includes a command completion queue and a command submission queue
  • NVMeSSD Send data transfer instructions to NVMeSSD through the hard disk control mapping address, so that NVMeSSD obtains the data transfer command corresponding to the data transfer command from the I/O queue, and transmits the data transfer command corresponding to the host storage mapping address corresponding to the data transfer command.
  • Data including:
  • the interrupt signal is processed when the NVMeSSD enables the I/O queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic, including:
  • the interrupt signal is processed when the NVMeSSD enables the command completion queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the data corresponding to the command it also includes:
  • the storage array card also includes hard disk control logic for establishing a management command queue for the NVMeSSD based on the I/O queue;
  • the storage array card After the storage array card establishes a management command queue for the NVMeSSD, it sends a data transfer command to the NVMeSSD through the hard disk control mapping address, so that the NVMeSSD obtains the data transfer command corresponding to the data transfer command from the I/O queue based on the management command queue, and communicates with the management command queue.
  • the host storage mapping address corresponding to the data transfer command transmits the data corresponding to the data transfer command;
  • the interrupt signal is processed when the NVMeSSD enables the I/O queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic, including:
  • the NVMeSSD After the storage array card establishes a management command queue for the NVMeSSD, the NVMeSSD enables the I/O queue through the management command queue and processes the interrupt signal when writing the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the NVMeSSD before sending a data transfer instruction to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transfer based on the data transfer instruction and the host storage mapping address in the storage array card, it also includes:
  • the data transfer instruction is a write data instruction
  • the write data command is sent to the storage array card, so that the storage array card receives and verifies the data corresponding to the write data command in the host, and compares the verified data with the write data command.
  • the data corresponding to the data command is written to the NVMeSSD;
  • the data transfer command is sent to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD is based on the data transfer command and the host storage mapping address in the storage array card. Steps for data transfer.
  • the data transmission device includes multiple NVMeSSDs connected to the storage array card;
  • NVMeSSD Before sending data transfer instructions to NVMeSSD through the hard disk control mapping address in the storage array card, so that NVMeSSD performs data transfer based on the data transfer instructions and the host storage mapping address in the storage array card, it also includes:
  • the data transfer instruction is a read data instruction
  • a read data command is sent to the target NVMeSSD through the hard disk control mapping address in the storage array card, so that the target NVMeSSD writes the data corresponding to the read data command into the storage
  • the host storage mapping address in the array card
  • the target NVMeSSD If the target NVMeSSD is in a normal state, send a read data command to the target NVMeSSD through the hard disk control mapping address in the storage array card, so that the target NVMeSSD writes the data corresponding to the read data command into the host storage mapping address in the storage array card;
  • the read data command is sent to the storage array card, so that the storage array card receives and verifies the data corresponding to the read data command in the target NVMeSSD, and sends the verified data corresponding to the read data command. Data is sent to the host.
  • this application provides a data transmission system, which is applied to the host in the data transmission device.
  • the data transmission device includes a host, a storage array card and an NVMeSSD connected in sequence. Between the host and the storage array card and the storage array The card and NVMeSSD are connected through the PCIe bus; the storage array card includes address mapping logic, NVMeSSD maps its own control address space to the storage array card through the address mapping logic of the storage array card.
  • the mapped control address space is the hard disk control mapping address; the system includes:
  • the address conversion unit is used to map its own storage address space to the storage array card through the address mapping logic of the storage array card.
  • the mapped storage address space is the host storage mapping address;
  • An instruction sending unit is used to send data transfer instructions to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transmission based on the data transfer instructions and the host storage mapping address in the storage array card.
  • this application provides a data transmission device, including:
  • Memory used to store computer programs
  • the host is used to implement the steps of the above data transmission method when executing the computer program.
  • the storage array card connected to the host through the PCIe bus is used to receive the host storage mapping address of the host and the hard disk control mapping address of the NVMeSSD;
  • the NVMeSSD connected to the storage array card through the PCIe bus is used to store data and transmit data to the host based on the host storage mapping address in the storage array card.
  • the storage array card includes address mapping logic, specifically configured to receive the storage address space mapped by the host through the address mapping logic, and receive the control address space mapped by the NVMeSSD through the address mapping logic.
  • the storage array card further includes interrupt mapping logic, and is further configured to receive the host's interrupt signal address space through the interrupt mapping logic.
  • the storage array card also includes hard disk control logic, which is used to establish a management command queue for the NVMeSSD after receiving the I/O queue established by the host, so that the NVMeSSD obtains and The data transfer command corresponding to the data transfer command, or the I/O queue is enabled based on the management command queue.
  • hard disk control logic which is used to establish a management command queue for the NVMeSSD after receiving the I/O queue established by the host, so that the NVMeSSD obtains and The data transfer command corresponding to the data transfer command, or the I/O queue is enabled based on the management command queue.
  • the I/O queue includes a command completion queue and a command submission queue
  • NVMeSSD is specifically used to store data, and obtains data transfer commands corresponding to data transfer instructions from the command submission queue based on the management command queue, or enables the command completion queue based on the management command queue for data transmission with the host.
  • the present application provides a non-volatile readable storage medium.
  • a computer program is stored on the non-volatile readable storage medium.
  • the computer program is executed by the processor, the above-mentioned data transmission method is implemented. step.
  • This application provides a data transmission method, system, device and storage medium, which relates to the field of data transmission and is used to transmit data.
  • the storage array card is set with address mapping logic, and the host transmits its own storage address space through the storage array card.
  • the address mapping logic is mapped to the storage array card.
  • the NVMeSSD can directly transmit the data transfer instruction and the host storage mapping address in the storage array card, and also That is, NVMeSSD can directly transmit data to the storage address space inside the host. It can be seen that in this application, there is no need for the storage array card to perform the intermediate data transmission instruction processing process, and there is no need for the storage array card to perform the intermediate data movement process.
  • the data can be directly transmitted between the host and the NVMeSSD, which improves the efficiency of data transmission and reduces the cost. Performance requirements for storage array cards.
  • Figure 1 is a schematic flow chart of a data transmission method provided by this application.
  • FIG. 2 is a schematic diagram of a RAID controller connection structure in the prior art
  • Figure 3 is a schematic diagram of the connection structure of a storage array card provided by this application.
  • Figure 4 is a schematic diagram of an address mapping provided by this application.
  • Figure 5 is a schematic diagram of a queue provided by this application.
  • Figure 6 is a data transmission flow chart in which a data transmission instruction provided by this application is a write data instruction
  • Figure 7 is a data transmission flow chart in which a data transmission instruction provided by this application is a read data instruction
  • Figure 8 is a schematic structural diagram of a data transmission system provided by this application.
  • Figure 9 is a schematic structural diagram of a data transmission device provided by this application.
  • the core of this application is to provide a data transmission method, system, device and storage medium that does not require a storage array card to perform intermediate data transmission instruction processing, and does not require a storage array card to perform an intermediate data movement process.
  • the data can be directly transferred to the host 92 Transmitting between NVMeSSD and NVMeSSD improves the efficiency of data transmission and reduces the performance requirements of storage array cards.
  • Figure 1 is a schematic flow chart of a data transmission method provided by the present application, which is applied to the host 92 in the data transmission device.
  • the data transmission device includes the host 92, the storage array card and the NVMeSSD connected in sequence.
  • the host 92 and The storage array cards and the storage array cards and the NVMeSSD are connected through the PCIe bus;
  • the storage array card includes address mapping logic, and the NVMeSSD maps its own control address space to the storage array card through the address mapping logic of the storage array card.
  • the control address space is the hard disk control mapping address; methods include:
  • S11 Map its own storage address space to the storage array card through the address mapping logic of the storage array card.
  • the mapped storage address space is the host storage mapping address;
  • the RAID disk redundant array technology in the existing technology combines multiple disk devices into one or more storage array groups to improve storage performance and increase redundancy to protect data.
  • the core of the traditional RAID system is the RAID controller chip.
  • the RAID controller implemented by hardware is guaranteed in terms of performance, reliability and data security.
  • Traditional RAID controllers are usually connected to SAS or SATA mechanical hard disks or SSDs (Solid State Disks).
  • the upstream of the RAID controller is connected to the host 92 through the PCIe bus, and the downstream is connected to multiple SAS through the SAS/SATA controller. /SATA hard drive connection.
  • Figure 2 is a schematic diagram of a RAID controller connection structure in the prior art.
  • Host is the host 92
  • HostDRAM is the storage address space of the host 92
  • RAID Controller ASIC is the RAID controller chip
  • DMA Engine is the DMA controller, used to store the cache data of the RAID controller
  • SAS/SATA controller is SAS/SATA. Controller
  • the SAS/SATA controller includes multiple ports to connect to multiple SAS/SATA hard drives. If the data to be transmitted does not require RAID check calculation, such as RAID0/1 read and write or RAID5/6 non-degraded read, the DMA controller inside the RAID controller can directly realize the direct connection between the hard disk and the host 52 storage address space. Data movement does not require entering the RAID DRAM cache, which reduces I/O latency, improves data transmission performance, and reduces the performance requirements for RAID DRAM.
  • NVMeSSD NVMe
  • NVMeSSD NVMe
  • the interface greatly unleashes the performance advantages of NAND Flash storage media.
  • the IOPS of traditional SAS/SATA hard disks is usually only a few dozen to more than two hundred. Even the SSD with SAS/SATA interface has only a few thousand to tens of thousands of IOPS, and no more than hundreds of thousands at most.
  • the IOPS of NVMe SSD are only a few hundred thousand. Starting at 100,000, the IOPS of NVMeSSD with PCIe4.0 interface can reach more than one million, and the IOPS of NVMeSSD with PCIe5.0 interface in the future can reach more than three million.
  • NVMeSSD directly uses PCIe as its I/O interface
  • traditional RAID controllers cannot directly handle the data of NVMeSSD unless a high-speed I/O interface or high-speed processor is used, which will undoubtedly increase the implementation cost of the RAID controller.
  • Huge increase, or the RAID controller acts as an intermediate device.
  • the data of the host 92 or the data of the NVMeSSD is first stored in the RAIDDRAM and then sent to the NVMeSSD or the host 92. This undoubtedly results in data loss.
  • the high latency during transmission and the extremely high access bandwidth of RAID DRAM are required.
  • RAID controllers in the existing technology cannot meet the performance requirements of NVMe SSD.
  • the storage array card and the host 92 are connected through the PCIe bus, and the storage array card and the NVMeSSD are also connected through the PCIe bus, and address mapping logic is set in the storage array card.
  • the host 92 can map its own storage address space to the storage array card through address mapping logic, and the host 92 can first convert its own storage address space into a host storage mapping address, and then send it to the storage array card, or directly convert its own storage address space to the storage array card.
  • the storage address space is mapped to the storage array card, and then the storage array card converts the storage address space of the host 92 into the host storage mapping address. This application does not limit this.
  • S12 Send a data transfer instruction to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transmission based on the data transfer instruction and the host storage mapping address in the storage array card.
  • NVMeSSD can also map its own control address space to the storage array card through the address mapping logic of the storage array card.
  • the host 92 needs to write data to the NVMeSSD or read data in the NVMeSSD, it can control the hard disk in the storage array card.
  • the mapped address is written into the data transfer command.
  • the host 92 directly writes the data transfer command into the control address space of the NVMeSSD, for example, into the Doorbell register of the NVMeSSD.
  • the NVMeSSD controller inside the NVMeSSD can directly read the data transfer instruction from its own control address space.
  • the address pointer of the data transfer instruction points to the host storage mapping address mapped by the host 92 through the address mapping logic, which also ensures that it is consistent with the NVMeSSD To ensure the accuracy of the location of the data transferred between them, the address that the host 92 writes the data transfer command into the NVMeSSD is also the hard disk control mapping address of the NVMeSSD after the address mapping logic.
  • the NVMeSSD internal controller writes the data in its own storage address space into the host storage mapping address according to the data transfer instructions.
  • the NVMeSSD directly writes the data in its own storage address space into the storage address space of the host 92, realizing the host 92 directly Read the data in the NVMeSSD to its own storage address space, or the NVMeSSD reads the data from the host storage mapping address according to the data transfer instruction and writes it into its own storage address space.
  • the NVMeSSD directly transfers the storage address of the host 92 The data in the space is moved to its own storage address space, thereby enabling the host 92 to directly write the data in its own storage address space into the NVMeSSD.
  • each storage array card can mount multiple NVMeSSDs. Before the NVMeSSD maps its control address space to the storage array card through address mapping logic, the storage array card must first initialize and configure the PCIe bus connected to the NVMeSSD and scan Each NVMeSSD mounted by itself then performs BAR (Base Address Register) space mapping for each NVMeSSD, that is, the control address space of each NVMeSSD is mapped to itself through its own address mapping logic, that is, the hard disk of each NVMeSSD is generated. Control mapping address. The host 92 can map the hard disk control mapping address of each NVMeSSD in the storage array card to the hard disk control mapping of the target NVMeSSD. Address write data transfer instructions.
  • BAR Basic Address Register
  • the storage array card in this application is a RAID controller.
  • the RAID controller is connected to each NVMeSSD through the PCIe bus, that is, the PCIeRC (PCIe Root Complex, PCIe root complex) controller, and the PCIeRC controller includes multiple PCIePorts, which can expand multiple NVMeSSDs.
  • Figure 3 is a schematic diagram of a storage array card connection structure provided by this application. Among them, the PCIeRC of the host 92 is connected to the PCIeEP (PCIe Endpoint device) of the storage array card.
  • Figure 4 is a schematic diagram of an address mapping provided by the present application.
  • the address space of the host 92 includes its own storage address space, that is, the HostDRAM address space. After being mapped to the RAID controller, it becomes the host storage. Mapping address, that is, HostDRAM mapping space.
  • NVMeSSD performs data transmission with the host 92, it accesses the host storage mapping address, that is, accesses the HostDRAM mapping space. In fact, it directly accesses the HostDRAM address space in the host 92.
  • the NVMeSSD 1BAR address space, NVMeSSD 2BAR address space and NVMeSSD xBAR address space in the RAID controller address space are the actual control signal address spaces of the NVMeSSD.
  • the host 92 accesses the hard disk control mapping address of the NVMeSSD, that is, the NVMeSSD1BAR mapping.
  • NVMeSSD 2BAR mapping space and NVMeSSD xBAR mapping space it actually accesses the actual control signal address space of NVMeSSD, that is, directly accesses the NVMeSSD 1BAR address space, NVMeSSD 2BAR address space and NVMeSSD xBAR address space of NVMeSSD, that is, different NVMeSSD of different address spaces.
  • NVMeSSD in this application has its own controller, such as a DMA controller.
  • the storage array card further includes interrupt mapping logic
  • NVMeSSD Before sending data transfer instructions to NVMeSSD through the hard disk control mapping address in the storage array card, so that NVMeSSD performs data transfer based on the data transfer instructions and the host storage mapping address in the storage array card, it also includes:
  • the mapped interrupt signal address space is the host interrupt signal mapping address
  • NVMeSSD After sending data transfer instructions to NVMeSSD through the hard disk control mapping address in the storage array card, so that NVMeSSD performs data transmission based on the data transfer instructions and the host storage mapping address in the storage array card, it also includes:
  • the interrupt signal is processed after the NVMeSSD writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the storage array card also includes interrupt mapping logic.
  • the host 92 can map its own interrupt signal address space to the storage array card through the interrupt logic.
  • the NVMeSSD needs to send an interrupt signal to the host 92, it directly By writing the host interrupt signal mapping address in the storage array card, the interrupt signal can be directly written into the interrupt signal address space of the host 92 .
  • the host 92 processes the interrupt signal after the interrupt signal is written into its own interrupt signal address space by the NVMeSSD, realizing the direct transmission of the interrupt signal between the NVMeSSD and the host 92 without the need for transmission through the storage array card, which improves signal transmission efficiency and interrupts. signal processing efficiency.
  • the interrupt signal in this application may, but is not limited to, include MSI/MSIX interrupt write operation or Pin interrupt.
  • MSI/MSIX interrupt write operation or Pin interrupt output by the NVMeSSD can be mapped to MSI/MSIX (MSI: Message Signaled Interrupts, message-based interrupts) write operation to the interrupt signal address space in the interrupt storage array card of the host 92.
  • the NVMeSSD before sending a data transfer instruction to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transmission based on the data transfer instruction and the host storage mapping address in the storage array card, it also includes:
  • the interrupt signal is processed, including:
  • the interrupt signal is processed when the NVMeSSD enables the I/O queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the host 92 before performing data transmission with the NVMeSSD, the host 92 first establishes an I/O queue, so that the host 92 sends a data transmission command corresponding to the specific data to be transmitted to the NVMeSSD through the I/O queue, or based on The I/O queue receives the interrupt signal sent by the NVMeSSD to the host 92. Specifically, the host 92 can directly send an I/O (Input/Output, input/output) command to the NVMeSSD, that is, a data transfer command. Specifically, the host 92 In its own storage address space, that is, the data structure of the I/O queue is established in HostDRAM.
  • I/O Input/Output, input/output
  • the host 92 sends a command to the storage array card to request the establishment of the I/O queue of the NVMeSSD.
  • the host 92 places the I/O queue in HostDRAM.
  • the base address in is mapped to the storage array card through the address mapping logic of the storage array card.
  • the storage array card receives the command to establish the I/O queue of the NVMeSSD, if the base address of the I/O queue sent by the host 92 is not converted into an address If the logically mapped address is mapped, the base address is converted into the logically mapped address of the address mapping.
  • an I/O queue is established for the NVMeSSD through NVMeSetFeature.
  • the host 92 can establish multiple I/O queues for the same NVMeSSD.
  • the total number of I/O queues of each NVMeSSD is not greater than the local I/O of the storage array card. Queues and the number of I/O queues reserved for host 92.
  • the local I/O queue of the storage array card is the I/O queue when data needs to be verified and calculated; the I/O queue reserved for host 92 There is no need for checksum calculation, but an I/O queue for direct data transmission between the NVMeSSD and the host 92.
  • NVMeSSD can directly obtain the data transmission command generated by the host 92, which can improve the efficiency and accuracy of data transmission command delivery during data transmission between the NVMeSSD and the host 92 to improve data transmission. efficiency.
  • the I/O queue includes a command completion queue and a command submission queue
  • NVMeSSD Send data transfer instructions to NVMeSSD through the hard disk control mapping address, so that NVMeSSD obtains the data transfer command corresponding to the data transfer command from the I/O queue, and transmits the data transfer command corresponding to the host storage mapping address corresponding to the data transfer command.
  • Data including:
  • the interrupt signal is processed when the NVMeSSD enables the I/O queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic, including:
  • the interrupt signal is processed when the NVMeSSD enables the command completion queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the I/O queue established by the host 92 includes a command completion queue and a command submission queue.
  • the command submission queue includes multiple data transfer commands, which can point to the storage address space, NVMeSSD, etc. in the host 92 The storage address space in the storage address space and the data to be transferred in each storage address space.
  • the NVMeSSD obtains the data corresponding to the data transfer instruction from the command submission queue according to the data transfer instruction.
  • the transmission command is used to determine the storage address space in the host 92 that currently needs to be data moved and the storage address space in itself that needs to be moved.
  • NVMeSSD When NVMeSSD completes the data movement corresponding to the data transfer command, it can enable the command completion queue and write the interrupt signal into the interrupt signal address space of the host 92. After the host 92 recognizes that the command completion queue is enabled, it interrupts itself. Interrupt signals in the signal address space are processed.
  • the SQ queue is the command submission queue
  • the CQ queue is the command completion queue, that is, the queue that receives the interrupt signal of NVMeSSD.
  • NVMeSSD When NVMeSSD enables the command completion queue, it specifically enables the CQ queue.
  • the data transfer command is sent to the NVMeSSD through the hard disk control mapping address, so that the NVMeSSD obtains the data transfer command corresponding to the data transfer command from the command submission queue, and transfers it with the host storage mapping address corresponding to the data transfer command.
  • the data transfer command Before the data corresponding to the data transfer command, it also includes:
  • the host 92 writes each data transfer command into the command submission queue.
  • the NVMeSSD obtains the data transfer command from the pre-established command submission queue, that is, the SQ queue.
  • the data transfer command includes the data to be transferred, the data should be read or written, and the address of the data to be transferred in the host 92 and NVMeSSD, so that the NVMeSSD controller can execute the corresponding data transfer operations.
  • the storage array card also includes hard disk control logic for establishing a management command queue for the NVMeSSD based on the I/O queue;
  • NVMeSSD Send data transfer instructions to NVMeSSD through the hard disk control mapping address, so that NVMeSSD obtains the data transfer command corresponding to the data transfer command from the I/O queue, and transmits the data transfer command corresponding to the host storage mapping address corresponding to the data transfer command.
  • Data including:
  • the storage array card After the storage array card establishes a management command queue for the NVMeSSD, it sends a data transfer command to the NVMeSSD through the hard disk control mapping address, so that the NVMeSSD obtains the data transfer command corresponding to the data transfer command from the I/O queue based on the management command queue, and communicates with the management command queue.
  • the host storage mapping address corresponding to the data transfer command transmits the data corresponding to the data transfer command;
  • the interrupt signal is processed when the NVMeSSD enables the I/O queue and writes the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic, including:
  • the NVMeSSD After the storage array card establishes a management command queue for the NVMeSSD, the NVMeSSD enables the I/O queue through the management command queue and processes the interrupt signal when writing the interrupt signal to the host interrupt signal mapping address through the interrupt mapping logic.
  • the storage array card uses its own hard disk control logic to establish a management command queue for the NVMeSSD based on the I/O queue. Based on this, the NVMeSSD can be managed through The command queue is indirectly "connected" to the I/O queue established by the host 92, so that the NVMeSSD can obtain the data transfer command in the I/O queue according to the management command queue, and when sending an interrupt signal to the host 92, the NVMeSSD can I/O queue is enabled to improve the efficiency of data transmission.
  • one or more I/O queues can be set for each NVMeSSD in the host 92, but there is only one management queue for each NVMeSSD in the storage array card.
  • Figure 5 is a schematic diagram of a queue provided by this application.
  • the base address of the I/O queue established by the host 92 for each NVMeSSD is located in the host 92 and is mapped to the storage array card through address mapping logic.
  • the address of the management command queue established by the storage array card for each NVMeSSD is located in the storage array card.
  • I/O queue 1 in Figure 5 is the I/O queue established by host 92 for NVMeSSD1
  • I/O queue 2 is the I/O queue established by host 92 for NVMeSSD2
  • management command queue 1 is the I/O queue established by the storage array card for NVMeSSD1.
  • Management command queue 2 is a management command queue established by the storage array card for NVMeSSD2.
  • Figure 5 takes this as an example.
  • the host 92 can establish multiple I/O queues for each NVMeSSD.
  • the NVMeSSD before sending a data transfer instruction to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transmission based on the data transfer instruction and the host storage mapping address in the storage array card, it also includes:
  • the data transfer instruction is a write data instruction
  • the write data command is sent to the storage array card, so that the storage array card receives and verifies the data corresponding to the write data command in the host 92, and the verified data is The data corresponding to the write data command is written to the NVMeSSD;
  • the data transfer command is sent to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD is based on the data transfer command and the host storage in the storage array card. Steps to map addresses for data transmission.
  • FIG. 6 is a data transmission flow chart in which a data transmission instruction provided by this application is a write data instruction.
  • some data can be directly transmitted between the host 92 and the NVMeSSD without verification, such as RAID 0/RAID 1/RAID 10, and some data Verification is required before it can be transferred to host 92 or NVMeSSD, such as RAID 5/RAID 6/RAID 50/RAID 60.
  • the data transfer instructions sent by the host 92 also include write data instructions and read data instructions.
  • the read data instructions mean that the host 92 reads data from the NVMeSSD, and the write input instructions mean that the data is written from the host 92 to the NVMeSSD for storage. .
  • the host 92 When the data transfer command in this application is a write data command, and the data corresponding to the write data command is data to be verified, the host 92 needs to send the write data command to the storage array card, and the storage array card responds to the write data command. Analysis is performed to obtain the data corresponding to the write data command from the host 92 and is verified. After the verification is completed, the data is written into the NVMeSSD, which requires the intermediate participation of the storage array card. If the data corresponding to the write data command is not data to be verified, that is, when the data can be directly transmitted between the host 92 and the NVMeSSD, the host 92 can directly write the write data command into the hard disk control mapping address of the NVMeSSD.
  • the NVMeSSD controller in the NVMeSSD directly obtains the data corresponding to the write data instruction from the host storage mapping address and writes it into its own storage space, thereby realizing direct movement of data in the host 92 to the NVMeSSD and improving data transmission efficiency.
  • the data transmission device includes multiple NVMeSSDs connected to the storage array card;
  • NVMeSSD Before sending data transfer instructions to NVMeSSD through the hard disk control mapping address in the storage array card, so that NVMeSSD performs data transfer based on the data transfer instructions and the host storage mapping address in the storage array card, it also includes:
  • the data transfer instruction is a read data instruction
  • a read data command is sent to the target NVMeSSD through the hard disk control mapping address in the storage array card, so that the target NVMeSSD writes the data corresponding to the read data command into the storage
  • the host storage mapping address in the array card
  • the target NVMeSSD If the target NVMeSSD is in a normal state, send a read data command to the target NVMeSSD through the hard disk control mapping address in the storage array card, so that the target NVMeSSD writes the data corresponding to the read data command into the host storage mapping address in the storage array card;
  • the read data command is sent to the storage array card, so that the storage array card receives and verifies the data corresponding to the read data command in the target NVMeSSD, and sends the verified data corresponding to the read data command.
  • the data is sent to host 92.
  • FIG. 7 is a data transmission flow chart in which a data transmission instruction provided by this application is a read data instruction.
  • the host 92 When the data transfer command is a read data command, the host 92 needs to read the data in the NVMeSSD. Similarly, if the data corresponding to the read data command does not need to be verified, the host 92 can directly write the read data command into the hard disk control. Mapping address to realize direct data transmission between host 92 and NVMeSSD. If the data corresponding to the read data command needs to be verified, the read data command is sent to the storage array card.
  • the NVMeSSD needs to first determine whether each NVMeSSD connected to itself is If all NVMeSSDs are normal, the host 92 can directly write the read data command to the hard disk control mapping address to realize direct data transmission between the host 92 and the NVMeSSD.
  • the host 92 can also directly write the read data command. The hard disk controls the mapping address to realize direct data transmission between the host 92 and the NVMeSSD.
  • the host 92 needs to send the read data command to the storage array card so that the storage array card can receive and verify the data in the target NVMeSSD.
  • the data corresponding to the read data command is sent to the host 92 after verification to ensure the integrity of the transmitted data.
  • Figure 8 is a schematic structural diagram of a data transmission system provided by this application.
  • the system is applied to the host 92 in the data transmission device.
  • the data transmission device includes the host 92, the storage array card 31 and the NVMeSSD connected in sequence.
  • the host 92 and the storage array card 31 and the storage array card 31 and the NVMeSSD are connected through the PCIe bus;
  • the storage array card 31 includes address mapping logic, and the NVMeSSD maps its own control address space to the storage array card 31 through the address mapping logic.
  • Storage array card 31, the mapped control address space is the hard disk control mapped address;
  • the system includes:
  • the address conversion unit 81 is used to map its own storage address space to the storage array card through the address mapping logic of the storage array card, and the mapped storage address space is the host storage mapping address;
  • the instruction sending unit 82 is configured to send a data transfer instruction to the NVMeSSD through the hard disk control mapping address in the storage array card, so that the NVMeSSD performs data transmission based on the data transfer instruction and the host storage mapping address in the storage array card.
  • FIG. 9 is a schematic structural diagram of a data transmission device provided by this application.
  • the device includes:
  • Memory 91 used to store computer programs
  • the host 92 is used to implement the steps of the above data transmission method when executing the computer program.
  • it also includes: a storage array card 31 connected to the host 92 through the PCIe bus, for receiving the host storage mapping address of the host 92 and the hard disk control mapping address of the NVMeSSD;
  • the NVMeSSD connected to the storage array card 31 through the PCIe bus is used to store data and perform data transmission with the host 92 based on the host storage mapping address in the storage array card 31 .
  • the storage array card 31 includes address mapping logic, specifically configured to receive the storage address space mapped by the host 92 through the address mapping logic, and receive the control address space mapped by the NVMeSSD through the address mapping logic.
  • the storage array card 31 further includes interrupt mapping logic and is further configured to receive the interrupt signal address space of the host 92 through the interrupt mapping logic.
  • the storage array card 31 also includes hard disk control logic, which is used to establish a management command queue for the NVMeSSD after receiving the I/O queue established by the host 92, so that the NVMeSSD starts from the I/O based on the management command queue. Obtain the data transfer command corresponding to the data transfer command in the queue, or enable the I/O queue based on the management command queue.
  • the I/O queue includes a command completion queue and a command submission queue
  • NVMeSSD is specifically used to store data, and obtain data transfer commands corresponding to data transfer instructions from the command submission queue based on the management command queue, or enable the command completion queue based on the management command queue to perform data transmission with the host 92 .
  • the storage array card 31 in some embodiments includes address mapping logic, interrupt mapping logic and hard disk control logic, which not only enables direct data interaction between the host 92 and the storage address space of the NVMeSSD, but also enables the host 92 and Data transfer instructions, data transfer commands, and interrupt signals are directly transmitted between NVMeSSDs, which improves the efficiency of data transmission.
  • the non-volatile readable storage medium in this application stores a computer program.
  • the computer program is executed by the host 52, the steps of the above-mentioned data transmission method are implemented.

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Abstract

本申请公开了一种数据传输方法、系统、装置及存储介质，涉及数据传输领域，用于对数据进行传输，存储阵列卡中设置了地址映射逻辑，主机将自身的存储地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，在通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令后，NVMeSSD可直接数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输，也即NVMeSSD可直接与主机内部的存储地址空间进行数据传输。可见，本申请中无需存储阵列卡进行中间的数据传输指令处理过程，也无需存储阵列卡对数据的中间搬移过程，数据可直接在主机和NVMeSSD之间传输，提高了数据传输的效率，降低了存储阵列卡的性能要求。

Description

一种数据传输方法、系统、装置及存储介质
相关申请的交叉引用
本申请要求于2022年06月30日提交中国专利局，申请号为202210759837.9，申请名称为“一种数据传输方法、系统、装置及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据传输领域，特别是涉及一种数据传输方法、系统、装置及存储介质。
背景技术
现有技术中主机在和SAS(Serial Attached SCSI，串行连接SCSI接口)/SATA(Serial Advanced Technology Attachment，串行高级技术附件)硬盘之间进行数据传输时，需要在主机和SAS/SATA硬盘之间设置RAID(Redundant Arrays of Independent Disks，磁盘阵列)存储阵列卡，而RAID控制器中包括控制模块和数据传输模块，控制模块在接收到主机发送的控制信号后，若待传输的数据无需进行RAID校验计算，可使主机和硬盘之间直接通过数据传输通道进行数据传输。
但是，若硬盘的IOPS(Input/Output Operations Per Second，每秒钟输入输出操作次数)较大时，例如NVMe(Non-Volatile Memory express，非易失性内存主机存储阵列卡接口规范)硬盘，硬盘和RAID控制器之间需通过PCIe(Peripheral component interconnect express，高速串行计算机扩展总线标准)总线进行连接，而RAID控制器中的控制模块无法控制NVMe硬盘和主机之间数据的直接传输，需要先通过自身的RAID DRAM(Dynamic Random Access Memory，动态随机存取存储器)进行缓冲，但是由于缓冲时造成的时间延迟，以及RAID DRAM自身的带宽限制，现有技术中的RAID无法实现主机和NVMe硬盘之间的直接数据传输，无法满足NVMe硬盘性能需求。
发明内容
本申请的目的是提供一种数据传输方法、系统、装置及存储介质，无需存储阵列卡进行中间的数据传输指令处理过程，也无需存储阵列卡对数据的中间搬移过程，数据可直接在主机和NVMeSSD之间传输，提高了数据传输的效率，降低了存储阵列卡的性能要求。
为解决上述技术问题，本申请提供了一种数据传输方法，应用于数据传输装置中的主机，数据传输装置包括依次连接的主机、存储阵列卡以及NVMeSSD，主机与存储阵列卡之间以及存储阵列卡与NVMeSSD之间通过PCIe总线连接；存储阵列卡包括地址映射逻辑，NVMeSSD将自身的控制地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的控制地址空间为硬盘控制映射地址；方法包括：
将自身的存储地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的存储地址空间为主机存储映射地址；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输。
可选地，存储阵列卡还包括中断映射逻辑；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使 NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
将自身的中断信号地址空间通过存储阵列卡的中断映射逻辑映射至存储阵列卡，映射后的中断信号地址空间为主机中断信号映射地址；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之后，还包括：
在NVMeSSD通过中断映射逻辑向主机中断信号映射地址中写入中断信号后处理中断信号。
可选地，通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
建立I/O队列，并将I/O队列的基地址通过存储阵列卡的地址映射逻辑映射至存储阵列卡；
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据；
在NVMeSSD通过中断映射逻辑向主机中断信号映射地址中写入中断信号后处理中断信号，包括：
在NVMeSSD使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号。
可选地，I/O队列包括命令完成队列和命令提交队列；
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据，包括：
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从命令提交队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据；
在NVMeSSD使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号，包括：
在NVMeSSD使能命令完成队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号。
可选地，通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从命令提交队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据之前，还包括：
将各个数据传输命令写入命令提交队列中。
可选地，存储阵列卡还包括硬盘控制逻辑，用于基于I/O队列为NVMeSSD建立管理命令队列；
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从I/O队列中 获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据，包括：
在存储阵列卡为NVMeSSD建立管理命令队列后，通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于管理命令队列从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据；
在NVMeSSD使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号，包括：
在存储阵列卡为NVMeSSD建立管理命令队列后，在NVMeSSD通过管理命令队列使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号。
可选地，通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
当数据传输指令为写数据指令时，判断与写数据指令对应的数据是否为待校验数据；
若写数据指令对应的数据为待校验数据，则将写数据指令发送至存储阵列卡，以使存储阵列卡接收并校验主机中与写数据指令对应的数据，将校验后的与写数据指令对应的数据写入至NVMeSSD中；
若写数据指令对应的数据不为待校验数据，则进入通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输的步骤。
可选地，数据传输装置包括多个NVMeSSD与存储阵列卡连接；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
当数据传输指令为读数据指令时，判断与读数据指令对应的数据是否为待校验数据；
若为待校验数据，则判断与存储阵列卡连接的各个NVMeSSD是否均处于正常状态；
若不为待校验数据，或各个NVMeSSD均处于正常状态，则通过存储阵列卡中的硬盘控制映射地址向目标NVMeSSD发送读数据指令，以使目标NVMeSSD将与读数据指令对应的数据写入存储阵列卡中的主机存储映射地址；
若各个NVMeSSD并非均处于正常状态，则判断目标NVMeSSD是否处于正常状态；
若目标NVMeSSD处于正常状态，则通过存储阵列卡中的硬盘控制映射地址向目标NVMeSSD发送读数据指令，以使目标NVMeSSD将与读数据指令对应的数据写入存储阵列卡中的主机存储映射地址；
若目标NVMeSSD未处于正常状态，则将读数据指令发送至存储阵列卡，以使存储阵列卡接收并校验目标NVMeSSD中与读数据指令对应的数据，将校验后的与读数据指令对应的数据发送至主机中。
为解决上述技术问题，本申请提供了一种数据传输系统，应用于数据传输装置中的主机，数据传输装置包括依次连接的主机、存储阵列卡以及NVMeSSD，主机与存储阵列卡之间以及存储阵列卡与NVMeSSD之间通过PCIe总线连接；存储阵列卡包括地址映射逻辑， NVMeSSD将自身的控制地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的控制地址空间为硬盘控制映射地址；系统包括：
地址转换单元，用于将自身的存储地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的存储地址空间为主机存储映射地址；
指令发送单元，用于通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输。
为解决上述技术问题，本申请提供了一种数据传输装置，包括：
存储器，用于存储计算机程序；
主机，用于执行计算机程序时实现如上述数据传输方法的步骤。
可选地，还包括：
与主机通过PCIe总线连接的存储阵列卡，用于接收主机的主机存储映射地址和NVMeSSD的硬盘控制映射地址；
与存储阵列卡通过PCIe总线连接的NVMeSSD，用于存储数据，并基于存储阵列卡中的主机存储映射地址与主机进行数据传输。
可选地，存储阵列卡包括地址映射逻辑，具体用于通过地址映射逻辑接收主机映射的存储地址空间，并通过地址映射逻辑接收NVMeSSD映射的控制地址空间。
可选地，存储阵列卡还包括中断映射逻辑，还用于通过中断映射逻辑接收主机的中断信号地址空间。
可选地，存储阵列卡中还包括硬盘控制逻辑，用于在接收到主机建立的I/O队列后，为NVMeSSD建立管理命令队列，以使NVMeSSD基于管理命令队列从I/O队列中获取与数据传输指令对应的数据传输命令，或基于管理命令队列对I/O队列进行使能。
可选地，I/O队列包括命令完成队列和命令提交队列；
NVMeSSD具体用于存储数据，并基于管理命令队列从命令提交队列中获取与数据传输指令对应的数据传输命令，或基于管理命令队列对命令完成队列进行使能，以与主机进行数据传输。
为解决上述技术问题，本申请提供了一种非易失性可读存储介质，非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上述的数据传输方法的步骤。
本申请提供了一种数据传输方法、系统、装置及存储介质，涉及数据传输领域，用于对数据进行传输，存储阵列卡中设置了地址映射逻辑，主机将自身的存储地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，在通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令后，NVMeSSD可直接数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输，也即NVMeSSD可直接与主机内部的存储地址空间进行数据传输。可见，本申请中无需存储阵列卡进行中间的数据传输指令处理过程，也无需存储阵列卡对数据的中间搬移过程，数据可直接在主机和NVMeSSD之间传输，提高了数据传输的效率，降低了存储阵列卡的性能要求。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的 附图。
图1为本申请提供的一种数据传输方法的流程示意图；
图2为现有技术中的一种RAID控制器连接结构示意图；
图3为本申请提供的一种存储阵列卡连接结构示意图；
图4为本申请提供的一种地址映射的示意图；
图5为本申请提供的一种队列示意图；
图6为本申请提供的一种数据传输指令为写数据指令的数据传输流程图；
图7为本申请提供的一种数据传输指令为读数据指令的数据传输流程图；
图8为本申请提供的一种数据传输系统的结构示意图；
图9为本申请提供的一种数据传输装置的结构示意图。
具体实施方式
本申请的核心是提供一种数据传输方法、系统、装置及存储介质，无需存储阵列卡进行中间的数据传输指令处理过程，也无需存储阵列卡对数据的中间搬移过程，数据可直接在主机92和NVMeSSD之间传输，提高了数据传输的效率，降低了存储阵列卡的性能要求。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参照图1，图1为本申请提供的一种数据传输方法的流程示意图，应用于数据传输装置中的主机92，数据传输装置包括依次连接的主机92、存储阵列卡以及NVMeSSD，主机92与存储阵列卡之间以及存储阵列卡与NVMeSSD之间通过PCIe总线连接；存储阵列卡包括地址映射逻辑，NVMeSSD将自身的控制地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的控制地址空间为硬盘控制映射地址；方法包括：
S11：将自身的存储地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的存储地址空间为主机存储映射地址；
在一些实施例中，考虑到现有技术中的RAID磁盘冗余阵列技术是将多个磁盘设备组合起来，成为一个或多个存储阵列组，以提高存储性能、增加冗余以对数据进行保护，传统的RAID系统的核心为RAID控制器芯片，由硬件实现的RAID控制器在性能、可靠性和数据的安全性上都得到了保证。传统的RAID控制器通常连接SAS或SATA机械硬盘或SSD(Solid State Disk，固态硬盘)，具体地，RAID控制器的上游通过PCIe总线与主机92连接，下游通过SAS/SATA控制器与多个SAS/SATA硬盘连接。请参照图2，图2为现有技术中的一种RAID控制器连接结构示意图。其中，Host为主机92，HostDRAM为主机92的存储地址空间，RAID Controller ASIC为RAID控制器芯片，DMA Engine为DMA控制器，用于存储RAID控制器的缓存数据，SAS/SATA controller为SAS/SATA控制器，SAS/SATA控制器包括多个Port，以与多个SAS/SATA硬盘连接。若待传输的数据不需要进行RAID校验计算，例如RAID0/1读写或RAID5/6的非降级读，RAID控制器内部的DMA控制器可直接实现硬盘和主机52存储地址空间之间的直接数据搬移，无需进入RAIDDRAM缓存，降低了I/O延迟，提高了数据传输的性能，且降低了对RAIDDRAM的性能要求。
但是，随着技术的更新，目前的硬盘可以采用NVMe接口，也即NVMeSSD，NVMe 接口极大释放了NANDFlash存储介质的性能优势。传统的SAS/SATA硬盘的IOPS通常只有几十到两百多，即便是SAS/SATA接口的SSD，其IOPS也只有几千到几万，最多不超过十几万，但是NVMeSSD的IOPS均为几十万起步，PCIe4.0接口的NVMeSSD的IOPS可达一百万以上，而未来的PCIe5.0接口的NVMeSSD的IOPS可达三百万以上。且由于NVMeSSD直接采用PCIe作为其I/O接口，导致传统的RAID控制器无法直接对NVMeSSD的数据进行搬运，除非采用高速I/O接口或高速处理器，这无疑导致RAID控制器的实现成本的巨大增加，或者RAID控制器作为中间设备，在NVMeSSD和主机92之间进行数据传输时，先将主机92的数据或NVMeSSD的数据存储至RAIDDRAM，再发送至NVMeSSD或主机92，这无疑导致了数据传输时的高延时，以及需要RAIDDRAM的极高访问带宽，实际上由于RAIDDRAM的带宽限制，现有技术中的RAID控制器无法满足NVMeSSD的性能需求。
为了解决上述技术问题，在一些实施例中的存储阵列卡和主机92之间通过PCIe总线连接，且存储阵列卡和NVMeSSD之间同样通过PCIe总线连接，且在存储阵列卡中设置了地址映射逻辑，主机92可将自身的存储地址空间通过地址映射逻辑映射至存储阵列卡，而主机92可先将自身的存储地址空间转换为主机存储映射地址，再发送至存储阵列卡，或直接将自身的存储地址空间映射至存储阵列卡，再由存储阵列卡将主机92的存储地址空间转换为主机存储映射地址，本申请对此不作限定。
S12：通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输。
NVMeSSD还可将自身的控制地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，当主机92需要将数据写入NVMeSSD或读取NVMeSSD内的数据时，可向存储阵列卡中的硬盘控制映射地址写入数据传输指令，实际上主机92是直接将数据传输指令写入NVMeSSD的控制地址空间，例如写入NVMeSSD的Doorbell寄存器中。此时NVMeSSD内部的NVMeSSD控制器可直接从自身的控制地址空间读取该数据传输指令，该数据传输指令的地址指针指向主机92通过地址映射逻辑进行映射后的主机存储映射地址，也保证和NVMeSSD之间传输数据的位置的准确性，主机92将数据传输命令写入NVMeSSD中的地址同样为NVMeSSD经地址映射逻辑映射后的硬盘控制映射地址。NVMeSSD内部控制器根据数据传输指令将自身存储地址空间的数据写入主机存储映射地址中，实际上为NVMeSSD直接将自身存储地址空间的数据写入主机92的存储地址空间中，实现了主机92直接读取NVMeSSD中的数据至自身的存储地址空间，或NVMeSSD根据数据传输指令从主机存储映射地址中读取数据，并写入自身的存储地址空间内，实际上为NVMeSSD直接将主机92的存储地址空间中的数据搬移至自身的存储地址空间中，便实现了主机92将自身的存储地址空间的数据直接写入NVMeSSD中。
需要说明的是，每个存储阵列卡可以挂载多个NVMeSSD，在NVMeSSD将其控制地址空间通过地址映射逻辑映射至存储阵列卡之前，存储阵列卡需先初始化配置与NVMeSSD连接的PCIe总线，扫描自身挂载的各个NVMeSSD，再为各个NVMeSSD进行BAR(Base Address Register，基地址寄存器)空间映射，也即将各个NVMeSSD的控制地址空间通过自身的地址映射逻辑映射至自身，也即生成各个NVMeSSD的硬盘控制映射地址，主机92可根据存储阵列卡中各个NVMeSSD的硬盘控制映射地址向目标NVMeSSD的硬盘控制映射 地址写入数据传输指令。
进一步需要说明的是，本申请中的存储阵列卡为RAID控制器。RAID控制器通过PCIe总线，也即PCIeRC(PCIe Root Complex，PCIe根复合体)控制器与各个NVMeSSD连接，且PCIeRC控制器包括多个PCIePort，可以扩展多个NVMeSSD。请参照图3，图3为本申请提供的一种存储阵列卡连接结构示意图。其中，主机92的PCIeRC与存储阵列卡的PCIeEP(PCIe Endpoint device)连接。
请参照图4，图4为本申请提供的一种地址映射的示意图，其中，主机92的地址空间中包括自身的存储地址空间，也即HostDRAM地址空间，映射至RAID控制器中后为主机存储映射地址，也即HostDRAM映射空间，NVMeSSD在和主机92进行数据传输时，访问主机存储映射地址，也即访问HostDRAM映射空间，实际上为直接访问主机92中的HostDRAM地址空间。而RAID控制器地址空间中的NVMeSSD 1BAR地址空间、NVMeSSD 2BAR地址空间以及NVMeSSD xBAR地址空间为NVMeSSD的实际控制信号地址空间，经过映射，主机92在访问NVMeSSD的硬盘控制映射地址，也即，NVMeSSD1BAR映射空间、NVMeSSD 2BAR映射空间以及NVMeSSD xBAR映射空间时，实际上为访问NVMeSSD的实际控制信号地址空间，也即直接访问NVMeSSD的NVMeSSD 1BAR地址空间、NVMeSSD 2BAR地址空间以及NVMeSSD xBAR地址空间，也即不同NVMeSSD的不同地址空间。
需要说明的是，本申请中的NVMeSSD中具备其自身的控制器，例如DMA控制器。
综上，本申请中无需存储阵列卡进行中间的数据传输指令处理过程，也无需存储阵列卡对数据的中间搬移过程，数据可直接在主机92和NVMeSSD之间传输，提高了数据传输的效率，降低了存储阵列卡的性能要求。
在上述一些实施例的基础上：
在一些实施例中，存储阵列卡还包括中断映射逻辑；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
将自身的中断信号地址空间通过存储阵列卡的中断映射逻辑映射至存储阵列卡，映射后的中断信号地址空间为主机中断信号映射地址；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之后，还包括：
在NVMeSSD通过中断映射逻辑向主机中断信号映射地址中写入中断信号后处理中断信号。
在一些实施例中，存储阵列卡中还包括中断映射逻辑，主机92可将自身的中断信号地址空间通过中断逻辑映射至存储阵列卡，NVMeSSD在需要向主机92发送中断信号时，直接将中断信号写入存储阵列卡中的主机中断信号映射地址，便可以实现直接将中断信号写入主机92的中断信号地址空间。主机92在自身的中断信号地址空间被NVMeSSD写入中断信号后对中断信号进行处理，实现NVMeSSD和主机92之间中断信号的直接传输，无需通过存储阵列卡简介传输，提高了信号传输效率以及中断信号处理效率。
需要说明的是，本申请中的中断信号可以但不限定包括MSI/MSIX中断写操作或Pin中断，具体地，通过中断映射逻辑可以实现将NVMeSSD输出的MSI/MSIX中断写操作或Pin中断映射为对主机92的中断存储阵列卡中的中断信号地址空间的MSI/MSIX(MSI：Message Signaled Interrupts，基于消息的中断)写操作。
在一些实施例中，通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
建立I/O队列，并将I/O队列的基地址通过存储阵列卡的地址映射逻辑映射至存储阵列卡；
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据；
在NVMeSSD通过中断映射逻辑向主机中断信号映射地址中写入中断信号后处理中断信号，包括：
在NVMeSSD使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号。
在一些实施例中，主机92在和NVMeSSD之间进行数据传输之前，先建立I/O队列，以使主机92通过I/O队列向NVMeSSD发送具体待传输的数据对应的数据传输命令，或者基于I/O队列接收NVMeSSD向主机92发送的中断信号，具体地，使主机92可以直接向NVMeSSD发送I/O(Input/Output，输入/输出)命令，也即数据传输命令，具体地，主机92在自身的存储地址空间中，也即HostDRAM中建立I/O队列的数据结构，主机92向存储阵列卡发送请求建立NVMeSSD的I/O队列的命令，首先，主机92将I/O队列在HostDRAM中的基地址通过存储阵列卡的地址映射逻辑映射至存储阵列卡，存储阵列卡接收到建立NVMeSSD的I/O队列的命令后，若主机92发送的I/O队列的基地址没有转换为地址映射逻辑映射后的地址，则将该基地址转换为地址映射逻辑映射后的地址。具体地，通过NVMeSetFeature为NVMeSSD建立I/O队列，当然，主机92可为同一NVMeSSD建立多个I/O队列，每个NVMeSSD的I/O队列的总个数不大于存储阵列卡本地I/O队列和为主机92预留的I/O队列个数，其中，存储阵列卡本地I/O队列为当数据需要进行校验计算时的I/O队列；为主机92预留的I/O队列为无需进行校验计算，而是NVMeSSD和主机92之间可直接进行数据传输的I/O队列。
基于此，通过设置I/O队列，NVMeSSD可直接获取主机92生成的数据传输指命令，可以提高NVMeSSD和主机92之间进行数据传输时数据传输命令传递的高效率以及准确性，以提高数据传输效率。
在一些实施例中，I/O队列包括命令完成队列和命令提交队列；
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据，包括：
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从命令提交队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地 址传输与数据传输命令对应的数据；
在NVMeSSD使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号，包括：
在NVMeSSD使能命令完成队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号。
在一些实施例中，主机92所建立的I/O队列包括命令完成队列和命令提交队列，其中，命令提交队列中包括了多个数据传输命令，其中可指向主机92中的存储地址空间、NVMeSSD中的存储地址空间以及各存储地址空间中待传输的数据，主机92在将数据传输指令写入NVMeSSD的控制地址空间后，NVMeSSD根据数据传输指令从命令提交队列中获取与数据传输指令对应的数据传输命令，以确定当前需要进行数据搬移的主机92中的存储地址空间以及自身中需要进行数据搬移的存储地址空间。
而NVMeSSD在完成数据传输命令对应的数据搬移时，可使能命令完成队列，并将中断信号写入主机92的中断信号地址空间中，主机92在识别到命令完成队列使能后，对自身中断信号地址空间中的中断信号进行处理。
其中，SQ队列为命令提交队列，CQ队列为命令完成队列，也即接收NVMeSSD的中断信号的队列，NVMeSSD在将命令完成队列进行使能时，具体是将CQ队列使能。
在一些实施例中，通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从命令提交队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据之前，还包括：
将各个数据传输命令写入命令提交队列中。
在一些实施例中，主机92通过将各个数据传输命令写入命令提交队列中，NVMeSSD在检测数据传输指令的输入后，从预先建立的命令提交队列中，也即SQ队列中获取与数据传输指令对应的数据传输命令，该数据传输命令中包括了待传输的数据，该数据应被读取或被写入，以及主机92和NVMeSSD中待进行数据传输的地址，以便NVMeSSD控制器执行相应的数据传输操作。
在一些实施例中，存储阵列卡还包括硬盘控制逻辑，用于基于I/O队列为NVMeSSD建立管理命令队列；
通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据，包括：
在存储阵列卡为NVMeSSD建立管理命令队列后，通过硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于管理命令队列从I/O队列中获取与数据传输指令对应的数据传输命令，并和数据传输命令对应的主机存储映射地址传输与数据传输命令对应的数据；
在NVMeSSD使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号，包括：
在存储阵列卡为NVMeSSD建立管理命令队列后，在NVMeSSD通过管理命令队列使能I/O队列，并通过中断映射逻辑向主机中断信号映射地址中写入中断信号时处理中断信号。
在一些实施例中，在主机92为NVMeSSD建立I/O队列后，为了保证NVMeSSD可以 直接获取I/O队列中的数据传输命令或对I/O队列进行使能，存储阵列卡还通过自身的硬盘控制逻辑基于I/O队列为NVMeSSD建立管理命令队列，基于此，使NVMeSSD通过管理命令队列和主机92所建立的I/O队列间接进行“连接”，使NVMeSSD可根据管理命令队列获取I/O队列中的数据传输命令，并在想主机92发送中断信号时通过管理命令队列对I/O队列进行使能，提高数据传输的效率。
需要说明的是，主机92中可为每个NVMeSSD设置一个或多个I/O队列，而存储阵列卡中每个NVMeSSD的管理队列仅有一个。
请参照图5，图5为本申请提供的一种队列示意图，其中，主机92为各个NVMeSSD所建立的I/O队列的基地址位于主机92中，通过地址映射逻辑映射至存储阵列卡中，而存储阵列卡为各个NVMeSSD建立的管理命令队列的地址位于存储阵列卡中。图5中的I/O队列1为主机92为NVMeSSD1建立的I/O队列，I/O队列2为主机92为NVMeSSD2建立的I/O队列，管理命令队列1为存储阵列卡为NVMeSSD1建立的管理命令队列，管理命令队列2为存储阵列卡为NVMeSSD2建立的管理命令队列，当然，图5以此为例，主机92可为每个NVMeSSD建立多个I/O队列。
在一些实施例中，通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
当数据传输指令为写数据指令时，判断与写数据指令对应的数据是否为待校验数据；
若判断与写数据指令对应的数据为待校验数据，则将写数据指令发送至存储阵列卡，以使存储阵列卡接收并校验主机92中与写数据指令对应的数据，将校验后的与写数据指令对应的数据写入至NVMeSSD中；
若判断与写数据指令对应的数据不为待校验数据，则进入通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输的步骤。
请参照图6，图6为本申请提供的一种数据传输指令为写数据指令的数据传输流程图。
在一些实施例中，考虑到主机92和NVMeSSD之间进行数据传输时，有些数据无需进行校验便可直接在主机92和NVMeSSD之间传输，例如RAID 0/RAID 1/RAID 10，而有些数据需要进行校验之后才可以被传输至主机92或NVMeSSD，例如RAID 5/RAID 6/RAID 50/RAID 60。而主机92发送的数据传输指令也包括写数据指令和读数据指令，其中，读数据指令为主机92从NVMeSSD中读取数据，而写输入指令为数据被从主机92中写入NVMeSSD中进行存储。
当本申请中的数据传输指令为写数据指令，且与写数据指令对应的数据为待校验数据时，需主机92需将写数据指令发送至存储阵列卡，由存储阵列卡对写数据指令进行分析，以从主机92中获取与写数据指令对应的数据，并对其进行校验，校验结束后将该数据写入NVMeSSD中，也即需要存储阵列卡的中间参与。而若与写数据指令对应的数据并非待校验数据，也即主机92和NVMeSSD之间可直接进行该数据的传输时，主机92可直接将该写数据指令写入NVMeSSD的硬盘控制映射地址，以便NVMeSSD中的NVMeSSD控制器直接从主机存储映射地址中获取与写数据指令对应的数据，写入自身的存储空间中，实现主机92中的数据向NVMeSSD中的直接搬移，提高数据传输效率。
在一些实施例中，数据传输装置包括多个NVMeSSD与存储阵列卡连接；
通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
当数据传输指令为读数据指令时，判断与读数据指令对应的数据是否为待校验数据；
若为待校验数据，则判断与存储阵列卡连接的各个NVMeSSD是否均处于正常状态；
若不为待校验数据，或各个NVMeSSD均处于正常状态，则通过存储阵列卡中的硬盘控制映射地址向目标NVMeSSD发送读数据指令，以使目标NVMeSSD将与读数据指令对应的数据写入存储阵列卡中的主机存储映射地址；
若各个NVMeSSD并非均处于正常状态，则判断目标NVMeSSD是否处于正常状态；
若目标NVMeSSD处于正常状态，则通过存储阵列卡中的硬盘控制映射地址向目标NVMeSSD发送读数据指令，以使目标NVMeSSD将与读数据指令对应的数据写入存储阵列卡中的主机存储映射地址；
若目标NVMeSSD未处于正常状态，则将读数据指令发送至存储阵列卡，以使存储阵列卡接收并校验目标NVMeSSD中与读数据指令对应的数据，将校验后的与读数据指令对应的数据发送至主机92中。
请参照图7，图7为本申请提供的一种数据传输指令为读数据指令的数据传输流程图。
而当数据传输指令为读数据指令时，主机92需读取NVMeSSD中的数据，同样地，若与读数据指令对应的数据不需要进行校验，主机92可直接将读数据指令写入硬盘控制映射地址，实现主机92和NVMeSSD之间直接的数据传输。若与读数据指令对应的数据需要进行校验，则将该读数据指令发送至存储阵列卡中，又由于每个存储阵列卡可连接多个NVMeSSD，NVMeSSD需先判断与自身连接的各个NVMeSSD是否均正常，若各个NVMeSSD均正常，主机92可直接将读数据指令写入硬盘控制映射地址，实现主机92和NVMeSSD之间直接的数据传输。而各个NVMeSSD并非均处于正常状态时，先判断与读数据指令对应的目标NVMeSSD是否处于正常状态，若与读数据指令对应的目标NVMeSSD处于正常状态，则主机92同样可直接将读数据指令写入硬盘控制映射地址，实现主机92和NVMeSSD之间直接的数据传输，而若目标NVMeSSD故障，则主机92需将该读数据指令发送至存储阵列卡，以便存储阵列卡接收并校验目标NVMeSSD中与读数据指令对应的数据，将校验后的与读数据指令对应的数据发送至主机92中，保证传输的数据的完整性。
需要说明的是，当主机92的读数据指令和写数据指令在写入硬盘控制映射地址或发送至存储阵列卡时，均需拆分为对目标NVMeSSD的读数据指令或写数据指令。
请参照图8，图8为本申请提供的一种数据传输系统的结构示意图，该系统应用于数据传输装置中的主机92，数据传输装置包括依次连接的主机92、存储阵列卡31以及NVMeSSD，主机92与存储阵列卡31之间以及存储阵列卡31与NVMeSSD之间通过PCIe总线连接；存储阵列卡31包括地址映射逻辑，NVMeSSD将自身的控制地址空间通过存储阵列卡31的地址映射逻辑映射至存储阵列卡31，映射后的控制地址空间为硬盘控制映射地址；该系统包括：
地址转换单元81，用于将自身的存储地址空间通过存储阵列卡的地址映射逻辑映射至存储阵列卡，映射后的存储地址空间为主机存储映射地址；
指令发送单元82，用于通过存储阵列卡中的硬盘控制映射地址向NVMeSSD发送数据传输指令，以使NVMeSSD基于数据传输指令和存储阵列卡中的主机存储映射地址进行数据传输。
对于本申请一些实施例提供的一种数据传输系统的介绍请参照上述方法实施例，本申请在此不再赘述。
请参照图9，图9为本申请提供的一种数据传输装置的结构示意图，该装置包括：
存储器91，用于存储计算机程序；
主机92，用于执行计算机程序时实现如上述数据传输方法的步骤。
在一些实施例中，还包括：与主机92通过PCIe总线连接的存储阵列卡31，用于接收主机92的主机存储映射地址和NVMeSSD的硬盘控制映射地址；
与存储阵列卡31通过PCIe总线连接的NVMeSSD，用于存储数据，并基于存储阵列卡31中的主机存储映射地址与主机92进行数据传输。
在一些实施例中，存储阵列卡31包括地址映射逻辑，具体用于通过地址映射逻辑接收主机92映射的存储地址空间，并通过地址映射逻辑接收NVMeSSD映射的控制地址空间。
在一些实施例中，存储阵列卡31还包括中断映射逻辑，还用于通过中断映射逻辑接收主机92的中断信号地址空间。
在一些实施例中，存储阵列卡31中还包括硬盘控制逻辑，用于在接收到主机92建立的I/O队列后，为NVMeSSD建立管理命令队列，以使NVMeSSD基于管理命令队列从I/O队列中获取与数据传输指令对应的数据传输命令，或基于管理命令队列对I/O队列进行使能。
在一些实施例中，I/O队列包括命令完成队列和命令提交队列；
NVMeSSD具体用于存储数据，并基于管理命令队列从命令提交队列中获取与数据传输指令对应的数据传输命令，或基于管理命令队列对命令完成队列进行使能，以与主机92进行数据传输。
可见，在一些实施例中的存储阵列卡31中包括地址映射逻辑、中断映射逻辑和硬盘控制逻辑，不仅能够实现主机92和NVMeSSD的存储地址空间之间的直接数据交互，还可使主机92和NVMeSSD之间直接进行数据传输指令、数据传输命令以及中断信号的传输，提高了数据传输的效率。
对于本申请提供的一种数据传输装置的具体介绍请参照上述方法实施例，本申请在此不再赘述。
本申请中的非易失性可读存储介质上存储有计算机程序，计算机程序被主机52执行时实现如上述的数据传输方法的步骤。
对于本申请提供的非易失性可读存储介质的介绍请参照上述方法实施例，本申请在此不再赘述。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括 要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种数据传输方法，其特征在于，应用于数据传输装置中的主机，所述方法包括：
    与所述数据传输装置中的存储阵列卡之间通过PCIe总线进行数据交换；其中，所述存储阵列卡包括地址映射逻辑；
    通过所述存储阵列卡与所述数据传输装置中的NVMeSSD之间通过PCIe总线进行数据交换；
    通过所述NVMeSSD将所述NVMeSSD自身的控制地址空间通过所述存储阵列卡的所述地址映射逻辑映射至所述存储阵列卡，并将映射后的所述控制地址空间作为硬盘控制映射地址；
    将自身的存储地址空间通过所述存储阵列卡的地址映射逻辑映射至所述存储阵列卡，映射后的所述存储地址空间为主机存储映射地址；
    通过所述存储阵列卡中的所述硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输。
  2. 如权利要求1所述的方法，其特征在于，所述数据传输指令的地址指针指向所述主机通过所述地址映射逻辑进行映射后的所述主机存储映射地址。
  3. 如权利要求1所述的数据传输方法，其特征在于，所述存储阵列卡还包括中断映射逻辑；
    通过所述存储阵列卡中的所述硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
    将自身的中断信号地址空间通过所述存储阵列卡的中断映射逻辑映射至所述存储阵列卡，映射后的所述中断信号地址空间为主机中断信号映射地址；
    通过所述存储阵列卡中的所述硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输之后，还包括：
    在所述NVMeSSD通过所述中断映射逻辑向所述主机中断信号映射地址中写入中断信号后处理所述中断信号。
  4. 如权利要求3所述的数据传输方法，其特征在于，通过所述存储阵列卡中的所述硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
    建立I/O队列，并将所述I/O队列的基地址通过所述存储阵列卡的所述地址映射逻辑映射至所述存储阵列卡；
    通过所述硬盘控制映射地址向所述NVMeSSD发送所述数据传输指令，以使所述NVMeSSD从所述I/O队列中获取与所述数据传输指令对应的数据传输命令，并和所述数据传输命令对应的所述主机存储映射地址传输与所述数据传输命令对应的数据；
    在所述NVMeSSD通过所述中断映射逻辑向所述主机中断信号映射地址中写入中断信号后处理所述中断信号，包括：
    在所述NVMeSSD使能所述I/O队列，并通过所述中断映射逻辑向所述主机中断信 号映射地址中写入中断信号时处理所述中断信号。
  5. 如权利要求4所述的方法，其特征在于，所述建立I/O队列的步骤，包括：
    针对同一所述NVMeSSD，所述主机建立至少一个I/O队列；其中，所述NVMeSSD的I/O队列的总个数不大于所述存储阵列卡本地I/O队列和为所述主机预留的I/O队列个数。
  6. 如权利要求4所述的数据传输方法，其特征在于，所述I/O队列包括命令完成队列和命令提交队列；
    通过所述硬盘控制映射地址向所述NVMeSSD发送所述数据传输指令，以使所述NVMeSSD从所述I/O队列中获取与所述数据传输指令对应的数据传输命令，并和所述数据传输命令对应的所述主机存储映射地址传输与所述数据传输命令对应的数据，包括：
    通过所述硬盘控制映射地址向所述NVMeSSD发送所述数据传输指令，以使所述NVMeSSD从所述命令提交队列中获取与所述数据传输指令对应的数据传输命令，并和所述数据传输命令对应的所述主机存储映射地址传输与所述数据传输命令对应的数据；
    在所述NVMeSSD使能所述I/O队列，并通过所述中断映射逻辑向所述主机中断信号映射地址中写入中断信号时处理所述中断信号，包括：
    在所述NVMeSSD使能所述命令完成队列，并通过所述中断映射逻辑向所述主机中断信号映射地址中写入中断信号时处理所述中断信号。
  7. 如权利要求6所述的数据传输方法，其特征在于，通过所述硬盘控制映射地址向所述NVMeSSD发送所述数据传输指令，以使所述NVMeSSD从所述命令提交队列中获取与所述数据传输指令对应的数据传输命令，并和所述数据传输命令对应的所述主机存储映射地址传输与所述数据传输命令对应的数据之前，还包括：
    将各个所述数据传输命令写入所述命令提交队列中。
  8. 如权利要求6或7所述的数据传输方法，其特征在于，所述数据传输命令中包括待传输的数据、以及所述主机和所述NVMeSSD中待进行数据传输的地址。
  9. 如权利要求4所述的数据传输方法，其特征在于，所述存储阵列卡还包括硬盘控制逻辑，用于基于所述I/O队列为所述NVMeSSD建立管理命令队列；
    通过所述硬盘控制映射地址向所述NVMeSSD发送所述数据传输指令，以使所述NVMeSSD从所述I/O队列中获取与所述数据传输指令对应的数据传输命令，并和所述数据传输命令对应的所述主机存储映射地址传输与所述数据传输命令对应的数据，包括：
    在所述存储阵列卡为所述NVMeSSD建立所述管理命令队列后，通过所述硬盘控制映射地址向所述NVMeSSD发送所述数据传输指令，以使所述NVMeSSD基于所述管理命令队列从所述I/O队列中获取与所述数据传输指令对应的数据传输命令，并和所述数据传输命令对应的所述主机存储映射地址传输与所述数据传输命令对应的数据；
    在所述NVMeSSD使能所述I/O队列，并通过所述中断映射逻辑向所述主机中断信号映射地址中写入中断信号时处理所述中断信号，包括：
    在所述存储阵列卡为所述NVMeSSD建立所述管理命令队列后，在所述NVMeSSD通过所述管理命令队列使能所述I/O队列，并通过所述中断映射逻辑向所述主机中断信号映射地址中写入中断信号时处理所述中断信号。
  10. 如权利要求9所述的方法，其特征在于，所述存储阵列卡中所述NVMeSSD的所述管理命令队列为一个。
  11. 如权利要求1所述的数据传输方法，其特征在于，通过所述存储阵列卡中的所述硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
    当所述数据传输指令为写数据指令时，判断与所述写数据指令对应的数据是否为待校验数据；
    若判断与所述写数据指令对应的数据为待校验数据，则将所述写数据指令发送至所述存储阵列卡，以使所述存储阵列卡接收并校验所述主机中与所述写数据指令对应的数据，将校验后的与所述写数据指令对应的数据写入至所述NVMeSSD中；
    若判断与所述写数据指令对应的数据不为待校验数据，则进入通过所述存储阵列卡中的硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输的步骤。
  12. 如权利要求11所述的方法，其特征在于，所述进入通过所述存储阵列卡中的硬盘控制映射地址向所述NVMeSSD发送数据传输指令的步骤，包括：
    将所述写数据指令写入所述NVMeSSD的硬盘控制映射地址。
  13. 如权利要求1-12任一项所述的数据传输方法，其特征在于，所述数据传输装置包括多个NVMeSSD与所述存储阵列卡连接；
    通过所述存储阵列卡中的硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输之前，还包括：
    当所述数据传输指令为读数据指令时，判断与所述读数据指令对应的数据是否为待校验数据；
    若为所述待校验数据，则判断与所述存储阵列卡连接的各个所述NVMeSSD是否均处于正常状态；
    若不为所述待校验数据，或各个所述NVMeSSD均处于正常状态，则通过所述存储阵列卡中的硬盘控制映射地址向目标NVMeSSD发送所述读数据指令，以使所述目标NVMeSSD将与所述读数据指令对应的数据写入所述存储阵列卡中的主机存储映射地址；
    若各个所述NVMeSSD并非均处于所述正常状态，则判断所述目标NVMeSSD是否处于正常状态；
    若所述目标NVMeSSD处于正常状态，则通过所述存储阵列卡中的所述硬盘控制映射地址向所述目标NVMeSSD发送所述读数据指令，以使所述目标NVMeSSD将与所述读数据指令对应的数据写入所述存储阵列卡中的主机存储映射地址；
    若所述目标NVMeSSD未处于所述正常状态，则将所述读数据指令发送至所述存储阵列卡，以使所述存储阵列卡接收并校验所述目标NVMeSSD中与所述读数据指令对应的数据，将校验后的与所述读数据指令对应的数据发送至所述主机中。
  14. 如权利要求13所述的方法，其特征在于，所述通过所述存储阵列卡中的硬盘控制映射地址向目标NVMeSSD发送所述读数据指令的步骤，包括：
    将所述读数据指令写入所述硬盘控制映射地址。
  15. 如权利要求1所述的方法，其特征在于，所述存储阵列卡挂载有多个所述NVMeSSD。
  16. 如权利要求15所述的方法，其特征在于，所述NVMeSSD通过以下方法挂载至 所述存储阵列卡：
    所述存储阵列卡初始化配置与所述NVMeSSD连接的PCIe总线；
    所述存储阵列卡扫描自身挂载的至少一个所述NVMeSSD；
    所述存储阵列卡分别为所述NVMeSSD进行基地址寄存器空间映射，以将所述NVMeSSD的控制地址空间通过所述存储阵列卡自身的地址映射逻辑映射至所述存储阵列卡自身，生成所述NVMeSSD的硬盘控制映射地址。
  17. 如权利要求15所述的方法，其特征在于，所述存储阵列卡通过PCIe根复合体控制器与所述NVMeSSD连接。
  18. 一种数据传输系统，其特征在于，应用于数据传输装置中的主机，所述数据传输装置包括依次连接的所述主机、存储阵列卡以及NVMeSSD，所述主机与所述存储阵列卡之间以及所述存储阵列卡与所述NVMeSSD之间通过PCIe总线连接；所述存储阵列卡包括地址映射逻辑，所述NVMeSSD将自身的控制地址空间通过所述存储阵列卡的所述地址映射逻辑映射至所述存储阵列卡，映射后的所述控制地址空间为硬盘控制映射地址；所述系统包括：
    地址转换单元，用于将自身的存储地址空间通过所述存储阵列卡的地址映射逻辑映射至所述存储阵列卡，映射后的所述存储地址空间为主机存储映射地址；
    指令发送单元，用于通过所述存储阵列卡中的硬盘控制映射地址向所述NVMeSSD发送数据传输指令，以使所述NVMeSSD基于所述数据传输指令和所述存储阵列卡中的主机存储映射地址进行数据传输。
  19. 一种电子设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    主机，用于执行所述计算机程序时实现如权利要求1至17任一项所述数据传输方法的步骤。
  20. 一种非易失性可读存储介质，其特征在于，所述非易失性可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至17任一项所述的数据传输方法的步骤。
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