WO2024000301A1 - 显示基板、其制作方法及显示装置 - Google Patents

显示基板、其制作方法及显示装置 Download PDF

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Publication number
WO2024000301A1
WO2024000301A1 PCT/CN2022/102459 CN2022102459W WO2024000301A1 WO 2024000301 A1 WO2024000301 A1 WO 2024000301A1 CN 2022102459 W CN2022102459 W CN 2022102459W WO 2024000301 A1 WO2024000301 A1 WO 2024000301A1
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WIPO (PCT)
Prior art keywords
electrode
layer
base substrate
pattern layer
orthographic projection
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PCT/CN2022/102459
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English (en)
French (fr)
Inventor
陈麒
高玉杰
吴伟
张昊
仝远
周逸琛
张荡
张伊伊
刘翔
朱陶和
代俊锋
李金力
黄波
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001980.XA priority Critical patent/CN117642689A/zh
Priority to PCT/CN2022/102459 priority patent/WO2024000301A1/zh
Publication of WO2024000301A1 publication Critical patent/WO2024000301A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • Liquid crystal display (Liquid Crystal Display, LCD) has the advantages of light weight, low power consumption, high image quality, low radiation and easy portability. It has gradually replaced the traditional cathode ray tube display (CRT). It is widely used in modern information equipment, such as virtual reality (VR) head-mounted display devices, laptops, TVs, mobile phones and digital products.
  • VR virtual reality
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • the specific solutions are as follows:
  • an embodiment of the present disclosure provides a display substrate, including:
  • An alignment layer located on the base substrate
  • a first electrode located between the base substrate and the alignment layer and in contact with the alignment layer;
  • a pattern layer located between the base substrate and the alignment layer and in contact with the alignment layer, the orthogonal projection of the pattern layer on the base substrate being the same as the first electrode on the base substrate Orthographic projections on do not overlap with each other, and the ratio of the contact angle of the pattern layer to the contact angle of the first electrode is greater than or equal to 7/12 and less than 3/2.
  • the pattern layer and the first electrode are provided in the same layer and with the same material.
  • the display substrate provided by the embodiment of the present disclosure, there are a plurality of first electrodes, and the plurality of first electrodes are arranged in an array on the base substrate;
  • the orthographic projection of the pattern layer on the base substrate is located within the orthographic projection of the row gap of each first electrode on the base substrate.
  • the first electrode includes a first strip-shaped electrode and a second strip-shaped electrode arranged integrally, and the extension direction of the first strip-shaped electrode is in line with the The row direction, the column direction, and the extension direction of the second strip-shaped electrode are all intersecting, and the extension direction of the second strip-shaped electrode is intersecting with the row direction and the column direction;
  • the pattern layer extends along the extension direction of the first strip electrode and/or the extension direction of the second strip electrode.
  • the extending directions of the pattern layers at two adjacent row gaps are different.
  • the line width of the pattern layer is the same as the line width of the first strip electrode or the second strip electrode in the same extension direction
  • the line spacing of the pattern layer is the same as the line spacing of the first strip electrode or the second strip electrode in the same extending direction
  • the pattern layer includes a plurality of block patterns spaced at intervals in the same row of each of the first electrodes, and the block patterns Extend along the row direction.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a first signal line, and the orthographic projection of the first signal line on the base substrate is located in the column of each of the first electrodes.
  • the gap is within the orthographic projection of the base substrate;
  • the orthographic projection of the pattern layer on the base substrate and the orthographic projection of the first signal line on the base substrate do not overlap with each other.
  • the above display substrate provided by the embodiment of the present disclosure further includes a transistor, and at least part of the first signal line is electrically connected to the transistor;
  • the orthographic projection of the pattern layer on the base substrate and the orthographic projection of the transistor on the base substrate do not overlap with each other.
  • the pattern layer includes a strip pattern extending along the row direction at the row gap of each of the first electrodes, and the strip pattern extends in the row direction.
  • the upward length is the same as the length of the row gap of each first electrode.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a second signal line, and the orthographic projection of the second signal line on the base substrate is located in the row of each of the first electrodes.
  • the gap is within the orthographic projection of the base substrate;
  • the orthographic projection of the pattern layer on the base substrate is located within the orthographic projection of the second signal line on the base substrate.
  • the ratio of the width of the pattern layer in the column direction to the width of the second signal line in the column direction is greater than or equal to 3/5 and less than equal to 1.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a second signal line, and the orthographic projection of the second signal line on the base substrate is located in the row of each of the first electrodes.
  • the gap is within the orthographic projection on the base substrate, and two second signal lines are correspondingly provided at the gaps in the same row of each of the first electrodes;
  • the orthographic projection of the two second signal lines on the base substrate is located within the orthographic projection of the pattern layer on the base substrate.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes first signal lines and second signal lines that are intersectingly arranged and insulated from each other, wherein the first signal lines are on the substrate substrate.
  • the orthographic projection on the substrate is located in the orthographic projection of the column gap of each first electrode on the base substrate.
  • the first signal line includes the column gap of each first electrode and two second second Island-like structure at the intersection location of signal lines;
  • the orthographic projection of the pattern layer on the base substrate coincides with the orthographic projection of the island structure on the base substrate.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a second signal line and a gate electrode.
  • the second signal line and the gate electrode are in an integral structure and the gate electrode is relative to the gate electrode.
  • the pattern layer includes a plurality of first sub-sections intersecting the row direction and the column direction, and a second sub-section extending along the row direction.
  • the orthographic projection of the first sub-section on the base substrate is located at The gate is within the orthographic projection on the base substrate, and the orthographic projection of the second branch on the base substrate is located within the orthographic projection of the second signal line on the base substrate. .
  • the above display substrate provided by the embodiment of the present disclosure further includes a second electrode located between the layer where the first electrode is located and the substrate substrate, and the first electrode is located on the substrate.
  • the orthographic projection on the base substrate overlaps with the orthographic projection of the second electrode on the base substrate.
  • the above display substrate provided by the embodiment of the present disclosure further includes an insulating layer between the layer where the first electrode is located and the layer where the second electrode is located, and the first electrode shielding part is The insulating layer, which is not blocked by the first electrode, is reused as the pattern layer.
  • the alignment layer includes a station area for setting spacers, and the orthographic projection of the station area on the base substrate is located at The pattern layer is within an orthographic projection on the base substrate.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned display substrate, including:
  • a pattern layer and a first electrode are formed on the base substrate, wherein the orthographic projection of the pattern layer on the base substrate and the orthographic projection of the first electrode on the base substrate do not intersect with each other. Stacked, the ratio of the contact angle of the pattern layer to the contact angle of the first electrode is greater than or equal to 7/12 and less than or equal to 3/2;
  • the alignment liquid is solidified to form an alignment layer.
  • forming a pattern layer and a first electrode on the base substrate specifically includes:
  • a pattern layer and a first electrode of the same layer and material are formed on the base substrate.
  • the same mask is used to form the pattern layer and the first electrode of the same layer and the same material on the base substrate, specifically including:
  • the pattern of the mask is offset relative to the area where the first electrode is to be made, so that the pattern of the mask is mutually exclusive with the area where the first electrode is to be made and the area where the pattern layer is to be made. overlap;
  • the photoresist layer in the area where the first electrode is to be produced and the photoresist layer in the area where the pattern layer is to be produced are exposed in a time-divided manner;
  • the conductive layer is etched to form the pattern layer and the first electrode of the same layer, same material, and separated.
  • the same mask is used to form the pattern layer and the first electrode of the same layer and the same material on the base substrate, specifically including:
  • a mask having a first pattern for making a first electrode and a second pattern for making a pattern layer, the first pattern being disconnected from the second pattern;
  • the photoresist layer in the area where the first electrode is to be made and the photoresist layer in the area where the pattern layer is to be made are simultaneously exposed;
  • the conductive layer is etched to form the pattern layer and the first electrode of the same layer, same material, and separated.
  • forming a pattern layer and the first electrode on the base substrate specifically includes:
  • ammonia and silane as reaction source gases to form an insulating layer arranged on the entire surface.
  • the flow ratio of ammonia to silane is greater than or equal to 2 and less than or equal to 8;
  • a first electrode is formed on the insulating layer in the pixel opening area of the base substrate, and the insulating layer outside the pixel opening area is reused as a pattern layer.
  • an embodiment of the present disclosure provides a display device, including the above display substrate provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of the breakage and aggregation of the wet film formed by the alignment liquid in the related art
  • Figure 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • Figure 3 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of the accumulation of wet film formed by the alignment liquid due to the overlapping of the first electrode and the pattern layer;
  • Figure 5 is a flow chart of contact angle testing provided by an embodiment of the present disclosure.
  • Figure 6 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 7 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 8 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 9 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 10 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 11 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 12 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 13 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic structural diagram of a transistor in a display substrate provided by an embodiment of the present disclosure.
  • Figure 15 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 16 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of the uneven box thickness caused by the aggregation of the alignment layer
  • Figure 18 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 19 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 20 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 21 is a schematic diagram of a pixel structure of a display substrate provided by an embodiment of the present disclosure.
  • Figure 22 is a schematic structural diagram of the second signal line and the gate of the transistor in Figure 21;
  • Figure 23 is a schematic structural diagram of the third signal line and the second electrode in Figure 21;
  • Figure 24 is a schematic structural diagram of the first signal line, the first pole, the second pole, the connecting electrode and the limiting structure of the transistor in Figure 21;
  • Figure 25 is a schematic structural diagram of the first electrode, the first transfer electrode and the pattern layer in Figure 21;
  • Figure 26 is a schematic structural diagram of the connecting electrode connected to the second electrode through the first transfer electrode
  • Figure 27 is a schematic diagram of another pixel structure of a display substrate provided by an embodiment of the present disclosure.
  • Figure 28 is a schematic diagram of the stacking of the first electrode and the second electrode in Figure 27;
  • Figure 29 is a schematic structural diagram of the first electrode in Figure 27;
  • Figure 30 is a schematic structural diagram of the second signal line, the gate of the transistor and the third signal line in Figure 27;
  • Figure 31 is a schematic structural diagram of the first signal line and the first pole and the second pole of the transistor in Figure 27;
  • Figure 32 is a schematic structural diagram of the second electrode, the second transfer electrode and the pattern layer in Figure 27;
  • Figure 33 is a schematic diagram of another pixel structure of a display substrate provided by an embodiment of the present disclosure.
  • Figure 34 is a schematic structural diagram of the second signal line and the gate of the transistor in Figure 33;
  • Figure 35 is a schematic structural diagram of the first signal line and the first pole and the second pole of the transistor in Figure 33;
  • Figure 36 is a schematic structural diagram of the first electrode and pattern layer in Figure 33;
  • FIG. 37 is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • the liquid crystal display device repeatedly detected lump-like stains under the L127 gray scale, affecting the display effect. After screen disassembly and analysis, it was found that there is aggregation of the alignment layer (PI) in the area where the lump stains occur, and the more severe the lump stains, the higher the accumulation of the alignment layer.
  • PI alignment layer
  • the manufacturing process of the alignment layer mainly includes two steps: first, through coating (Inkjet) equipment, the alignment droplets are spread on the surface of the display substrate to form a wet film 102'; second, in the pre-curing (Pre-Cure) Heating in the equipment causes the solvent of the wet film 102' to evaporate and form an alignment layer.
  • the contact angle of the display substrate plays a decisive role. It is generally believed that the smaller the interfacial tension between solid and liquid, the smaller the contact angle, the better the wetting degree of the liquid on the solid, and the less likely it is for the liquid and solid to separate; the larger the interfacial tension between solid and liquid, the larger the contact angle. , the worse the wetting degree of the liquid on the solid, the easier it is for the liquid and solid to separate.
  • the film layer under the alignment layer that is in contact with the alignment layer includes a first electrode located in the pixel opening area and an insulating layer located in the non-pixel opening area, such as an insulating layer corresponding to the gate line of the display panel, where the first electrode
  • the contact angle of the insulating layer is 60°
  • the contact angle of the insulating layer is 20° to 30°. It can be seen that the contact angle of the insulating layer is 1/3 to 1/2 of the contact angle of the first electrode. The difference in contact angle between the two is too large.
  • the interfacial tension between the alignment liquid and the first electrode is much greater than the interfacial tension between the alignment liquid and the insulating layer, so the first electrode and the insulating layer form a "pull effect" on the alignment liquid, causing the diffusion of the alignment liquid into The wet film 102' breaks and gathers, as shown in Figure 1.
  • a smaller contact angle is beneficial to the wetting and diffusion of the alignment liquid, the solvent evaporation rate is inconsistent during the pre-curing process.
  • the alignment liquid is not easy to transfer on an interface with good wettability, and is prone to breakage, shrinkage and accumulation. Therefore, poor stacking of the alignment layer occurs on the insulating layer with a small contact angle.
  • a display substrate as shown in Figures 2 and 3, including:
  • Alignment layer 102 is located on the base substrate 101;
  • the first electrode 103 is located between the base substrate 101 and the alignment layer 102 and is in contact with the alignment layer 102;
  • the pattern layer 104 is located between the base substrate 101 and the alignment layer 102 and is in contact with the alignment layer 102.
  • the orthographic projection of the pattern layer 104 on the base substrate 101 is different from the orthographic projection of the first electrode 103 on the base substrate 101. Overlapping, the ratio of the contact angle of the pattern layer 104 to the contact angle of the first electrode 103 is greater than or equal to 7/12 and less than 3/2.
  • the staggered pattern layer 104 and the first electrode 103 are both in contact with the alignment layer 102, which is equivalent to the alignment liquid being coated on the surfaces of the pattern layer 104 and the first electrode 103.
  • the present disclosure sets the ratio of the contact angle of the pattern layer 104 to the contact angle of the first electrode 103 to be greater than or equal to 7/12 and less than 3/2.
  • the contact angle of the first electrode 103 is 60°
  • the contact angle of the pattern layer 104 is greater than or equal to 7/12 and less than 3/2. Equal to 35° and less than 90°, so that the difference between the contact angle of the pattern layer 104 and the contact angle of the first electrode 103 is small.
  • the interfacial tension between the alignment liquid and the first electrode 103 is different from the interfacial tension between the alignment liquid and the pattern layer 104.
  • the difference in interfacial tension between them is small, thereby effectively weakening the "pull effect" of the first electrode 103 and the pattern layer 104 on the alignment liquid, and reducing the risk of breakage and aggregation of the wet film 102' formed by the diffusion of the alignment liquid.
  • the contact angle of the insulating layer before improvement is greater than or equal to 1/3 of the contact angle of the first electrode 103 and less than or equal to 1/2 of the contact angle of the first electrode 103.
  • the contact angle of the pattern layer 104 is greater than or equal to the first
  • the contact angle of the electrode 103 is 7/12 and less than 3/2 of the contact angle of the first electrode 103.
  • the contact angle of the pattern layer 104 of the present disclosure is greater than the contact angle of the insulating layer before improvement. It can be seen that the greater the contact angle, the worse the wettability.
  • the wettability of the alignment liquid on the pattern layer 104 is slightly worse than the wettability of the alignment liquid on the insulating layer before improvement.
  • the alignment liquid is not easy to transfer on the interface with good wettability and is prone to breakage, shrinkage and accumulation
  • the alignment liquid is more likely to transfer on the pattern layer 104 with poor wettability and is less likely to cause breakage and shrinkage. and accumulation.
  • the present disclosure can significantly improve the aggregation phenomenon of the alignment layer 102 and improve the display effect.
  • the pattern layer 104 may change the first electrode.
  • the interface resistance at the first via V 1 affects signal transmission and display quality.
  • the orthographic projection of the pattern layer 104 on the base substrate 101 and the orthographic projection of the first electrode 103 on the base substrate 101 are set to not overlap each other, so that the pattern layer 104 and the first electrode 103 are disconnected to avoid The pattern layer 104 and the first electrode 103 are overlapped together. Therefore, the pattern layer 104 will not affect signal transmission and display quality, and at the same time, the alignment layer 102 is prevented from gathering at the overlap position N.
  • the contact angle can be tested by the method shown in FIG. 5 .
  • the specific process is: dropping a preset volume (for example, 1 ⁇ L) of hydrophilic droplets 1 (for example, 1 ⁇ L) on the pattern layer 104 or the first electrode 103 . deionized water), the liquid droplet 1 begins to expand on the pattern layer 104 or the first electrode 103, wait until the liquid droplet 1 stops expanding, take pictures of the liquid droplet 1 and the pattern layer 104 or the first electrode 103, and measure
  • the included angle ⁇ between the droplet-air interface (l-g) and the droplet-solid interface (l-s) in the photographed picture is the contact angle of the pattern layer 104 or the first electrode 103.
  • the present disclosure conducted an adhesion measurement experiment of the alignment layer 102 on the first electrode 103 and the insulating layer.
  • the specific method is to use an eraser to wipe the alignment layer 102 with the same strength, and then observe the remaining alignment layer 102 under a microscope. It is found that after wiping, compared with the alignment layer 102 remaining on the insulating layer, the alignment layer 102 on the first electrode 103 is The remaining alignment layer 102 is more complete, which indicates that the alignment layer 102 and the first electrode 103 are more closely combined.
  • the present disclosure found that the surface roughness of the first electrode 103 is small, and the alignment layer 102 does not aggregate on the first electrode 103 . Therefore, as shown in FIG. 3 , in the above-mentioned display substrate provided by the embodiment of the present disclosure, the pattern layer 104 and the first electrode 103 can be arranged in the same layer and with the same material. This not only enables the alignment layer 102 and the pattern layer 104 to be closely combined , it can also ensure that the alignment layer 102 does not aggregate on the pattern layer 104.
  • the display substrate provided by the embodiment of the present disclosure, as shown in FIGS. 6 to 8 , there are a plurality of first electrodes 103 , and the plurality of first electrodes 103 are arranged in an array on the base substrate 101 . cloth; the orthographic projection of the pattern layer 104 on the base substrate 101 is located within the orthographic projection of the row gap of each first electrode 103 on the base substrate 101.
  • a black matrix (BM) blocking the row gaps of each first electrode 103 is provided on the counter substrate opposite to the display substrate.
  • the orthographic projection of the pattern layer 104 on the base substrate 101 is located at When the row gaps of each first electrode 103 are within the orthographic projection on the base substrate 101, the pattern layer 104 will be blocked by the black matrix, and no light leakage failure will occur. Moreover, since the area where the black matrix is located does not display the image, the pattern layer 104 will not affect the display effect.
  • the first electrode 103 includes an integrally arranged first strip electrode 31 and a second strip electrode. 32.
  • the extension direction D 1 of the first strip electrode 31 intersects the row direction X, the column direction Y, and the extension direction D 2 of the second strip electrode 32 .
  • the extension direction D 2 of the second strip electrode 32 intersects with The row direction
  • the pattern layer 104 at each row gap of the first electrode 103 extends along the extension direction D 1 of the first strip electrode 31 .
  • the pattern layer 104 at each row gap of each first electrode 103 extends along the extension direction D 1 of the first strip electrode 31 .
  • the extension direction D2 of the second strip electrode 32 extends.
  • the extension directions of the pattern layers 104 at two adjacent row gaps of each first electrode 103 are different, that is, the pattern layers at two adjacent row gaps are different.
  • the extension direction of 104 is the same as the extension direction D 1 of the first strip electrode 31 and the extension direction D 2 of the second strip electrode 32 respectively.
  • the morphology of the pattern layer 104 can be similar to the local morphology of the first electrode 103, which is conducive to forming a more uniform alignment layer 104 on the first electrode 103 and the pattern layer 104.
  • the schematic diagram in Figure 6 The first strip electrode 31 and the second strip electrode 32 can refer to Figure 21 and Figure 25.
  • FIG 21 and Figure 25 they are strip electrodes formed by opening slits on the plate electrode; or Figure 6
  • the first strip electrode 31 and the second strip electrode 32 illustrated in can also refer to Figure 27, Figure 32, Figure 33 and Figure 36.
  • Figure 27, Figure 32, Figure 33 and Figure 36 multiple strip electrodes are directly formed. electrically connected strip electrodes, wherein the strip electrodes shown in Figures 27 and 32 are dual-domain electrodes and the included angle of the domain-directed electrodes is an obtuse angle. In some embodiments, the included angle of the domain-directed electrodes can also be an acute angle. ;
  • the strip electrodes shown in Figures 33 and 36 are single domain electrodes.
  • the pattern layer 104 can be produced using a mask for producing the first electrode 103 in the related art.
  • the mask for making the first electrodes 103 can be moved along the A direction in FIG. 6 to the row gaps of each first electrode 103, and the light source can be controlled to illuminate only the partial mask corresponding to the row gaps of the first electrodes 103.
  • the light source illuminates the entire mask, the mask corresponding to the first electrode 103 is blocked, so that only the row gaps of the first electrodes 103 are exposed and developed, so that the mask is produced at the row gaps of each first electrode 103.
  • the pattern layer 104 has an extension direction equal to the extension direction D1 of the first strip electrode 31 .
  • the mask for making the first electrodes 103 when the mask for making the first electrodes 103 is moved along the A' direction in FIG. 7 to the row gaps of each first electrode 103, an extended mask can be made at the row gaps of each first electrode 103.
  • the pattern layer 104 is oriented in a direction consistent with the extending direction D2 of the second strip electrode 32 .
  • the mask for making the first electrodes 103 can also be moved along the A direction in FIG. 8 to the row gaps of each first electrode 103, and the light source can be controlled to illuminate only the parts corresponding to the odd-numbered row gaps of the first electrodes 103.
  • Partial mask or when the light source illuminates the entire mask, the mask corresponding to the first electrode 103 and the partial mask corresponding to the even-numbered row gaps are blocked to achieve only the odd-numbered row gaps. Exposure and development are performed to produce a pattern layer 104 whose extension direction is equal to the extension direction D1 of the first strip electrode 31 at the odd-numbered row gap; the pattern layer 104 of the first electrode 103 can also be produced by moving along the A' direction in FIG.
  • the mask corresponding to the first electrode 103 and the partial mask corresponding to the odd-numbered row gaps realize that only the even-numbered row gaps are exposed and developed, thereby creating a pattern with the extension direction and the third row gap at the even-numbered row gaps.
  • the extension direction of the two strip-shaped electrodes 32 is D2 of the pattern layer 104, so that the extension directions of the pattern layer 104 at the gaps between two adjacent rows are different.
  • the line width of the pattern layer 104 is the same as the line width of the first strip electrode 31 or the second strip electrode 32 in the same extending direction, and the line spacing of the pattern layer 104 is the same as that of the first strip electrode 31 or the second strip electrode 32 .
  • the line spacing of the first strip electrode 31 or the second strip electrode 32 with the same extension direction is the same, that is, the morphology of the pattern layer 104 is the same as the local morphology of the first electrode 103, which is more conducive to the connection between the first electrode 103 and the pattern layer.
  • An alignment layer 102 with better uniformity is formed on 104.
  • the pattern layer 104 includes a plurality of block patterns 41 spaced at intervals in the same row gap of each first electrode 103, and The block pattern 41 extends in the row direction X.
  • the structure of the pattern layer 104 composed of the block patterns 41 is relatively simple, and the corresponding manufacturing difficulty is relatively low.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may also include a first signal line 105.
  • the first signal line 105 is located on the substrate.
  • the first signal lines 105 may all be data lines V data , or may include data lines V data and common electrode lines.
  • V com may also include touch signal lines, etc., which are not limited here.
  • the orthographic projection of the first signal line 105 on the base substrate 101 is located within the orthographic projection of the column gap of each first electrode 103 on the base substrate 101; the orthographic projection of the pattern layer 104 on the base substrate 101 is consistent with the first signal
  • the orthographic projections of the lines 105 on the base substrate 101 do not overlap with each other. Since the material of the first electrode 103 is a conductive material, the pattern layer 104 made of the same layer and material as the first electrode 103 also has conductivity. If the pattern layer 104 and the first signal line 105 overlap each other, a parasitic capacitance will be formed between them, causing the pattern layer 104 to interfere with the signal of the first signal line 105 .
  • the present disclosure sets the orthographic projection of the pattern layer 104 on the base substrate 101 and the orthographic projection of the first signal line 105 on the base substrate 101 to not overlap with each other. .
  • the above display substrate provided by the embodiment of the present disclosure may also include a transistor 107, and at least part of the first signal line 105 is electrically connected to the transistor 107.
  • the first signal line 105 is all the data line V data
  • the first signal line 105 is electrically connected to the transistor 107;
  • the first signal line 105 includes the data line V data and the common electrode line V com
  • the first signal line 105 is electrically connected to the transistor 107.
  • the data line V data in the signal line 105 is electrically connected to the transistor 107 .
  • the data line V data and the first electrode of the transistor 107 to which it is electrically connected may be formed through one patterning process.
  • the first electrode of the transistor 107 may be a source electrode or a drain electrode.
  • the orthographic projection of the pattern layer 104 on the substrate 101 and the transistor 107 can be set on the substrate. The orthographic projections on the base substrate 101 do not overlap with each other.
  • the orthographic projections of the pattern layer 104 on the base substrate 101 and the orthographic projections of the transistors 107 on the base substrate 101 can also be arranged to overlap with each other; in another example, in some embodiments, as shown in FIG. 13 , the pattern layer 104 includes a strip pattern 42 extending along the row direction X at the row gap. The length of the strip pattern 42 in the row direction X is the same as the length of the row gap.
  • the orthographic projection of the pattern layer 104 on the base substrate 101, the orthographic projection of the first signal line 105 on the base substrate 101, and the orthographic projection on the base substrate 101 may overlap with each other.
  • the pattern layer 104 is composed of multiple strip structures 42 extending at the row gaps. The structure is simpler and the corresponding manufacturing difficulty is smaller.
  • the strip patterns 42 extend in the row direction. The length in X is different from the length of the row gap. For example, the extension direction of the stripe pattern 42 in the row direction
  • a second signal line 108 may also be included.
  • the second signal line 108 may be connected to the transistor 107
  • the gate electrode 71 is integrally provided with the gate line V g , and the second signal line 108 is located between the layer where the first signal line 105 is located and the base substrate 101 .
  • the orthographic projection of the second signal line 108 on the base substrate 101 can be located within the orthographic projection of the row gap of each first electrode 103 on the base substrate 101, and at the same time, the pattern layer 104 can be disposed on the base substrate 101.
  • the orthographic projection on is located within the orthographic projection of the second signal line 108 on the base substrate 101 . Since the present disclosure finds that the aggregation area of the alignment layer 102 is located in the area where the second signal line 108 is located, the present disclosure provides a pattern layer 104 in the area where the second signal line 108 is located to help prevent the alignment layer 102 from aggregating.
  • the present disclosure found that when the accumulation width of the alignment layer 102 on the second signal line 108 is more than 60% of the line width of the second signal line 108, macroscopic defects may occur. Based on this, in order to avoid the occurrence of defects, in the above-mentioned display substrate provided by the embodiment of the present disclosure, the ratio of the width of the pattern layer 104 in the column direction Y to the width of the second signal line 108 in the column direction Y can be set to be greater than or equal to 3 /5 and less than or equal to 1.
  • part of the gate line V g can be multiplexed as the gate 71 of the transistor 107 ; or, as shown in FIGS. 14 , 27 , 30 , 33 and 34 As shown, the gate electrode 71 may also be disposed protrudingly relative to the gate line Vg .
  • the pattern layer 104 can be set to include multiple lines intersecting the row direction X and the column direction Y.
  • the orthographic projection of the two branches 44 on the base substrate 101 is located within the orthographic projection of the second signal line 108 on the base substrate 101 .
  • the first subsection 43 shown in Figure 13 has a diagonal strip structure, that is, it can be a strip electrode with the same extension direction and width as the pixel electrode domain
  • the second subsection 44 has a block structure; of course, in some embodiments, the first sub-section 43 and the second sub-section 44 can also be a block-shaped structure or a diagonal strip-shaped structure at the same time, or the first sub-section 43 is a block-shaped structure and the second sub-section 44 is a diagonal strip.
  • the structure, that is, the structure of the first part 43 and the structure of the second part 44 may be the same or different, and are not specifically limited here.
  • two second signal lines 108 are provided correspondingly at the same row gap of each first electrode 103, and each first electrode 103 is provided with two second signal lines 108.
  • the orthographic projection of the two second signal lines 108 on the base substrate 101 is located within the orthographic projection of the pattern layer 104 on the base substrate 101, so as to prevent the alignment layer 102 from being blocked by the pattern layer 104.
  • the area where the second signal line 108 is located is aggregated.
  • the first signal line 105 includes a column gap located at each first electrode 103 and a gap between the two second signal lines 108 .
  • the "coincidence" may coincide exactly, or there may be some deviation (for example, a deviation of ⁇ 2 ⁇ m).
  • the orthographic projection of the pattern layer 104 on the base substrate 101 is on the island structure 51 on the base substrate 101 within the orthographic projection on the substrate 101 or partially beyond the orthographic projection of the structure 51 on the base substrate 101 are within the scope of protection of this case.
  • the pattern layer 104 shown in FIG. 15 simultaneously covers the two second signal lines 108 in the same row gap, since the island structure 51 is located in the column gap of each first electrode 103 and the two second signal lines 108 , the pattern layer 104 in FIG. 15 also covers the island structure 51 , that is, the pattern layer 104 is provided on both the second signal line 108 and the island structure 51 .
  • a spacer PS is provided on the counter substrate opposite to the display substrate to maintain a stable cell thickness (Gap) between the display substrate and the counter substrate, and the spacer PS is aligned with the position of the island structure 51 Layer 102 contacts. As shown in FIG. 17 , if the alignment layer 102 accumulates at the position of the island-shaped structure 51 , the spacer PS will resist the accumulated alignment layer 102 , which will cause the cell thickness at the position of the island-shaped structure 51 to increase, and a box will appear. The problem of uneven display (Mura) caused by uneven thickness.
  • Mura uneven display
  • the pattern layer 104 that can prevent the alignment layer 102 from aggregating is provided at the position of the island structure 51, so that at the position of the island structure 51, the spacer PS contacts the alignment layer 102 with a uniform film thickness. Therefore, no The abnormal phenomenon of increased cell thickness will occur, thereby effectively solving the problem of uneven display.
  • liquid crystal display panels include color filter substrates (such as the above-mentioned opposite substrate) and array substrates (such as the above-mentioned display substrate) ) and the liquid crystal added between the color filter substrate and the array substrate.
  • the spacer PS can be disposed on one side of the color filter substrate, and the other end of the spacer PS faces the island structure 51 of the array substrate, or
  • the spacer PS can be disposed on one side of the array substrate, that is, directly disposed at a position corresponding to the island-shaped structure 51.
  • the island-shaped structure 51 here can be directly prepared from the same layer and material as the data line.
  • the position of the spacer PS is not limited to corresponding to the position of the island structure 51 .
  • the spacer PS can also be positioned in the area where the second signal line 108 is located. That is, after the display substrate and the opposite substrate are aligned, the spacer PS and the second signal line 108 are connected to each other.
  • the alignment layer PI in the area where line 108 is located is in contact.
  • the alignment layer 102 since the uppermost film layer of the display substrate is the alignment layer PI, no matter where the spacer PS is, the spacer PS is in contact with the alignment layer 102, that is, the alignment layer 102 includes a station for setting the spacer PS. bit area.
  • the orthographic projection of the station area of the spacer PS on the base substrate 101 can be set within the orthographic projection of the pattern layer 104 on the base substrate 101.
  • an island structure 51 can be electrically connected to the first poles of the two transistors 107 respectively.
  • the gate electrode of one transistor 107 is electrically connected to a second signal line 108
  • the gate electrode of the other transistor 107 is electrically connected to another second signal line 108
  • the second electrode of one transistor 107 is connected to the row gap.
  • the first electrode 103 of the odd-numbered column on one side is electrically connected, and the second electrode of the other transistor 107 is electrically connected to the first electrode 103 of the even-numbered column on the other side of the row gap, so that the first electrode 103 of the two columns can be connected through a data line V data .
  • the electrode 103 is loaded with signals, thereby saving the number of data lines V data and wiring space.
  • the saved wiring space can be used to set the common electrode line V com , which can be electrically connected to the second electrode 109 , thereby making the overall resistance of the second electrode 109 lower, and at the same time, the second electrode 109 has a lower overall resistance. Voltage uniformity and stability on the 109 have also been improved.
  • the second electrode 109 may be located between the layer where the first electrode 103 is located and the base substrate 101 , and the orthographic projection of the first electrode 103 on the base substrate 101 is in direct contact with the second electrode.
  • the orthographic projections of 109 on the base substrate 101 overlap with each other, so that an electric field for driving liquid crystal deflection can be formed between the first electrode 103 and the second electrode 109 .
  • the second electrode 109 may be disposed in the same layer as the gate electrode 71 of the transistor 107 .
  • the second electrode 109 is made of transparent conductive materials such as indium tin oxide (ITO), indium tin oxide (IZO), and zinc oxide (ZnO).
  • the gate 71 can be made of metal materials, alloy materials, etc.
  • the material of the gate 71 may include molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu), etc.
  • the gate 71 may be a single-layer metal structure or a multi-layer metal structure, for example.
  • the multi-layer metal structure may be composed of a stacked titanium metal layer/aluminum metal layer/titanium metal layer.
  • the first electrode 103 can also be made of transparent conductive materials such as indium tin oxide (ITO), indium tin oxide (IZO), zinc oxide (ZnO), etc.
  • ITO indium tin oxide
  • IZO indium tin oxide
  • ZnO zinc oxide
  • the first electrode 103 can be a pixel electrode and the second electrode 109 can be a common electrode.
  • the first electrode 103 can also be set as a common electrode
  • the second electrode 109 can be a pixel electrode, that is, as shown in Figures 21, 23, 25, 33 and 36, it can be a pixel electrode.
  • the common electrode is a plate-shaped electrode; or, as shown in Figures 27 to 29 and Figure 32, the common electrode can be a strip-shaped electrode formed by a slit design, and the pixel electrode is a plate-shaped electrode.
  • the present disclosure shows that the first electrode 103 and the second electrode 109 are both located on the display substrate, but in some embodiments, the first electrode 103 and the second electrode 109 may also be provided on the display substrate and the counter substrate respectively. , no specific limitation is made here.
  • the insulating layer 106 may be located between the layer where the first electrode 103 is located and the layer where the second electrode 109 is located, and the One electrode 103 blocks part of the insulating layer 106, and the insulating layer 106 that is not blocked by the first electrode 103 is reused as the pattern layer 104. Therefore, there is no need to make an additional pattern layer 104. That is, in this case, the insulating layer can be adjusted without being provided with the first electrode. 103Patterns of the same layer and material.
  • the process of the film quality of the insulating layer 106 can be optimized, so that the film quality of the insulating layer 106 is denser, the roughness is reduced, and the contact angle is increased, so that it can be reused as the pattern layer 104.
  • the film quality of the insulating layer 106 can be changed by adjusting the ratio of the reaction source gas used to make the insulating layer 106 .
  • ammonia (NH 3 ) and silane (SiH 4 ) can be used as reaction source gases, and when the flow ratio of ammonia to silane is greater than or equal to 2 and less than or equal to 8, the insulating layer produced
  • the contact angle of the insulating layer 106 can be greater than or equal to 35° and less than 90°.
  • the contact angle of the insulating layer 106 is 37.5°, 52°, 58.7°, etc.
  • the pattern layer 104 be made by using the material of the first electrode 103 alone, or the film quality of the insulating layer 106 can be adjusted alone so that the insulating layer 106 can be reused as the pattern layer 104; These two solutions are combined, that is, on the basis of using the insulating layer 106 to be reused as the pattern layer 104, the material of the first electrode 103 can also be used to make the pattern layer 104. Moreover, it should be understood that when the morphology of the pattern layer 104 made of the material of the first electrode 103 is the same as the local morphology of the first electrode 103, the inclined strip structure and the inclined structure of the pattern layer 104 can be utilized at the same time. The insulating layer 106 at the gap of the strip structure prevents the alignment layer 102 from gathering.
  • the first signal line 105 at the position where the first signal line 105 and the second signal line 108 are intersected, the first signal line 105
  • the line width and the line width of the second signal line 108 are both reduced, which can reduce the facing area of the first signal line 105 and the second signal line 108, thereby ensuring that the connection between the first signal line 105 and the second signal line 108 is The parasitic capacitance between them is smaller, or the width of one of the first signal line 105 and the second signal line 108 is reduced.
  • two adjacent second electrodes 109 in the same column are electrically connected through the connecting electrode 110, so that the voltage uniformity and stability of the second electrodes 109 in the same column are better, and the second electrodes 109 in two adjacent rows are electrically connected.
  • the two electrodes 109 realize electrical connection.
  • the connection electrode 110 and the first electrode 72 and the second electrode 73 of the transistor 107 are in the same layer and made of the same material.
  • the gate insulating layer 111 in the related art is made using an open mask, a patterning process is not required. In this disclosure, if a hole is drilled in the gate insulating layer 111 to connect the transfer electrode 110 and the second electrode 109, an additional patterning process is required.
  • the first electrode 103 is electrically connected to the second electrode 73 of the transistor 107 through the first via V 1 that penetrates the insulating layer 106 , and there is an insulating layer 106 and a gate insulating layer between the second electrode 109 and the first electrode 103 111.
  • the electrical connection between the connecting electrode 110 and the second electrode 109 can be achieved through the first transfer electrode 112 which is in the same layer and material as the second electrode 109 and is insulated from the second electrode 109.
  • the through insulating layer 106 may be simultaneously formed and used to realize the connection.
  • the second via hole V 2 electrically connects the electrode 110 to the first transfer electrode 112
  • the third via hole V 2 penetrates the insulating layer 106 and the gate insulating layer 111 and is used to realize the electrical connection between the second electrode 109 and the first transfer electrode 112 .
  • hole V 3 thus avoiding the patterning process of additionally adding the gate insulating layer 111 .
  • two adjacent second electrodes 109 in the same row can be electrically connected through a third signal line 113, and in Figure 23 the third signal line 113 is integrally provided with each of the second electrodes 109 in the same row.
  • the third signal line 113 and the second signal line 108 are provided in the same layer and with the same material.
  • Two adjacent second electrodes 109 in the same row are electrically connected through the third signal line 113, which can make the voltage uniformity and stability of each second electrode 109 in the same row better.
  • the second electrodes 109 in the same column can also be connected together through the connecting electrodes 110.
  • the second electrodes 109 in each row and column constitute an electrically connected Overall, it is thus ensured that all second electrodes 109 have excellent voltage uniformity and stability.
  • the line width of the first signal line 105 and the line width of the third signal line 113 become smaller, which can reduce the first signal
  • the facing area of the line 105 and the third signal line 113 ensures that the parasitic capacitance between the first signal line 105 and the third signal line 113 is small.
  • two positioning structures 114 are also provided in the layer where the first pole 72 and the second pole 73 of the transistor 107 are located. These two positioning structures 114 are used to position spacers. For example, the orthographic projection position of the spacer PS on the display substrate is located at the middle position between the two positioning structures 114 .
  • the first electrode 103 is a slit electrode, and the pattern between each two adjacent slits can be a first strip electrode 31 or a second strip electrode 32 .
  • the first signal line 105 may be a straight line extending along the column gap of each first electrode 103 , or, as shown in FIGS. 27 , 31 to 33 , and 35 , As shown in FIG. 36 , the first signal line 105 may have the same extension direction and the same shape as the strip electrode of the first electrode 103 or the second electrode 109 , which is not limited here.
  • a second transfer electrode 115 may also be included in the same layer and material as the second electrode 109 , so that the transistor 107 can be implemented through the second transfer electrode 115
  • the second electrode 73 is electrically connected to the first electrode 103 .
  • the transistor 107 provided by the embodiment of the present disclosure may be a top-gate transistor or a bottom-gate transistor.
  • the transistor 107 may be an oxide transistor, an amorphous silicon transistor, a polysilicon transistor, or the like.
  • the transistor 107 may be a P-type transistor or an N-type transistor, wherein the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the transistor 107 may further include an active layer 74 and a contact layer 75 between the active layer 74 and the first electrode 72 and between the active layer 74 and the second electrode 73 . The electrical connection effect between the active layer 74 and the first electrode 72 and the active layer 74 and the second electrode 73 is improved.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned display substrate, as shown in Figure 37, which may include the following steps:
  • the ratio of the contact angle of the pattern layer 104 to the contact angle of the first electrode 103 is greater than or equal to 7/12 and less than or equal to 3/2;
  • the above-mentioned step S3702 forming the pattern layer and the first electrode on the base substrate, can be implemented in two ways: first, using the same mask; The stencil forms a pattern layer and a first electrode of the same layer and material on the base substrate. Second, two masks are used to form a pattern layer and a first electrode on the base substrate respectively. The pattern layer and the first electrode are located on the same layer, and the material of the pattern layer and the first electrode are the same.
  • the same mask is used to form the pattern layer 104 and the first electrode 103 of the same layer and the same material on the base substrate 101.
  • the same mask is used to form the pattern layer 104 and the first electrode 103 of the same layer and the same material on the base substrate 101.
  • the first possible implementation could include the following steps:
  • a conductive layer and a photoresist layer are sequentially formed on the base substrate 101 .
  • a mask is provided.
  • the mask only has a pattern for making the first electrode 103 .
  • the third step is to shift the pattern of the mask relative to the area where the first electrode is to be made, so that the pattern of the mask overlaps with the area where the first electrode 103 is to be made and the area where the pattern layer 104 is to be made. .
  • the fourth step is to perform exposure processing on the photoresist layer in the area where the first electrode 103 is to be made and the photoresist layer in the area where the pattern layer 104 is to be made under the cover of the mask.
  • the area of the first electrode 103 to be made and the area where the pattern layer 104 is to be made are realized.
  • the photoresist layer is developed to retain the photoresist layer in the area where the first electrode 103 is to be formed and the photoresist layer in the area where the pattern layer 104 is to be formed.
  • the conductive layer is etched under the cover of the photoresist layer to form the pattern layer 104 and the first electrode 103 of the same layer, same material, and separated.
  • a second possible implementation could include the following steps:
  • a conductive layer and a photoresist layer are sequentially formed on the base substrate 101 .
  • a mask is provided.
  • the mask has a first pattern for making the first electrode 103 and a second pattern for making the pattern layer 104.
  • the first pattern is disconnected from the second pattern.
  • the photoresist layer in the area where the first electrode 103 is to be formed and the photoresist layer in the area where the pattern layer 104 is to be formed are simultaneously exposed.
  • the fourth step is to develop the photoresist layer, leaving the photoresist layer in the area where the first electrode 103 is to be formed and the photoresist layer in the area where the pattern layer 104 is to be formed.
  • the conductive layer is etched under the cover of the photoresist layer to form the pattern layer 104 and the first electrode 103 of the same layer, same material, and separated.
  • the step of peeling off the photoresist layer may also be performed.
  • the above-mentioned step S2602 forming the pattern layer 104 and the first electrode 103 on the base substrate, can also be implemented in the following manner:
  • Ammonia and silane are used as reaction source gases to form an insulating layer 106 arranged on the entire surface.
  • the flow ratio of ammonia to silane is greater than or equal to 2 and less than or equal to 8.
  • the flow ratio of ammonia to silane can be 2, 2.5, 3, or 3.5. , 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, etc.;
  • the first electrode 103 is formed on the insulating layer 106 in the pixel opening area of the base substrate 101, and the insulating layer 106 outside the pixel opening area is reused as the pattern layer 104.
  • the gate electrode 71 of the transistor 107 may also be sequentially formed on the base substrate 101 , the second electrode 109, the gate insulating layer 111, the active layer 74 of the transistor 107, the first electrode 72, the second electrode 73 and the connection electrode 110 of the transistor arranged in the same layer.
  • a first via hole penetrating the insulating layer 106 may also be formed at the same time.
  • the transfer electrode 112 can be fabricated simultaneously with the formation of the first electrode 103 .
  • the patterning process involved in forming each layer structure may not only include deposition, photoresist coating, masking, exposure, development, etching, Part or all of the process, such as photoresist stripping, may also include other processes.
  • the details are subject to the required pattern formation during the actual production process, which is not limited here.
  • a post-bake process may be included after development and before etching.
  • the deposition process can be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here;
  • the mask used in the mask process can be a half tone mask (Half Tone Mask) ), single slit diffraction mask (Single Slit Mask) or gray tone mask (Gray Tone Mask), which are not limited here;
  • etching can be dry etching or wet etching, which is not limited here.
  • embodiments of the disclosure provide a display device, including the above display substrate provided by embodiments of the disclosure. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the above-mentioned display substrate, therefore, the implementation of the display device provided by the embodiment of the present disclosure can be referred to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the duplication will not be repeated. Repeat.
  • the above display device provided by the embodiments of the present disclosure can be applied to mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, smart watches, fitness wristbands, Any product or component with a display function, such as a personal digital assistant.
  • the above-mentioned display device provided by the embodiment of the present disclosure is a liquid crystal display screen.
  • the liquid crystal display screen may include a backlight module and a display panel located on the light exit side of the backlight module.
  • the display panel includes an opposite display substrate and a counter substrate, a liquid crystal layer located between the display substrate and the counter substrate, a sealant surrounding the liquid crystal layer between the display substrate and the counter substrate, and a sealant located between the display substrate and the liquid crystal a first alignment layer on one side of the display substrate, a second alignment layer on the side of the opposite substrate close to the liquid crystal layer, a first polarizer on the side of the display substrate away from the liquid crystal layer, and a third polarizer on the side of the opposite substrate away from the liquid crystal layer. Two polarizers, etc.
  • the backlight module can be a direct-type backlight module or an edge-type backlight module.
  • the backlight module may include a light source, a stacked reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc.
  • the light source can be a light-emitting diode (LED), such as a miniature light-emitting diode (Mini LED, Micro LED, etc.).
  • Miniature light-emitting diodes at the submillimeter or even micron level are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have lower power consumption, better resistance to high and low temperatures, and longer service life than organic light-emitting diodes based on organic matter. Longer advantage. And when micro light-emitting diodes are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlights between bright and dark areas of the screen, optimizing the visual experience. .
  • the above-mentioned display device may include but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip and other components.
  • the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), etc.
  • the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additional wires, signal lines, etc.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • VLSI very large scale integration
  • existing semiconductors such as logic chips, transistors, or other discrete components
  • hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above display device provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.

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Abstract

本公开的显示基板、其制作方法及显示装置，包括衬底基板；配向层，位于衬底基板之上；第一电极，位于衬底基板与配向层之间且与配向层接触；图案层，位于衬底基板与配向层之间且与配向层接触，图案层在衬底基板上的正投影与第一电极在衬底基板上的正投影互不交叠，图案层的接触角与第一电极的接触角之比大于等于7/12且小于3/2。

Description

显示基板、其制作方法及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、其制作方法及显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有重量轻、耗电少、画质高、辐射低和携带方便等优点，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，而被广泛应用于现代化信息设备，如虚拟现实(VR)头戴式显示设备、笔记本电脑、电视、移动电话和数字产品等。
发明内容
本公开实施例提供的一种显示基板、其制作方法及显示装置，具体方案如下：
一方面，本公开实施例提供的一种显示基板，包括：
衬底基板；
配向层，位于所述衬底基板之上；
第一电极，位于所述衬底基板与所述配向层之间且与所述配向层接触；
图案层，位于所述衬底基板与所述配向层之间且与所述配向层接触，所述图案层在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影互不交叠，所述图案层的接触角与所述第一电极的接触角之比大于等于7/12且小于3/2。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述图案层与所述第一电极同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一电 极为多个，多个所述第一电极在所述衬底基板上呈阵列排布；
所述图案层在所述衬底基板上的正投影位于各所述第一电极的行间隙在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一电极包括一体设置的第一条状电极和第二条状电极，所述第一条状电极的延伸方向与行方向、列方向、以及所述第二条状电极的延伸方向均交叉设置，所述第二条状电极的延伸方向与行方向、以及列方向均交叉设置；
所述图案层沿所述第一条状电极的延伸方向和/或所述第二条状电极的延伸方向延伸。
在一些实施例中，在本公开实施例提供的上述显示基板中，相邻两个行间隙处的所述图案层的延伸方向不同。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述图案层的线宽与其延伸方向相同的所述第一条状电极或所述第二条状电极的线宽相同，且所述图案层的线距与其延伸方向相同的所述第一条状电极或所述第二条状电极的线距相同。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述图案层包括在各所述第一电极的同一行间隙处间隔设置有多个块状图案，且所述块状图案沿行方向延伸。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括第一信号线，所述第一信号线在所述衬底基板上的正投影位于各所述第一电极的列间隙在所述衬底基板上的正投影内；
所述图案层在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括晶体管，至少部分所述第一信号线与所述晶体管电连接；
所述图案层在所述衬底基板上的正投影与所述晶体管在所述衬底基板上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述图案层包括在各所述第一电极的行间隙处沿行方向延伸的条状图案，所述条状图案在行方向上的长度与各所述第一电极的行间隙的长度相同。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括第二信号线，所述第二信号线在所述衬底基板上的正投影位于各所述第一电极的行间隙在所述衬底基板上的正投影内；
所述图案层在所述衬底基板上的正投影位于所述第二信号线在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述图案层在列方向上的宽度与所述第二信号线在列方向上的宽度之比大于等于3/5且小于等于1。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括第二信号线，所述第二信号线在所述衬底基板上的正投影位于各所述第一电极的行间隙在所述衬底基板上的正投影内，各所述第一电极的同一行间隙处对应设置有两条所述第二信号线；
在各所述第一电极的同一行间隙处，两条所述第二信号线在所述衬底基板上的正投影位于所述图案层在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括交叉设置且相互绝缘的第一信号线和第二信号线，其中，所述第一信号线在所述衬底基板上的正投影位于各所述第一电极的列间隙在所述衬底基板上的正投影内，所述第一信号线包括在各所述第一电极的列间隙与两条所述第二信号线的间隙交叉位置处的岛状结构；
所述图案层在所述衬底基板上的正投影与所述岛状结构在所述衬底基板上的正投影重合。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括第二信号线和栅极，所述第二信号线与所述栅极为一体结构且所述栅极相对于所述第二信号线凸出设置；
所述图案层包括与行方向、列方向均交叉设置的多个第一分部，以及沿行方向延伸的第二分部，所述第一分部在所述衬底基板上的正投影位于所述栅极在所述衬底基板上的正投影内，所述第二分部在所述衬底基板上的正投影位于所述第二信号线在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一电极所在层与所述衬底基板之间的第二电极，所述第一电极在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影相互交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一电极所在层与所述第二电极所在层之间的绝缘层，所述第一电极遮挡部分所述绝缘层，未被的所述第一电极遮挡的所述绝缘层复用为所述图案层。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述配向层包括用于设置隔垫物的站位区，所述站位区在所述衬底基板上的正投影位于所述图案层在所述衬底基板上的正投影内。
另一方面，本公开实施例提供了一种上述显示基板的制作方法，包括：
提供一个衬底基板；
在所述衬底基板上形成图案层和第一电极，其中，所述图案层在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影互不交叠，所述图案层的接触角与所述第一电极的接触角之比大于等于7/12且小于等于3/2；
在所述图案层和所述第一电极所在层上涂布配向液；
对所述配向液进行固化处理，形成配向层。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述衬底基板上形成图案层和第一电极，具体包括：
采用同一掩膜版，在所述衬底基板上形成同层、同材料设置的图案层和第一电极。
在一些实施例中，在本公开实施例提供的上述制作方法中，采用同一掩膜版，在所述衬底基板上形成同层、同材料设置的图案层和第一电极，具体 包括：
在所述衬底基板上依次形成导电层和光刻胶层；
提供一个掩膜版，所述掩膜版仅具有用于制作第一电极的图案；
将所述掩膜版的图案相对于待制作所述第一电极的区域偏移，使得所述掩膜版的图案同时与待制作所述第一电极的区域、以及待制作图案层的区域相互交叠；
在所述掩膜版的遮挡下，分时对待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层进行曝光处理；
对所述光刻胶层进行显影处理，保留待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层；
在所述光刻胶层的遮挡下，对所述导电层进行刻蚀，形成同层、同材料且断开设置的所述图案层和所述第一电极。
在一些实施例中，在本公开实施例提供的上述制作方法中，采用同一掩膜版，在所述衬底基板上形成同层、同材料设置的图案层和第一电极，具体包括：
在所述衬底基板上依次形成导电层和光刻胶层；
提供一个掩膜版，所述掩膜版具有用于制作第一电极的第一图案、以及用于制作图案层的第二图案，所述第一图案与所述第二图案断开设置；
在所述掩膜版的遮挡下，同时对待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层进行曝光处理；
对所述光刻胶层进行显影处理，保留待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层；
在所述光刻胶层的遮挡下，对所述导电层进行刻蚀，形成同层、同材料且断开设置的所述图案层和所述第一电极。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述衬底基板上形成图案层和所述第一电极，具体包括：
以氨气和硅烷作为反应源气体形成整面设置的绝缘层，氨气与硅烷的流 量比大于等于2且小于等于8；
在所述衬底基板所含像素开口区的所述绝缘层上形成第一电极，所述像素开口区之外的所述绝缘层复用为图案层。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板。
附图说明
图1为相关技术中配向液形成的湿膜发生断裂、聚集的示意图；
图2为本公开实施例提供的显示基板的一种结构示意图；
图3为本公开实施例提供的显示基板的又一种结构示意图；
图4为因第一电极与图案层搭接导致配向液形成的湿膜聚集的示意图；
图5为本公开实施例提供的接触角的测试流程图；
图6为本公开实施例提供的显示基板的又一种结构示意图；
图7为本公开实施例提供的显示基板的又一种结构示意图；
图8为本公开实施例提供的显示基板的又一种结构示意图；
图9为本公开实施例提供的显示基板的又一种结构示意图；
图10为本公开实施例提供的显示基板的又一种结构示意图；
图11为本公开实施例提供的显示基板的又一种结构示意图；
图12为本公开实施例提供的显示基板的又一种结构示意图；
图13为本公开实施例提供的显示基板的又一种结构示意图；
图14为本公开实施例提供的显示基板中晶体管的一种结构示意图；
图15为本公开实施例提供的显示基板的又一种结构示意图；
图16为本公开实施例提供的显示基板的又一种结构示意图；
图17为配向层聚集导致盒厚不均一的示意图；
图18为本公开实施例提供的显示基板的又一种结构示意图；
图19为本公开实施例提供的显示基板的又一种结构示意图；
图20为本公开实施例提供的显示基板的又一种结构示意图；
图21为本公开实施例提供的显示基板的一种像素结构示意图；
图22为图21中第二信号线和晶体管的栅极的结构示意图；
图23为图21中第三信号线和第二电极的结构示意图；
图24为图21中第一信号线、晶体管的第一极、第二极、连接电极、限位结构的结构示意图；
图25为图21中第一电极、第一转接电极和图案层的结构示意图；
图26为连接电极通过第一转接电极与第二电极连接的结构示意图；
图27为本公开实施例提供的显示基板的又一种像素结构示意图；
图28为图27中第一电极与第二电极的叠层示意图；
图29为图27中第一电极的结构示意图；
图30为图27中第二信号线、晶体管的栅极和第三信号线的结构示意图；
图31为图27中第一信号线、晶体管的第一极和第二极的结构示意图；
图32为图27中第二电极、第二转接电极和图案层的结构示意图；
图33为本公开实施例提供的显示基板的又一种像素结构示意图；
图34为图33中第二信号线和晶体管的栅极的结构示意图；
图35为图33中第一信号线、晶体管的第一极和第二极的结构示意图；
图36为图33中第一电极和图案层的结构示意图；
图37为本公开实施例提供的显示基板的制作流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在产品开发过程中，本公开发现液晶显示装置在L127灰阶下多次检测出团状污渍，影响显示效果。经过拆屏解析后发现在团状污渍发生区存在配向层(PI)聚集的现象，而且团状污渍越严重，配向层堆积越高。
配向层的制作过程主要包括两个步骤：其一，通过涂布(Inkjet)设备，使得配向液滴在显示基板表面使其扩散形成湿膜102'；其二，在预固化(Pre-Cure)设备中加热使得湿膜102'的溶剂挥发后形成配向层。在这两个过程中，显示基板的接触角都发挥了决定性的作用。一般认为，固体与液体之间界面张力越小，接触角越小，液体对固体的润湿程度越好，液体与固体越不容易分离；固体与液体之间界面张力越大，接触角越大，液体对固体的润湿程度越差，液体与固体越容易分离。
经进一步研究发现，在配向层下方与配向层接触的膜层包括位于像素开口区的第一电极和位于非像素开口区的绝缘层，例如显示面板栅线对应的绝缘层，其中，第一电极的接触角为60°，绝缘层的接触角为20°～30°，可以看出绝缘层的接触角是第一电极的接触角的1/3～1/2，二者的接触角差异太大，配向液与第一电极之间的界面张力远大于配向液与绝缘层之间的界面张力，所以第一电极和绝缘层对配向液形成“拉拽效应”，造成由配向液扩散成的湿膜102'断裂、聚集，如图1所示。并且，虽然较小的接触角有利于配向液的润湿和扩散，但是在预固化过程中溶剂挥发速率不一致，在润湿性好的界面上配向液不易转移，容易产生断裂、收缩和堆积，因此，配向层在接触角较小的绝缘层上发生了堆积不良。
基于此，为了改善相关技术中存在的上述技术问题，本公开实施例提供的一种显示基板，如图2和图3所示，包括：
衬底基板101；
配向层102，位于衬底基板101之上；
第一电极103，位于衬底基板101与配向层102之间且与配向层102接触；
图案层104，位于衬底基板101与配向层102之间且与配向层102接触，图案层104在衬底基板101上的正投影与第一电极103在衬底基板101上的正投影互不交叠，图案层104的接触角与第一电极103的接触角之比大于等于7/12且小于3/2。
在本公开实施例提供的上述显示基板中，错开设置的图案层104与第一电极103均与配向层102接触，相当于配向液是涂布在图案层104与第一电极103的表面上的。本公开通过设置图案层104的接触角与第一电极103的接触角之比大于等于7/12且小于3/2，例如第一电极103的接触角为60°，图案层104的接触角大于等于35°且小于90°，使得图案层104的接触角与第一电极103的接触角差异较小，相应地，配向液、第一电极103之间的界面张力与配向液、图案层104之间的界面张力差异较小，从而有效弱化了第一电极103和图案层104对配向液的“拉拽效应”，降低了配向液扩散形成的湿膜102'断裂、聚集的风险。并且，改善前绝缘层的接触角大于等于第一电极103的接触角的1/3且小于等于第一电极103的接触角的1/2，本公开中图案层104的接触角大于等于第一电极103的接触角的7/12且小于第一电极103的接触角的3/2，对比可知，本公开图案层104的接触角大于改善前绝缘层的接触角。由接触角越大，润湿性越差可知，配向液在图案层104上的润湿性比配向液在改善前绝缘层上的润湿性稍差。结合上述记载的“在润湿性好的界面上配向液不易转移，容易产生断裂、收缩和堆积”可知，配向液在润湿性稍差的图案层104上更容易转移，不易产生断裂、收缩和堆积。基于上述两个方面的原因，本公开可显著改善配向层102的聚集现象，提高显示效果。
另外，如图4所示，如果第一电极103与图案层104搭接在一起，一方面会 导致搭接位置N的配向层102堆积更高，另一方面图案层104可能会改变第一电极103在第一过孔V 1处的界面电阻，影响信号传递和显示画质。本公开中设置图案层104在衬底基板101上的正投影与第一电极103在衬底基板101上的正投影互不交叠，使得图案层104与第一电极103之间断开设置，避免了图案层104与第一电极103搭接在一起，因此，图案层104不会影响信号传递和显示画质，同时避免了配向层102在搭接位置N聚集。
在一些实施例中，可通过图5所示的方法测试接触角，具体过程为：在图案层104或第一电极103上滴入预设体积(例如1μL)亲水性的液滴l(例如去离子水)，液滴l开始在图案层104或第一电极103上扩展，等待至液滴l不再扩展运动后，对液滴l与图案层104或第一电极103进行拍照，并测量拍摄图片中液滴-空气界面(l-g)与液滴-固体界面(l-s)之间的夹角θ，该夹角θ即为图案层104或第一电极103的接触角。
针对配向层102在第一电极103和改善前绝缘层上的“接着力”，本公开进行了配向层102在第一电极103和绝缘层上的粘附性测定实验。具体做法是用橡皮按照同样的力度去擦拭配向层102，然后在显微镜下观察配向层102的残留情况，结果发现，在擦拭后，相对于绝缘层上残留的配向层102，第一电极103上残留的配向层102更完整，这说明了配向层102与第一电极103的结合更紧密。另外，本公开发现第一电极103的表面粗糙度小，配向层102在第一电极103上并未出现聚集现象。因此，如图3所示，在本公开实施例提供的上述显示基板中，可将图案层104与第一电极103同层、同材料设置，这样不仅可以使配向层102与图案层104紧密结合，还可以保证配向层102在图案层104上不发生聚集。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图6至图8所示，第一电极103为多个，多个第一电极103在衬底基板101上呈阵列排布；图案层104在衬底基板101上的正投影位于各第一电极103的行间隙在衬底基板101上的正投影内。通常在与显示基板相对而置的对向基板上，设置有遮挡各第一电极103的行间隙的黑矩阵(BM)，在本公开中设置图案层104在衬底 基板101上的正投影位于各第一电极103的行间隙在衬底基板101上的正投影内的情况下，图案层104会被黑矩阵遮挡，不会出现漏光不良。并且，由于黑矩阵所在区并不进行画面显示，因此图案层104不会影响显示效果。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图6至图8所示，第一电极103包括一体设置的第一条状电极31和第二条状电极32，第一条状电极31的延伸方向D 1与行方向X、列方向Y、以及第二条状电极32的延伸方向D 2均交叉设置，第二条状电极32的延伸方向D 2与行方向X、以及列方向Y均交叉设置；图案层104沿第一条状电极31的延伸方向D 1和/或第二条状电极32的延伸方向D 2延伸，例如在图6中在各第一电极103的每个行间隙处的图案层104均沿第一条状电极31的延伸方向D 1延伸，在图7中各第一电极103的每个行间隙处的图案层104均沿第二条状电极32的延伸方向D 2延伸，在图8中各第一电极103的相邻两个行间隙处的图案层104的延伸方向不同，即相邻两个行间隙处的图案层104的延伸方向分别与第一条状电极31的延伸方向D 1、第二条状电极32的延伸方向D 2相同。这样可以使得图案层104的形貌与第一电极103的局部形貌相近，利于在第一电极103与图案层104上形成均一性较好的配向层104，需要说明的是，图6中示意的第一条状电极31和第二条状电极32可以参考图21和图25，具体地，在图21和图25中是在板状电极上开狭缝形成的条状电极；或者图6中示意的第一条状电极31和第二条状电极32也可以参考图27、图32、图33和图36，具体地，图27、图32、图33和图36中是直接形成多个电连接的条状电极，其中，图27和图32所示条状电极为双畴电极且畴向电极的夹角为钝角，在一些实施例中，畴向电极的夹角也可以为锐角；图33和图36所示条状电极为单畴电极。
在一些实施例中，可利用相关技术中制作第一电极103的掩膜版实现图案层104的制作。例如可沿图6中的A方向移动制作第一电极103的掩膜版至各第一电极103的行间隙处，并通过控制光源仅照射第一电极103的行间隙对应的局部掩膜版，或在光源照射整张掩膜版的情况下遮挡第一电极103对应的掩膜版，实现仅对第一电极103的行间隙进行曝光、显影，从而在各第一电极103 的行间隙处制作出延伸方向与第一条状电极31的延伸方向D 1的图案层104。同理，在沿图7中的A'方向移动制作第一电极103的掩膜版至各第一电极103的行间隙处的情况下，可在各第一电极103的行间隙处制作出延伸方向与第二条状电极32的延伸方向D 2的图案层104。另外，还可沿图8中的A方向移动制作第一电极103的掩膜版至各第一电极103的行间隙处，并通过控制光源仅照射第一电极103的第奇数个行间隙对应的局部掩膜版，或在光源照射整张掩膜版的情况下遮挡第一电极103对应的掩膜版、以及第偶数个行间隙对应的局部掩膜版，实现仅对第奇数个行间隙进行曝光、显影，从而在第奇数个行间隙处制作出延伸方向与第一条状电极31的延伸方向D 1的图案层104；还可沿图8中的A'方向移动制作第一电极103的掩膜版至各第一电极103的行间隙处，并通过控制光源仅照射第一电极103的第偶数个行间隙对应的局部掩膜版，或在光源照射整张掩膜版的情况下遮挡第一电极103对应的掩膜版、以及第奇数个行间隙对应的局部掩膜版，实现仅对第偶数个行间隙进行曝光、显影，从而在第偶数个行间隙处制作出延伸方向与第二条状电极32的延伸方向D 2的图案层104，这样就可以实现相邻两个行间隙处的图案层104的延伸方向不同。
在采用第一电极103的掩膜版制作图案层104的情况下，可以避免额外提供制作图案层104的掩膜版，利于节约成本。且如图6至图8所示，所制作出的图案层104的线宽与其延伸方向相同的第一条状电极31或第二条状电极32的线宽相同，图案层104的线距与其延伸方向相同的第一条状电极31或第二条状电极32的线距相同，即图案层104的形貌与第一电极103的局部形貌相同，更利于在第一电极103与图案层104上形成均一性较好的配向层102。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图9所示，图案层104包括在各第一电极103的同一行间隙处间隔设置有多个块状图案41，且块状图案41沿行方向X延伸。块状图案41构成的图案层104的结构较简单，相应的制作难度较小。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图6至图9所示，还可以包括第一信号线105，可选地，第一信号线105位于衬底基 板101与第一电极103所在层之间，且通过绝缘层106与第一电极103相互绝缘，第一信号线105可以全部为数据线V data，也可以包括数据线V data和公共电极线V com，也可以包括触控信号线等，在此不做限定。第一信号线105在衬底基板101上的正投影位于各第一电极103的列间隙在衬底基板101上的正投影内；图案层104在衬底基板101上的正投影与第一信号线105在衬底基板101上的正投影互不交叠。由于第一电极103的材料是导电材料，因此与第一电极103同层、同材料制作的图案层104也具有导电性。若图案层104与第一信号线105相互交叠，则二者之间会形成寄生电容，导致图案层104对第一信号线105的信号造成干扰。因此，为了避免图案层104干扰第一信号线105的信号，本公开设置图案层104在衬底基板101上的正投影与第一信号线105在衬底基板101上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图10和图11所示，还可以包括晶体管107，至少部分第一信号线105与晶体管107电连接，可选地，在第一信号线105全部为数据线V data的情况下，第一信号线105与晶体管107电连接；在第一信号线105包括数据线V data和公共电极线V com的情况下，第一信号线105中的数据线V data与晶体管107电连接。在一些实施例中，可通过一次构图工艺形成数据线V data及其电连接的晶体管107的第一极，可选地，晶体管107的第一极可以为源极或漏极。可选地，为了避免图案层104与第一信号线105交叠形成寄生电容而影响晶体管107的稳定性，本公开中可以设置图案层104在衬底基板101上的正投影与晶体管107在衬底基板101上的正投影互不交叠。
应当理解的是，由于第一信号线105所在层与图案层104所在层之间具有绝缘层106，因此，二者之间不会短接。基于此，在一些实施例中，如图1和图12所示，也可以设置图案层104在衬底基板101上的正投影晶体管107在衬底基板101上的正投影相互交叠；在另一些实施例中，如图13所示，图案层104包括在行间隙处沿行方向X延伸的条状图案42，条状图案42在行方向X上的长度与行间隙的长度相同，此时图案层104在衬底基板101上的正投影与第一信 号线105在衬底基板101上的正投影、以及在衬底基板101上的正投影均可以相互交叠。在此图13所示的情况下，图案层104由在行间隙处延伸的多个条状结构42组成，结构更简单，相应的制作难度更小，可选的，条状图案42在行方向X上的长度与行间隙的长度不相同，例如条状图案42在行方向X延伸方向和栅线延伸方向相同，具体长度宽度不限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图10和图11所示，还可以包括第二信号线108，可选地，第二信号线108可以为与晶体管107的栅极71一体设置的栅线V g，且第二信号线108位于第一信号线105所在层与衬底基板101之间。并且本公开中第二信号线108在衬底基板101上的正投影可以位于各第一电极103的行间隙在衬底基板101上的正投影内，同时可设置图案层104在衬底基板101上的正投影位于第二信号线108在衬底基板101上的正投影内。由于本公开发现配向层102的聚集区位于在第二信号线108所在区内，因此本公开在第二信号线108所在区内设置了有助于防止配向层102聚集的图案层104。
另外，本公开发现当配向层102在第二信号线108上的聚集宽度为第二信号线108的线宽的60％以上时，宏观上会有不良发生。基于此，为了避免不良发生，在本公开实施例提供的上述显示基板中，可以设置图案层104在列方向Y上的宽度与第二信号线108在列方向Y上的宽度之比大于等于3/5且小于等于1。
在一些实施例中，如图10和图11所示，栅线V g的局部可以复用为晶体管107的栅极71；或者，如图14、图27、图30、图33和图34所示，栅极71也可以相对于栅线V g凸出设置。继续参见图13，为了防止配向层102在第二信号线108(即栅线V g)和栅极71的位置聚集，可设置图案层104包括与行方向X、列方向Y均交叉设置的多个第一分部43，以及沿行方向X延伸的第二分部44，第一分部43在衬底基板101上的正投影位于栅极71在衬底基板101上的正投影内，第二分部44在衬底基板101上的正投影位于第二信号线108在衬底基板101上的正投影内。可以看出，图13所示的第一分部43为斜条状结构，即可以是和 像素电极畴向延伸方向、宽度相同的条状电极，第二分部44为块状结构；当然，在一些实施例中，第一分部43和第二分部44也可以同时为块状结构或斜条状结构，或者，第一分部43为块状结构，第二分部44为斜条状结构，即第一分部43的结构和第二分部44的结构可以相同、也可以不相同，在此不做具体限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图15所示，各第一电极103的同一行间隙处对应设置有两条第二信号线108，并且在各第一电极103的同一行间隙处，两条第二信号线108在衬底基板101上的正投影位于图案层104在衬底基板101上的正投影内，以通过图案层104防止配向层102在第二信号线108所在区产生聚集。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图16所示，第一信号线105包括位于各第一电极103的列间隙与两条第二信号线108的间隙交叉位置处的岛状结构51；图案层104在衬底基板101上的正投影与岛状结构51在衬底基板101上的正投影重合。需要说明的是，在本公开提供的实施例中，由于工艺条件的限制或测量等其他因素的影响，“重合”可能会恰好重合，也可能会有一些偏差(例如具有±2μm的偏差)，因此相关特征之间“重合”的关系只要满足误差允许，均属于本公开的保护范围，需要说明的是，图案层104在衬底基板101上的正投影在岛状结构51在衬底基板101上的正投影内或者部分超出状结构51在衬底基板101上的正投影均是本案的保护范围。并且，在图15所示图案层104同时覆盖同一行间隙处的两条第二信号线108的情况下，因岛状结构51位于各第一电极103的列间隙与两条第二信号线108的间隙交叉位置处，所以图15中的图案层104还覆盖了岛状结构51，即在第二信号线108和岛状结构51上均设置了图案层104。
通常在与显示基板相对而置的对向基板上，设置有维持显示基板与对向基板之间盒厚(Gap)稳定的隔垫物PS，且隔垫物PS与岛状结构51位置的配向层102接触。如图17所示，若配向层102在岛状结构51的位置产生聚集，则隔垫物PS抵住堆积的配向层102后，会导致岛状结构51的位置的盒厚增大，出现 盒厚不均一造成的显示不均(Mura)问题。本公开中通过在岛状结构51的位置设置可防止配向层102聚集的图案层104，使得在岛状结构51的位置，隔垫物PS接触的是膜厚均匀的配向层102，因此，不会出现盒厚增大的异常现象，从而有效解决了显示不均的问题，可选的，对于液晶显示面板而言，包括彩膜基板(例如上述对向基板)和阵列基板(例如上述显示基板)以及加设在彩膜基板和阵列基板之间的液晶，此时隔垫物PS可以是设置在彩膜基板一侧，则隔垫物PS的另外一端朝向阵列基板的岛状结构51，或者隔垫物PS可以是设置在阵列基板一侧，即直接设置在岛状结构51对应的位置，这里岛状结构51可以和数据线同层同材料直接制备，当隔垫物PS顶在岛状结构51的位置时，可以增加液晶显示面板的抗压能力。
需要说明的是，在本公开中隔垫物PS的位置不限于与岛状结构51的位置对应。在一些实施例中，如图18所示，隔垫物PS的位置还可以设置在第二信号线108所在区，即在显示基板与对向基板对盒后，隔垫物PS与第二信号线108所在区的配向层PI接触。但由于显示基板最上层的膜层为配向层PI，无论隔垫物PS的具体位置在哪，隔垫物PS均与配向层102接触，即配向层102包括用于设置隔垫物PS的站位区。且为了防止配向层102聚集引起的局部盒厚增大，可将隔垫物PS的站位区在衬底基板101上的正投影设置在图案层104在衬底基板101上的正投影内。
继续参见图16，在第一信号线105为数据线V data的情况下，在各第一电极103的一个行间隙处，一个岛状结构51可以与两个晶体管107的第一极分别电连接，并且其中一个晶体管107的栅极与一条第二信号线108电连接，另一个晶体管107的栅极与另一条第二信号线108电连接，其中一个晶体管107的第二极与该行间隙一侧奇数列的第一电极103电连接，另一个晶体管107的第二极与该行间隙另一侧偶数列的第一电极103电连接，这样就可以通过一条数据线V data为两列第一电极103加载信号，从而可节约数据线V data的数量及布线空间。可选地，节约出的布线空间可用于设置公共电极线V com，该公共电极线V com可与第二电极109电连接，由此使得第二电极109的整体电阻较低，同时第二 电极109上的电压均一性和稳定性也得到了提升。
在一些实施例中，如图16所示，第二电极109可以位于第一电极103所在层与衬底基板101之间，且第一电极103在衬底基板101上的正投影与第二电极109在衬底基板101上的正投影相互交叠，以使得第一电极103与第二电极109之间可以形成驱动液晶偏转的电场。可选地，第二电极109可以与晶体管107的栅极71同层设置。但为了保证透过率，第二电极109采用氧化铟锡(ITO)、氧化铟锡(IZO)、氧化锌(ZnO)等透明导电材料制作。为了使得栅极71的电阻较小，栅极71可采用金属材料、合金材料等制作。可选地，栅极71的材料可以包括钼(Mo)、铝(Al)、钛(Ti)、铜(Cu)等，栅极71可以为单层金属结构或多层金属结构，示例性地，多层金属结构可由层叠设置的钛金属层/铝金属层/钛金属层构成。另外，为满足透过率的要求，第一电极103也可以采用氧化铟锡(ITO)、氧化铟锡(IZO)、氧化锌(ZnO)等透明导电材料制作。在第一电极103为由第一条状电极31和第二条状电极32构成的狭缝电极的情况下，可通过狭缝进一步提高透过率。
值得注意的是，如图21、图23、图25、图33和图36所示，第一电极103可以为像素电极、第二电极109为公共电极，在一些实施例中，如图27至图29、图32所示，也可以设置第一电极103为公共电极，第二电极109为像素电极，即如图21、图23、图25、图33和图36所示，可以是像素电极有开缝设计形成的条状电极，公共电极为板状电极；或者，如图27至图29、图32所示，可以是公共电极有开缝设计的条状电极，像素电极为板状电极，在此不做具体限定。另外，本公开示出了第一电极103和第二电极109均位于显示基板上，但在一些实施例中，第一电极103和第二电极109也可以分别设置在显示基板和对向基板上，在此不做具体限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图19和图20所示，绝缘层106可以位于第一电极103所在层与第二电极109所在层之间，且第一电极103遮挡部分绝缘层106，未被的第一电极103遮挡的绝缘层106复用为图案层104，从而无需额外制作图案层104，即本案可以通过调整绝缘层 而不设置与第一电极103同层同材料的图案。在这种情况下，可以对绝缘层106的膜质进行工艺优化，使得绝缘层106的膜质更致密、粗糙度减小、接触角增大，从而可复用为图案层104。具体可通过调整制作绝缘层106的反应源气体的比值来改变绝缘层106的膜质。在一些实施例中，可以氨气(NH 3)和硅烷(SiH 4)作为反应源气体，且在氨气与硅烷的流量比大于等于2且小于等于8的情况下，所制作出的绝缘层106的接触角可满足大于等于35°且小于90°，例如绝缘层106的接触角为37.5°、52°、58.7°等。
需要说明的是，在本公开中不仅可以单独通过采用第一电极103的材料制作图案层104，或单独通过调节绝缘层106的膜质使得绝缘层106可复用为图案层104；还可以将这两种方案进行结合，即在采用绝缘层106复用为图案层104的基础上，还可以采用第一电极103的材料制作图案层104。并且，应当理解的是，在采用第一电极103的材料制作的图案层104形貌与第一电极103的局部形貌相同的情况下，可同时利用图案层104的倾斜条状结构、以及倾斜条状结构的间隙处的绝缘层106防止配向层102聚集。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图21至图25所示，在第一信号线105与第二信号线108交叉设置的位置，第一信号线105的线宽、以及第二信号线108的线宽均变小，这样可以减小第一信号线105与第二信号线108的正对面积，从而保证第一信号线105与第二信号线108之间的寄生电容较小，或者第一信号线105与第二信号线108二者中的一个宽度减小。
继续参见图21至图25，同列中相邻两个第二电极109通过连接电极110电连接，以使得同列第二电极109的电压均一性和稳定性较好，且使得相邻两行的第二电极109实现电连接。可选地，如图24所示，连接电极110与晶体管107的第一极72、第二极73同层、同材料。如图3所示，在第二电极109与晶体管107的第一极72、第二极73之间具有栅绝缘层111，因此，可通过在栅绝缘层111中打孔的方式，实现连接电极110与第二电极109的电连接。但由于相关技术中的栅绝缘层111采用开放式掩膜版(Open mask)制作，并不需要进行构图工艺。本公开若在栅绝缘层111中打孔以连接转接电极110与第二电极109，需 要增加一道构图工序。考虑到第一电极103通过贯穿绝缘层106的第一过孔V 1与晶体管107的第二极73电连接，且在第二电极109与第一电极103之间具有绝缘层106和栅绝缘层111，因此，可通过与第二电极109同层、同材料且与第二电极109相互绝缘的第一转接电极112，实现连接电极110与第二电极109的电连接。具体如图3和图26所示，在形成用于连接第一电极103与晶体管107的第二极73的第一过孔V 1的过程中，可同时形成贯穿绝缘层106且用于实现连接电极110与第一转接电极112电连接的第二过孔V 2，以及贯穿绝缘层106和栅绝缘层111且用于实现第二电极109与第一转接电极112电连接的第三过孔V 3，这样就避免了额外增加栅绝缘层111的构图工艺。
在一些实施例中，如图23、图27、图30和图32所示，同行中相邻两个第二电极109可以通过第三信号线113电连接，并且在图23中第三信号线113与同行中各第二电极109一体设置，在图27、图30和图32中第三信号线113与第二信号线108同层同材料设置。同行中相邻两个第二电极109通过第三信号线113电连接，可以使得同行中各第二电极109的电压均一性和稳定性较好。结合上文可知，在一些实施例中，还可通过连接电极110将同列中各第二电极109连接在了一起，在此情况下，各行、各列的第二电极109构成了一个电连接的整体，由此可以保证全部第二电极109具有优异的电压均一性和稳定性。可选地，在第一信号线105与第三信号线113交叉设置的位置，第一信号线105的线宽、以及第三信号线113的线宽均变小，这样可以减小第一信号线105与第三信号线113的正对面积，从而保证第一信号线105与第三信号线113之间的寄生电容较小。
在一些实施例中，如图24所示，在晶体管107的第一极72、第二极73所在层内，还设置有两个定位结构114，这两个定位结构114用于对隔垫物PS的位置进行定位，示例性地，隔垫物PS在显示基板上的正投影位置位于两个定位结构114之间的中间位置。另外，由图25可见，本公开中第一电极103为狭缝电极，每相邻两个狭缝之间的图案可以为第一条状电极31或第二条状电极32。
在一些实施例中，如图21和图24所示，第一信号线105可以为沿各第一电 极103的列间隙延伸的直线，或者，如图27、图31至图33、图35、图36所示，第一信号线105可以与第一电极103或第二电极109的条状电极延伸方向相同、形状相同，在此不做限定。另外，如图27、图29、图31和图32所示，还可以包括与第二电极109同层、同材料设置的第二转接电极115，以通过第二转接电极115实现晶体管107的第二极73与第一电极103的电连接。
在一些实施中，本公开实施例提供的晶体管107可以为顶栅型晶体管或底栅型晶体管。晶体管107可以为氧化物晶体管、非晶硅晶体管、多晶硅晶体管等。晶体管107可以为P型晶体管或N型晶体管，其中，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs<V th时导通，在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs≥V th时截止；N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs＞V th时导通，在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs≤V th时截止。另外，如图3所示，晶体管107还可以包括有源层74，且在有源层74与第一极72之间、以及有源层74与第二极73之间具有接触层75，以提高有源层74与第一极72、以及有源层74与第二极73之间的电连接效果。
基于同一发明构思，本公开实施例提供了一种上述显示基板的制作方法，如图37所示，可以包括以下步骤：
S3701、提供一个衬底基板101；
S3702、在衬底基板101上形成图案层104和第一电极103，其中，图案层104在衬底基板101上的正投影与第一电极103在衬底基板101上的正投影互不交叠，图案层104的接触角与第一电极103的接触角之比大于等于7/12且小于等于3/2；
S3703、在图案层104和第一电极103所在层上涂布配向液；
S3704、对配向液进行固化处理，形成配向层102。
在一些实施例中，在本公开实施例提供的上述制作方法中，上述步骤S3702、在衬底基板上形成图案层和第一电极，具体可以通过两种方式进行实现：其一，采用同一掩膜版，在衬底基板上形成同层、同材料设置的图案层 和第一电极。其二，采用两张掩膜版，分别在衬底基板上形成图案层和第一电极，图案层和第一电极位于同一层、且图案层的材料和第一电极的材料相同。
在一些实施例中，在本公开实施例提供的上述制作方法中，采用同一掩膜版，在衬底基板101上形成同层、同材料设置的图案层104和第一电极103，具体可以通过以下两种可能的方式进行实现：
第一种可能的实现方式可以包括以下步骤：
第一步，在衬底基板101上依次形成导电层和光刻胶层。
第二步，提供一个掩膜版，掩膜版仅具有用于制作第一电极103的图案。
第三步，将掩膜版的图案相对于待制作第一电极的区域偏移，使得掩膜版的图案同时与待制作第一电极103的区域、以及待制作图案层104的区域相互交叠。
第四步，在掩膜版的遮挡下，分时对待制作第一电极103的区域的光刻胶层、以及待制作图案层104的区域的光刻胶层进行曝光处理；
可选地，通过控制光源仅照射待制作第一电极103的区域或待制作图案层104的区域的光刻胶层，实现对待制作第一电极103的区域、以及待制作图案层104的区域的光刻胶层的分时曝光处理；或者，在光源照射整张掩膜版的情况下，可通过遮挡待制作图案层104的区域或待制作第一电极103的区域的光刻胶层，实现对待制作第一电极103的区域、以及待制作图案层104的区域的光刻胶层的分时曝光处理。
第五步，对光刻胶层进行显影处理，保留待制作第一电极103的区域的光刻胶层、以及待制作图案层104的区域的光刻胶层。
第六步，在光刻胶层的遮挡下，对导电层进行刻蚀，形成同层、同材料且断开设置的图案层104和第一电极103。
第二种可能的实现方式可以包括以下步骤：
第一步，在衬底基板101上依次形成导电层和光刻胶层。
第二步，提供一个掩膜版，掩膜版具有用于制作第一电极103的第一图案、 以及用于制作图案层104的第二图案，第一图案与第二图案断开设置。
第三步，在掩膜版的遮挡下，同时对待制作第一电极103的区域的光刻胶层、以及待制作图案层104的区域的光刻胶层进行曝光处理。
第四步，对光刻胶层进行显影处理，保留待制作第一电极103的区域的光刻胶层、以及待制作图案层104的区域的光刻胶层。
第五步，在光刻胶层的遮挡下，对导电层进行刻蚀，形成同层、同材料且断开设置的图案层104和第一电极103。
可选地，在上述两种可能的实现方式中，形成同层、同材料且断开设置的图案层104和第一电极103之后，还可以执行剥离光刻胶层的步骤。
在一些实施例中，在本公开实施例提供的上述制作方法中，上述步骤S2602、在衬底基板上形成图案层104和第一电极103，还可以通过以下方式进行实现：
以氨气和硅烷作为反应源气体形成整面设置的绝缘层106，氨气与硅烷的流量比大于等于2且小于等于8，例如氨气与硅烷的流量比可以为2、2.5、3、3.5、4、4.5、5、5.5、6、6.5、7、7.5、8等；
在衬底基板101所含像素开口区的绝缘层106上形成第一电极103，像素开口区之外的绝缘层106复用为图案层104。
可选地，在提供一个衬底基板101之后，且在以氨气和硅烷作为反应源气体形成整面设置的绝缘层106之前，还可以在衬底基板101上依次形成晶体管107的栅极71、第二电极109、栅绝缘层111、晶体管107的有源层74、同层设置的晶体管的第一极72、第二极73和连接电极110。并在以氨气和硅烷作为反应源气体形成整面设置的绝缘层106之后，且在像素开口区的绝缘层106上形成第一电极之前，还可以同时形成贯穿绝缘层106的第一过孔V 1、第二过孔V 2，以及贯穿绝缘层106和栅绝缘层111的第三过孔V 3，其中，第一过孔V 1用于实现晶体管107的第二极73与第一电极103的电连接，第二过孔V 2用于实现连接电极110与转接电极112的电连接，第三过孔V 3用于实现转接电极112与第二电极109的电连接。在一些实施例中，可在形成第一电极103的同时实现转接电 极112的制作。
需要说明的是，在本公开实施例提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板。由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在一些实施例中，本公开实施例提供的上述显示装置可应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。可选地，本公开实施例提供的上述显示装置为液晶显示屏。该液晶显示屏可以包括背光模组、以及位于背光模组出光侧的显示面板。其中，显示面板包括相对而置的显示基板和对向基板，位于显示基板和对向基板之间的液晶层，在显示基板和对向基板之间包围液晶层的密封胶，位于显示基板靠近液晶层一侧的第一配向层，位于对向基板靠近液晶层一侧的第二配向层，位于显示基板远离液晶层一侧的第一偏光片、以及位于对向基板远离液晶层一侧的第二偏光片等。背光模组可以为直下式背光模组，也可以为侧入式背光模组。背光模组可以包括光源、层叠设置的反射片、导光板、扩散片、棱镜组等。光源可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区域之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的上述显示装置可以包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (24)

  1. 一种显示基板，其中，包括：
    衬底基板；
    配向层，位于所述衬底基板之上；
    第一电极，位于所述衬底基板与所述配向层之间且与所述配向层接触；
    图案层，位于所述衬底基板与所述配向层之间且与所述配向层接触，所述图案层在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影互不交叠，所述图案层的接触角与所述第一电极的接触角之比大于等于7/12且小于3/2。
  2. 如权利要求1所述的显示基板，其中，所述图案层与所述第一电极同层、同材料设置。
  3. 如权利要求2所述的显示基板，其中，所述第一电极为多个，多个所述第一电极在所述衬底基板上呈阵列排布；
    所述图案层在所述衬底基板上的正投影位于各所述第一电极的行间隙在所述衬底基板上的正投影内。
  4. 如权利要求3所述的显示基板，其中，所述第一电极包括一体设置的第一条状电极和第二条状电极，所述第一条状电极的延伸方向与行方向、列方向、以及所述第二条状电极的延伸方向均交叉设置，所述第二条状电极的延伸方向与行方向、以及列方向均交叉设置；
    所述图案层沿所述第一条状电极的延伸方向和/或所述第二条状电极的延伸方向延伸。
  5. 如权利要求4所述的显示基板，其中，各所述第一电极的相邻两个行间隙处的所述图案层的延伸方向不同。
  6. 如权利要求4或5所述的显示基板，其中，所述图案层的线宽与其延伸方向相同的所述第一条状电极或所述第二条状电极的线宽相同，且所述图案层的线距与其延伸方向相同的所述第一条状电极或所述第二条状电极的线 距相同。
  7. 如权利要求3所述的显示基板，其中，所述图案层包括在各所述第一电极的同一行间隙处间隔设置有多个块状图案，且所述块状图案沿行方向延伸。
  8. 如权利要求4～7任一项所述的显示基板，其中，还包括第一信号线，所述第一信号线在所述衬底基板上的正投影位于各所述第一电极的列间隙在所述衬底基板上的正投影内；
    所述图案层在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影互不交叠。
  9. 如权利要求8所述的显示基板，其中，还包括晶体管，至少部分所述第一信号线与所述晶体管电连接；
    所述图案层在所述衬底基板上的正投影与所述晶体管在所述衬底基板上的正投影互不交叠。
  10. 如权利要求3所述的显示基板，其中，所述图案层包括在各所述第一电极的行间隙处沿行方向延伸的条状图案，所述条状图案在行方向上的长度与行间隙的长度相同。
  11. 如权利要求3～10任一项所述的显示基板，其中，还包括第二信号线，所述第二信号线在所述衬底基板上的正投影位于各所述第一电极的行间隙在所述衬底基板上的正投影内；
    所述图案层在所述衬底基板上的正投影位于所述第二信号线在所述衬底基板上的正投影内。
  12. 如权利要求11所述的显示基板，其中，所述图案层在列方向上的宽度与所述第二信号线在列方向上的宽度之比大于等于3/5且小于等于1。
  13. 如权利要求3所述的显示基板，其中，还包括第二信号线，所述第二信号线在所述衬底基板上的正投影位于各所述第一电极的行间隙在所述衬底基板上的正投影内，同一行间隙处对应设置有两条所述第二信号线；
    在各所述第一电极的同一行间隙处，两条所述第二信号线在所述衬底基 板上的正投影位于所述图案层在所述衬底基板上的正投影内。
  14. 如权利要求3所述的显示基板，其中，还包括交叉设置且相互绝缘的第一信号线和第二信号线，其中，所述第一信号线在所述衬底基板上的正投影位于各所述第一电极的列间隙在所述衬底基板上的正投影内，所述第一信号线包括位于列间隙与两条所述第二信号线的间隙交叉位置处的岛状结构；
    所述图案层在所述衬底基板上的正投影与所述岛状结构在所述衬底基板上的正投影重合。
  15. 如权利要求2所述的显示基板，其中，还包括第二信号线和栅极，所述第二信号线与所述栅极为一体结构且所述栅极相对于所述第二信号线凸出设置；
    所述图案层包括与行方向、列方向均交叉设置的多个第一分部，以及沿行方向延伸的第二分部，所述第一分部在所述衬底基板上的正投影位于所述栅极在所述衬底基板上的正投影内，所述第二分部在所述衬底基板上的正投影位于所述第二信号线在所述衬底基板上的正投影内。
  16. 如权利要求1所述的显示基板，其中，还包括位于所述第一电极所在层与所述衬底基板之间的第二电极，所述第一电极在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影相互交叠。
  17. 如权利要求16所述的显示基板，其中，还包括位于所述第一电极所在层与所述第二电极所在层之间的绝缘层，所述第一电极遮挡部分所述绝缘层，未被的所述第一电极遮挡的所述绝缘层复用为所述图案层。
  18. 如权利要求1～17任一项所述的显示基板，其中，所述配向层包括用于设置隔垫物的站位区，所述站位区在所述衬底基板上的正投影位于所述图案层在所述衬底基板上的正投影内。
  19. 一种如权利要求1～18任一项所述显示基板的制作方法，其中，包括：
    提供一个衬底基板；
    在所述衬底基板上形成图案层和第一电极，其中，所述图案层在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影互不交叠，所 述图案层的接触角与所述第一电极的接触角之比大于等于7/12且小于等于3/2；
    在所述图案层和所述第一电极所在层上涂布配向液；
    对所述配向液进行固化处理，形成配向层。
  20. 如权利要求19所述的制作方法，其中，在所述衬底基板上形成图案层和第一电极，具体包括：
    采用同一掩膜版，在所述衬底基板上形成同层、同材料设置的图案层和第一电极。
  21. 如权利要求20所述的制作方法，其中，采用同一掩膜版，在所述衬底基板上形成同层、同材料设置的图案层和第一电极，具体包括：
    在所述衬底基板上依次形成导电层和光刻胶层；
    提供一个掩膜版，所述掩膜版仅具有用于制作第一电极的图案；
    将所述掩膜版的图案相对于待制作所述第一电极的区域偏移，使得所述掩膜版的图案同时与待制作所述第一电极的区域、以及待制作图案层的区域相互交叠；
    在所述掩膜版的遮挡下，分时对待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层进行曝光处理；
    对所述光刻胶层进行显影处理，保留待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层；
    在所述光刻胶层的遮挡下，对所述导电层进行刻蚀，形成同层、同材料且断开设置的所述图案层和所述第一电极。
  22. 如权利要求20所述的制作方法，其中，采用同一掩膜版，在所述衬底基板上形成同层、同材料设置的图案层和第一电极，具体包括：
    在所述衬底基板上依次形成导电层和光刻胶层；
    提供一个掩膜版，所述掩膜版具有用于制作第一电极的第一图案、以及用于制作图案层的第二图案，所述第一图案与所述第二图案断开设置；
    在所述掩膜版的遮挡下，同时对待制作所述第一电极的区域的所述光刻胶 层、以及待制作所述图案层的区域的所述光刻胶层进行曝光处理；
    对所述光刻胶层进行显影处理，保留待制作所述第一电极的区域的所述光刻胶层、以及待制作所述图案层的区域的所述光刻胶层；
    在所述光刻胶层的遮挡下，对所述导电层进行刻蚀，形成同层、同材料且断开设置的所述图案层和所述第一电极。
  23. 如权利要求20所述的制作方法，其中，在所述衬底基板上形成图案层和所述第一电极，具体包括：
    以氨气和硅烷作为反应源气体形成整面设置的绝缘层，氨气与硅烷的流量比大于等于2且小于等于8；
    在所述衬底基板所含像素开口区的所述绝缘层上形成第一电极，所述像素开口区之外的所述绝缘层复用为图案层。
  24. 一种显示装置，其中，包括如权利要求1～18任一项所述的显示基板。
PCT/CN2022/102459 2022-06-29 2022-06-29 显示基板、其制作方法及显示装置 WO2024000301A1 (zh)

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