WO2023287569A1

WO2023287569A1 - Vias including a plurality of traces, devices including the vias, and methods for fabricating the vias

Info

Publication number: WO2023287569A1
Application number: PCT/US2022/035101
Authority: WO
Inventors: Qiumei Bian; Donald Seton Farquhar; Rajesh Vaddi
Original assignee: Corning Incorporated
Priority date: 2021-07-13
Filing date: 2022-06-27
Publication date: 2023-01-19
Also published as: TW202303554A

Abstract

A through glass via (TGV) includes a first glass substrate, a first through-hole, and a plurality of electrically conductive first traces. The first glass substrate includes a first surface and a second surface opposite to the first surface. The first through-hole includes sidewalls extending through the first glass substrate from the first surface to the second surface. The plurality of electrically conductive first traces are on the sidewalls of the first through-hole and extend through the first glass substrate from the first surface to the second surface.

Description

VIAS INCLUDING A PLURALITY OF TRACES, DEVICES INCLUDING THE VTAS. AND METHODS FOR FABRICATING THFVTAS

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application Serial No.: 63/221,064, filed on July 13, 2021, the content of which is relied upon and incorporated herein by reference in its entirety.

BACKGROUND

Field

[0002] The present disclosure relates generally to vias for electrical interconnects. More particularly, it relates to vias for electrical interconnects including a plurality of electrically conductive traces.

Technical Background

[0003] The desire for miniaturization and improved electrical performance has resulted in the emergence of 3D and 2.5D chip stacking architectures, which use vertical electrical interconnects. These vertical interconnects may be fabricated by forming holes through substrates and forming a conductive path within each hole, resulting in short interconnects having a high electrical performance. Through-silicon via (TSV) has been the most prominent vertical interconnect. The challenges associated with 3D stacking of chips, however, has shifted attention to 2.5D chip stacking architectures, as 2.5D chip stacking architectures are less expensive and present fewer integration challenges. The 2.5D chip stacking architectures may be realized by the use of non-active substrates (having no integrated front end devices) with vertical interconnects, which are often referred to as interposers. Interposer substrates may be made of silicon or glass.

[0004] Glass interposers with through-glass vias (TGV) are attractive due to the many advantages of glass over silicon that includes lower cost, tunable coefficient of thermal expansion (CTE), and superior high frequency performance. TGVs, however, provide one interconnect per via. In addition, the formation of TGVs presents thermo -mechanical challenges that arise due to the CTE mismatch b etween the glass matrix (e .g. , ab out 0.6 ppm/°C for fused silica) and the metal fill (e.g., Cu is about 16.7 ppm/°C). This CTE difference leads to high stress buildup that results in different failure modes, such as cracks in the substrate, via voiding, sidewall delamination, etc. SUMMARY

[0005] Some embodiments of the present disclosure relate to a via. The via includes a first dielectric substrate, a first through -hole, and a plurality of electrically conductive first traces. The first dielectric substrate includes a first surface and a second surface opposite to the first surface. The first through-hole includes sidewalls extending through the first dielectric substrate from the first surface to the second surface. The plurality of electrically conductive first traces are on the sidewalls of the first through-hole and extend through the first dielectric substrate from the first surface to the second surface.

[0006] Yet other embodiments of the present disclosure relate to a device. The device includes a glass substrate, a through-hole, an electronic component, and a plurality of electrically conductive traces. The glass substrate includes a first surface and a second surface opposite to the first surface. The through-hole includes sidewalls extending through the glass substrate from the first surface to the second surface. The electronic component is attached to the first surface of the glass substrate. The plurality of electrically conductive traces are electrically coupled to the electronic component. Each trace of the plurality of traces extends on a sidewall of the through-hole through the glass substrate from the first surfaceto the second surface.

[0007] Yet other embodiments of the present disclosure relate to a method for fabricating a device. The method includes forming a through-hole through a glass substrate including a first surface and a second surface opposite to the first surface such that the through-hole extends through the glass substrate from the first surface to the second surface. The method further includes forming a plurality of electrically conductive traces on sidewalls of the through-hole extending from the first surface to the second surface.

[0008] Yet other embodiments of the present disclosure relate to a device. The device includes a glass substrate, a blind hole, an electronic component, and a plurality of electrically conductive traces. The glass substrate includes a first surface and a second surface opposite to the first surface. The blind hole is within the glass substrate and includes sidewalls extending into the glass substrate from the first surface and a bottom surface extending between the sidewalls. The electronic component is attached to the bottom surface of the blind hole. The plurality of electrically conductive traces are electrically coupled to the electronic component. Each trace of the plurality of traces extends on the bottom surface of the blind hole, a sidewall of the blind hole, and the first surface of the glass substrate. [0009] Yet other embodiments of the present disclosure relate to a micro light emitting diode (microLED) display. The microLED display includes a glass substrate, a matrix backplane, a driver component, a firstthrough-hole, and a second through-hole. The glass substrate includes a first surface and a second surface opposite to the first surface. The matrix backplane is on the first surface and includes an array of microLEDs arranged in rows and columns, a plurality of row lines corresponding to the rows of microLEDs, and a plurality of column lines corresponding to the columns of microLEDs. The driver component is on the second surface of the glass substrate. The firstthrough-hole extends through the glass substrate from the first surface to the second surface. The second through-hole extends through the glass substrate from the first surface to the second surface. The plurality of row lines are electrically coupled to the driver component through the first through -hole and the plurality of column lines are electrically coupled to the driver component through the second through-hole.

[0010] By includingmultiple(e.g., atleast two) electrically conductive traces within one via, the interconnect density of a device may be improved. Compared to vias providing a single interconnect, vias providing multiple interconnects may have a larger diameter or width, which may be easier to fabricate and have a reduced cost. In addition, multiple electrically conductive traces within one via may reduce the stress within the via compared to vias providing a single interconnect.

[0011] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.

[0012] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description explain principles and operation of the various embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIGS. 1 A-1C are a top view and cross-sectional views, respectively, of exemplary vias including a plurality of electrically conductive traces; [0014] FIGS. 2A-2C are a top view and cross-sectional views, respectively, of exemplary tapered vias including a plurality of electrically conductive traces;

[0015] FIGS. 3 A-3D are top views of a via during each step of an exemplary process for fabricating the via;

[0016] FIGS. 4 A-4F are top views of exemplary vias having different shapes and including a plurality of electrically conductive traces;

[0017] FIG. 5 is an isometric view of an exemplary device including a via including a plurality of electrically conductive traces;

[0018] FIG. 6 is an isometric view of an exemplary device including a blind hole with a plurality of electrically conductive traces extending on surfaces of the blind hole;

[0019] FIGS. 7A-7F are simplified cross-sectional views of exemplary multilayer interconnect structures;

[0020] FIGS. 8A and 8B are a top view and a cross-sectional view, respectively, of an exemplary micro light emitting diode (microLED) display; and

[0021] FIGS. 9A-9C are flow diagrams illustrating an exemplary method for fabricating a device including a via including a plurality of electrically conductive traces.

DETAILED DESCRIPTION

[0022] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0023] Ranges can be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

[0024] Directional terms as used herein - for example up, down, right, left, front, back, top, bottom, vertical, horizontal - are made only with reference to the figures as drawn and are not intended to imply absolute orientation. [0025] Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order, nor that with any apparatus, specific orientations be required. Accordingly, where a method claim does not actually recite an orderto be followed by its steps, orthat any apparatus claim does not actually recite an order or orientation to individual components, or it is not otherwise specifically stated in the claims or description that the steps are to be limited to a specific order, or that a specific order or orientation to components of an apparatus is not recited, it is in no way intended that an order or orientation be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps, operational flow, order of components, or orientation of components; plain meaning derived from grammatical organization or punctuation, and; the number or type of embodiments described in the specification.

[0026] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a” component includes aspects having two or more such components, unless the context clearly indicates otherwise.

[0027] In through silicon vias (TSVs) and through glass vias (TGVs), as well as printed wiring boards (PWBs), a single conductive path is provided for each via, such as by a plated through hole (PTH). The ability to connect one layer to another layer increases interconnect density, and may generally be referred to as z-interconnect. Z-interconnect may be used at all levels of packaging from board, to module, to chip including 2.5D and 3D chip stacking architectures. Z-interconnect features between inner or outer layers may be used in combination with circuit features on layers that provide fan out or redistribution.

[0028] To provide a more dense interconnect structure than can be provided by vias including a single conductive path (i.e., single conductor vias), disclosed herein are vias including multiple conductive paths through a single through-hole (i.e., multiple conductor vias). The disclosed multiple conductor vias are particularly suited to applications that utilize TGV s due to the improved ease and reduced cost of f abri cation, increased interconnect density, and lower stress configuration. The disclosed multiple conductor vias may be applicable to microelectromechanical (MEMs) devices, wafer caps, TSV alternatives, and display technologies. The disclosed vias may also be used for making more complex interposers and interconnect devices (e.g., multilayer interconnect structures) for semiconductor packaging. [0029] Referring now to FIGS. 1A and IB, a top view and a cross-sectional view, respectively, of an exemplary via 100a is depicted. Via 100a includes a substrate (e.g., a first glass or other dielectric substrate) 102, a through-hole (e.g., a first through-hole) 108, and a plurality of electrically conductive traces (e.g., first traces) 112ao to 112a₃. The substrate 102 includes a first surface (e.g., bottom surface) 104 and a second surface (e.g., top surface) 106. The through -hole 108 includes sidewalls 110 extending through the sub strate 102 from the first surface 104 to the second surface 106. The plurality of electrically conductive traces 112ao to 112a₃ are on the sidewalls 110 of the through-hole 108 and extend through the substrate 102 from the first surface 104 to the second surface 106. In certain exemplary embodiments, the sidewalls 110 of the through -hole 108 are perpendicular to the first surface 104 and the second surface 106 ofthe sub strate 102. Each electrically conductive trace 112a₀to 112a₃ also partially extends on the first surface 104 and the second surface 106 of the substrate 102. Each electrically conductive trace 112a₀ to 112a₃ may be electrically coupled to circuit(s), component(s), etc. (not shown) on the first surface 104 and/or on the second surface 106 of the substrate 102. Dependingupon the particular design of a device including a via 100a, aportion ofthe electrically conductive traces 112a₀ to 112a₃ may be formed but unused (e.g., are not electrically coupled to circuit(s), component(s), etc.)

[0030] In certain exemplary embodiments, substrate 102 is a glass substrate, a ceramic substrate (e.g., A1₂0₃), or a glass-ceramic substrate. In other embodiments, substrate 102 may include Alumina, AIN, Quartz (Sapphire), InGaN, GaAs, InGaAs, GaP, GaSb, InP, InAs, InSb, GaN on Sapphire, SOI, SIMOX, Ge, crystal aluminum oxide (Garnet), or another suitable material or combination thereof. In other embodiments, substrate 102 may include any suitable dielectric material. For example, substrate 102 may include an organic dielectric material, such as an epoxy, polyimide, or fluoropolymer with or without organic and/or inorganic fillers and reinforcements that tailor the material properties. In certain exemplary embodiments, the substrate 102 may, for example, have a thickness between the first surface 104 and the second surface 106 within a range from about 0.3 millimeters to about 2 millimeters.

[0031] Each electrically conductive trace 112ao to 112a₃ may include copper or another suitable electrically conductive material. While via 100a includes four electrically conductive traces 112a₀to 112a₃ as illustrated in FIG. 1 A, in other embodiments, via 100a may include less than four traces (e.g., 2 or 3) or more than four traces (e.g., 5 or more).

[0032] FIG. 1C is a cross-sectional view of an exemplary via 100b. Via 100b is similar to via 100a previously described and illustrated with reference to FIGS. 1 A and IB, exceptthat via 100b includes a plurality of electrically conductive traces 112b₀ to 112b₃ (112b₀ and 112bi are not visible in FIG. 1C) in place of the plurality of electrically conductive traces 112ao to 112a₃. For via 100b, the plurality of electrically conductive traces 112boto 112b₃ extend on the sidewalls HO ofthethrough-hole 108 but not on the first surface 104 andthe secondsurface 106 of the substrate 102. Such arrangement of traces 112bo to 112b₃ may be used in multilayer interconnect structures as will be described below with reference to FIGS. 7A-7F.

[0033] FIGS. 2A and 2B are a top view and a cross-sectional view, respectively, of an exemplary tapered via 200a. Via 200a includes a substrate (e.g., a first glass or other dielectric substrate) 102, a tapered through-hole (e.g., first tapered through-hole) 208, and a plurality of electrically conductive traces (e.g., first traces) 212aoto 212a₃. The substrate 102 includes a first surface (e.g., bottom surface) 104 and a secondsurface (e.g., top surface) 106. The tapered through-hole 208 includes tapered sidewalls 210 extending through the substrate 102fromthe first surface 104 to the second surface 106. The width or diameter ofthe tapered through-hole 208 at the first surface 104 is less than the width or diameter of the tapered through-hole 208 at the second surface 106. The plurality of electrically conductive traces 212a₀ to 212a₃ are on the tapered sidewalls 210 of the tapered through-hole 208 and extend through the substrate 102 from the first surface 104 to the second surface 106. In certain exemplary embodiments, the tapered sidewalls 210 of the tapered through-hole 208 have an angle 214 with respect to the first surface 104 within a range between about 45 degrees and about 89 degrees and a corresponding angle 216 with respect to second surface 106 within a range between about 91 degrees and about 135 degrees. In other embodiments, angles 214 and 216 may have other suitable values. Each electrically conductive trace 212a₀ to 212a₃ also partially extends on the first surface 104 andthe second surface 106 of the substrate 102. Each electrically conductive trace 212a₀ to 212a₃ may be electrically coupled to circuit(s), component(s), etc. (not shown) on the first surface 104 and/or on the second surface 106 of the substrate 102.

[0034] Each electrically conductive trace 212ao to 212a₃ may include copper or another suitable electrically conductive material. While via 200a includes four electrically conductive traces 212a₀ to 212a₃ as illustrated in FIG. 2 A, in other embodiments, via 200a may include less than four traces (e.g., 2 or 3) or more than four traces (e.g., 5 or more). The tapered sidewalls 210 of the tapered through-hole 208 may simplify the fabrication of tapered via 200a when using line-of-sight deposition techniques such as sputtering or other processes to form the traces 212a₀ to 212a₃.

[0035] FIG. 2C is a cross-sectional view of an exemplary via 200b. Via 200b is similar to via 200a previously described and illustrated with reference to FIGS. 2 A and 2B, except that via 200b includes a plurality of electrically conductive traces 212b₀ to 212b₃ (212b₀ and 212bi are not visible in FIG. 2C) in place of the plurality of electrically conductive traces 212ao to 212a₃. For via 200b, the plurality of electrically conductive traces 212bo to 212b₃ extend on the tapered sidewalls 210 of the tapered through-hole 208 but not on the first surface 104 and the second surface 106 of the substrate 102. Such arrangement of traces 212t>o to 212t>₃ may be used in multilayer interconnect structures as will be described below with ref erenceto FIGS. 7A-7F.

[0036] FIGS. 3A-3D are top views of a multiple conductor via during each step of an exemplary process for fabricating the multiple conductor via in a substrate 102. As shown in FIG. 3A, a through-hole 300 is formed through the substrate 102. In certain exemplary embodiments, the through-hole 300 may be formed by laser damaging the substrate 102 and etching the damaged substrate to remove the damaged portions of the substrate. In other embodiments, the through-hole 300 may be formed using other suitable processes.

[0037] In the exemplary embodiment where the through-hole 300 is formed via laser damaging and etching, damage tracks may be formed, for example, in a 0.4 millimeter thick 100 millimeter diameter glass wafer using a 532 nanometer picosecond pulsed laser. A 12 watt and 100 kilohertz Gaussian-Bessel laser beam may be focused on the wafer surface to create uniform damage tracks. The wafer may then be rinsed in deionized (DI) water for about 10 minutes. The wafer may then be placed in a bath of 9.8 percent (w/w) aqueous hydrofluoric acid solution for about 300 minutes (removing about 100 micrometers of glass). This process may have an etch rate of about 0.3 -0.5 micrometers/minute. A 138 kilohertz ultrasonic agitation may be applied in the etching process to improve the etching process speed and uniformity. The wafer may then be rinsed in DI water for about 10 minutes. In this example, the through-hole 300 may have an entry diameter of about 450 micrometers with a segment pitch of about 70 micrometers with 26 percent taper. Due to the process used to form the through-hole 300 in this embodiment, the sidewalls of the through -hole 300 may have a scalloped shape as shown in FIG. 3 A. In certain exemplary embodiments, the scalloped shape is the result of a hole formation process termed “trepanning”, where multiple damage tracks are configured to form the outer perimeter of the desired hole, which may have any cross- sectional shape.

[0038] With through-hole 300 formed, the through-hole 300 may be metallized as indicated by metallization 302 in FIG. 3B. In certain exemplary embodiments, the sidewalls of the through-hole 300 may be metallized using a plating process, a sputtering process, or other suitable metal deposition process. In other embodiments, the sidewalls of the through -hole 300 may be coated with a non-metallic conductor, such as indium tin oxide (ITO). In general, a plating process may be subject to a minimum through-hole 300 diameter and/or maximum substrate 102 thickness. Methods for platingthrough-holes of about25 micrometers or smaller are known, and methods for plating through -holes having aspect ratios (thickness to diameter) of up to about 6:1 or more are known. It is generally easier to plate lower aspect ratio through- holes, such as through-holes having aspect ratios closer to 1 : 1. In addition, a tapered through- hole as previously described and illustrated with reference to FIGS. 2A-2C is generally easier to plate, especially when using line of sight deposition techniques.

[0039] In a certain exemplary embodiment, a plating process may include an ultrasonic cleaning process followed by an electroless deposition process. An electroless copper plating process may include immersion in a tin-palladium activator for about 8 minutes, a DI water rinse, immersion in an accelerator solution for about 3 minutes, and finally immersion in an electroless copper sulfate bath maintained at about 35 degrees Celsius for about 5 minutes. In this example, the plating rate is about 30 nanometers/minute, resulting in a plating thickness of about 150 nanometers for the copper thin film. The plating process could be continued to provide a substantially thicker copper thin film if desired for the application.

[0040] With the metallization 302 formed, the metallization 302 may be segmented to form a plurality of conductors (e.g., traces) 306 as shown in FIG. 3C. In certain exemplary embodiments, the metallization 302 may be segmented using laser ablation as indicated at 304. For example, a 1064 nanometer pulsed picosecond laser may be used to segment the copper thin film. Removal of about 3 to 5 micrometers of copper thin film may be implemented with 30 watts laser power and a 200 kilohertz repetition rate. The scanning speed may be about 200 millimeters/second. In other embodiments, metallization 302 may be segmented using other suitable processes, such as etching, mechanical grinding, etc.

[0041] With the metallization 302 segmented, the via with a plurality of conductors 306 is complete as shown in FIG. 3D. As shown in FIG. 3D, 20 individual conductors 306 through a single through-hole 300 were formed in this embodiment. In other embodiments, less than 20 conductors or more than 20 conductors may be formed using a similar process. Using multiple conductor vias as disclosed herein may significantly reduce (e.g., by a factor of up to about 16 or more) the number of through-holes used for interconnections within a device compared to when using single conductor vias. The aspect ratio of the vias may also be significantly reduced. A lower aspect ratio allows line-of-sight deposition techniques such as sputtering to be used to coatthe via sidewall with a conductive material. In certain exemplary embodiments, instead of segmenting a metallization 302 on the sidewalls of the through -hole 300 as described with reference to FIG. 3C, the metallization 302 may be selectively applied to predetermined portions (e.g., via lithography processes) of the sidewalls of the through-hole to form the plurality of electrically conductive traces 306. [0042] FIG. 4A is a simplified top view of an exemplary via 400. Via 400 includes a substrate 102, a through-hole 402, and a plurality of electrically conductive traces 404₀ to 404₃. In this embodiment, through-hole 402 comprises a cross-section that is circular shaped and includes four traces 404₀ to 404₃ on sidewalls of the through-hole 402 extending through the substrate 102 and substantially equally spaced around the through-hole 402. In this embodiment, one trace 404₀ is arranged on a first side of through-hole 402, one trace 404₄ is arranged on a second side of through-hole 402, one trace 404₂ is arranged on a third side of through-hole 402, and one trace 404₃ is arranged on a fourth side of through-hole 402. Each trace 404₀ to 404₃ may be electrically coupled to circuit(s), component(s), etc. on either surface of the substrate 102.

[0043] FIG. 4B is a simplified top view of an exemplary via 410. Via 410 includes a substrate 102, athrough-hole412, and a plurality of electrically conductive traces 414₀ to 414₆. In this embodiment, through-hole 412 comprises a cross-section that is oval shaped and includes seven traces 414₀ to 414₆ on sidewalls of the through-hole 412 extending through the substrate 102. Three traces 414₀ to 414₂ are arranged on a first side of through-hole 412, one trace 414₃ is arranged on a second side of through-hole 412, two traces 414₄ to 414₅ are arranged on a third side of through -hole 412, and one trace 414₆ is arranged on a fourth side of through-hole 412. Each trace 414₀ to 414₆ may be electrically coupled to circuit(s), component(s), etc. on either surface of the substrate 102.

[0044] FIG. 4C is a simplified top view of an exemplary via 420. Via 420 includes a substrate 102, a through -hole 422, and a plurality of electrically conductive traces 424₀ to 424₈. In this embodiment, through-hole 422 comprises a cross-section that is square shaped and includes nine traces 424₀ to 424₈ on sidewalls of the through-hole 422 extending through the substrate 102. Three traces 424₀ to 424₂ are arranged on a first side of through -hole 422, two traces 424₃ to 424₄ are arranged on a second side of through-hole 422, one trace 424₅ is arranged on a third side of through-hole 422, and three traces 424₆ to 424₈ are arranged on a fourth side of through-hole 422. Each trace 424₀ to 424₈ may be electrically coupled to circuit(s), component(s), etc. on either surface of the substrate 102.

[0045] FIG. 4D is a simplified top view of an exemplary via 430. Via 430 includes a substrate 102, a through-hole 432, and a plurality of electrically conductive traces 434₀ to 434₉. In this embodiment, through-hole 432 comprises a cross-section that is rectangular shaped and includes ten traces 434₀ to 434₉ on sidewalls of the through-hole 432 extending through the substrate 102. Four traces 434₀ to 434₃ are arranged on a first side of through-hole 432, one trace 434 is arranged on a second side of through-hole 432, two traces 434₅ to 434₆ are arranged on a third side of through-hole 432, and three traces 434₇ to 434₉ are arranged on a fourth side of through-hole 432. Each trace 434₀ to 434₉ may be electrically coupled to circuit(s), component(s), etc. on either surface of the substrate 102.

[0046] FIG. 4E is a simplified top view of an exemplary via 440. Via 440 includes a substrate 102, a through-hole 442, and a plurality of electrically conductive traces 444₀ to 444₅. In this embodiment, through-hole 442 comprises a cross-section that is hexagon shaped and includes six traces 444₀ to 444₅ on sidewalls of the through-hole 442 extending through the substrate 102. One trace 444₀ is arranged on a first side of through-hole 442, two traces 444i to 444₂ are arranged on a second side of through-hole 442, no traces are arranged on a third side of through-hole 442, one trace 444₃ is arranged on a fourth side of through-hole 442, no traces are arranged on a fifth side of through-hole 442, and two traces 444₄to 444₅ are arranged on a sixth side of through-hole 442. Each trace 444₀ to 444₅ may be electrically coupled to circuit(s), component(s), etc. on either surface of the substrate 102.

[0047] FIG. 4F is a simplified top view of an exemplary via 450. Via 450 includes a substrate 102, a through-hole 452, and a plurality of electrically conductive traces 454₀ to 454₄. In this embodiment, through-hole 452 comprises a cross-section that is triangular shaped and includes five traces 454₀ to 454₄ on sidewalls of the through-hole 452 extending through the substrate 102. One trace 454₀ is arranged on a first side of through-hole 452, one trace 454i is arranged on a first corner of through-hole 452, one trace 454₂ is arranged on a second side of through-hole 452, one trace 454₃ is arranged on a second corner of through-hole 452, no traces are arranged on a third side of through-hole 452, and one trace 454₄ is arranged on a third corner of through-hole 452. Each trace 454₀ to 454₄ may be electrically coupled to circuit(s), component(s), etc. on either surface of the substrate 102.

[0048] While FIGS. 4 A-4F include a plurality of exemplary vias having different shapes and including different pluralities of electrically conductive traces, in other examples, the vias may include other shapes (e.g., polygonal shapes, freeform cross-sectional shapes, etc.) and include different numbers of electrically conductive traces having different arrangements. In any embodiment, each via includes at least two electrically conductive traces on sidewalls of a single through-hole extending through a substrate. The vias may be fabricated using the trepanning process previously described.

[0049] FIG. 5 is an isometric view of an exemplary device 500. Device 500 includes a substrate 102, a through -hole 502, a plurality of electrically conductive traces 504₀ to 504₃, an electronic component 506 (e.g., a semiconductor chip), and a plurality of contact pads 508₀ to 508₃. The substrate 102 includes a first surface 104 and a second surface 106 opposite to the first surface 104. The through-hole 502includes sidewalls extendingthrough the substrate 102 from the first surface 104 to the second surface 106. In this embodiment, through-hole 502 comprises a cross-section that is oval shaped. In other embodiments, however, through-hole 502 may have another suitable shape. The electronic component 506 is attached to the first surface 104 of the substrate 102 (e.g., via an adhesive material). The plurality of electrically conductive traces 504₀ to 504₃ are electrically coupled to the electronic component 506. Each trace 504₀to 504₃ extends on a sidewall of the through -hole 502 through the substrate 102 from the first surface 104 to the second surface 106. In other embodiments, additional electrically conductive traces (not shown) may extend on a sidewall of the through-hole 502 through the substrate 102 from the first surface 104 to the second surface 106 that are not electrically coupled to the electronic component 506. In certain exemplary embodiments, each trace 504₀ to 504₃ further extends on the first surface 104 and the second surface 106 of the substrate 102. Each contactpad 508₀ to 508₃ is on the second surface 106 of the substrate 102. Each contact pad 508₀ to 508₃ may be electrically coupled to a respective trace 504₀ to 504₃. In other embodiments (not shown), device 500 may include a plurality of through-holes each comprising sidewalls extending through the substrate 102 from the first surface 104 to the second surface 106. In such an embodiment, a plurality of electrically conductive traces (e.g, at least two traces) are on the sidewalls of each through-hole and extend through the substrate 102 from the first surface 104 to the second surface 106.

[0050] FIG. 6 is an isometric view of an exemplary device 600. Device 600 includes a substrate 102, a blind hole 602, a plurality of electrically conductive traces 604₀ to 604₉, and an electronic component 606 (e.g., a semiconductor chip). The substrate 102 includes a first surface 104 and a second surface 106 opposite to the first surface 104. The blind hole 602 is within the substrate 102 and includes sidewalls 608₀ to 608₃ extending into the substrate 102 from the first surface 104 and a bottom surface 610 extending between the sidewalls 608₀to 608₃. The electronic component 606 is attached to the bottom surface 610 of the blind hole 602 (e.g. , via an adhesive material). The plurality of electrically conductive traces 604₀ to 604₉ are electrically coupled to the electronic component 606. Each trace 604₀ to 604₉ extends on the bottom surface 610 of the blind hole 602, a sidewall 608₀ to 608₃ of the blind hole 602, and the first surface 104 of the substrate 102. Each trace 604₀ to 604₉ may be electrically coupled to other circuit(s), component(s), etc. (not shown) on the first surface 104 of the substrate 102. [0051] The plurality of traces 604₀ to 604₉ include first traces 604₀ to 604₂ extending on a first sidewall 608₀ of the blind hole 602 and second traces 604₅ to 604₇ extending on a second sidewall 608₂ of the blind hole 602 opposite to the first sidewall 608₀. The plurality of traces 604o to 604₉ include third traces 604₃ to 604₄ extending on a third sidewall 6081 of the blind hole 602 and fourth traces 604₈ to 604₉ extending on a fourth sidewall 608₃ of the blind hole 602 opposite to the third sidewall 608_3. While blind hole 602 of device 600 is rectangular shaped, in other embodiments, blind hole 602 may have another suitable shape (e.g., circular or oval cross-sectional shape). In addition, while blind hole 602 of device 600 includes sidewalls 608₀ to 608₃ that are perpendicular to the first surface 104 and the bottom surface 610, in other embodiments, sidewalls 608₀ to 608₃ may be tapered between the first surface 104 and the bottom surface 610.

[0052] FIG. 7 A is a simplified cross-sectional view of an exemplary multilayer interconnect structure 700 including a TGV 710. Multilayer interconnect structure 700 includes two substrates 702₀ to 7021 (e.g., glass or other dielectric substrates). Each substrate 702₀ to 702₃ includes a first surface 704₀ to 7041 and a second surface 706₀to 706i opposite to the first surface 704₀to 704₃, respectively. A through-hole 712₀ to 712₃ includes sidewalls extending through the substrate 702₀ to 702_| from the first surface 704₀ to 7041 to the second surface 706₀ to 706i, respectively. A plurality of electrically conductive trace portions 716o_,o-716_{0 i} to 716_{1 0}-716_i 1 on sidewalls of the through-holes 712₀ to 7121 extend through the sub strates 702₀ to 702i from the first surface 704₀ to 7041 to the second surface 706₀to706i, respectively. The substrates 702₀ to 702i are bonded to each other (e.g., as indicated at 708₀) such that the through-holes 712₀ to 712_\ are aligned and the plurality of electrically conductivetrace portions 716_{0 O}-716_{0 I} to 716i ₀-716i i are electrically coupled to form traces 714₀ to 714₃, respectively. Each trace 714₀ to 714₃ may be electrically coupled to circuit(s), component(s), etc. (not shown) on first surface 704₀ to 704₃ and/or second surface 706₀ to 706i of each substrate 702₀ to 7021, respectively.

[0053] In other words, TGV 710 includes a first substrate 702₀ including a first surface 704₀ and a second surface 706₀ opposite to the first surface 704_0. A first through -hole 712₀ includes sidewalls extending through the first substrate 702₀ from the first surface 704₀to the second surface 706_0. A plurality of electrically conductive first traces 716₀ o to 716_{0, i} on the sidewalls of the first through-hole 712₀ extend through the first substrate 702₀ from the first surface 704₀ to the second surface 706_0. TGV 710 also includes a second substrate 7021 including a third surface 704₃ and a fourth surface 706₃ opposite to the third surface 704i. A second through- hole 7121 includes sidewalls extending through the second sub strate 702i from the third surface 704i to the fourth surface 706i. A plurality of electrically conductive second traces 716i₀ to 716i i on the sidewalls of the second through -hole 712₃ extend through the second substrate 7021 from the third surf ace 7041 to the f ourth surface 706i. The second sub strate 702i is bonded to the first substrate 702₀ such that the first through -hole 712₀ is aligned with the second through-hole 712iand at least one of the first traces 716_0,o to 716_{0, i} is electrically coupled to at least one of the second traces 716i₀ to 716i i. In certain exemplary embodiments, the second substrate 702i may be bonded to the first substrate 702₀ via an adhesive material (e.g., as indicated at 708₀). In other embodiments, the second substrate 702 may be fusion bonded to the first substrate 702₀.

[0054] FIG. 7B is a simplified cross-sectional view of an exemplary multilayer interconnect structure 720 including a TGV 722. Multilayer interconnect structure 720 includes three substrates 702₀ to 702₂ (e.g., glass or other dielectric substrates). In this embodiment, via 722 includes aligned through-holes 712₀ to 712₂ extending through each substrate 702₀ to 702_¾ respectively, and traces 724₀ to 724i on the sidewalls of the through-holes 712₀ to 712₂ extending through each substrate 702₀ to 702₂. Each trace 724₀ to 724i may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of each substrate 702₀ to 702₂.

[0055] FIG. 7C is a simplified cross-sectional view of an exemplary multilayer interconnect structure 730 including a TGV 732. Multilayer interconnect structure 730 includes four substrates 702₀ to 702₃ (e.g., glass or other dielectric substrates). In this embodiment, via 732 includes aligned through-holes 712₀ to 712₃ extending through each substrate 702₀ to 702_¾ respectively, and traces 734₀ to 734₃ on the sidewalls of the through-holes 712₀ to 712₃ extending through each substrate 702₀ to 702₃. Each trace 734₀ to 734₃ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of each substrate 702₀ to 702₃.

[0056] FIG. 7D is a simplified cross-sectional view of an exemplary multilayer interconnect structure 740 including a TGV 742. Multilayer interconnect structure 740 includes four substrates 702₀ to 702₃. In this embodiment, via 742 includes aligned through-holes 712₀to 712₃extendingthrough each substrate702₀ to 702₃, respectively, and traces 744₀ to 744₂. Trace 744₀ is on the sidewalls of the through-holes 712₂to 712₃ and extends through substrates 702₂ to 702₃. Trace 744 is on the sidewalls of the through-hole 712₀ and extends through substrate 702₀. Trace 744₂ is on the sidewalls of the through-holes 712₃ to 712₂ and extends through substrates 702₃ to 702₂. Trace 744₀ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of each substrate 702₂ to 702₃. Trace 744 may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of substrate 702₀. Trace 744₂ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of each substrate 702i to 702₂. [0057] FIG. 7E is a simplified cross-sectional view of an exemplary multilayer interconnect structure 750 including a TGV 752. Multilayer interconnect structure 750 includes four substrates 702₀ to 702₃. In this embodiment, via 752 includes aligned through-holes 712₀to 712₃extendingthrough each substrate702₀ to 702₃, respectively, and traces 754₀ to 754i. Trace 754₀ is on the sidewalls of the through -holes 712₀ to 712₃ and extends through substrates 702₀ to 702₃. Trace 754₃ is on the sidewalls of the through -hole 712₂ and extends through substrate 702₂. Trace 754₀ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of each substrate 702₀ to 702₃. Trace 754₃ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of substrate 702₂.

[0058] FIG. 7F is a simplified cross-sectional view of an exemplary multilayer interconnect structure 760 including a TGV 762. Multilayer interconnect structure 760 includes four substrates 702₀ to 702₃. In this embodiment, via 762 includes aligned through-holes 712₀to 712₃extendingthrough each substrate702₀ to 702₃, respectively, and traces 764₀ to 764₂. Trace 764₀ is on the sidewalls of the through-holes 712₂to 712₃ and extends through substrates 702₂ to 702₃. Trace 7641 is on a sidewall of the through-hole 712₀ and extends through substrate 702₀. Trace 764₂ is on a sidewall of the through-hole 712₂ and extends through sub strates 702₂. Trace 764₀ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of each substrate 702₂ to 702₃. Trace 764i may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of substrate 702₀. Trace 764₂ may be electrically coupled to circuit(s), component(s), etc. (not shown) on either surface of substrate 702₂.

[0059] While FIGS. 7A-7F include a plurality of exemplary multilayer interconnect structures having different configurations, in other embodiments, the multilayer interconnect structures may have other suitable configurations. For example, the multilayer interconnect structures may include different numbers of substrates, different numbers of electrically conductive traces, and different arrangements of the electrically conductive traces extending through the various layers of the multilayer interconnect structures. In addition, while one via is illustrated in each of FIGS. 7A-7F, a multilayer interconnect structure may include multiple vias extending through the substrates and each of the multiple vias may include a different configuration. Further, while the vias are depicted in a co-axial stacked arrangement, in other embodiments, the vias may be stacked in a staggered arrangement, thus forming a variety of different interconnect structures. For example, one layer comprising a via may be stacked and connected to circuit elements on a surface of another layer in a region not comprising a via, thus forming a blind via with a plurality of electrically conductive traces on its sidewall. [0060] In multilayer interconnect structures, the interconnect options increase as the number of conductive traces increases. This provides a significant advantage over single conductor vias since without altering the location of the through-holes in the substrate, many wiring combinations are possible by altering the segmentation process. This creates manufacturing efficiency by reducing the part numbers in addition to reducing the overall number of through- holes. For example, each of the layers in FIGS. 7A-7F would typically have a different through-hole pattern, but with the multiple conductor vias disclosed herein, a single hole pattern could be used for all layers and the customization could be accomplished through lithography processes.

[0061] Vertical or 3D integration may help to address an interconnect bottleneck in modem device development. The development of 3D integration technologies is motivated by shorter chip-to-chip interconnection length, reduced parasitic wiring resistance and capacitance and hence higher signal speed and reduced power consumption, as compared to conventional lateral chip placement and wiring approaches. Multiple conductor vias as disclosed herein enable a system designer to partition complex systems and assemble them vertically by metallized through via connections.

[0062] 3D integration techniques may include aligning and stacking two or more substrates including multiple conductor vias using low-temperature wafer bonding. Additionally, interconnecting the multiple conductor vias of the various substrates may involve various techniques such as copper to copper thermocompression bonding, Au-Sn-Cu soldering, and/or other approaches using low K dielectrics. Alternatively, the multilayer structures could be configured using glass fusion methods in combination with metal bonding methods.

[0063] FIGS. 8A and 8B are a top view and a cross-sectional view, respectively, of an exemplary micro light emitting diode (microLED) display 800. MicroLED display 800 includes a substrate 802 (e.g., a glass or other dielectric substrate), a matrix backplane 808, a driver component 820, a power controller 822, a plurality of first through -holes 824₀ to 824i, and a plurality of second through-holes 826₀ to 826i. The substrate 802 includes a first surface 804 and a second surface 806 opposite to the first surface 804. The matrix backplane 808 is on the first surface 804 and includes an array of microLEDs 810 arranged in rows and columns, a plurality of row lines 812 corresponding to the rows of microLEDs 810, and a plurality of column lines 814 correspondingto the columns of microLEDs 810. The driver component 820 is on the second surface 806 of the substrate 802. The first through-holes 824₀ to 824i extend through the substrate 802 from the first surface 804 to the second surface 806. The second through-holes 826₀to 826i also extend through the substrate 802 from the first surface 804 to the second surface 806. The plurality of row lines 812 are electrically coupled to the driver component 820 through the first through -holes 824₀ to 824 and the plurality of column lines 814 are electrically coupled to the driver component 820 through the second through-holes 826₀ to 826 ·

[0064] In certain exemplary embodiments, the matrix backplane 808 may include an array of thin-film transistors (TFTs) 816, where each thin-film transistor is electrically coupled to a microLED 810 of the array of microLEDs and the corresponding row line and column line. The power controller 822 may be on the second surface of the substrate 802. The power controller 822 maybe electrically coupled to the matrix backplane 808 through a first through- hole 824₀ to 824i (e.g., via a trace 828 as illustrated in FIG. 8B).

[0065] MicroLED displays in general have higher brightness and contrast ratio compared to liquid crystal (LCD) and organic light emitting diode (OLED) displays. Other benefits may exist depending on the specific application. To enable high resolution and large area displays, there is an interest in the fabrication of microLED display s with active matrix backplanes based on low-temperature polysilicon (LTPS) or oxide TFTs. One example configuration is to have top emitting microLED panels with driver boards located on the display backside. If the displays are used in a large area tiled display application, the multiple conductor vias enable electrical interconnections between the two substrate surfaces in a way that enables close tile- to-tile spacing (e.g., less than 100 micrometers). The multiple conductor vias enable electrical signal routing from multiple row and column lines of the TFT backplane to the driver board. Additionally, the availability of multiple conductors in a single via, not only enables the backplane connection to the driver board but also provides the signal connections to the power controllers that can feed through other active elements on the backplane. The multiple conductor vias also provide strain relief during any thermal excursions associated with manufacturing, assembly, or product use. The multiple conductors within a via may expand without constraint, thus providing a lower stress and more reliable interconnect compared to a single conductor via.

[0066] FIGS. 9A-9C are flow diagrams illustrating an exemplary method 900 for fabricating a device including a via including a plurality of electrically conductive traces, such as a device including a via 100a, 100b, 200a, 200b, 400, 410,420, 430, 440, or 450 as previously described and illustrated with reference to FIGS. 1 A-2C and 4A-4F. As illustrated in FIG. 9A at 902, method 900 includes forming a through-hole (e.g., 108, 208, 402, 412, 422, 432, 442, or 452) through a glass substrate (e.g., 102) comprising a first surface (e.g., 104) and a second surface (e.g., 106) opposite to the first surface such that the through-hole extends through the glass substrate from the first surface to the second surface. At 904, method 900 includes forming a plurality of electrically conductive traces (e.g., 112, 212, 404, 414, 424, 434, 444, or 454) on sidewalls of the through-hole extending from the first surface to the second surface. In certain exemplary embodiments, forming the plurality of traces may comprise selectively applying a conductive material to predetermined portions of the sidewalls of the through-hole.

[0067] As illustrated in FIG. 9B at 906, the step 902 of formingthe through-hole may include laser damaging an area of the glass substrate. At 908, step 902 may further include etching the glass substrate such that the laser damaged area of the glass substrate is removed to form the through-hole (e.g., as described with reference to FIG. 3 A).

[0068] As illustrated in FIG. 9C at 910, the step 904 for formingthe plurality of electrically conductive traces may include applying a conductive coating to sidewalls of the through-hole. In certain exemplary embodiments, applying the conductive coating to sidewalls of the through-hole may comprise electroless plating of the conductive coating (e.g., as described with reference to FIG. 3B). At 912, step 904 may further include segmenting the conductive coating to form the plurality of traces. In certain exemplary embodiments, segmenting the conductive coating may comprise laser ablating the conductive coating (e.g., as described with reference to FIG. 3C).

[0069] It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended thatthe present disclosure cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

What is claimed is:

1. A via comprising: a first dielectric substrate comprising a first surface and a second surface opposite to the first surface; a firstthrough-hole comprising sidewalls extending through the first dielectric substrate from the first surface to the second surface; and a plurality of electrically conductive first traces on the sidewalls of the first through- hole extending through the first dielectric substrate from the first surface to the second surface.

2. The via of claim 1, wherein the sidewalls of the firstthrough-hole are perpendicular to the first surface and the second surface of the first dielectric substrate.

3. The via of claim 1 , wherein the first through-hole is tapered between the first surface and the second surface of the first dielectric substrate.

4. The via of claim 1 , wherein the sidewalls of the first through-hole comprise a scalloped shape.

5. The via of claim 1, wherein the first through-hole comprises a cross-section that is circular or oval shaped.

6. The via of claim 1, wherein the first through-hole comprises a cross-section that is polygonal shaped.

7. The via of claim 1, wherein the first dielectric substrate comprises a glass-ceramic substrate.

8. The via of claim 1 , further comprising: a second dielectric substrate comprising a third surface and a fourth surface opposite to the third surface; a second through-hole comprising sidewalls extending through the second dielectric substrate from the third surface to the fourth surface; and a plurality of electrically conductive second traces on the sidewalls of the second through-hole extending through the second dielectric substrate from the third surface to the fourth surface, wherein the second dielectric substrate is bonded to the first dielectric substrate such that the first through-hole is aligned with the second through-hole and at least one of the first traces of the plurality of first traces is electrically coupled to at least one of the second traces of the plurality of second traces.

9. The via of claim 8, wherein the second dielectric substrate is bonded to the first dielectric substrate via an adhesive material.

10. The via of claim 8, wherein the second dielectric substrate is fusion bonded to the first dielectric substrate.

11. A device comprising: a glass substrate comprising a first surface and a second surface opposite to the first surface; a through-hole comprising sidewalls extendingthrough the glass sub strate from the first surface to the second surface; an electronic component attached to the first surface of the glass substrate; and a plurality of electrically conductive traces electrically coupled to the electronic component, each trace of the plurality of traces extending on a sidewall of the through-hole through the glass substrate from the first surface to the second surface.

12. The device of claim 11 , wherein each trace of the plurality of traces further extends on the first surface and the second surface of the glass substrate.

13. The device of claim 12, further comprising: a plurality of contact pads on the second surface of the glass substrate, each contact pad of the plurality of contact pads electrically coupled to a respective trace of the plurality of traces.

14. The device of claim 11, further comprising: a plurality of through-holes each comprising sidewalls extending through the glass substrate from the first surface to the second surface; and a plurality of electrically conductive traces on the sidewalls of each through-hole of the plurality of through-holes extending through the glass substrate from the first surface to the second surface.

15. The device of claim 11, wherein the plurality of traces comprises more than two traces.

16. A method for fabricating a device, the method comprising: forming a through-hole through a glass substrate comprising a first surface and a second surface opposite to the first surface such that the through-hole extends through the glass substrate from the first surface to the second surface; and forming a plurality of electrically conductive traces on sidewalls of the through-hole extending from the first surface to the second surface.

17. The method of claim 16, wherein forming the through-hole comprises: laser damaging an area of the glass substrate; and etching the glass substrate such that the laser damaged area of the glass substrate is removed to form the through-hole.

18. The method of claim 16, wherein forming the plurality of traces comprises: applying a conductive coating to sidewalls of the through-hole; and segmentingthe conductive coatingto form the plurality of traces.

19. The method of claim 18, wherein applying the conductive coatingto sidewalls of the through-hole comprises electroless plating of the conductive coating.

20. The method of claim 18, wherein segmenting the conductive coating comprises laser ablating the conductive coating.

21. The method of claim 16, wherein forming the plurality of traces comprises selectively applying a conductive material to predetermined portions of the sidewalls of the through-hole.

22. A device comprising: a glass substrate comprising a first surface and a second surface opposite to the first surface; a blind hole within the glass substrate comprising sidewalls extending into the glass substrate from the first surface and a bottom surface extending between the sidewalls; an electronic component attached to the bottom surface of the blind hole; and a plurality of electrically conductive traces electrically coupled to the electronic component, each trace of the plurality of traces extending on the bottom surface of the blind hole, a sidewall of the blind hole, and the first surface of the glass substrate.

23. The device of claim 22, wherein the plurality of traces comprises first traces extending on a first sidewall of the blind hole and second traces extending on a second sidewall of the blind hole opposite to the first sidewall.

24. The device of claim 23, wherein the plurality of traces comprises third traces extending on a third sidewall of the blind hole and fourth traces extending on a fourth sidewall of the blind hole opposite to the third sidewall.

25. The device of claim 22, wherein the blind hole comprises a cross-section that is rectangular shaped.

26. The device of claim 22, wherein the blind hole comprises a cross-section thatis circular or oval shaped.

27. A micro light emitting diode (microLED) display comprising: a glass substrate comprising a first surface and a second surface opposite to the first surface; a matrix backplane on the first surface comprising an array of microLEDs arranged in rows and columns, a plurality of row lines corresponding to the rows of microLEDs, and a plurality of column lines corresponding to the columns of microLEDs; a driver component on the second surface of the glass substrate; a first through-hole extending through the glass substrate from the first surface to the second surface; and a second through -hole extendingthrough the glass sub strate from the first surface to the second surface, wherein the plurality of row lines are electrically coupled to the driver component through the first through-hole and the plurality of column lines are electrically coupled to the driver component through the second through-hole.

28. The microLED display of claim 27, wherein the matrix backplane comprises an array of thin-film transistors, each thin film transistor electrically coupled to a microLED of the array of microLEDs.

29. The microLED display of claim 27, further comprising: a power controller on the second surface of the glass substrate, wherein the power controller is electrically coupled to the matrix backplane through the first through-hole.