WO2023286330A1 - Photo detection device and electronic apparatus - Google Patents

Abstract

The present invention improves phase difference detection accuracy. This photo detection device comprises a photoelectric conversion cell provided in a semiconductor layer. The photoelectric conversion cell includes first and second photoelectric conversion parts provided adjacent to each other via a first diffusion isolation region in a plan view in the semiconductor layer; a charge storing part (floating diffusion) provided in the first diffusion isolation region on the first surface side of the semiconductor layer; a first transfer transistor having a gate electrode provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion part in a plan view, and transferring signal charges from the first photoelectric conversion part to the charge storing part; a second transfer transistor having a gate electrode provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion part in a plan view, and transferring signal charges from the second photoelectric conversion part to the charge storing part; and an insulating separator provided in the first diffusion isolation region on the first surface side of the semiconductor layer, separated from the charge storing part, and extending between the gate electrodes of the first and second transfer transistors in a plan view.

Description

Photodetector and electronic equipment

The present technology (technology according to the present disclosure) relates to a photodetection device and an electronic device, and more particularly to a technology effectively applied to a photodetection device having phase difference detection pixels and an electronic device having the same.

A solid-state imaging device is known as a photodetector. As a technology related to this solid-state imaging device, a method of performing pupil division by embedding a plurality of photoelectric conversion elements in a semiconductor layer under one on-chip lens is known. For example, electronic devices such as single-lens reflex cameras and smartphones. used in solid-state imaging devices for built-in cameras. There is also known a method of detecting a phase difference by reading, as independent signals, signal charges photoelectrically converted by a plurality of photoelectric conversion units arranged under one on-chip lens during phase difference detection. (For example, Patent Document 1).

JP 2019-140251 A

By the way, the pixels of a solid-state imaging device that employs a phase detection autofocus method are, for example, first and second pixels arranged adjacent to each other via a diffusion isolation region made of a p-type semiconductor region. 2 photoelectric conversion units, a first transfer transistor that transfers signal charges from the first photoelectric conversion unit to a floating diffusion, and a second transfer transistor that transfers signal charges from the second photoelectric conversion unit to the floating diffusion and a photoelectric conversion cell including.

In this type of photoelectric conversion cell, in the phase mode, when the signal charge on the first photoelectric conversion unit side is read, for example, the first transfer transistor is turned on to transfer the signal charge of the first photoelectric conversion unit to the floating diffusion. During the period in which the first transfer transistor is turned on, the potential of the diffusion isolation region between the first photoelectric conversion section and the second photoelectric conversion section is modulated. Then, part of the signal charge on the side of the second photoelectric conversion unit that is not read out is read out as the signal of the first photoelectric conversion unit via this potential modulation region, which may degrade the phase difference detection performance. be. This deterioration in phase difference detection performance may also occur when reading signal charges on the second photoelectric conversion unit side.

The purpose of this technology is to improve the accuracy of phase difference detection.

(1) A photodetector according to an aspect of the present technology includes a first surface and a second surface located on opposite sides of each other.
A semiconductor layer having a surface of and a photoelectric conversion cell provided in the semiconductor layer,
The photoelectric conversion cell is
first and second photoelectric conversion units provided adjacent to each other via a first diffusion isolation region in plan view in the semiconductor layer;
a floating diffusion provided in the first diffusion isolation region on the first surface side of the semiconductor layer;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion section in plan view, and the first photoelectric conversion section transfers signal charges from the first photoelectric conversion section to the floating diffusion. a transfer transistor;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion section in a plan view, and the second photoelectric conversion section transfers signal charges from the second photoelectric conversion section to the floating diffusion. a transfer transistor;
provided in the first diffusion isolation region on the first surface side of the semiconductor layer, separated from the floating diffusion, and extending between the gate electrodes of the first and second transfer transistors in plan view and an insulating separator.

(2) A photodetector according to another aspect of the present technology,
a semiconductor layer having first and second surfaces opposite to each other;
first and second photoelectric conversion units provided adjacent to each other via a diffusion separation region in the semiconductor layer;
a floating diffusion provided in the diffusion isolation region on the first surface side of the semiconductor layer;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion section in plan view, and transfers signal charges photoelectrically converted by the first photoelectric conversion section to the floating diffusion. a first transfer transistor to
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion section in plan view, and transfers signal charges photoelectrically converted by the second photoelectric conversion section to the floating diffusion. a second transfer transistor to
an insulating separator provided in the diffusion isolation region apart from the charge holding portion and extending between the gate electrodes of the first and second transfer transistors in plan view.

(3) An electronic device according to another aspect of the present technology includes the photodetector according to (1) or (2) above.

1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology; FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology; FIG. It is an equivalent circuit diagram of the pixel unit of the solid-state imaging device according to the first embodiment of the present technology. 1 is a schematic plan view showing one configuration example of a pixel of a solid-state imaging device according to a first embodiment of the present technology; FIG. FIG. 5 is a schematic vertical cross-sectional view showing a cross-sectional structure along the a4-a4 cutting line in FIG. 4; FIG. 6 is a schematic longitudinal sectional view enlarging a part of FIG. 5; FIG. 5 is a schematic vertical cross-sectional view showing a cross-sectional structure along the b4-b4 cutting line in FIG. 4; FIG. 5 is a diagram showing a potential distribution of pixels in FIG. 4; 4 is a graph showing the output of the photoelectric conversion unit of the solid-state imaging device according to the first embodiment of the present technology with respect to incident light; It is a figure which shows the change of the signal charge amount accumulate|stored in the photoelectric conversion part of the solid-state imaging device which concerns on 1st Embodiment of this technique. FIG. 10B is a diagram showing a change subsequent to FIG. 10A; FIG. 10B is a diagram showing a change subsequent to FIG. 10B; FIG. 10B is a diagram showing a change subsequent to FIG. 10C; FIG. 10 is a diagram showing changes in the amount of signal charge accumulated in a conventional photoelectric conversion unit; FIG. 11B is a diagram showing a change subsequent to FIG. 11A; It is a schematic plan view which shows the modification of 1st Embodiment. It is a schematic plan view showing one configuration example of a pixel of a solid-state imaging device according to a second embodiment of the present technology. FIG. 14 is a schematic vertical cross-sectional view showing a cross-sectional structure along the line a13-a13 of FIG. 13; It is a schematic plan view showing one configuration example of a pixel of a solid-state imaging device according to a third embodiment of the present technology. FIG. 16 is a schematic vertical cross-sectional view showing a cross-sectional structure taken along line a15-a15 of FIG. 15; FIG. 11 is a schematic plan view showing one configuration example of a pixel of a solid-state imaging device according to a fourth embodiment of the present technology; FIG. 18 is a schematic vertical cross-sectional view showing a cross-sectional structure taken along line a17-a17 of FIG. 17; FIG. 19 is a schematic cross-sectional view showing a cross-sectional structure along the line a19-a19 of FIG. 18; FIG. 11 is a schematic plan view showing one configuration example of a pixel of a solid-state imaging device according to a fifth embodiment of the present technology; FIG. 21 is a schematic vertical cross-sectional view showing the cross-sectional structure taken along the line a20-a20 of FIG. 20; It is a figure showing a schematic structure of electronic equipment concerning a 6th embodiment of this art.

Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.
In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimension, the ratio of thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

In addition, it goes without saying that there are parts with different dimensional relationships and ratios between the drawings. Moreover, the effects described in this specification are only examples and are not limited, and other effects may be obtained.

In addition, the following embodiments exemplify devices and methods for embodying the technical idea of the present technology, and do not specify the configurations as those below. That is, the technical idea of the present technology can be modified in various ways within the technical scope described in the claims.

Also, the definitions of directions such as up and down in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present technology. For example, if an object is observed after being rotated by 90°, it will be read with its top and bottom converted to left and right, and if it is observed after being rotated by 180°, it will of course be read with its top and bottom reversed.

Further, in the following embodiments, a case where the first conductivity type is p-type and the second conductivity type is n-type will be exemplified. The type and the second conductivity type may be p-type.

Further, in the following embodiments, among the three mutually orthogonal directions in space, the first direction and the second direction, which are orthogonal to each other in the same plane, are the X direction and the Y direction, respectively. A third direction orthogonal to each of the second directions is the Z direction. In the following embodiments, the thickness direction of the semiconductor layer 21, which will be described later, will be described as the Z direction.

[First embodiment]
In the first embodiment, an example in which the present technology is applied to a solid-state imaging device, which is a backside illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor, will be described as a photodetector.

<<Overall Configuration of Solid-State Imaging Device>>
First, the overall configuration of the solid-state imaging device 1A will be described.

As shown in FIG. 1, a solid-state imaging device 1A according to the first embodiment of the present technology mainly includes a semiconductor chip 2 having a square two-dimensional planar shape when viewed from above. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2. FIG. As shown in FIG. 22, this solid-state imaging device 1A (101) takes in image light (incident light 106) from an object through an optical lens 102, and measures the light quantity of the incident light 106 imaged on the imaging surface. Each pixel is converted into an electric signal and output as a pixel signal.

As shown in FIG. 1, a semiconductor chip 2 on which a solid-state imaging device 1A is mounted has a square-shaped pixel array section 2A provided in the center in a two-dimensional plane including X and Y directions orthogonal to each other, A peripheral portion 2B is provided outside the pixel array portion 2A so as to surround the pixel array portion 2A.

The pixel array section 2A is a light receiving surface that receives light condensed by an optical lens (optical system) 102 shown in FIG. 22, for example. In the pixel array section 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

As shown in FIG. 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of four sides in the two-dimensional plane of the semiconductor chip 2 . Each of the plurality of bonding pads 14 is an input/output terminal used when electrically connecting the semiconductor chip 2 to an external device.

<Logic circuit>
As shown in FIG. 2, the semiconductor chip 2 includes a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like. The logic circuit 13 is composed of a CMOS (Complementary MOS) circuit including, for example, an n-channel conductivity type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-channel conductivity type MOSFET as field effect transistors.

The vertical driving circuit 4 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses for driving the pixels 3 to the selected pixel drive lines 10, and drives the pixels 3 in row units. That is, the vertical driving circuit 4 sequentially selectively scans the pixels 3 of the pixel array section 2A in the vertical direction row by row, and outputs signals from the pixels 3 based on the signal charges generated by the photoelectric conversion elements of the pixels 3 according to the amount of received light. is supplied to the column signal processing circuit 5 through the vertical signal line 11 .

The column signal processing circuit 5 is arranged, for example, for each column of the pixels 3, and performs signal processing such as noise removal on the signals output from the pixels 3 of one row for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion for removing pixel-specific fixed pattern noise.

The horizontal driving circuit 6 is composed of, for example, a shift register. The horizontal driving circuit 6 sequentially outputs a horizontal scanning pulse to the column signal processing circuit 5 to select each of the column signal processing circuits 5 in order, and the pixels subjected to the signal processing from each of the column signal processing circuits 5 are selected. A signal is output to the horizontal signal line 12 .

The output circuit 7 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12 and outputs the processed signal. As signal processing, for example, buffering, black level adjustment, column variation correction, and various digital signal processing can be used.

The control circuit 8 generates a clock signal and a control signal that serve as references for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Generate. The control circuit 8 then outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

<Pixel unit>
The semiconductor chip 2 has a pixel unit PU shown in FIG. The pixel unit PU includes a pixel block 15 and a readout circuit 16, as shown in FIG. As shown in FIG. 4, the pixel block 15 includes, for example, two pixels 3 adjacent to each other in the Y direction, and one floating diffusion (charge holding portion) FD shared by the two pixels 3. I have. One readout circuit 16 is electrically connected to the floating diffusion FD of the pixel block 15 . That is, the pixel array section 2A of the solid-state imaging device 1A according to the first embodiment includes two pixels 3 adjacent to each other in the Y direction, a floating diffusion FD shared by the two pixels 3, and this floating diffusion FD. Pixel units PU each including a readout circuit 16 connected to the FD are repeatedly arranged in each of the X and Y directions.

<Pixel>
As shown in FIG. 3 , each pixel 3 of the plurality of pixels 3 has a photoelectric conversion cell 31 . The photoelectric conversion cell 31 includes a first photoelectric conversion unit 32L including a first photoelectric conversion element PD1, a second photoelectric conversion unit 32R including a second photoelectric conversion element PD2, and the first and second photoelectric conversion units 32L and 32R. and a floating diffusion FD for accumulating signal charges photoelectrically converted by the (first and second photoelectric conversion elements PD1 and PD2). Further, the photoelectric conversion cell 31 includes a first transfer transistor TR1 that transfers signal charges photoelectrically converted by the first photoelectric conversion unit 32L (first photoelectric conversion element PD1) to the floating diffusion FD, and a second photoelectric conversion unit 32R ( and a second transfer transistor TR2 for transferring the signal charge photoelectrically converted by the second photoelectric conversion element PD2) to the floating diffusion FD.

Each of the two photoelectric conversion elements PD1 and PD2 generates signal charges according to the amount of light received. Each of the two photoelectric conversion elements PD1 and PD2 temporarily accumulates (holds) the generated signal charge. The photoelectric conversion element PD1 has a cathode side electrically connected to the source region of the first transfer transistor TR1, and an anode side electrically connected to a reference potential line (for example, ground). The photoelectric conversion element PD2 has a cathode side electrically connected to the source region of the transfer transistor TR2, and an anode side electrically connected to a reference potential line (for example, ground). Photodiodes, for example, are used as the photoelectric conversion elements PD1 and PD2.

Among the two transfer transistors TR1 and TR2, the first transfer transistor TR1 has a source region electrically connected to the cathode side of the photoelectric conversion element PD1, and a drain region electrically connected to the floating diffusion FD. A gate electrode of the first transfer transistor TR1 is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2). The second transfer transistor TR2 has a source region electrically connected to the cathode side of the photoelectric conversion element PD2, and a drain region electrically connected to the floating diffusion FD. A gate electrode of the second transfer transistor TR2 is electrically connected to a transfer transistor drive line among the pixel drive lines 10 .

The floating diffusion FD is shared by the two photoelectric conversion units 32L and 32R of one photoelectric conversion cell 31. Also, the floating diffusion FD is shared by, for example, two pixels 3, in other words, two photoelectric conversion cells 31, although not limited to this. That is, one floating diffusion FD of the first embodiment is provided for every two pixels 3 (every two photoelectric conversion cells 31), and four photoelectric conversion units (32L×2+32R× 2=4).

The floating diffusion FD shared by the two photoelectric conversion cells 31 (two pixels 3) temporarily stores the signal charge transferred from the first photoelectric conversion element PD1 via the first transfer transistor TR1 in the first photoelectric conversion unit 32L. In the second photoelectric conversion unit 32R, the signal charges transferred from the second photoelectric conversion element FD2 via the second transfer transistor TR2 are temporarily accumulated and held.

As shown in FIG. 3, the input stage side of the readout circuit 16 is connected to the floating diffusion FD. The readout circuit 16 reads out the signal charge accumulated in the floating diffusion FD and outputs a pixel signal based on the signal charge. The readout circuit 16 is shared by, but not limited to, two pixels 3, in other words, two photoelectric conversion cells 31, for example. The readout circuit 16 includes an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are composed of MOSFETs having a gate insulating film made of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions functioning as a source region and a drain region. ing. Further, these transistors may be MISFETs (Metal Insulator Semiconductor FET) whose gate insulating film is a silicon nitride film (Si ₃ N ₄ film) or a laminated film of a silicon nitride film and a silicon oxide film.

The amplification transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, and a drain region electrically connected to the power supply line VDD. A gate electrode of the amplification transistor AMP is electrically connected to the floating diffusion FD.

The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL) and a drain electrically connected to the source region of the amplification transistor AMP. A gate electrode of the select transistor SEL is electrically connected to a select transistor drive line among the pixel drive lines 10 (see FIG. 2).

The reset transistor RST has a source region electrically connected to the floating diffusion FD and a drain region electrically connected to the power supply line VDD. A gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

An electronic device equipped with the solid-state imaging device 1A reads signal charges from the first and second photoelectric conversion elements PD1 and PD2 (first and second photoelectric conversion units 32L and 32R), respectively, and detects the phase difference. When the focus is correct, there is no difference in the amount of signal charges accumulated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. On the other hand, when the focus is not correct, for example, as shown in FIG. A difference occurs between the amount Q2 of the signal charge accumulated in the second photoelectric conversion element PD2. If the focus is out of focus, the electronic device performs an operation such as operating the objective lens so that the line of Q1 and the line of Q2 in the first range between 0 and L1 of the light amount are aligned. match. This is autofocus.

Then, when the focus adjustment is completed, the electronic device generates an image using the added signal charges Q3 accumulated in the light amount range from 0 to L3 in FIG. 9, for example. Here, the added signal charge Q3 is the sum of Q1 and Q2 (Q3=Q1+Q2).

<<Specific Configuration of Solid-State Imaging Device>>
Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4 to 7. FIG. In order to make the drawings easier to see, the illustration of a multilayer wiring layer, which will be described later, is omitted in FIGS. 4 is upside down with respect to FIG. 1 shows the light incident surface side of the semiconductor chip 2, but FIG. 4 shows the semiconductor chip 2 when viewed from the side opposite to the light incident surface side (multilayer wiring layer side) shown in FIG. is a plan view of the.

<Semiconductor chip>
As shown in FIGS. 4 to 7, the semiconductor chip 2 includes a semiconductor layer 21 having a first surface S1 and a second surface S2 located opposite to each other in the thickness direction (Z direction), and the semiconductor layer 21 having a first surface S1 and a second surface S2. 21 is further provided with a color filter 45 and a microlens (on-chip lens) 46 which are sequentially laminated from the second surface S2 side. The semiconductor chip 2 further includes a multilayer wiring layer including an insulating layer and a wiring layer provided on the first surface S1 side of the semiconductor layer 21 (not shown). The semiconductor layer 21 is composed of, for example, a single crystal silicon substrate.

A color filter 45 and a microlens 46 are provided for each pixel 3 (photoelectric conversion cell 31). The color filter 45 color-separates the incident light incident from the light incident surface side of the semiconductor chip 2 . The microlenses 46 condense the irradiation light and allow the condensed light to enter the pixels 3 (photoelectric conversion cells 31) efficiently. Also, one color filter 45 and one microlens 46 are provided so as to cover both the first photoelectric conversion section 32L and the second photoelectric conversion section 32R.

Here, the first surface S1 of the semiconductor layer 21 is sometimes called an element formation surface or main surface, and the second surface S2 side is sometimes called a light incident surface or back surface. The solid-state imaging device 1A of the first embodiment converts light incident from the second surface (light incident surface, back surface) S2 side of the semiconductor layer 21 into the first and second photoelectric conversion cells 31 provided on the semiconductor layer 21 . Photoelectric conversion is performed by the second photoelectric conversion units 32L and 32R (first and second photoelectric conversion elements PD1 and PD2).

<Photoelectric conversion cell>
As shown in FIGS. 4 to 7, the semiconductor layer 21 has photoelectric conversion cells 31 partitioned by inter-cell diffusion isolation regions 22 as second diffusion isolation regions. This photoelectric conversion cell 31 is provided for each pixel 3 . Although two photoelectric conversion cells 31 are illustrated in FIG. 4, the number of photoelectric conversion cells 31 is not limited to two. Although not shown in detail, the photoelectric conversion cells 31 are repeatedly arranged for each pixel 3 via the inter-cell diffusion separation regions 22 in the X direction and the Y direction in plan view. The photoelectric conversion cell 31 has a rectangular planar pattern with four sides.

As shown in FIGS. 4 to 7, the photoelectric conversion cell 31 includes first and second photoelectric conversion cells provided adjacent to each other via an intra-cell diffusion isolation region 23 as a first diffusion isolation region in a semiconductor layer 21 in plan view. It has second photoelectric conversion units 32L and 32R, and a floating diffusion FD (see FIG. 4) provided in the intra-cell diffusion separation region 23 on the first surface S1 side of the semiconductor layer 21 . The inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23 are diffusion isolation regions having the first conductivity type in which impurities are diffused.

In the photoelectric conversion cell 31, the gate electrode 42L is provided on the first surface S1 side of the semiconductor layer 21 so as to overlap the first photoelectric conversion unit 32L in plan view, and the floating diffusion is provided from the first photoelectric conversion unit 32L. It further has a first transfer transistor TR1 for transferring signal charges to the FD.

In the photoelectric conversion cell 31, the gate electrode 42R is provided on the first surface S1 side of the semiconductor layer 21 so as to overlap the second photoelectric conversion unit 32R in plan view, and the floating diffusion is provided from the second photoelectric conversion unit 32R. It further has a second transfer transistor TR2 for transferring signal charges to the FD.

The photoelectric conversion cell 31 is provided in the intra-cell diffusion isolation region 23 on the first surface S1 side of the semiconductor layer 21, separated from the floating diffusion FD, and is configured to have the first and second transfer transistors TR1 and TR2 in plan view. and an insulating separator 35 extending between and outside each of the gate electrodes 42L, 42R.

As shown in FIG. 4, the photoelectric conversion cells 31 have a square planar pattern with four sides. Although not shown in detail, the photoelectric conversion cells 31 are repeatedly arranged for each pixel 3 in each of the X direction and the Y direction in a plan view via the inter-cell diffusion isolation region 22 .

<Diffusion Separation Region>
As shown in FIGS. 4 to 7, the inter-cell diffusion separation region 22 extends across the first surface S1 and the second surface S2 of the semiconductor layer 21, and the photoelectric conversion cells 31 adjacent to each other in the two-dimensional plane. are electrically separated. The intra-cell diffusion separation region 23 extends across the first surface S1 and the second surface S2 of the semiconductor layer 21 in the same manner as the inter-cell diffusion separation region 22, and is connected to the first photoelectric conversion section 32L of the photoelectric conversion cell 31. It is electrically isolated from the second photoelectric conversion unit 32R. Each of the inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23 is composed of, for example, a p-type semiconductor region (first conductivity type first semiconductor region) 24 .

As shown in FIG. 4, the inter-cell diffusion separation region 22 corresponding to one photoelectric conversion cell 31 (pixel 3) has a square planar annular pattern (square ring planar pattern) in plan view. It has become. The inter-cell diffusion separation regions 22 corresponding to the plurality of photoelectric conversion cells 31 (pixels 3) have a grid plane pattern. The photoelectric conversion cell 31 is composed of two inter-cell diffusion separation regions 22 extending in the X direction with the photoelectric conversion cell 31 interposed therebetween and two inter-cell diffusion separation regions 22 extending in the Y direction with the photoelectric conversion cell 31 interposed therebetween. being surrounded.

As shown in FIG. 4, the intra-cell diffusion separation region 23 extends along the Y direction in a plan view, and extends between two inter-cell diffusion separation regions 22 extending in the X direction with the photoelectric conversion cell 31 interposed therebetween. It is connected with the department and integrated.

<Photoelectric converter>
Each of the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R photoelectrically converts light incident from the second surface (light incident surface, rear surface) S2 side of the semiconductor layer 21 to generate signal charges. Each of the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R also functions as a floating diffusion that temporarily accumulates the generated signal charge. The first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R are arranged in the photoelectric conversion cell 31 along the first direction. Here, the first direction is described as being the X direction, but it may be any direction other than the X direction as long as it is perpendicular to the thickness direction. Further, each of the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R includes, for example, an n-type semiconductor region (second conductivity type second semiconductor region) 25, and constitutes the photoelectric conversion elements PD1 and PD2 described above. are doing.

<Floating Diffusion>
As shown in FIGS. 4 and 7, the floating diffusion FD is provided in the inter-cell diffusion isolation region 22 on the first surface S1 side of the semiconductor layer 21 . Specifically, in the pixel block 15, the floating diffusion FD is such that the inter-cell diffusion isolation region 22 between the two photoelectric conversion cells 31 and the intra-cell diffusion isolation region 23 of each of the two photoelectric conversion cells 31 intersect. It is located at the intersection of diffusion isolation regions including regions, ie inter-cell diffusion isolation regions 22 and intra-cell diffusion isolation regions 23 . Around the floating diffusion FD, in the two photoelectric conversion cells 31 of the pixel block 15, gate electrodes 42L and 42R of the two transfer transistors TR1 and TR2 included in one photoelectric conversion cell 31 and Gate electrodes 42L and 42R of two transfer transistors TR1 and TR2 included in the photoelectric conversion cell 31 are arranged. The floating diffusion FD is composed of, for example, an n-type semiconductor region and is an n-type floating diffusion region. In the first embodiment, carriers as signal charges accumulated in the floating diffusion FD are electrons (e ⁻ ).

<Transfer transistor>
As shown in FIGS. 5 to 7, the first transfer transistor TR1 is provided on the first surface S1 side of the semiconductor layer 21 . The first transfer transistor TR1 is, for example, an n-channel conductivity type MOSFET. The first transfer transistor TR1 is provided so as to form a channel in the active region between the first photoelectric conversion unit 32L and the floating diffusion FD. It has an electrode 42L. When the first transfer transistor TR1 is turned on and off according to the voltage between the gate and the source, the signal charge is transferred from the first photoelectric conversion unit 32L functioning as the source region to the floating diffusion FD functioning as the drain region. and there are cases where it is not transferred. Here, it is assumed that the signal charge is transferred when the first transfer transistor TR1 is on, and the signal charge is not transferred when it is off.

As shown in FIG. 8, when the first transfer transistor TR1 is off, that is, when signal charges are not transferred from the first photoelectric conversion unit 32L to the floating diffusion FD, the intra-cell diffusion separation region 23 (p-type semiconductor region 24), a second potential barrier P2a higher than the first potential barrier P1 can be formed. When the first transfer transistor TR1 is turned on, the modulation lowers the second potential barrier P2a, and signal charges flow from the first photoelectric conversion unit 32L to the floating diffusion FD.

As shown in FIGS. 5 to 7, the second transfer transistor TR2 is provided on the first surface S1 side of the semiconductor layer 21. As shown in FIGS. The second transfer transistor TR2 is, for example, an n-channel conductivity type MOSFET. The second transfer transistor TR2 is provided so as to form a channel in the active region between the second photoelectric conversion unit 32R and the floating diffusion FD. It has an electrode 42R. When the second transfer transistor TR2 is turned on and off according to the voltage between the gate and the source, the signal charge is transferred from the second photoelectric conversion unit 32R functioning as the source region to the floating diffusion FD functioning as the drain region. and may not be transferred. Here, it is assumed that the signal charge is transferred when the second transfer transistor TR2 is on, and the signal charge is not transferred when it is off.

As shown in FIG. 8, when the second transfer transistor TR2 is off, that is, when signal charges are not transferred from the second photoelectric conversion unit 32R to the floating diffusion FD, the intra-cell diffusion separation region 23 (p-type semiconductor region 24), a second potential barrier P2b higher than the first potential barrier P1 can be formed. When the second transfer transistor TR2 is turned on, the second potential barrier P2b is lowered by modulation, and signal charges flow from the second photoelectric conversion unit 32R to the floating diffusion FD.

The gate insulating film 41 is composed of, for example, a silicon oxide film. Each of the gate electrodes 42L and 42R is composed of, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities for reducing resistance are introduced.
As shown in FIG. 4, in one photoelectric conversion cell 31, the insulating separator 35 extends in the Y direction between the gate electrode 42L of the first transfer transistor TR1 and the gate electrode 42R of the second transistor in plan view. It extends linearly from the floating diffusion FD side to the opposite side and protrudes outward from between the two gate electrodes 42L and 42T. In the first embodiment, the insulating separator 35 is formed with a length exceeding half of the Y-direction length of the photoelectric conversion units (32L, 32R) from a position slightly away from the floating diffusion FD.

As shown in FIG. 6, the insulating separator 35 includes a groove portion 36 extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side, and an insulating film 37 embedded in the groove portion 36. including. The insulating separator 35 is covered with a gate insulating film 41 .

<Other configurations>
As shown in FIGS. 5 to 7, the photoelectric conversion cells 31 are provided on the surface layer portions of the first and second photoelectric conversion units 32L and 32R on the first surface S1 side of the semiconductor layer 21. It further has a p-type semiconductor region (first conductivity type third semiconductor region) 27 . Further, the photoelectric conversion cell 31 is an n-type semiconductor region (second It further has a conductivity type fourth semiconductor region) 26 .

The p-type semiconductor region 27 is provided on the surface layer of each of the first and second photoelectric conversion units 32L and 32R so as to be in contact with the side surfaces of the gate insulating film 41 and the insulating separator 35 . Thus, by providing the p-type semiconductor region 27 in contact with the side surfaces of the gate insulating film 41 and the insulating separator 35, pinning of the side surfaces of the insulating separator 35 can be ensured.

The n-type semiconductor region 26 is in contact with the bottom of the p-type semiconductor region 27 in the surface layer of each of the first and second photoelectric conversion units 32L and 32R, and forms the inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region. 23 are provided in contact with each side surface. The n-type semiconductor region 26 has a higher impurity concentration than the n-type semiconductor region 25 . In this way, by providing the n-type semiconductor region 26 in contact with the side surfaces of the inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23, each of the first and second photoelectric conversion units 32L and 32R is parasitic Capacitance can be added, and the saturation signal quantity Qs can be improved.

Also, in the photoelectric conversion cell 31, the parasitic capacitance having the insulating separator 35 as a dielectric is added to each of the photoelectric conversion units 32L and 32R, so that the saturation signal amount Qs can be further improved. Moreover, since this parasitic capacitance increases in proportion to the length of the insulating separator 35, the parasitic capacitance added to the photoelectric conversion units 32L and 32R can be adjusted by adjusting the length of the insulating separator 35. can be done.

<<Operation of solid-state imaging device>>
Next, operation of the solid-state imaging device 1A according to the first embodiment will be described with reference to FIGS. 9 and 10A to 10D. FIG. 9 is a graph showing the output of the photoelectric conversion unit of the solid-state imaging device with respect to the amount of incident light. The horizontal axis of FIG. 9 is the amount of incident light, and the vertical axis is the output of the photoelectric conversion unit. 10A to 10D are schematic diagrams showing changes in signal charges accumulated in the photoelectric conversion unit of the solid-state imaging device 1A.

When light enters the solid-state imaging device 1A, the light passes through the microlenses 46, the color filters 45, etc., and enters the first photoelectric conversion section 32L and the second photoelectric conversion section 32R. An output Q1 is obtained from the first photoelectric conversion section 32L and an output Q2 is obtained from the second photoelectric conversion section 32R according to the amount of incident light. Autofocusing is performed based on the outputs Q1 and Q2, and an image is generated based on the addition signal Q3 (Q3=Q1+Q2) which is the sum of Q1 and Q2. FIG. 9 shows the output Q1 of the first photoelectric conversion section 32L, the output Q2 of the second photoelectric conversion section 32R, and the addition signal Q3 (Q3=Q1+Q2) which is the sum of Q1 and Q2. Also, the first range is a region where the light quantity is from 0 to L1, the second range is a region where the light quantity exceeds L1 and reaches L2, the third range is a region where the light quantity exceeds L2 and reaches L3, and the light quantity exceeds L3. The region is called the fourth range. Also, FIG. 9 shows an example in which the first photoelectric conversion unit 32L is saturated before the second photoelectric conversion unit 32R.

In the first range shown in FIG. 9, no overflow occurs between the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R. This is the state shown in FIG. 10A, in which the signal charges generated by the first photoelectric conversion unit 32L and the signal charges generated by the second photoelectric conversion unit 32R are not mixed. Phase difference detection for autofocus is performed in this first range. More specifically, phase difference detection is performed in a first range where both the output Q1 of the first photoelectric conversion section 32L and the output Q2 of the second photoelectric conversion section 32R maintain linearity with respect to the amount of light.

In the second range shown in FIG. 9, the first photoelectric conversion unit 32L is saturated earlier than the second photoelectric conversion unit 32R, and part of the signal charge of the first photoelectric conversion unit 32L is transferred to the intra-cell diffusion isolation region 23. crosses the first potential barrier P1 and flows to the second photoelectric conversion portion 32R. This is the overflow (Fig. 10B).

In the third range shown in FIG. 9, the second photoelectric conversion section 32R is also saturated. This is the state shown in FIG. 10C, in which signal charges are accumulated beyond the first potential barrier P1 of the intra-cell diffusion separation region 23 without distinguishing between the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R. be done. Then, the outputs of the first photoelectric conversion section 32L and the second photoelectric conversion section 32R increase until the charge overflows into the floating diffusion FD beyond the second potential barriers P2a and P2b.

In the fourth range shown in FIG. 9, the signal charge exceeds the second potential barrier P1a of the first transfer transistor TR1 and the second potential barrier P2b of the second transfer transistor TR2 and overflows into the floating diffusion FD (FIG. 10D). ). The overflowed signal charges are erased by the reset transistor RST.

The image formation is performed using the addition signal Q3 from the first range to the third range. More specifically, the addition signal Q3 is performed within the first to third ranges where the linearity with respect to the amount of light is maintained.

<<Main effects of the first embodiment>>
Next, main effects of the first embodiment will be described with reference to conventional photoelectric conversion cells (pixels) shown in FIGS. 11A and 11B. FIG. 11A is a diagram showing changes in signal charge amount accumulated in a conventional photoelectric conversion unit. FIG. 11B is a diagram showing changes subsequent to FIG. 11A.

In the conventional photoelectric conversion cell, when the signal charge of the first photoelectric conversion unit 32L is read out in the phase mode, for example, the first transfer transistor TR1 is turned on to transfer the signal charge of the first photoelectric conversion unit 32L to the floating diffusion ( FIG. 11A). During the period in which the first transfer transistor TR1 is turned on, the potential of the intra-cell diffusion isolation region 23 between the first photoelectric conversion section 32L and the second photoelectric conversion section 32R is modulated. Then, the potential barrier of the intra-cell diffusion separation region 23 is lowered by the amount corresponding to this potential modulation region (FIG. 11B). In the conventional photoelectric conversion cell, part of the signal charge on the side of the second photoelectric conversion unit 32R that is not read is read out via this modulation region, which may degrade the phase difference detection performance.

On the other hand, the photoelectric conversion cell 31 of this first embodiment has an insulating separator 35 . Therefore, during the period in which the first transfer transistor TR1 is turned on, the potential of the intra-cell diffusion isolation region 23 between the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32R is modulated. , the blooming path in the modulation region can be physically closed by the insulating separator 35 even if the potential barrier of the intra-cell diffusion separation region 23 is lowered by an amount equivalent to Leakage of signal charges to the photoelectric conversion unit 32L side can be suppressed. This makes it possible to improve the phase difference detection performance. In addition, even during the period in which the second transfer transistor TR2 is turned on, the blooming path in the modulation region can be closed by the insulating separator 35, and the voltage from the first photoelectric conversion unit 32L side that is not read out to the second photoelectric conversion unit 32R side can be closed. signal charge leakage can be suppressed. This makes it possible to improve the phase difference detection performance.

The depth De (see FIG. 6) of the insulating separator 35 in the Z direction is such that the first photoelectric conversion unit 32L and the second photoelectric conversion unit 32L and the second photoelectric conversion unit 32L during the period in which one of the first and second transfer transistors TR1 and TR2 is turned on. It is preferable to make it deeper than the thickness (height) of the modulation region in which the potential of the intra-cell diffusion separation region 23 between the conversion portion 32R is modulated.

Further, the insulating separator 35 preferably extends between and outside the gate electrode 42L of the first transfer transistor TR1 and the gate electrode 42R of the second transfer transistor TR2 in plan view. Moreover, it is preferable that the insulating separator 35 is separated from the floating diffusion FD in plan view.

In the solid-state imaging device 1A according to the first embodiment, four photoelectric conversion units (31L, 31R, 31L, 31R) share one floating diffusion FD. In this case, compared to the case where the floating diffusion FD is provided for each of the four photoelectric conversion units (31L, 31R, 31L, 31R), the volume of the photoelectric conversion unit (Photo Diode) can be increased to increase the volume. It is possible to measure the saturation signal amount.

<<Modification of First Embodiment>>
In the above-described first embodiment, the case where the insulating separator 35 is configured to have a length exceeding half the length of the photoelectric conversion units 32L and 32R in the Y direction from a position slightly away from the floating diffusion FD has been described. However, the present technology is not limited to the length of the first embodiment. For example, as shown in FIG. 12, the Y-direction length of the insulating separator 35 may be less than half the Y-direction length of the photoelectric conversion units 32L and 32R. However, the insulating separator 35 preferably has a length extending between and outside the gate electrode 42L of the first transfer transistor TR1 and the gate electrode 42R of the second transfer transistor TR2 in plan view.

[Second embodiment]
A solid-state imaging device 1B according to the second embodiment of the present technology basically has the same configuration as that of the solid-state imaging device 1A according to the above-described first embodiment, except for the following configurations.

That is, as shown in FIGS. 13 and 14, the solid-state imaging device 1B according to the second embodiment newly includes an n-type semiconductor region 28 (fifth semiconductor region). Other configurations are the same as those of the above-described first embodiment.

As shown in FIGS. 13 and 14, the n-type semiconductor region 28 crosses the intra-cell diffusion separation region 23 to control the potential barrier between the first photoelectric conversion section 32L and the second photoelectric conversion section 32R. there is The n-type semiconductor region 28 is arranged at a position deeper than the insulating separator 35 and is separated from the insulating separator 35 . The n-type semiconductor region 28 extends along the Y direction in plan view, and the width in the X direction is wider than the width of the insulating separator 35 in the X direction. The n-type semiconductor region 28 crosses directly under the insulating separator 35 and partially overlaps the insulating separator 35 in a plan view.

The n-type semiconductor region 28 has an impurity concentration capable of canceling the impurities contained in the p-type semiconductor region 24 and inverting the conductivity type from p-type to n-type. In the second embodiment, the n-type semiconductor region 28 has an impurity concentration higher than that of the p-type semiconductor region 24 and the n-type semiconductor region 25, for example.

The solid-state imaging device 1B according to the second embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment.

Further, in the solid-state imaging device 1B according to the second embodiment, the n-type semiconductor region 28 is provided directly below the insulating separator, so that a A desired potential can be formed, and the supernatant signal amount and the saturation signal amount Qs in the single photoelectric conversion cell 31 can be adjusted.

Note that the n-type semiconductor region 28 may be selectively formed in the intra-cell diffusion isolation region 23 with a width substantially equal to that of the intra-cell diffusion isolation region 23 .

[Third embodiment]
A solid-state imaging device 1C according to the third embodiment of the present technology basically has the same configuration as that of the solid-state imaging device 1A according to the above-described first embodiment, except for the following configurations.

That is, as shown in FIGS. 15 and 16, in the solid-state imaging device 1C according to the third embodiment, the inter-cell diffusion isolation region 22 between the two photoelectric conversion cells 31 arranged in the Y direction is also insulated and isolated. A body 35 is provided. Other configurations are the same as those of the above-described first embodiment. The insulating separator 35 may be provided in the inter-cell diffusion separation region 22 between the photoelectric conversion cells 31 of the same color, or may be provided in the inter-cell diffusion separation region 22 between the photoelectric conversion cells 31 of different colors.

Also in the solid-state imaging device 1C according to the third embodiment, effects similar to those of the solid-state imaging device 1A according to the above-described first embodiment can be obtained.

[Fourth embodiment]
A solid-state imaging device 1D according to the fourth embodiment of the present technology basically has the same configuration as that of the solid-state imaging device 1A according to the above-described first embodiment, except for the following configurations.

That is, as shown in FIGS. 17 to 19, in the solid-state imaging device 1D according to the fourth embodiment, an inter-cell diffusion separation region 22 (first diffusion an inter-cell isolation region 52 (first isolation region) provided so as to overlap with the isolation region), and an inter-cell isolation region 52 (first isolation region), which overlaps the intra-cell diffusion isolation region 23 in a plan view on the second surface S2 side of the semiconductor layer 21. and a provided intra-cell isolation region 53 . Further, the inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23 of the fourth embodiment are different in the Z direction than the inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23 of the above-described first embodiment. is thinner. The inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23 of the fourth embodiment are thicker in the Z direction than the insulation separator 35 in the Z direction. In the fourth embodiment, the inter-cell isolation region has a multi-stage structure including inter-cell diffusion isolation regions 22 and inter-cell insulating isolation regions 52 . Further, in the fourth embodiment, the intra-cell isolation region has a multi-stage structure including the intra-cell diffusion isolation region 23 and the intra-cell insulation isolation region 53 . The inter-cell diffusion isolation region 22 and the intra-cell diffusion isolation region 23 are arranged on the first surface S1 side of the semiconductor layer 21 . The inter-cell insulating isolation region 52 and the intra-cell insulating isolation region 53 include, for example, a trench provided in the semiconductor layer 21 and an insulating film 54 embedded in the trench. Membranes can be used.

As shown in FIGS. 17 and 19, the inter-cell insulating isolation region 52 has a planar pattern of the same shape as the inter-cell diffusion isolation region 22 . The inter-cell insulating isolation region 52 corresponding to one photoelectric conversion cell 31 (pixel 3) has an annular planar pattern ( It is a square ring-shaped plane pattern). The inter-cell insulating separation regions 52 corresponding to the plurality of photoelectric conversion cells 31 (pixels 3) have a grid plane pattern similar to the plane pattern of the inter-cell diffusion separation regions 22 . The photoelectric conversion cell 31 of the fourth embodiment includes two inter-cell diffusion separation regions 22 and two inter-cell insulation separation regions 52 extending in the X direction with the photoelectric conversion cell 31 interposed therebetween. It is surrounded by two inter-cell diffusion separation regions 22 and two inter-cell insulation separation regions 52 extending in the Y direction.

As shown in FIGS. 17 and 19, the planar pattern of the intra-cell insulating isolation region 53 is different from the planar pattern of the intra-cell diffusion isolation region 23 .

As shown in FIG. 17, the intra-cell diffusion separation region 23 extends along the Y direction in a plan view, and extends between two inter-cell diffusion separation regions 22 extending in the X direction with the photoelectric conversion cell 31 interposed therebetween. It is connected with the department and integrated.

On the other hand, as shown in FIG. 19, the intra-cell insulating isolation region 53 extends inward from the intermediate portion of each of the two inter-cell insulating isolation regions 52 extending in the X direction with the photoelectric conversion cell 31 interposed therebetween in plan view. They protrude toward (the photoelectric conversion cell 31 side) and are spaced apart from each other. A space between the two intra-cell insulating isolation regions 53 functions as an overflow path.

In the solid-state imaging device 1D according to the fourth embodiment as well, the same effects as those of the solid-state imaging device 1A according to the first embodiment can be obtained.

Further, as in the fourth embodiment, the continuous intra-cell diffusion isolation region 23 and the intermittent intra-cell insulation isolation are provided between the first photoelectric conversion portion 32L and the second photoelectric conversion portion 32R of the photoelectric conversion cell 31. By arranging the region 53, regardless of whether the two photoelectric conversion units 32L and 32R in the photoelectric conversion cell 31 have the same color or different colors, it is possible to improve potential-induced separation breakdown and optical performance.

[Fifth Embodiment]
In the first to fourth embodiments described above, pixels (photoelectric conversion cells) including two photoelectric conversion units have been described. In this fifth embodiment, a pixel (photoelectric conversion section) including one photoelectric conversion section and a transfer transistor will be described.

A solid-state imaging device 1E according to the fifth embodiment of the present technology includes a pixel block (cell block) 15A shown in FIG.

As shown in FIGS. 20 and 21, the pixel block 15A includes four pixels 3a arranged two by two in the X direction and the Y direction, and one floating diffusion shared by the four pixels 3a. FD. For example, the readout circuit 16 shown in FIG. 3 of the first embodiment is electrically connected to the floating diffusion FD.

Further, the pixel block 15A includes a photoelectric conversion section 33 provided adjacent to each other via a diffusion separation region 22a for each pixel 3a of the four pixels 3a in the semiconductor layer 21, and a first photoelectric conversion section 33 of the semiconductor layer 21. On the surface S1 side, there is provided a transfer transistor TR in which the gate electrode 42 overlaps the photoelectric conversion unit 33 in plan view for each pixel 3a of the four pixels 3a. The diffusion isolation region 22a and the transfer transistor TR correspond to the inter-cell diffusion isolation region 22 and the transfer transistors TR1 and TR2 shown in FIGS. 4 and 5 of the first embodiment, respectively.
Also, the pixel block 15A has an insulating separator 35 .

Here, the pixel block 15A of the fifth embodiment includes two photoelectric conversion units 33 arranged adjacent to each other in the Y direction with the diffusion isolation region 22a extending in the X direction interposed therebetween, and a diffusion isolation region extending in the Y direction. and two photoelectric conversion units 33 arranged in the X direction adjacent to each other via 22a. Therefore, in the two photoelectric conversion units 33 arranged adjacent to each other in the Y direction via the diffusion separation region 22a extending in the X direction, one photoelectric conversion unit 33 corresponds to the first photoelectric conversion unit of the present technology, The other photoelectric conversion unit 33 corresponds to the second photoelectric conversion unit of the present technology. In addition, in the two photoelectric conversion units 33 arranged adjacent to each other in the X direction via the diffusion isolation region 22a extending in the Y direction, one photoelectric conversion unit 33 corresponds to the first photoelectric conversion unit of the present technology, The other photoelectric conversion unit 33 corresponds to the second photoelectric conversion unit of the present technology.

In addition, the transfer transistor TR in which one photoelectric conversion unit 33 and the gate electrode 42 of the two photoelectric conversion units 33 arranged adjacent to each other in the Y direction via the diffusion isolation region 22a extending in the X direction overlap in plan view. corresponds to the first transistor of the present technology, and the transfer transistor TR in which the photoelectric conversion unit 33 and the gate electrode 42 overlap each other in plan view corresponds to the second transistor of the present technology. In addition, the transfer transistor TR in which one photoelectric conversion unit 33 and the gate electrode 42 of the two photoelectric conversion units 33 arranged adjacent to each other in the X direction via the diffusion isolation region 22a extending in the Y direction overlap in plan view. corresponds to the first transistor of the present technology, and the transfer transistor TR in which the photoelectric conversion unit 33 and the gate electrode 42 overlap each other in plan view corresponds to the second transistor of the present technology.

As shown in FIGS. 20 and 21, the photoelectric conversion section 33 of each of the four pixels 3a is partitioned by the diffusion isolation region 22a. That is, the two photoelectric conversion units 33 arranged in the Y direction are adjacent to each other via the diffusion isolation region 22a extending in the X direction. Also, the two photoelectric conversion units 33 arranged in the X direction are adjacent to each other with the diffusion isolation region 22a extending in the Y direction interposed therebetween.

The photoelectric conversion unit 33 photoelectrically converts light incident from the second surface (light incident surface, back surface) S2 of the semiconductor layer 21 to generate signal charges. Further, the photoelectric conversion unit 33 includes, for example, an n-type semiconductor region (second conductivity type second semiconductor region), similar to the first and second photoelectric conversion units 32L and 32R shown in FIG. ) 25, constituting a photoelectric conversion element PD. The photoelectric conversion unit 33 of this embodiment also functions as a floating diffusion that temporarily accumulates the generated signal charges.

As shown in FIG. 20, the floating diffusion FD is provided at an intersection where the diffusion isolation region 22a extending in the X direction and the diffusion isolation region 22a extending in the Y direction intersect. That is, the floating diffusion FD is provided in the diffusion isolation region 22a on the first surface S1 side of the semiconductor layer 21, like the floating diffusion FD shown in FIG. 7 of the first embodiment.

A gate electrode 42 of each of the four transfer transistors TR included in each of the four pixels 3a is arranged around the floating diffusion FD. The floating diffusion FD is an n-type floating diffusion region made of, for example, an n-type semiconductor region as in the first embodiment described above.

As shown in FIGS. 20 and 21, the transfer transistor TR has basically the same configuration as the transfer transistors TR1 and TR2 shown in FIGS. 3 and 4 of the first embodiment. transfer the signal charge photoelectrically converted to the floating diffusion FD. The floating diffusion FD accumulates and holds signal charges transferred from the photoelectric conversion unit 33 via the transfer transistor TR. The transfer transistor TR is provided so as to form a channel in the active region between the photoelectric conversion portion 33 and the floating diffusion FD, and has a gate insulating film 41 and a gate electrode 42 which are sequentially stacked on the first surface S1. . The transfer transistor TR is turned on and off according to the voltage between the gate and the source, thereby transferring signal charges from the photoelectric conversion unit 33 functioning as a source region to the floating diffusion FD functioning as a drain region.

As shown in FIGS. 20 and 21, the insulating separator 35 is provided in the diffusion isolation region 22a between the two photoelectric conversion units 33 aligned in the Y direction, and is located between the two photoelectric conversion units 33 aligned in the X direction. is provided in the diffusion isolation region 22a between the . In the fifth embodiment, two photoelectric conversion units 33 are arranged in each of the X direction and the Y direction along with the arrangement of the pixels 3a. and two on each side in the Y direction and separated from the floating diffusion FD.

The insulating separator 35 has a groove portion 36 extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side in the same manner as the insulating separator 35 shown in FIG. 6 of the first embodiment described above. , and an insulating film 37 embedded in the trench 36. As shown in FIG.

The Z-direction depth De (see FIG. 6) of the insulating separator 35 turns on one of the transfer transistors TR in two pixels 3a arranged in the X-direction or the Y-direction, as in the first embodiment described above. It is preferable to make it deeper than the thickness (height) of the modulation region in which the potential of the diffusion isolation region 22a between the two photoelectric conversion portions 33 is modulated during the period.

As in the first embodiment described above, the insulating separator 35 is formed between the gate electrode 42 of one transfer transistor TR and the other transfer transistor TR in two pixels 3a arranged in the X direction or the Y direction in a plan view. It preferably extends between and outside the gate electrode 42 . Moreover, it is preferable that the insulating separator 35 is separated from the floating diffusion FD in plan view.

As shown in FIG. 21, on the second surface S2 side of the semiconductor layer 21, similarly to the first embodiment described above, color filters 45 and microlenses 46 are sequentially laminated from the second surface S2 side. is provided. In this fifth embodiment, each of the color filters 45 and the microlenses 46 is arranged for each pixel block 15A.

According to the solid-state imaging device 1E according to the fifth embodiment, in the two pixels 3a arranged in the X direction or the Y direction, when the transfer transistor TR of one pixel 3a is turned on, the transfer transistor TR of the other pixel 3a is unintentionally A phenomenon in which the signal charge of the photoelectric conversion unit 33 leaks into the floating diffusion FD can be suppressed.

[Sixth Embodiment]
≪Example of application to electronic equipment≫
The present technology (technology according to the present disclosure) is applied to various electronic devices such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions. can do.

FIG. 22 is a diagram showing a schematic configuration of an electronic device (for example, camera) according to the sixth embodiment of the present technology.

As shown in FIG. 22, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a driving circuit 104, and a signal processing circuit 105. This electronic device 100 shows an embodiment in which the solid-state imaging devices according to the first to fifth embodiments of the present technology are used as the solid-state imaging device 101 in an electronic device (for example, a camera).

The optical lens 102 forms an image of image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. As a result, signal charges are accumulated in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls a light irradiation period and a light shielding period for the solid-state imaging device 101 . A drive circuit 104 supplies drive signals for controlling the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103 . Signal transfer of the solid-state imaging device 101 is performed by a driving signal (timing signal) supplied from the driving circuit 104 . The signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101 . The video signal that has undergone signal processing is stored in a storage medium such as a memory, or output to a monitor.

With such a configuration, in the electronic device 100 of the sixth embodiment, the light reflection suppression unit in the solid-state imaging device 101 suppresses light reflection from the light shielding film and the insulating film in contact with the air layer. This can be suppressed, and the image quality can be improved.

Note that the electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to cameras, and can be applied to other electronic devices. For example, the present invention may be applied to imaging devices such as camera modules for mobile devices such as mobile phones and tablet terminals.

In addition to the above-described solid-state imaging device as an image sensor, the present technology is also called a ToF (Time of Flight) sensor, and can be applied to light detection devices in general, including ranging sensors that measure distance. can. A ranging sensor emits irradiation light toward an object, detects the reflected light that is reflected from the surface of the object, and detects the light that returns after the irradiation light is emitted. A sensor that calculates the distance to an object based on flight time. As the structure of the element isolation region of this distance measuring sensor, the structure of the element isolation region described above can be adopted.

Note that the present technology may be configured as follows.
(1)
a semiconductor layer having first and second surfaces opposite to each other;
and a photoelectric conversion cell provided in the semiconductor layer,
The photoelectric conversion cell is
first and second photoelectric conversion units provided adjacent to each other via a first diffusion isolation region in plan view in the semiconductor layer;
a floating diffusion provided in the first diffusion isolation region on the first surface side of the semiconductor layer;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion section in plan view, and the first photoelectric conversion section transfers signal charges from the first photoelectric conversion section to the floating diffusion. a transfer transistor;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion section in a plan view, and a second photoelectric conversion section for transferring signal charges from the second photoelectric conversion section to the floating diffusion. a transfer transistor;
provided in the first diffusion separation region on the first surface side of the semiconductor layer, separated from the floating diffusion, and extending between the gate electrodes of the first and second transfer transistors in plan view an insulating separator that
A photodetector having
(2)
The photodetector according to (1), wherein the insulating separator extends between and outside the gate electrodes of the first and second transfer transistors in plan view.
(3)
The depth of the insulating isolation is the thickness of the modulation region in which the potential of the first diffusion isolation region is modulated while one of the first and second transfer transistors is turned on in the phase difference mode. The photodetector according to (1) or (2) above, which is deeper than the depth.
(4)
the first diffusion isolation region is composed of a first conductivity type first semiconductor region,
The photodetector according to any one of (1) to (3), wherein each of the first and second photoelectric conversion units includes a second conductivity type second semiconductor region.
(5)
The first and second transfer transistors each have a gate insulating film provided on the first surface side of the semiconductor layer,
The photodetector according to any one of (1) to (4) above, wherein the insulating separator is covered with the gate insulating film.
(6)
The light according to any one of (1) to (5) above, wherein the insulating separator includes a groove provided on the first surface side of the semiconductor layer and an insulating film embedded in the groove. detection device.
(7)
From (1) above, wherein the photoelectric conversion cell further includes a third semiconductor region of a first conductivity type provided in each of the first and second photoelectric conversion units on the first surface side of the semiconductor layer The photodetector according to any one of (6).
(8)
The photoelectric conversion cell is provided in the first and second photoelectric conversion portions on the first surface side of the semiconductor layer so as to be in contact with the bottom portion of the third semiconductor region, and has an impurity concentration higher than that of the second semiconductor region. The photodetector according to any one of (1) to (7) above, further comprising a fourth semiconductor region of the second conductivity type with a high .
(9)
The above ( The photodetector according to any one of 1) to (8).
(10)
the photoelectric conversion cells are arranged adjacent to each other with the second diffusion isolation region interposed therebetween in plan view;
The photodetector according to any one of (1) to (9) above, wherein the insulating separator is also provided in the second diffusion separation region.
(11)
a first isolation region provided on the second surface side of the semiconductor layer so as to overlap with the first diffusion isolation region in plan view;
Any one of (1) to (10) above, further comprising a second isolation region provided on the second surface side of the semiconductor layer so as to overlap with the second diffusion isolation region in a plan view. photodetector.
(12)
a semiconductor layer having first and second surfaces opposite to each other;
first and second photoelectric conversion units provided adjacent to each other via a diffusion isolation region in the semiconductor layer;
a floating diffusion provided in the diffusion isolation region on the first surface side of the semiconductor layer;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the first photoelectric conversion unit to the floating diffusion. a first transfer transistor to
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the second photoelectric conversion unit to the floating diffusion. a second transfer transistor to
an insulating separator provided in the diffusion isolation region apart from the charge holding portion and extending between the gate electrodes of the first and second transfer transistors in a plan view. .
(13)
The photodetector according to (12) above, wherein the insulating separator extends between and outside the gate electrodes of the first and second transfer transistors in plan view.
(14)
the diffusion isolation region extends in a first direction;
The photodetector according to (12) or (13) above, wherein the first and second photoelectric conversion units are arranged on the same plane in a second direction orthogonal to the first direction.
(15)
a photodetector, an optical lens that forms an image of image light from a subject on an imaging surface of the photodetector, and a signal processing circuit that performs signal processing on a signal output from the photodetector,
The photodetector is
a semiconductor layer having first and second surfaces opposite to each other;
and a photoelectric conversion cell provided in the semiconductor layer,
The photoelectric conversion cell is
first and second photoelectric conversion units provided adjacent to each other via a first diffusion isolation region in plan view in the semiconductor layer;
a floating diffusion provided in the first diffusion isolation region on the first surface side of the semiconductor layer;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion section in plan view, and the first photoelectric conversion section transfers signal charges from the first photoelectric conversion section to the floating diffusion. a transfer transistor;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion section in a plan view, and a second photoelectric conversion section for transferring signal charges from the second photoelectric conversion section to the floating diffusion. a transfer transistor;
provided in the first diffusion separation region on the first surface side of the semiconductor layer, separated from the floating diffusion, and extending between the gate electrodes of the first and second transfer transistors in plan view an insulating separator that
electronic equipment.
(16)
a photodetector, an optical lens that forms an image of image light from a subject on an imaging surface of the photodetector, and a signal processing circuit that performs signal processing on a signal output from the photodetector,
The photodetector is
a semiconductor layer having first and second surfaces opposite to each other;
first and second photoelectric conversion units provided adjacent to each other via a diffusion isolation region in the semiconductor layer;
a floating diffusion provided in the diffusion isolation region on the first surface side of the semiconductor layer;
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the first photoelectric conversion unit to the floating diffusion. a first transfer transistor to
A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the second photoelectric conversion unit to the floating diffusion. a second transfer transistor to
and an insulating separator provided in the diffusion isolation region apart from the charge holding portion and extending between the gate electrodes of the first and second transfer transistors in a plan view.

The scope of the present technology is not limited to the illustrated and described exemplary embodiments, but also includes all embodiments that achieve effects equivalent to those intended by the present technology. Furthermore, the scope of the technology is not limited to the combination of inventive features defined by the claims, but may be defined by any desired combination of the particular features of each and every disclosed feature.

1 solid-state imaging device 2 semiconductor chip 2A pixel array section 2B peripheral section 3 pixel 4 vertical drive circuit 5 column signal processing circuit 6 horizontal drive circuit 7 output circuit 8 control circuit 10 pixel drive line 12 horizontal signal line 13 logic circuit 14 bonding pad 15 , 15A pixel block 16 readout circuit 21 semiconductor layer 22 inter-cell diffusion isolation region 22a diffusion isolation region 23 intra-cell diffusion isolation region 24 p-type semiconductor region (first semiconductor region)
25 n-type semiconductor region (second semiconductor region)
26 n-type semiconductor region (fourth semiconductor region)
27 p-type semiconductor region (third semiconductor region)
28 n-type semiconductor region (fifth semiconductor region)
31 Photo Diode
32L first photoelectric conversion unit 32R second photoelectric conversion unit 33 photoelectric conversion unit 35 insulating separator 36 groove 37 insulating film 41 gate insulating film 42, 42L, 42R gate electrode 45 color filter 46 microlens 52 inter-cell insulating separation region 53 cell Inner isolation region 54 Insulating film FD Floating diffusion PD Photoelectric conversion element PD1 First photoelectric conversion element PD2 Second photoelectric conversion element RST Reset transistor SEL Selection transistor TR Transfer transistor TR1 First transfer transistor TR2 Second transfer transistor

Claims (16)

1. a semiconductor layer having first and second surfaces opposite to each other;
   and a photoelectric conversion cell provided in the semiconductor layer,
   The photoelectric conversion cell is
   first and second photoelectric conversion units provided adjacent to each other via a first diffusion isolation region in plan view in the semiconductor layer;
   a floating diffusion provided in the first diffusion isolation region on the first surface side of the semiconductor layer;
   A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion section in plan view, and the first photoelectric conversion section transfers signal charges from the first photoelectric conversion section to the floating diffusion. a transfer transistor;
   A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion section in a plan view, and a second photoelectric conversion section for transferring signal charges from the second photoelectric conversion section to the floating diffusion. a transfer transistor;
   provided in the first diffusion separation region on the first surface side of the semiconductor layer, separated from the floating diffusion, and extending between the gate electrodes of the first and second transfer transistors in plan view an insulating separator that
   A photodetector having
2. 2. The photodetector according to claim 1, wherein said insulating separator extends between and outside said gate electrodes of said first and second transfer transistors in plan view.
3. The depth of the insulating isolation is the thickness of the modulation region in which the potential of the first diffusion isolation region is modulated while one of the first and second transfer transistors is turned on in the phase difference mode. 2. The photodetector of claim 1, deeper than the depth.
4. the first diffusion isolation region is composed of a first conductivity type first semiconductor region,
   2. The photodetector according to claim 1, wherein each of said first and second photoelectric conversion units includes a second conductivity type second semiconductor region.
5. The first and second transfer transistors each have a gate insulating film provided on the first surface side of the semiconductor layer,
   2. The photodetector according to claim 1, wherein said insulating separator is covered with said gate insulating film.
6. The photodetector according to claim 1, wherein the insulating separator includes a groove provided on the first surface side of the semiconductor layer, and an insulating film embedded in the groove.
7. 2. The photoelectric conversion cell according to claim 1, further comprising a third semiconductor region of a first conductivity type provided in each of said first and second photoelectric conversion parts on said first surface side of said semiconductor layer. photodetector.
8. The photoelectric conversion cell is provided in the first and second photoelectric conversion portions on the first surface side of the semiconductor layer so as to be in contact with the bottom portion of the third semiconductor region, and has an impurity concentration higher than that of the second semiconductor region. 8. The photodetector of claim 7, further comprising a fourth semiconductor region of the second conductivity type with a high .
9. 3. The photoelectric conversion cell further includes a second conductivity type fifth semiconductor region that crosses the first diffusion separation region and electrically connects the first photoelectric conversion unit and the second photoelectric conversion. 2. The photodetector according to 1.
10. the photoelectric conversion cells are arranged adjacent to each other with the second diffusion isolation region interposed therebetween in plan view;
    2. The photodetector according to claim 1, wherein said insulating separator is also provided in said second diffusion separation region.
11. a first isolation region provided on the second surface side of the semiconductor layer so as to overlap with the first diffusion isolation region in plan view;
    11. The photodetector according to claim 10, further comprising a second isolation region provided on the second surface side of the semiconductor layer so as to overlap with the second diffusion isolation region in plan view.
12. a semiconductor layer having first and second surfaces opposite to each other;
    first and second photoelectric conversion units provided adjacent to each other via a diffusion isolation region in the semiconductor layer;
    a floating diffusion provided in the diffusion isolation region on the first surface side of the semiconductor layer;
    A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the first photoelectric conversion unit to the floating diffusion. a first transfer transistor to
    A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the second photoelectric conversion unit to the floating diffusion. a second transfer transistor to
    an insulating separator provided in the diffusion isolation region apart from the charge holding portion and extending between the gate electrodes of the first and second transfer transistors in plan view;
    A photodetector, comprising:
13. 13. The photodetector according to claim 12, wherein the insulating separator extends between and outside the gate electrodes of each of the first and second transfer transistors in plan view.
14. the diffusion separation region extends in a first direction;
    13. The photodetector according to claim 12, wherein said first and second photoelectric conversion units are arranged in a second direction orthogonal to said first direction within the same plane.
15. a photodetector, an optical lens that forms an image of image light from a subject on an imaging surface of the photodetector, and a signal processing circuit that performs signal processing on a signal output from the photodetector,
    The photodetector is
    a semiconductor layer having first and second surfaces opposite to each other;
    and a photoelectric conversion cell provided in the semiconductor layer,
    The photoelectric conversion cell is
    first and second photoelectric conversion units provided adjacent to each other via a first diffusion isolation region in plan view in the semiconductor layer;
    a floating diffusion provided in the first diffusion isolation region on the first surface side of the semiconductor layer;
    A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion section in plan view, and the first photoelectric conversion section transfers signal charges from the first photoelectric conversion section to the floating diffusion. a transfer transistor;
    A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion section in a plan view, and a second photoelectric conversion section for transferring signal charges from the second photoelectric conversion section to the floating diffusion. a transfer transistor;
    provided in the first diffusion separation region on the first surface side of the semiconductor layer, separated from the floating diffusion, and extending between the gate electrodes of the first and second transfer transistors in plan view an insulating separator that
    electronic equipment.
16. a photodetector, an optical lens that forms an image of image light from a subject on an imaging surface of the photodetector, and a signal processing circuit that performs signal processing on a signal output from the photodetector,
    The photodetector is
    a semiconductor layer having first and second surfaces opposite to each other;
    first and second photoelectric conversion units provided adjacent to each other via a diffusion isolation region in the semiconductor layer;
    a floating diffusion provided in the diffusion isolation region on the first surface side of the semiconductor layer;
    A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the first photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the first photoelectric conversion unit to the floating diffusion. a first transfer transistor to
    A gate electrode is provided on the first surface side of the semiconductor layer so as to overlap with the second photoelectric conversion unit in plan view, and transfers signal charges photoelectrically converted by the second photoelectric conversion unit to the floating diffusion. a second transfer transistor to
    an insulating separator provided in the diffusion isolation region apart from the charge holding portion and extending between the gate electrodes of the first and second transfer transistors in plan view;
    electronic equipment.

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