WO2023282888A1 - Schéma d'activité de données à latence pour une optimisation de puissance de couche 2 - Google Patents

Schéma d'activité de données à latence pour une optimisation de puissance de couche 2 Download PDF

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Publication number
WO2023282888A1
WO2023282888A1 PCT/US2021/040496 US2021040496W WO2023282888A1 WO 2023282888 A1 WO2023282888 A1 WO 2023282888A1 US 2021040496 W US2021040496 W US 2021040496W WO 2023282888 A1 WO2023282888 A1 WO 2023282888A1
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WIPO (PCT)
Prior art keywords
layer
processing circuit
microcontroller
pdu
baseband chip
Prior art date
Application number
PCT/US2021/040496
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English (en)
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WO2023282888A8 (fr
Inventor
Su-Lin Low
Yunhong Li
Hausting Hong
Chun-I Lee
Sheethal KOVOOR
Tianan MA
Jianzhou Li
Sonali Bagchi
Sammy Tzu-Kiang PAO
Na CHEN
Sangwon Ki
Zengyu Wang
Swaminathan Sureshchandran
Sun Hee WEE
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Zeku, Inc.
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Application filed by Zeku, Inc. filed Critical Zeku, Inc.
Priority to PCT/US2021/040496 priority Critical patent/WO2023282888A1/fr
Publication of WO2023282888A1 publication Critical patent/WO2023282888A1/fr
Publication of WO2023282888A8 publication Critical patent/WO2023282888A8/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/0252—Traffic management, e.g. flow control or congestion control per individual bearer or channel
    • H04W28/0263—Traffic management, e.g. flow control or congestion control per individual bearer or channel involving mapping traffic to individual bearers or channels, e.g. traffic flow template [TFT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/0231—Traffic management, e.g. flow control or congestion control based on communication conditions
    • H04W28/0236—Traffic management, e.g. flow control or congestion control based on communication conditions radio quality, e.g. interference, losses or delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/0268—Traffic management, e.g. flow control or congestion control using specific QoS parameters for wireless networks, e.g. QoS class identifier [QCI] or guaranteed bit rate [GBR]

Definitions

  • Embodiments of the present disclosure relate to apparatus and method for wireless communication.
  • Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts.
  • a radio access technology is the underlying physical connection method for a radio-based communication network.
  • Many modem terminal devices such as mobile devices, support several RATs in one device.
  • the 3rd Generation Partnership Project defines a Radio Layer 2 (referred to here as “Layer 2”) as part of the cellular protocol stack structure corresponding to the data plane (DP) (also referred to as the “user plane”), which includes a Service Data Adaptation Protocol (SDAP) layer, a Packet Data Convergence Protocol (PDCP) layer, a Radio Link Control (RLC) layer, and a Medium Access Control (MAC), from top to bottom in the stack.
  • DP data plane
  • SDAP Service Data Adaptation Protocol
  • PDCP Packet Data Convergence Protocol
  • RLC Radio Link Control
  • MAC Medium Access Control
  • a baseband chip including a downlink (DL) Layer 2 block may include a buffer configured to receive a DL Layer 2 protocol data unit (PDU) from a MAC circuit.
  • the DL Layer 2 block may also include a microcontroller.
  • the microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active.
  • the microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive.
  • the DL Layer 2 block may further include a DL Layer 2 processing circuit.
  • the DL Layer 2 processing circuit may be configured to fetch the PDU from the buffer when activated.
  • the DL Layer 2 processing circuit may be further configured to perform Layer 2 processing of the PDU.
  • a baseband chip including a uplink (UL) Layer 2 block may include a microcontroller.
  • the microcontroller may be configured to activate a UL Layer 2 processing circuit when a UL grant indication for a UL Layer 2 PDU is received.
  • the microcontroller may be configured to send an activation signal to DL microcontroller when the UL Layer 2 processing circuit is activated.
  • the activation signal may trigger an activation of a DL Layer 2 processing circuit.
  • the UL Layer 2 block may also include a UL Layer 2 processing circuit.
  • the UL Layer 2 processing circuit may be configured to retrieve a first upper layer packet when the UL grant indication is received.
  • the UL Layer 2 processing circuit may be configured to generate the UL Layer 2 PDU by processing the first upper layer packet.
  • the UL Layer 2 processing circuit may be configured to send the UL Layer 2 PDU to a UL buffer.
  • a baseband chip including a
  • the DL Layer 2 block may include a buffer configured to receive a DL Layer 2 PDU from a MAC circuit.
  • the DL Layer 2 block may further include a DL microcontroller.
  • the DL microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active.
  • the DL microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive.
  • the UL Layer 2 block may include a UL microcontroller.
  • the UL microcontroller may be configured to activate a UL Layer 2 processing circuit when a UL grant indication for a UL Layer 2 PDU is received.
  • the UL microcontroller may be configured to send an activation signal to DL microcontroller when the UL Layer 2 processing circuit is activated, the activation signal triggering an activation of a DL Layer 2 processing circuit.
  • a method of wireless communication of a baseband chip may include receiving, by a buffer, a DL Layer 2 PDU from a MAC circuit. The method may further include determining, by a microcontroller, whether a DL Layer 2 processing circuit is active. The method may further include delaying, by the microcontroller, an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive. [0008] According to yet another aspect of the present disclosure, a method of wireless communication of a baseband chip is disclosed.
  • the method may include activating, by a microcontroller, a UL Layer 2 processing circuit when a UL grant indication for a UL Layer 2 PDU is received.
  • the method may include sending, by the microcontroller, an activation signal to DL microcontroller when the UL Layer 2 processing circuit is activated.
  • the activation signal may trigger an activation of a DL Layer 2 processing circuit.
  • FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.
  • FIG. 2 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.
  • RF radio frequency
  • FIG. 3A illustrates a first detailed block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure.
  • FIG. 3B illustrates a second detailed block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure.
  • FIG. 3C illustrates a data flow of exemplary DL/UL Layer 2 data processing using the baseband chip of FIG. 3 A, according to some embodiments of the present disclosure.
  • FIG. 4A illustrates a flow chart of a first exemplary method for DL Layer 2 data processing, according to some embodiments of the present disclosure.
  • FIG. 4B illustrates a flow chart of a second exemplary method for UL Layer 2 data processing, according to some embodiments of the present disclosure.
  • FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.
  • FIG. 6 illustrates a block diagram of a conventional baseband chip.
  • references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
  • the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense.
  • terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
  • CDMA code division multiple access
  • TDMA time division multiple access
  • FDMA frequency division multiple access
  • OFDMA orthogonal frequency division multiple access
  • SC- FDMA single-carrier frequency division multiple access
  • WLAN wireless local area network
  • a CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc.
  • RAT radio access technology
  • UTRA Universal Terrestrial Radio Access
  • E-UTRA evolved UTRA
  • CDMA 2000 etc.
  • GSM global system for mobile communications
  • An OFDMA network may implement a first RAT, such as LTE or NR.
  • a WLAN system may implement a second RAT, such as Wi-Fi.
  • the techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.
  • Layer 2 is the protocol stack layer responsible for ensuring a reliable, error-free datalink for the wireless modem (referred to herein as a “baseband chip”) of a UE. More specifically, Layer 2 interfaces with Radio Layer 1 (also referred to as “Layer 1” or the “physical (PHY) layer”) and Radio Layer 3 (also referred to as “Layer 3” or the “Internet Protocol (IP) layer”), passing data packets up or down the protocol stack structure, depending on whether the data packets (also referred to herein as protocol data units (PDUs) are associated with UL or DL transmissions.
  • Radio Layer 1 also referred to as “Layer 1” or the “physical (PHY) layer”
  • Radio Layer 3 also referred to as “Layer 3” or the “Internet Protocol (IP) layer”
  • IP Internet Protocol
  • Layer 2 may perform de-multiplexing / multiplexing, segmentation / reassembly, aggregation / de-aggregation, and sliding window automatic repeat request (ARQ) techniques, among others, to ensure reliable end-to-end data integrity and in-order error-free delivery of data packets.
  • Layer 3 data packets e.g., IP data packets
  • MAC layer packets e.g., 5G NR
  • Layer 1 data packets may be input into the Layer 2 protocol stack, where Layer 2 data processing operations are performed on the data packets before being passed up to Layer 3.
  • Layer 3 performs IP header extraction, IP checksum, IP tracing, and IP routing and classification, among other things.
  • FIG. 6 illustrates a block diagram of a conventional baseband chip 600. As seen in
  • a conventional baseband chip 600 may include PHY subsystem 602 configured to transmit and/or receive data packets over an air interface, a protocol stack 604 (e.g., residing at the baseband chip) that includes a control plane 606 and a data plane 608, Layer 3/Layer 4 subsystems 610, and an application processor (AP) host 612.
  • Control plane 606 performs two main functions: non-access stratum (NAS) function and radio resource control (RRC) function.
  • the NAS function performs network layer control that relates to mobility management, session management, security management, and system selection, just to name a few.
  • the RRC function performs radio resource allocation and configuration, as well as the radio channel control of radio bearers, logical channels, and security (ciphering, integrity configurations).
  • Data plane 608 performs Layer 2 and Layer 3/4 functions.
  • Layer 2 functions relate to PDU processing.
  • the MAC layer performs multiplexing and demultiplexing, and mapping of logical channels to transport channels.
  • the RLC layer performs automatic repeat request (ARQ) procedures at the radio link level and the error recovery of each logical channel.
  • the PDCP layer performs packet level processing for data ciphering, integrity, and compression.
  • the SDAP layer performs quality-of-service (QoS) classification of IP flows to data radio bearers.
  • QoS quality-of-service
  • Layer 2 protocol data stack Namely, the data stack processing resides on a Layer 2 main processor and uses a limited number of hardware accelerators.
  • the Layer 2 main processor (not shown) may access a data packet by direct memory access (DMA) from a PHY layer memory at the PHY subsystem(s) 602.
  • the HW accelerators may DMA a UL data packet to the Layer 3 external DDR memory of Layer 3 subsystem 610.
  • Layer 2 data processing e.g., processing the transport blocks received from Layer 1 (e.g., PHY subsystem 602) in the DL user plane or processing data packets received from Layer 3 in the UL user plane
  • a generic baseband processor such as a central processing unit (CPU) or a digital signal processor (DSP).
  • CPU central processing unit
  • DSP digital signal processor
  • data may be frequently transferred between the generic main processor (not shown) and external memory (Layer 3 external DDR memory or Layer 2 buffer - not shown), e.g., for buffering between each layer.
  • Layer 3 external DDR memory or Layer 2 buffer - not shown external memory
  • the known solutions for Layer 2 data processing suffer from high power consumption, large data buffer, and long process delays.
  • a user equipment is configurated with Carrier Aggregation
  • CA Component Carriers
  • CCs Component Carriers
  • the UE may receive multiple grants concurrently, one from each CC and Cell, which determines the scheduled packets reception and transmission in the downlink and uplink directions, respectively.
  • the DL MAC layer receives code blocks from the
  • the DL MAC layer may then re-order each Transport Block (TB), extract the MACsubPDU headers to obtain the MAC PDUs, and transfer the packet to the RLC and PDCP DP Layer 2 for further processing in each logical channel and associated radio bearers.
  • TB Transport Block
  • the packets are sent to Layer 3/Layer 4 subsystems 610, where the QoS flows in each radio bearer are routed to the appropriate application.
  • the Layer 3/Layer 4 subsystems 610 prepare the UL packets from multiple QoS flows for each radio bearers, and the UL packets may then be transferred to Layer 2 logical channel queues, ready for transmission.
  • the UL MAC layer receives the UL grant, which allocates resources for the physical uplink shared channel (PUSCH)) using the physical downlink control channel (PDCCH) at the beginning of a slot.
  • the UL grant may be received in a downlink control indicator (DCI) on the PDCCH.
  • DCI downlink control indicator
  • the UL grant may inform the UE to transmit the UL MACPDU at a time delay equivalent to K2 slots away from the current slot.
  • K2 ⁇ 1 grants are implied to be serviced for low latency application data, and hence, radio bearers/logical channels (LCs) data are pulled into such grants to be sent out as soon as possible.
  • the UL MAC scheduling algorithm uses a Logical Channel Prioritization (LCP) method to schedule packets from a logical channel (LC) according to allocated grant bytes from a configured maximum bucket size setting.
  • LCP Logical Channel Prioritization
  • One challenge of conventional data plane 608 processing relates to the power consumption by baseband chip 600, which needs to support different application types (including high throughput high latency data transfers), as well as low latency low data rate applications.
  • the power usage at conventional baseband chip 600 is not optimized.
  • conventional data plane 608 processing uses resources inefficiently when processing DL/UL Layer 2/Layer 3 data packets, consumes power unnecessarily during low data rate transfers, uses an increased double data rate (DDR) transfer, and an increased data plane interconnect bus transactions during periods of activity, and Layer 2 to Layer 3 data transfers are unoptimized and cause undue delays.
  • DDR double data rate
  • NoC network- on-chip
  • the present disclosure provides a data plane processing technique that optimizes processing activity scheduling for the DL and UL processing, which significantly reduces power consumption, as compared to known approaches.
  • the DL data activity is triggered at optimized times to lower the power usage during low data rate applications. For example, these DL activity timelines are either aligned with UL activity periods, or triggered at optimal latency periods, or when an inline buffer memory is full.
  • a minimum tolerant-latency time (derived from the QoS characteristics of all active flows of the radio bearer) is used to minimize power from data processing activity without sacrificing latency performance.
  • the UL Layer 2 data activity period is optimized to align with the DL activity periods to minimize power usage, without sacrificing QoS latency performance. Additional details of these techniques are provided below in connection with FIGs. 1-5.
  • Layer 2 data processing the same or similar techniques may be applied to Layer 3 and/or Layer 4 data processing to optimize power consumption at Layer 3 and/or Layer 4 subsystems without departing from the scope of the present disclosure.
  • FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.
  • wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106.
  • User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (IoT) node.
  • V2X vehicle to everything
  • IoT Intemet-of-Things
  • Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments.
  • BS base station
  • eNodeB or eNB enhanced Node B
  • gNodeB or gNB next-generation NodeB
  • gNodeB next-generation NodeB
  • access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102.
  • mmW millimeter wave
  • the access node 104 may be referred to as an mmW base station.
  • Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave.
  • Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters.
  • the super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range.
  • the mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.
  • Access nodes 104 which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface).
  • EPC evolved packet core network
  • 5GC 5G core network
  • access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages.
  • Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface).
  • the backhaul links may be wired or wireless.
  • Core network element 106 may serve access node 104 and user equipment 102 to provide core network services.
  • core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW).
  • HSS home subscriber server
  • MME mobility management entity
  • SGW serving gateway
  • PGW packet data network gateway
  • EPC evolved packet core
  • core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system.
  • the AMF may be in communication with a Unified Data Management (UDM).
  • UDM Unified Data Management
  • the AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.
  • IMS IP Multimedia Subsystem
  • Core network element 106 may connect with a large network, such as the Internet
  • IP Internet Protocol
  • data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114.
  • computer 110 and tablet 112 provide additional examples of possible user equipments
  • router 114 provides an example of another possible access node.
  • a generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118.
  • Database 116 may, for example, manage data related to user subscription to network services.
  • a home location register (HLR) is an example of a standardized database of subscriber information for a cellular network.
  • authentication server 118 may handle authentication of users, sessions, and so on.
  • an authentication server function (AUSF) device may be the entity to perform user equipment authentication.
  • a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.
  • Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5.
  • Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1.
  • node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1.
  • node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted.
  • node 500 When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible.
  • UI user interface
  • sensors sensors
  • core network element 106 Other implementations are also possible.
  • Transceiver 506 may include any suitable device for sending and/or receiving data.
  • Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration.
  • An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams.
  • examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques.
  • access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106.
  • Other communication hardware such as a network interface card (NIC), may be included as well.
  • NIC network interface card
  • node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included.
  • Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure.
  • Processor 502 may be a hardware device having one or more processing cores.
  • Processor 502 may execute software.
  • node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage.
  • memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502.
  • RAM random-access memory
  • ROM read-only memory
  • SRAM static RAM
  • DRAM dynamic RAM
  • FRAM ferro electric RAM
  • EEPROM electrically erasable programmable ROM
  • CD-ROM compact disc read only memory
  • HDD hard disk drive
  • Flash drive such as magnetic disk storage or other magnetic storage devices
  • SSD solid-state drive
  • memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.
  • Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions.
  • processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs).
  • SoCs system-on-chips
  • processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted.
  • API application processor
  • OS operating system
  • processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS).
  • BP baseband processor
  • RTOS real-time operating system
  • processor 502 and transceiver 506 may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508.
  • RF SoC sometimes known as a “transceiver,” referred to herein as an “RF chip”
  • some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC.
  • a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.
  • user equipment 102 may determine when a data rate threshold has been met, which indicates a low data rate scenario. Under a low data rate scenario, user equipment 102 may switch to a latency-driven data activity scheme for data plane Layer 2 power optimization.
  • user equipment 102 may receive a data packet from an external device, e.g., such as access node 104. After MAC processing of the data packet, the data packet may be input into a logical channel (LC) of an inline buffer that is part of the DL Layer 2 hardware of its baseband chip.
  • LC logical channel
  • a DL microcontroller circuit Prior to performing Layer 2 processing of the data packet and transfer to the appropriate radio bearer, a DL microcontroller circuit may determine whether a trigger event has taken place.
  • the trigger event may include one or more of, e.g., active UL Layer 2 data processing, a latency threshold being met, or an inline buffer threshold being met.
  • the DL Layer 2 processing circuit delays the DL Layer 2 processing of the data packet until one of the trigger events occurs.
  • the DL microcontroller may receive a signal from the UL microcontroller indicating a UL Layer 2 processing circuit is active. In this case, the DL microcontroller activates the DL Layer 2 processing circuit.
  • the data packet may be fetched from its LC in the inline buffer, and DL Layer 2 processing circuit may be processing the data packet.
  • the DL microcontroller may activate the DL Layer 2 processing circuit when either the latency threshold or the buffer threshold is met. In this way, the latency requirements of certain QoS flows can be achieved, and incoming DL data packets can be moved into their LCs in the inline buffer so that data packet loss is avoided.
  • Each of the DL and UL hardware blocks of user equipment 102 may be controlled on a per data packet level by microcontroller(s) (uC) through command and status queues residing in the uC local shared memory.
  • the DL and UL uC clusters may each comprise several small processor cores, specifically used to program each hardware layer block (e.g., MAC layer, RLC layer, PDCP layer, SDAP layer, etc.) in a pipelined fashion.
  • each hardware layer block e.g., MAC layer, RLC layer, PDCP layer, SDAP layer, etc.
  • the NoC interconnect resources e.g., such as bus transactions, external DDR memory access, etc.
  • FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip
  • Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210.
  • baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5.
  • apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus.
  • external memory 208 e.g., the system memory or main memory
  • baseband chip 202 is illustrated as a standalone SoC in FIG.
  • baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.
  • host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM).
  • MPSK multi-phase shift keying
  • QAM quadrature amplitude modulation
  • Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission.
  • baseband chip 202 may send the modulated signal to RF chip 204 via interface 214.
  • RF chip 204 through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion.
  • Antenna 210 e.g., an antenna array
  • antenna 210 may receive RF signals from an access node or other wireless device.
  • the RF signals may be passed to the receiver (Rx) of RF chip 204.
  • RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202.
  • baseband chip 202 may include a data plane DL Layer 2 block
  • DL Layer 2 block 220a (hereinafter “DL Layer 2 block 220a”) and a data plane UL Layer 2 block 220b (hereinafter “UL Layer 2 block 220b”).
  • DL Layer 2 block 220a may include different DL Layer 2 circuits each configured to perform certain tasks in a pipelined fashion.
  • a DL uC may also be included in DL Layer 2 block 220a.
  • the DL uC may determine whether a trigger event has taken place prior to activating the DL Layer 2 processing circuit.
  • UL Layer 2 block 220b may also include UL Layer 2 processing circuits and a UL uC.
  • the UL uC determines whether the DL Layer 2 processing circuit is active before deactivating the UL Layer 2 processing circuits.
  • the UL Layer 2 processing circuit may fetch data packets from Layer 3/Layer 4 subsystems to begin preparing a subsequent UL PDU for transmission associated with the subsequent UL grant.
  • power consumption of these uC processor cores may be minimized, as well as the Layer 2 DL/UL blocks 220a/220b and NoC interconnect resources. Additional details of these techniques are provided below in connection with FIGs. 3 A, 3B, 3C, 4A, and 4B.
  • FIG. 3A illustrates a first detailed diagram 300 of the exemplary baseband chip 202 of FIG. 2, according to some embodiments of the present disclosure.
  • FIG. 3B illustrates a second detailed diagram 325 of the exemplary baseband chip 202 of FIG. 2, according to some embodiments of the present disclosure.
  • FIG. 3C illustrates a data flow 350 of DL/UL Layer 2 data processing using the baseband chip of FIG. 2, according to some embodiments of the present disclosure.
  • FIGs. 3A, 3B, and 3C will be described together.
  • baseband chip 202 may include, e.g., PHY subsystems 302,
  • DL Layer 2 block 220a may include, e.g., DL MAC circuit 308a, DL inline buffer 310a, RLC circuit 312a, PDCP circuit 314a, DL uC LC shared memory 316a, and DL uC 318a (e.g., uC cluster).
  • UL Layer 2 block 220b may include, e.g., UL MAC circuit 308b, UL inline buffer 310b, RLC circuit 312b, PDCP circuit 314b, UL uC LC shared memory 316b, and UL microcontroller (UL uC) 318b (e.g., uC cluster).
  • UL uC UL microcontroller
  • RLC circuit 312a and PDCP circuit 314a may be collectively referred to herein as the “DL Layer 2 processing circuit.”
  • RLC circuit 312b and PDCP circuit 314b may be collectively referred to as a “UL Layer 2 processing circuit.”
  • Each of DL Layer 2 block 220a and UL Layer 2 block 220b are controlled on a per packet level basis by their respective DL/UL uC 318a, 318b, through command and status queues residing in the respective DL/UL uC LC shared memories 316a, 316b.
  • Each of DL uC 318a and UL uC 318b may each include several small processor cores, which are specifically used to program each of the Layer 2 circuits in a pipelined fashion.
  • Phase 1 includes DL MAC processing, which is driven by PHY decode tasks.
  • the PHY decoder sends decoded code blocks (CBs) to DL MAC circuit 308a, which performs CB re-ordering, stitches the CBs together, and searches for complete MACPDU packets.
  • DL MAC circuit 308a then performs MACSubPDU header extraction to decode the fields in the header and stores the MACSubPDU packets in the respective LC queues at DL inline buffer 310a, as identified by the LC identifier (LCId) of the PDU.
  • CBs code blocks
  • DL MAC circuit 308a performs MACSubPDU header extraction to decode the fields in the header and stores the MACSubPDU packets in the respective LC queues at DL inline buffer 310a, as identified by the LC identifier (LCId) of the PDU.
  • LCId LC identifier
  • Phase 2 includes DL Layer 2 processing of the MACSubPDU by the DL
  • Layer 2 processing circuit e.g., RLC circuit 312a and PDCP circuit 314a
  • Layer 2 processing circuit may be delayed to align with UL Layer 2 processing tasks, until a tolerant-latency threshold is reached, or until the DL inline buffer threshold is reached (e.g., when DL inline buffer 310a is full).
  • DL uC 318a determines whether any of the trigger events has taken place before activating the DL Layer 2 processing circuit. For example, DL uC 318a may determine whether the UL Layer 2 processing circuit is active.
  • this may be determined when a signal is received from UL uC 318b, which indicates the UL Layer 2 processing circuit is active. Otherwise, DL uC 318a may send a signal to UL uC 318b to probe whether the UL Layer 2 processing circuit is active. In some embodiments, when the UL Layer 2 processing circuit is inactive, DL uC 318a may determine whether the amount of packet data stored in the DL inline buffer 310a has reached a buffer threshold, and thus, the PDU should be processed to prevent buffer overflow. In some other embodiments, when the UL Layer 2 processing circuit is inactive, DL uC 318a may determine whether a latency threshold associated with the PDU has been reached. Additional details of the latency threshold are provided below in connection with FIG. 3B.
  • the tolerant-latency time ⁇ TLi may be associated with the
  • DL uC 318a may determine the TLi from the QoS characteristics of all active QoS flows 340 of the radio bear, and which restricts the delay of DL Layer 2 processing while minimizing power from data processing activity without sacrificing latency performance.
  • each LC 330 is mapped to an associated Radio Bearer (RBm), which may include several QoS flows i.
  • RBm Radio Bearer
  • DL uC 318a may determine the latency threshold TLi using Equation (1):
  • TLi (K1 i x PDBi) . (K2 i x PRi) . (K3 i x Ri) (1), where, for QoS flow z, PDBi is the Packet Delay Budget (PDB), PRi is the Priority Level (PR), Ri is the Resource Type (R), Kl_i is the PDB scale factor, K2_i is the PR scale factor, and K3_i is the R scale factor.
  • PDB may be in the range of about 5ms - 500ms and PR may be in the range of 1-100, e.g., where 1 is the highest priority.
  • resource type 1 may be associated with delay critical guaranteed bit rate (GBR) QoS
  • resource type 2 may include GBR
  • resource type 3 may include non-GBR.
  • DL uC 318a may determine a tolerant-time TLn using Equation (2):
  • TLn is the latency threshold that indicates the maximum amount of time the PDU can wait in the LC of DL inline buffer 310a without sacrificing DL latency performance for the QoS flow.
  • phase 2 when one of the trigger events takes place, DL uC 318a activates the DL Layer 2 processing circuit, which processes the PDU and sends it to the external DDR memory 320.
  • the PDU may then be fetched into the Layer 3/Layer 4 subsystems 322 for higher layer processing.
  • Phase 3 (at 305) includes UL MAC processing, which is driven by a PHY UL grant
  • a UL grant may arrive at every slot for each CC.
  • UL MAC circuit 308b may perform logical channel prioritization to retrieve PDUs from the LC queues in UL inline buffer 310b.
  • UL MAC circuit 308b generates MAC packets for transmission by PHY subsystems 602.
  • Phase 4 includes a determination (while phase 3 is ongoing) by UL uC
  • the UL Layer 2 processing circuit may continue processing packets for subsequent UL grants. These packets may be fetched from Layer 3Layer 4 subsystem 322 and enqueued in the appropriate LC of UL inline buffer 310b.
  • FIG. 3C Referring to FIG. 3C, the data plane Layer 2 processing resources active periods are consolidated to the aligned DL and UL activity times, where larger duration inactive period blocks are realized to minimize power consumption.
  • the data plane Layer 2 processing resources here refers to the bulk of the DL Layer 2 block 220a, UL Layer 2 block 220b, DL uC 318a, UL uC 318b, and bus interconnect and memory resources usage, just to name a few.
  • the processing resources of DL and UL MAC circuits 308a, 308b, which is performed to extract the MAC packet headers into the DL/UL inline buffers 310a, 310b, is minimal in phase 1.
  • the present techniques may be used to align Layer 3/Layer 4 activity operations, where further power minimization can be applied at Layer 3/4.
  • FIG. 4A illustrates a flow chart of a first exemplary method 400 for DL Layer 2 data processing, according to some embodiments of the present disclosure.
  • Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, DL Layer 2 block 220a, DL uC 318a, and/or node 500.
  • Method 400 may include steps 402-424 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4A.
  • phase 1 (at 301) includes DL MAC processing, which is driven by PHY decode tasks.
  • the PHY decoder sends decoded code blocks (CBs) to DL MAC circuit 308a, which performs CB re-ordering, stitches the CBs together, and searches for complete MACPDU packets, at 404.
  • CBs decoded code blocks
  • DL MAC circuit 308a then performs MAC SubPDU header extraction to decode the fields in the header, and stores the MACSubPDU packets in the respective LC queues (at 406) at DL inline buffer 310a, identified by the LC identifier (LCId) of the PDU.
  • LCId LC identifier
  • the apparatus determines whether the DL Layer 2 processing circuit is active. For example, referring to FIG. 3 A, once the packets arrive in DL inline buffer 310a, DL uC 318a determines whether the DL Layer 2 processing circuit was already activated. If so, the DL L2 processing continues; otherwise, DL uC 318a delays further DL Layer 2 processing activity until a trigger event occurs.
  • the apparatus determines the latency threshold ( TLn ) for all LCs with any active packets. For example, referring to FIG. 3B, for each LC and its mapped radio bear, DL uC 318a may determine a tolerant-time TLn using Equation (2) shown above. TLn is the latency threshold that indicates the maximum amount of time the PDU can wait in the LC of DL inline buffer 310a without sacrificing DL latency performance for the QoS flow. The next section shows how this TLn is applied to the DL processing to optimize the power usage during a low data rate. [0073] At 412, the apparatus may start a wait timer Wn if the LC was previously empty.
  • DL uC 318a may start a timer, which expires at TLn.
  • the apparatus may determine whether the buffer threshold is met. For example, referring to FIG. 3 A, DL uC 318a determines whether a buffer threshold associated with DL inline buffer 310a has been met, namely, whether DL inline buffer 310a is full. If not, at 416, the apparatus determines whether the UL Layer 2 processing circuit is active. For example, referring to FIG. 3A, DL uC 318a may determine whether the UL Layer 2 processing circuit is active.
  • this may be determined when a signal is received from UL uC 318b, which indicates the UL Layer 2 processing circuit is active. Otherwise, DL uC 318a may send a signal to UL uC 318b, probing whether the UL Layer 2 processing circuit is active. When the UL Layer 2 processing circuit is inactive, then, at 418, the apparatus may determine whether Wn has exceeded TLn. If the answer is still no, the operation may return to 402. However, if any of the trigger events of 414, 416, or 418 has occurred, then, at 420, the apparatus may activate the DL Layer 2 processing circuit, and the packet is fetched from the LC of the DL inline buffer 310a into RLC circuit 312a.
  • FIG. 4B illustrates a flow chart 450 of a second exemplary method for UL Layer 2 data processing, according to some embodiments of the present disclosure.
  • Exemplary method 450 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, UL Layer 2 block 220b, UL uC 318b, and/or node 500.
  • Method 450 may include steps 452-462 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4B.
  • the apparatus may receive a UL grant, which may arrive at every slot for each CC.
  • UL MAC circuit 308b may receive a UL grant.
  • the UL MAC circuit 308b may perform logical channel prioritization (LCP) to retrieve packets from the LC queues of UL inline buffer 310b, and compose the MAC packets for PHY transmission.
  • LCP logical channel prioritization
  • the apparatus may determine whether the DL Layer 2 processing circuit is active. For example, referring to FIG.
  • UL uC 318b may determine whether the DL Layer 2 processing circuit is still active. If so, at 456, the apparatus may maintain the UL Layer 2 processing circuit in an active state. Referring to FIG. 3B, UL Layer 2 processing circuit may continue to run UL Layer 2 RLC and PDCP operations, which includes retrieving Layer 3 data packets from Layer 3/Layer 4 subsystems 322 and enqueuing them to the Layer 2 LC queues of UL inline buffer 310b. At 458, the apparatus may determine whether a DL Activity Off signal is received. If it is not received, the operation returns to 456.
  • the apparatus may determine whether the UL inline buffer cannot accommodate subsequent packets for the next UL grant. If the UL inline buffer is able to accommodate subsequent packets, the operation returns to 456. Otherwise, at 462, the apparatus may deactivate the UL Layer 2 processing circuit. For example, referring to FIG. 3 A, UL uC 318b deactivates the UL Layer 2 processing circuit and sends a signal indicating as much to DL uC 318a.
  • the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium.
  • Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5.
  • such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer.
  • Disk and disc includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
  • a baseband chip including a DL
  • the DL Layer 2 block may include a buffer configured to receive a DL Layer 2 PDU from a MAC circuit.
  • the DL Layer 2 block may also include a microcontroller.
  • the microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active.
  • the microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive.
  • the DL Layer 2 block may further include a DL Layer 2 processing circuit.
  • the DL Layer 2 processing circuit may be configured to fetch the PDU from the buffer when activated.
  • the DL Layer 2 processing circuit may be further configured to perform Layer 2 processing of the PDU.
  • the trigger event may include a buffer threshold.
  • the microcontroller may be further configured to determine whether the buffer threshold is met when it is determined that the DL Layer 2 processing circuit is inactive. In some embodiments, the microcontroller may be further configured to [0083] activate the DL Layer 2 processing circuit when it is determined that the buffer threshold is met.
  • the trigger event may include an activation of a UL Layer 2 processing circuit.
  • the microcontroller may be further configured to determine whether the UL Layer 2 processing circuit is active when it is determined that the DL Layer 2 processing circuit is inactive. In some embodiments, the microcontroller may be further configured to activate the DL Layer 2 processing circuit when it is determined that the UL Layer 2 processing circuit is active.
  • the trigger event may include a latency threshold associated with the DL Layer 2 PDU.
  • the microcontroller may be further configured to determine whether the latency threshold associated with the DL Layer 2 PDU is met when it is determined that the DL Layer 2 processing circuit is inactive. In some embodiments, the microcontroller may be further configured to activate the DL Layer 2 processing circuit when it is determined that the latency threshold is met.
  • the microcontroller may be further configured to queue the
  • the microcontroller may be further configured to determine the latency threshold associated with the DL Layer 2 PDU based at least in part on the QoS flow.
  • a baseband chip including a
  • the UL Layer 2 block may include a microcontroller.
  • the microcontroller may be configured to activate a UL Layer 2 processing circuit when a UL grant indication for a UL Layer 2 PDU is received.
  • the microcontroller may be configured to send an activation signal to DL microcontroller when the UL Layer 2 processing circuit is activated.
  • the activation signal may trigger an activation of a DL Layer 2 processing circuit.
  • the UL Layer 2 block may also include a UL Layer 2 processing circuit.
  • the UL Layer 2 processing circuit may be configured to retrieve a first upper layer packet when the UL grant indication is received.
  • the UL Layer 2 processing circuit may be configured to generate the UL Layer 2 PDU by processing the first upper layer packet.
  • the UL Layer 2 processing circuit may be configured to send the UL Layer 2 PDU to a UL buffer.
  • the microcontroller may be further configured to determine whether the DL Layer 2 processing circuit is active when the UL Layer 2 PDU is received in the UL buffer. In some embodiments, the microcontroller may be further configured to determine whether available buffer space meets a buffer threshold. In some embodiments, the UL Layer 2 processing circuit may be further configured to retrieve a second upper layer packet when the microcontroller determines that the DL Layer 2 processing circuit is active and that the buffer threshold has not been exceeded.
  • a baseband chip including a
  • the DL Layer 2 block may include a buffer configured to receive a DL Layer 2 PDU from a MAC circuit.
  • the DL Layer 2 block may further include a DL microcontroller.
  • the DL microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active.
  • the DL microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive.
  • the UL Layer 2 block may include a UL microcontroller.
  • the UL microcontroller may be configured to activate a UL Layer 2 processing circuit when a UL grant indication for a UL Layer 2 PDU is received.
  • the UL microcontroller may be configured to send an activation signal to DL microcontroller when the UL Layer 2 processing circuit is activated, the activation signal triggering an activation of a DL Layer 2 processing circuit.
  • the DL Layer 2 processing circuit is configured to fetch the PDU from the buffer when activated. In some embodiments, the DL Layer 2 processing circuit is configured to perform Layer 2 processing of the PDU.
  • the UL Layer 2 processing circuit may be configured to retrieve a first upper layer packet when the UL grant indication is received. In some embodiments, the UL Layer 2 processing circuit may be configured to generate the UL Layer 2 PDU by processing the first upper layer packet. In some embodiments, the UL Layer 2 processing circuit may be configured to send the UL Layer 2 PDU to a UL buffer.
  • the trigger event may include a buffer threshold.
  • the microcontroller may be further configured to determine whether the buffer threshold is met when it is determined that the DL Layer 2 processing circuit is inactive. In some embodiments, the microcontroller may be further configured to activate the DL Layer 2 processing circuit when it is determined that the buffer threshold is met.
  • the trigger event may include an activation of a UL Layer 2 processing circuit.
  • the microcontroller may be further configured to determine whether the UL Layer 2 processing circuit is active when it is determined that the DL Layer 2 processing circuit is inactive. In some embodiments, the microcontroller may be further configured to activate the DL Layer 2 processing circuit when it is determined that the UL Layer 2 processing circuit is active.
  • the trigger event may include a latency threshold associated with the DL Layer 2 PDU.
  • the microcontroller may be further configured to determine whether the latency threshold associated with the DL Layer 2 PDU is met when it is determined that the DL Layer 2 processing circuit is inactive. In some embodiments, the microcontroller may be further configured to activate the DL Layer 2 processing circuit when it is determined that the latency threshold is met.
  • the microcontroller may be further configured to queue the
  • the microcontroller may be further configured to determine the latency threshold associated with the DL Layer 2 PDU based at least in part on the QoS flow.
  • a method of wireless communication of a baseband chip may include receiving, by a buffer, a DL Layer 2 PDU from a MAC circuit. The method may further include determining, by a microcontroller, whether a DL Layer 2 processing circuit is active. The method may further include delaying, by the microcontroller, an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive.
  • a method of wireless communication of a baseband chip may include activating, by a microcontroller, a UL Layer 2 processing circuit when a UL grant indication for a UL Layer 2 PDU is received.
  • the method may include sending, by the microcontroller, an activation signal to DL microcontroller when the UL Layer 2 processing circuit is activated.
  • the activation signal may trigger an activation of a DL Layer 2 processing circuit.
  • the method may include determining, by the microcontroller, whether the DL Layer 2 processing circuit is active when the UL Layer 2 PDU is received in the UL buffer. In some embodiments, the method may include determining, by the microcontroller, whether available buffer space meets a buffer threshold. In some embodiments, the method may include retrieving, by the UL Layer 2 processing circuit, a second upper layer packet when the microcontroller determines that the DL Layer 2 processing circuit is active and that the buffer threshold has not been exceeded.

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  • Computer Networks & Wireless Communication (AREA)
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Abstract

Selon un aspect de la présente divulgation, une puce de bande de base comprenant un bloc de couche 2 de liaison descendante (DL) est divulguée. Le bloc de couche 2 de DL peut comprendre un tampon configuré pour recevoir, d'un circuit de commande d'accès au support (MAC), une unité de données de protocole (PDU) de couche 2 de DL. Le bloc de couche 2 de DL peut également comprendre un microcontrôleur. Le microcontrôleur peut être configuré pour déterminer si un circuit de traitement de couche de DL 2 est actif. Le microcontrôleur peut également être configuré pour retarder une activation du circuit de traitement de couche 2 de DL jusqu'à ce qu'un événement de déclenchement se produise lorsqu'il est déterminé que le circuit de traitement de couche de DL 2 est inactif. Le bloc de couche 2 de DL peut également comprendre un circuit de traitement de couche 2 de DL. Le circuit de traitement de couche 2 de DL peut être configuré pour extraire la PDU du tampon lorsqu'il est activé. Le circuit de traitement de couche 2 de DL peut également être configuré pour effectuer un traitement de couche 2 de la PDU.
PCT/US2021/040496 2021-07-06 2021-07-06 Schéma d'activité de données à latence pour une optimisation de puissance de couche 2 WO2023282888A1 (fr)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20100325393A1 (en) * 2009-04-27 2010-12-23 Lerzer Juergen Technique for performing layer 2 processing using a distributed memory architecture
WO2016105568A1 (fr) * 2014-12-23 2016-06-30 Interdigital Patent Holdings, Inc. Procédés pour une intégration wifi dans des systèmes cellulaires
WO2018132100A1 (fr) * 2017-01-12 2018-07-19 Intel Corporation Récepteur de réveil cellulaire pour réduire la consommation d'énergie d'un équipement d'utilisateur utilisant l'agrégation lte-wlan
WO2021092585A1 (fr) * 2019-11-07 2021-05-14 Ofinno, Llc Accès aléatoire sur de multiples empilements de protocoles actifs

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100325393A1 (en) * 2009-04-27 2010-12-23 Lerzer Juergen Technique for performing layer 2 processing using a distributed memory architecture
WO2016105568A1 (fr) * 2014-12-23 2016-06-30 Interdigital Patent Holdings, Inc. Procédés pour une intégration wifi dans des systèmes cellulaires
WO2018132100A1 (fr) * 2017-01-12 2018-07-19 Intel Corporation Récepteur de réveil cellulaire pour réduire la consommation d'énergie d'un équipement d'utilisateur utilisant l'agrégation lte-wlan
WO2021092585A1 (fr) * 2019-11-07 2021-05-14 Ofinno, Llc Accès aléatoire sur de multiples empilements de protocoles actifs

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