WO2023279739A1 - 一种图像处理方法及装置、电子设备和存储介质 - Google Patents

一种图像处理方法及装置、电子设备和存储介质 Download PDF

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WO2023279739A1
WO2023279739A1 PCT/CN2022/078434 CN2022078434W WO2023279739A1 WO 2023279739 A1 WO2023279739 A1 WO 2023279739A1 CN 2022078434 W CN2022078434 W CN 2022078434W WO 2023279739 A1 WO2023279739 A1 WO 2023279739A1
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convolution
processing
sub
features
size
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French (fr)
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刘宇玺
谢天
杨修齐
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上海商汤智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/50—Information retrieval; Database structures therefor; File system structures therefor of still image data
    • G06F16/51—Indexing; Data structures therefor; Storage structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/25—Fusion techniques
    • G06F18/253—Fusion techniques of extracted features
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Definitions

  • the present disclosure relates to the field of computer technology, and in particular to an image processing method and device, electronic equipment, storage media and computer program products.
  • GPU Graphics Processing Unit
  • AI artificial intelligence
  • the massive data to be processed in the training and reasoning process of deep learning is accelerated by the GPU.
  • the characteristics of the image can be represented in the form of a matrix, and each value in the matrix represents the pixel at the corresponding position in the image.
  • the convolution of the matrix can be realized.
  • the disclosure proposes an image processing technical solution.
  • an image processing method including:
  • the convolution kernel is divided into multiple sub-convolution kernels
  • the multiple sub-convolution features are subjected to feature fusion processing to obtain convolution features, and the convolution features are used to characterize the extraction result of the image features.
  • the use of the multiple sub-convolution kernels to perform convolution processing on the image features in parallel respectively to obtain multiple sub-convolution features including:
  • index position data in at least one sub-convolution kernel is read, and the at least one read data is convoluted with the image feature in parallel to obtain multiple sub-convolution features.
  • the method further includes:
  • the first matrix and the second matrix for matrix multiplication operation are determined, and the size of the channel K dimension of the first matrix and the second matrix is the channel of the image feature Number multiplied by the number of sub-convolution kernels;
  • the use of the multiple sub-convolution kernels to perform convolution processing on the image features in parallel to obtain multiple sub-convolution features including:
  • the described multiple sub-convolution features are subjected to feature fusion processing to obtain convolution features, including:
  • the method further includes:
  • the method further includes:
  • the method further includes:
  • the graphics processor kernel function is also used to fuse at least one first processing result of at least one group in a single thread block deal with.
  • an image processing device including:
  • An extraction unit is used to extract image features in the target image
  • a processing unit configured to use the plurality of sub-convolution kernels to perform convolution processing on the image features in parallel to obtain a plurality of sub-convolution features
  • the fusion unit is configured to perform feature fusion processing on the plurality of sub-convolution features to obtain convolution features, and the convolution features are used to characterize the extraction result of the image features.
  • the processing unit is configured to determine an index position of at least one sub-convolution kernel in the storage space; read data in at least one sub-convolution kernel according to the index position, and perform parallel Convoluting the at least one read data with the image features to obtain multiple sub-convolution features.
  • the device further includes:
  • An expansion unit configured to determine a first matrix and a second matrix for performing matrix multiplication operations according to the image features and at least one sub-convolution kernel, and the size of the channel K dimension of the first matrix and the second matrix is the specified
  • the number of channels of the image features is multiplied by the number of sub-convolution kernels
  • a matrix division unit configured to divide the first matrix and the second matrix into a plurality of feature blocks in the K dimension.
  • the processing unit is configured to perform matrix multiplication processing in parallel in multiple thread blocks of a graphics processor to obtain a first processing result, wherein each of the thread blocks performs at least a matrix multiplication process;
  • the fusion unit is configured to perform feature fusion on the first processing result obtained from at least one matrix multiplication process in a single thread block in the shared memory of the graphics processor, to obtain the second processing result in at least one thread block. processing the result, and writing the second processing result into a global storage space; performing feature fusion on at least one second processing result in the global storage space to obtain a convolution feature.
  • the device further includes:
  • the first size determination unit is configured to determine multiple first sizes of feature blocks that can be processed in a single thread warp, and generate a graphics processor kernel function for dividing feature blocks based on the first size; wherein, the The maximum value of the first size is determined according to the register capacity, the minimum value of the first size is the size of the smallest matrix unit calculated by the matrix multiplication and addition operation instruction, and the values of the various first sizes are multiples of the minimum value .
  • the device further includes:
  • the second size determination unit is configured to determine multiple second sizes of feature blocks that can be processed in a single thread block TB, and generate a graphics processor kernel function for dividing feature blocks based on the second size; wherein, the The minimum value of the second size is the first size of a feature block that can be processed by a single thread warp, the second size is a multiple of the first size, and the maximum value of the second size is based on the capacity of the shared memory and The upper limit of the number of threads in a TB is determined.
  • the device further includes:
  • the third size determination unit is used to determine the third size of the grouping divided by the feature block in the channel K dimension in a single thread block, and the number of the grouping; determine the first group to be fused based on the number of the grouping number of processing results; generating a graphics processor kernel function based on the third size and the number of the first processing results, and the graphics processor kernel function is also used to group at least one first in at least one of the single thread blocks A fusion process is performed on the processing results.
  • an electronic device including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above-mentioned method.
  • a computer-readable storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented.
  • a computer program product including computer readable codes, or a non-volatile computer readable storage medium bearing computer readable codes, when the computer readable codes are stored in an electronic device
  • the processor in the electronic device is used to implement the above method.
  • the plurality of sub-convolution kernels are used to parallelize the
  • the image features are subjected to convolution processing to obtain multiple sub-convolution features
  • the multiple sub-convolution features are subjected to feature fusion processing to obtain convolution features. Therefore, by splitting the convolution kernel in the first layer in the channel dimension, and splitting the second layer in the dimensions of length and width, the convolution kernel can be split as much as possible through the two-layer split. Segmentation, multiple sub-convolution kernels perform convolution processing on the image features in parallel, and this parallel process can be executed in parallel by multiple computing units, making full use of processing resources in the GPU and improving the efficiency of convolution operations.
  • FIG. 1 shows a schematic diagram of feature map dimensions according to an embodiment of the disclosure.
  • FIG. 2 shows a schematic diagram of a convolution process of a matrix multiplication operation according to an embodiment of the present disclosure.
  • Fig. 3 shows a flowchart of an image processing method according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of an image processing process according to an embodiment of the disclosure.
  • Fig. 5 shows a block diagram of an image processing device according to an embodiment of the present disclosure.
  • Fig. 6 shows a block diagram of an electronic device according to an embodiment of the present disclosure.
  • Fig. 7 shows a block diagram of an electronic device according to an embodiment of the present disclosure.
  • the convolution operation can be performed based on a tensor computing unit (Tensor Core).
  • Tensor Core is a matrix multiply-accumulate computing unit, which can complete multiple multiply-accumulate operations in one cycle, and can achieve very high computing performance.
  • the computing performance of Tensor Core's int8 precision can even reach 624TOPS.
  • the increase in chip computing power is mainly to accelerate high-frequency calculation-intensive operators such as convolution/matrix multiplication, but it also brings about the difficulty of how to efficiently use computing power, that is, how to efficiently implement convolution operations on Tensor Core. son.
  • a typical convolutional neural network consists of an input layer (Input), a convolutional layer (Conv), an activation function (Relu), and a fully connected layer (FC).
  • CNN convolutional neural network
  • Conv convolutional layer
  • Relu activation function
  • FC fully connected layer
  • the convolution operation is the process of multiplying and adding the feature map (Feature Map) of the image and the filter kernel (Filter Kernel) to extract the image information.
  • the convolution operation is the most time-consuming operation in the neural network. Most of the time overhead of the deep learning model is on the convolution operator. The performance of the convolution operator has an important impact on the program performance.
  • the convolution type can be divided into a large image less channel type and a small image multi channel type, as shown in Figure 1.
  • the three dimensions of the feature map "length ⁇ width ⁇ channel” are marked on the top of the feature map, such as 224 ⁇ 224 ⁇ 3, 56 ⁇ 56 ⁇ 64, etc.
  • the convolution kernel size "length ⁇ width” is marked below the convolution kernel, such as 7x7, 1x1, etc.
  • This type of convolution generally exists in the initial stage of the neural network. It is characterized by a large length and width of the feature map (ie, a large image), such as 224, but the number of channels is relatively small (ie, more channel), such as 3. This type of convolution is a memory-intensive operation, and the computing power of Tensor Core cannot be fully utilized for this type.
  • Small image multi-channel type This type of convolution exists in the middle and end stages of the neural network. It is characterized by a small length and width of the feature map (ie small image), such as 56/28/14, etc., but the number of channels Relatively large (that is, multi-channel), such as 64/128/256, etc.
  • This type of convolution is a computationally intensive operation, which is very suitable for utilizing the computing power of Tensor Core.
  • the convolution algorithm used on TensorCore is mainly an implicit matrix multiplication algorithm.
  • the calculation form of matrix multiplication can be expressed as the multiplication of two matrices A of M ⁇ K and matrix B of K ⁇ N, and the Kth element of each row in A corresponds to the Kth element of the corresponding column in B Multiply to get the process of matrix C of M ⁇ N.
  • the programming model of GPU often includes three layers: thread network (Grid), thread block (Thread Block, TB) and thread (Thread); among them, thread block is the basic unit of task allocation, and enough thread blocks can ensure that the GPU hardware The computing unit is fully utilized.
  • the matrix multiplication uses a block technology to divide the entire large matrix multiplication task into multiple small matrix multiplication tasks, and then assign each small task to a different thread block for execution. For example, the matrix multiplication operation will divide the task of the matrix C (M ⁇ N dimension), and each thread block calculates a small matrix block of Mtile ⁇ Ntile, where Mtile is the size of the M-dimensional feature block, and Ntile is the size of the N-dimensional feature block. size.
  • SM Streaming Multiprocessor
  • the size of the matrix multiplication is shown in Figure 2.
  • the plurality of sub-convolution kernels are used to parallelize the
  • the image features are subjected to convolution processing to obtain multiple sub-convolution features
  • the multiple sub-convolution features are subjected to feature fusion processing to obtain convolution features. Therefore, by splitting the convolution kernel in the first layer in the channel dimension, and splitting the second layer in the dimensions of length and width, the convolution kernel can be split as much as possible through the two-layer split. Segmentation, multiple sub-convolution kernels perform convolution processing on the image features in parallel, and this parallel process can be executed in parallel by multiple computing units, making full use of processing resources in the GPU and improving the efficiency of convolution operations.
  • the execution subject of the steps of the image processing method may be executed by hardware, or executed by a processor running computer executable codes.
  • the image processing method may be executed by an electronic device such as a terminal device or a server,
  • the terminal device can be user equipment (User Equipment, UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (Personal Digital Assistant, PDA), handheld device, computing device, vehicle-mounted device, wearable device etc.
  • the method may be implemented by a processor invoking computer-readable instructions stored in a memory.
  • the execution subject of the image processing method may be a graphics processing unit (graphics processing unit, GPU).
  • graphics processing unit graphics processing unit, GPU
  • the execution subject of the method is the GPU, which is only an exemplary description, and should not be understood as a limitation of the method.
  • FIG. 3 shows a flow chart of an image processing method according to an embodiment of the present disclosure. As shown in FIG. 3 , the image processing method includes:
  • step S11 image features in the target image are extracted.
  • the expression of an image in computer technology can be a matrix composed of pixel values, so the analysis of the image can be the analysis of the matrix representing the pixel values of the image.
  • the image feature here may be used to represent the pixel value of the image, and the image feature may be a matrix composed of the pixel values of the image, or may be an image feature obtained after multiple convolution operations, which is not limited in the present disclosure.
  • step S12 the convolution kernel is divided into multiple sub-convolution kernels on the channel dimension and the length and width dimensions of the convolution kernel.
  • the specific form of the convolution kernel can be a matrix, and the elements in the matrix are the weights during convolution. Through the weights, the desired image features can be extracted through the convolution operation, and other image features can be suppressed.
  • the division of the convolution kernel here can specifically divide each weight of the convolution kernel into a sub-convolution kernel, or more than one weight can be divided into a sub-convolution kernel.
  • the disclosure of the sub-convolution kernel The division size is not limited.
  • the split of the convolution kernel can be split from two levels. The first split is to split the convolution kernel in the channel dimension, while the second split is split in the length and width dimensions. By splitting the two layers, the convolution kernel can be split as much as possible.
  • step S13 the plurality of sub-convolution kernels are used to perform convolution processing on the image features in parallel to obtain a plurality of sub-convolution features.
  • step S14 perform feature fusion processing on the plurality of sub-convolution features to obtain convolution features, and the convolution features are used to characterize the extraction result of the image features.
  • the process of feature fusion processing may be to accumulate multiple sub-convolution features, or may be to accumulate each sub-convolution feature by multiplying a certain weight. The specific process of feature fusion is not described here.
  • the convolution kernel is divided into multiple sub-convolution kernels, the dimension of the convolution kernel can be further divided into blocks to improve the efficiency of parallel execution.
  • 72 feature blocks are operated in parallel, making full use of the processing resources in the GPU and improving the convolution efficiency.
  • the plurality of sub-convolution kernels are used to parallelize the
  • the image features are subjected to convolution processing to obtain multiple sub-convolution features
  • the multiple sub-convolution features are subjected to feature fusion processing to obtain convolution features. Therefore, by splitting the convolution kernel in the first layer in the channel dimension, and splitting the second layer in the dimensions of length and width, the convolution kernel can be split as much as possible through the two-layer split. Segmentation, multiple sub-convolution kernels perform convolution processing on the image features in parallel, and this parallel process can be executed in parallel by multiple computing units, making full use of processing resources in the GPU and improving the efficiency of convolution operations.
  • the using the plurality of sub-convolution kernels to perform convolution processing on the image features in parallel respectively to obtain a plurality of sub-convolution features includes: determining that at least one sub-convolution kernel is stored in An index position in space; according to the index position, read data in at least one sub-convolution kernel, and perform convolution processing on at least one read data and the image feature in parallel to obtain multiple sub-convolution features .
  • index value which is used to represent the storage location of the data in the storage space.
  • the index value of the sub-convolution kernel will be recorded in advance.
  • the index value can be the convolution kernel The start and end values in the memory space. Then directly read the value in the storage space according to the index value to perform convolution calculation with the image feature, without expanding the convolution kernel into a matrix and then performing convolution calculation, which can save memory resources.
  • the method further includes: according to the image features and at least one sub-convolution kernel, determine The first matrix and the second matrix of the first matrix and the second matrix, the size of the channel K dimension of the first matrix and the second matrix is the number of channels of the image feature multiplied by the number of sub-convolution kernels; on the K dimension, The first matrix and the second matrix are divided into a plurality of feature blocks.
  • the calculation form of matrix multiplication can be expressed as the multiplication of two matrices A of M ⁇ K and matrix B of K ⁇ N, and the Kth element of each row in A is equal to the corresponding column of B.
  • the convolution kernel can be used to convert the M ⁇ N matrix into two M ⁇ K matrix A and K ⁇ N matrix B, which can be realized by the im2col algorithm. Do repeat.
  • a convolution kernel when a sub-convolution kernel is a value in the convolution kernel, each sub-convolution kernel can be used to convert the M ⁇ N matrix (characterizing image features) into a matrix A and matrix B, then the obtained multiple matrices A can be accumulated in the K dimension as the first matrix, and the obtained multiple matrices B can be accumulated in the K dimension as the second matrix. Then, obviously, the size of the channel K dimension of the first matrix and the second matrix is the number of channels of the image features multiplied by the number of sub-convolution kernels.
  • the size of the convolution kernel is 3 ⁇ 3, and the size of each sub-convolution kernel is 1, then there are 9 sub-convolution kernels.
  • the channel number of the image feature matrix is 1024
  • the first matrix and the second matrix are divided into multiple feature blocks.
  • they can also be divided in the row and column (M and N) dimensions of the matrix, which will not be repeated this time.
  • M and N row and column
  • the size of the first matrix and the second matrix in the K dimension is multiplied, then, in the K dimension, the first matrix and the second matrix are multiplied
  • the second matrix is divided into a plurality of feature blocks, more feature blocks can be obtained by dividing, thus, matrix multiplication operations can be performed on each of the feature blocks in parallel to obtain multiple sub-convolution features, due to the increase in the number of feature blocks , therefore, the number of feature blocks that can be processed in parallel during the convolution operation is further increased, which further improves the efficiency of convolution calculation.
  • the use of the multiple sub-convolution kernels to perform convolution processing on the image features in parallel to obtain multiple sub-convolution features includes: multiple thread blocks of the graphics processor Performing matrix multiplication processing in parallel to obtain a first processing result, wherein at least one matrix multiplication processing is performed in each thread block; performing feature fusion processing on the plurality of sub-convolution features to obtain convolution features, comprising: in the shared memory of the graphics processor, performing feature fusion on the first processing result obtained from at least one matrix multiplication processing in a single thread block to obtain a second processing result in at least one thread block, and Writing the second processing result into a global storage space; performing feature fusion on at least one second processing result in the global storage space to obtain a convolution feature.
  • the thread block TB is loaded and run on the computing unit SM, and the thread block TB can perform calculation operations in parallel. Therefore, multiple TBs of the graphics processor can perform calculation operations in parallel. At least one computing operation, so that multiple first processing results can be obtained in the TB.
  • the feature blocks in a single TB can be further divided into one or more groups in the channel K dimension, that is, one or more groups of feature blocks can be calculated in each TB, and the number of groups of feature blocks calculated in a TB is 2 Exponential power, for example, can be 1, 2, 4 and so on. Then, after the TB calculates one or more sets of feature blocks, it will get one or more sets of first processing results, and the first processing results will be located in the shared memory (Shared Memory, SMem), and then the same TB in the same TB The first processing result is subjected to feature fusion to obtain the second processing result in each TB.
  • the shared memory Shared Memory
  • the size of the shared memory is limited, it has high read and write speed and bandwidth. Therefore, considering that the amount of calculation required for feature fusion of the first processing result in a single TB is not large, therefore, through SMem to TB The feature fusion of the internal first calculation results can improve the efficiency of fusion of the first calculation results.
  • the convolution processing is performed in parallel in multiple thread blocks of the graphics processor.
  • the first processing result obtained by the matrix multiplication processing is subjected to feature fusion, and the second processing result in each thread block is obtained, and the second processing result is written into the global storage space; and then each second processing result in the global storage space is As a result, feature fusion is performed to obtain convolutional features. Therefore, since the shared memory has a higher reading and writing speed and bandwidth, the feature fusion of the first calculation result inside the TB can be performed through the shared memory, which can improve the efficiency of fusion of the first calculation result.
  • the calculation efficiency of the second processing result fusion between thread blocks through the global storage space will not decrease with the increase of the number of feature blocks, which can ensure that The output efficiency of the second processing result.
  • the parallelism of the convolution task is further improved, and the hardware resources of the GPU are better utilized.
  • the feature size segmentation and the convolution kernel size segmentation are performed through the graphics processor kernel function kernel.
  • the kernel with a fixed feature block division size cannot be applied to all
  • every possible feature block size is traversed as much as possible to generate a convolution kernel, and a convolution kernel corresponds to a feature block size. Therefore, based on the image feature Size, choose the appropriate kernel to divide into blocks, and get multiple feature libraries.
  • various possible feature block sizes of TB, warp, and K dimension can be determined, and various corresponding kernels can be finally generated, so as to facilitate later selection of an appropriate kernel according to the size of image features.
  • the three dimensions are described in detail below.
  • the method further includes: determining multiple first sizes of feature blocks that can be processed in a single warp, and based on the first A size generates a graphics processor kernel function for feature block division; wherein, the maximum value of the first size is determined according to the register capacity, and the minimum value of the first size is the minimum matrix unit calculated by a matrix multiply-add operation instruction The values of the multiple first sizes are multiples of the minimum value.
  • the convolution operation is performed through the issued matrix multiply and accumulate (MMA) instruction.
  • MMA matrix multiply and accumulate
  • the smallest matrix unit processed by an MMA instruction is 16 ⁇ 8 in the M ⁇ N dimension , which is 8 in the K dimension.
  • the size of the smallest matrix unit that can be processed is the size of the smallest matrix unit that can be processed by the MMA instruction, and since the operation of the instruction is accumulated in the form of an exponential power of 2, the characteristics that can be processed by a single Warp
  • the size of the block is the size of the smallest matrix unit multiplied by the power of 2
  • N can be 8
  • M can be 16, 32, 64, 128, then the obtained value of M ⁇ N is as follows Table 1 shows.
  • the size of the feature block cannot be increased infinitely, and its maximum value can be determined according to the register capacity. Due to the limitation of the register capacity, the Warp feature block of 128x64 cannot be stored in the register. Therefore, the feature block The maximum value of the first size is 128 ⁇ 32 or 64 ⁇ 64, as shown in Table 1 for details.
  • the first size of all feature blocks can be traversed in the Warp dimension, and then the graphics processor kernel function kernel can be generated based on the first size, and the kernel obtained in this way can be applied to image features of various sizes Segmentation, the resulting kernel has high universality.
  • the method further includes: determining various second sizes of feature blocks that can be processed in a single thread block TB, and based on the first Two dimensions are used to generate a graphics processor kernel function for feature block division; wherein, the minimum value of the second size is the first size of a feature block that can be processed by a single warp warp, and the second size is the first size of the feature block that can be processed by the second size A multiple of a size, the maximum value of the second size is determined according to the capacity of the shared memory and the upper limit of the number of threads in a TB.
  • a TB contains one or more warps
  • the minimum value of the second size is the first size of the feature block that can be processed by a single thread warp, and the second size can also be a multiple of the first size, which is Powers of 2, ie 2, 4.
  • the specific values of M TB and NT TB in Table 3 are multiples of the first size.
  • a TB can often have up to 1024 threads, that is, 16 Warps.
  • the number of threads is 128-512
  • the calculation efficiency is high, so 16 Warps are often not run, so , in order to ensure GPU computing efficiency, a maximum of 8 warps can be run in one TB, that is, the maximum value of M TB ⁇ N TB is 2 ⁇ 4 or 4 ⁇ 2, as shown in Table 2.
  • Table 2 Feature block size at TB level.
  • the numbers in the table represent the multiples of the corresponding Warp-level feature block size
  • the second size of all feature blocks can be traversed in the TB dimension, and then the graphics processor kernel function kernel can be generated based on the second size, and the kernel obtained in this way can be applied to image features of various sizes Segmentation, the resulting kernel has high universality.
  • the method further includes: determining a third size of a group divided by feature blocks in a single thread block in the channel K dimension, and the the quantity of the grouping; determine the quantity of the first processing result to be merged based on the quantity of the grouping; generate a graphics processor kernel function based on the third size and the quantity of the first processing result, the graphics processing The kernel function is further used to perform fusion processing on at least one first processing result of at least one group in a single thread block.
  • the size of the smallest matrix unit that can be processed is the size of the smallest matrix unit that can be processed by the MMA instruction.
  • the smallest matrix unit processed by an MMA instruction is in the M ⁇ N dimension is 16 ⁇ 8, which is 8 in the K dimension.
  • multiple possible K-dimensional sizes in a single TB include k8, k16, k32, k64, and so on.
  • a TB is composed of multiple warps. These warps are divided into multiple groups S, and different groups will be further divided in the size of the K dimension.
  • the division size can be s8, s16, s32, etc.
  • the size of the K dimension in the TB is K128. If these 8 warps are divided into 2 groups (4 warps in each group), then the feature blocks processed by a single group are in the K dimension The size is s64.
  • the number of groups in a single TB is the size of the K-dimensional feature block divided by the K-dimensional size of a single group.
  • the number of groups is 1; the second row 2 ⁇ , the grouping The number is 2; the third line is 4 ⁇ , and its grouping number is 4.
  • k32_s16 means that the size of the group is 16, and k32 means that the size of the K dimension of the feature block is 32. Therefore, the number of groups is 2.
  • Table 3 Feature block size and grouping size of K dimension.
  • the number of groups can be used as the number of first processing results, and then the graphics processing kernel function can be generated based on the number of first processing results and the third size.
  • the third size of the group can be traversed on the K dimension of the feature block, and then based on the third size and the size of the feature block, multiple quantities of the first processing results to be fused are determined, A graphics processor kernel function kernel is generated based on the third size and the number of first processing results, and the kernel obtained in this way can be applied to fusion processing of the first results of groups of various sizes, and the obtained kernel has high universality.
  • FIG. 4 is a schematic diagram of an application scenario of the image processing method of the embodiment of the present disclosure.
  • multiple GPU computing units are included: SM1, SM2...SMn, and one pair of TBs in each SM
  • the matrix multiplication operation is performed on the characteristic blocks, and one characteristic block is divided into two groups for parallel processing.
  • the first processing results obtained after grouping are marked as S1_0, S1_1, S2_0, S2_1, ... Sn_0, Sn_1 in Figure 4, the first The processing result is located on the SMem, and the TB intra-TB reduction (feature fusion processing) is performed on the SMem to obtain the second processing result, which is marked as S1, S2, ... Sn in sequence in Fig. 4 .
  • the obtained second processing result will be written into GMem, and then inter-TB reduction (feature fusion processing) processing will be performed on GMem to obtain the convolution result S.
  • the present disclosure also provides image processing devices, electronic equipment, computer-readable storage media, and programs, all of which can be used to implement any image processing method provided in the present disclosure.
  • image processing devices electronic equipment, computer-readable storage media, and programs, all of which can be used to implement any image processing method provided in the present disclosure.
  • Fig. 5 shows a block diagram of an image processing device according to an embodiment of the present disclosure. As shown in Fig. 5, the device 50 includes:
  • An extraction unit 51 configured to extract image features in the target image
  • the division unit 52 is used to divide the convolution kernel into a plurality of sub-convolution kernels on the channel dimension of the convolution kernel and on the dimensions of length and width;
  • the processing unit 53 is configured to use the plurality of sub-convolution kernels to perform convolution processing on the image features in parallel to obtain a plurality of sub-convolution features;
  • the fusion unit 54 is configured to perform feature fusion processing on the plurality of sub-convolution features to obtain convolution features, and the convolution features are used to characterize the extraction result of the image features.
  • the processing unit is configured to determine an index position of at least one sub-convolution kernel in the storage space; read data in at least one sub-convolution kernel according to the index position, and perform parallel Convoluting the at least one read data with the image features to obtain multiple sub-convolution features.
  • the device further includes:
  • An expansion unit configured to determine a first matrix and a second matrix for performing matrix multiplication operations according to the image features and at least one sub-convolution kernel, and the size of the channel K dimension of the first matrix and the second matrix is the specified
  • the number of channels of the image features is multiplied by the number of sub-convolution kernels
  • a matrix division unit configured to divide the first matrix and the second matrix into a plurality of feature blocks in the K dimension.
  • the processing unit is configured to perform matrix multiplication processing in parallel in multiple thread blocks of a graphics processor to obtain a first processing result, wherein each of the thread blocks performs at least a matrix multiplication process;
  • the fusion unit is configured to perform feature fusion on the first processing result obtained from at least one matrix multiplication process in a single thread block in the shared memory of the graphics processor, to obtain the second processing result in at least one thread block. processing the result, and writing the second processing result into a global storage space; performing feature fusion on at least one second processing result in the global storage space to obtain a convolution feature.
  • the device further includes:
  • the first size determination unit is configured to determine multiple first sizes of feature blocks that can be processed in a single thread warp, and generate a graphics processor kernel function for dividing feature blocks based on the first size; wherein, the The maximum value of the first size is determined according to the register capacity, the minimum value of the first size is the size of the smallest matrix unit calculated by the matrix multiplication and addition operation instruction, and the values of the various first sizes are multiples of the minimum value .
  • the device further includes:
  • the second size determination unit is configured to determine multiple second sizes of feature blocks that can be processed in a single thread block TB, and generate a graphics processor kernel function for dividing feature blocks based on the second size; wherein, the The minimum value of the second size is the first size of a feature block that can be processed by a single thread warp, the second size is a multiple of the first size, and the maximum value of the second size is based on the capacity of the shared memory and The upper limit of the number of threads in a TB is determined.
  • the device further includes:
  • the third size determination unit is used to determine the third size of the grouping divided by the feature block in the channel K dimension in a single thread block, and the number of the grouping; determine the first group to be fused based on the number of the grouping number of processing results; generating a graphics processor kernel function based on the third size and the number of the first processing results, and the graphics processor kernel function is also used to group at least one first in at least one of the single thread blocks A fusion process is performed on the processing results.
  • the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments, and its specific implementation and technical effects can refer to the descriptions of the above method embodiments, for It is concise and will not be repeated here.
  • Embodiments of the present disclosure also provide a computer-readable storage medium, on which computer program instructions are stored, and the above-mentioned method is implemented when the computer program instructions are executed by a processor.
  • Computer readable storage media may be volatile or nonvolatile computer readable storage media.
  • An embodiment of the present disclosure also proposes an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to invoke the instructions stored in the memory to execute the above method.
  • An embodiment of the present disclosure also provides a computer program product, including computer-readable codes, or a non-volatile computer-readable storage medium carrying computer-readable codes, when the computer-readable codes are stored in a processor of an electronic device When running in the electronic device, the processor in the electronic device executes the above method.
  • Electronic devices may be provided as terminals, servers, or other forms of devices.
  • FIG. 6 shows a block diagram of an electronic device 800 according to an embodiment of the present disclosure.
  • the electronic device 800 may be a terminal such as a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, or a personal digital assistant.
  • electronic device 800 may include one or more of the following components: processing component 802, memory 804, power supply component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814 , and the communication component 816.
  • the processing component 802 generally controls the overall operations of the electronic device 800, such as those associated with display, telephone calls, data communications, camera operations, and recording operations.
  • the processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above method. Additionally, processing component 802 may include one or more modules that facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802 .
  • the memory 804 is configured to store various types of data to support operations at the electronic device 800 . Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and the like.
  • the memory 804 can be implemented by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic or Optical Disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • EPROM erasable Programmable Read Only Memory
  • PROM Programmable Read Only Memory
  • ROM Read Only Memory
  • Magnetic Memory Flash Memory
  • Magnetic or Optical Disk Magnetic Disk
  • the power supply component 806 provides power to various components of the electronic device 800 .
  • Power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for electronic device 800 .
  • the multimedia component 808 includes a screen providing an output interface between the electronic device 800 and the user.
  • the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user.
  • the touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense a boundary of a touch or swipe action, but also detect duration and pressure associated with the touch or swipe action.
  • the multimedia component 808 includes a front camera and/or a rear camera. When the electronic device 800 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capability.
  • the audio component 810 is configured to output and/or input audio signals.
  • the audio component 810 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 800 is in operation modes, such as call mode, recording mode and voice recognition mode. Received audio signals may be further stored in memory 804 or sent via communication component 816 .
  • the audio component 810 also includes a speaker for outputting audio signals.
  • the I/O interface 812 provides an interface between the processing component 802 and a peripheral interface module, which may be a keyboard, a click wheel, a button, and the like. These buttons may include, but are not limited to: a home button, volume buttons, start button, and lock button.
  • Sensor assembly 814 includes one or more sensors for providing status assessments of various aspects of electronic device 800 .
  • the sensor component 814 can detect the open/closed state of the electronic device 800, the relative positioning of components, such as the display and the keypad of the electronic device 800, the sensor component 814 can also detect the electronic device 800 or a Changes in position of components, presence or absence of user contact with electronic device 800 , electronic device 800 orientation or acceleration/deceleration and temperature changes in electronic device 800 .
  • Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact.
  • Sensor assembly 814 may also include an optical sensor, such as a complementary metal-oxide-semiconductor (CMOS) or charge-coupled device (CCD) image sensor, for use in imaging applications.
  • CMOS complementary metal-oxide-semiconductor
  • CCD charge-coupled device
  • the sensor component 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor.
  • the communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices.
  • the electronic device 800 can access a wireless network based on a communication standard, such as a wireless network (WiFi), a second generation mobile communication technology (2G) or a third generation mobile communication technology (3G), or a combination thereof.
  • the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel.
  • the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication.
  • the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology and other technologies.
  • RFID Radio Frequency Identification
  • IrDA Infrared Data Association
  • UWB Ultra Wideband
  • Bluetooth Bluetooth
  • electronic device 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable A programmable gate array (FPGA), controller, microcontroller, microprocessor or other electronic component implementation for performing the methods described above.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGA field programmable A programmable gate array
  • controller microcontroller, microprocessor or other electronic component implementation for performing the methods described above.
  • a non-volatile computer-readable storage medium such as the memory 804 including computer program instructions, which can be executed by the processor 820 of the electronic device 800 to implement the above method.
  • FIG. 7 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure.
  • electronic device 1900 may be provided as a server.
  • electronic device 1900 includes processing component 1922 , which further includes one or more processors, and a memory resource represented by memory 1932 for storing instructions executable by processing component 1922 , such as application programs.
  • the application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions.
  • the processing component 1922 is configured to execute instructions to perform the above method.
  • Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input-output (I/O) interface 1958 .
  • the electronic device 1900 can operate based on the operating system stored in the memory 1932, such as the Microsoft server operating system (Windows Server TM ), the graphical user interface-based operating system (Mac OS X TM ) introduced by Apple Inc., and the multi-user and multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ), or the like.
  • Microsoft server operating system Windows Server TM
  • Mac OS X TM graphical user interface-based operating system
  • Unix TM multi-user and multi-process computer operating system
  • Linux TM free and open source Unix-like operating system
  • FreeBSD TM open source Unix-like operating system
  • a non-transitory computer-readable storage medium such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to implement the above method.
  • the present disclosure can be a system, method and/or computer program product.
  • a computer program product may include a computer readable storage medium having computer readable program instructions thereon for causing a processor to implement various aspects of the present disclosure.
  • a computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device.
  • a computer readable storage medium may be, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
  • Computer-readable storage media include: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or flash memory), static random access memory (SRAM), compact disc read only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded device, such as a printer with instructions stored thereon A hole card or a raised structure in a groove, and any suitable combination of the above.
  • RAM random access memory
  • ROM read-only memory
  • EPROM erasable programmable read-only memory
  • flash memory static random access memory
  • SRAM static random access memory
  • CD-ROM compact disc read only memory
  • DVD digital versatile disc
  • memory stick floppy disk
  • mechanically encoded device such as a printer with instructions stored thereon
  • a hole card or a raised structure in a groove and any suitable combination of the above.
  • computer-readable storage media are not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., pulses of light through fiber optic cables), or transmitted electrical signals.
  • the computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or downloaded to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and/or a wireless network.
  • the network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers.
  • a network adapter card or a network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .
  • Computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or Source or object code written in any combination, including object-oriented programming languages—such as Smalltalk, C++, etc., and conventional procedural programming languages—such as the “C” language or similar programming languages.
  • Computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement.
  • the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as via the Internet using an Internet service provider). connect).
  • LAN local area network
  • WAN wide area network
  • an electronic circuit such as a programmable logic circuit, field programmable gate array (FPGA), or programmable logic array (PLA)
  • FPGA field programmable gate array
  • PDA programmable logic array
  • These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that when executed by the processor of the computer or other programmable data processing apparatus , producing an apparatus for realizing the functions/actions specified in one or more blocks in the flowchart and/or block diagram.
  • These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause computers, programmable data processing devices and/or other devices to work in a specific way, so that the computer-readable medium storing instructions includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks in flowcharts and/or block diagrams.
  • each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.
  • the computer program product can be specifically realized by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.
  • a software development kit Software Development Kit, SDK

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Abstract

提供了一种图像处理方法及装置、电子设备和存储介质，方法包括：提取目标图像中的图像特征（S11）；在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核（S12）；利用多个子卷积核并行地分别对图像特征进行卷积处理，得到多个子卷积特征（S13）；将多个子卷积特征进行特征融合处理，得到卷积特征（S14），卷积特征用于表征对图像特征的提取结果。提高了图像处理中卷积操作的效率。

Description

一种图像处理方法及装置、电子设备和存储介质
本申请要求2021年07月09日提交、申请号为202110778863.1，发明名称为“一种图像处理方法及装置、电子设备和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及计算机技术领域，尤其涉及一种图像处理方法及装置、电子设备、存储介质和计算机程序产品。
背景技术
图形处理器(Graphics Processing Unit，GPU)作为硬件加速器在高性能计算领域得到广泛的应用。特别是近几年，GPU广泛应用在人工智能(AI)领域，特别是深度学习领域。深度学习的训练和推理过程中所要处理的海量数据由GPU来加速处理。
图像的特征可以表征为矩阵的形式，矩阵中的每一个值表征图像中相应位置的像素点，通过对矩阵进行矩阵乘累加操作，可以实现对矩阵的卷积。
发明内容
本公开提出了一种图像处理技术方案。
根据本公开的一方面，提供了一种图像处理方法，包括：
提取目标图像中的图像特征；
在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核；
利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征；
将所述多个子卷积特征进行特征融合处理，得到卷积特征，所述卷积特征用于表征对所述图像特征的提取结果。
在一种可能的实现方式中，所述利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，包括：
确定至少一个子卷积核在存储空间中的索引位置；
根据所述索引位置，读取至少一个子卷积核中的数据，并行地将读取到的至少一个数据与所述图像特征进行卷积处理，得到多个子卷积特征。
在一种可能的实现方式中，在所述将卷积核划分为多个子卷积核后，所述方法还包括：
根据所述图像特征和至少一个子卷积核确定用于进行矩阵乘运算的第一矩阵和第二矩阵，所述第一矩阵和第二矩阵的通道K维度的尺寸为所述图像特征的通道数乘以所述子卷积核的数量；
在所述K维度上，将所述第一矩阵和第二矩阵划分为多个特征块。
在一种可能的实现方式中，所述利用所述多个子卷积核并行地分别对所述图像特征 进行卷积处理，得到多个子卷积特征，包括：
在图形处理器的多个线程块内并行地进行矩阵乘处理，得到第一处理结果，其中，每个所述线程块内进行至少一个矩阵乘处理；
所述将所述多个子卷积特征进行特征融合处理，得到卷积特征，包括：
在所述图形处理器的共享内存中，将单个所述线程块内的至少一个矩阵乘处理得到的第一处理结果进行特征融合，得到至少一个线程块内的第二处理结果，并将所述第二处理结果写入全局存储空间中；
将所述全局存储空间中的至少一个第二处理结果进行特征融合，得到卷积特征。
在一种可能的实现方式中，在所述提取目标图像中的图像特征后，所述方法还包括：
确定单个线程束Warp中能够处理的特征块的多种第一尺寸，并基于所述第一尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第一尺寸的最大值根据寄存器容量确定，所述第一尺寸的最小值为矩阵乘加运算指令计算的最小矩阵单元的尺寸，所述多种第一尺寸的值为所述最小值的倍数。
在一种可能的实现方式中，在所述提取目标图像中的图像特征后，所述方法还包括：
确定单个线程块TB中能够处理的特征块的多种第二尺寸，并基于所述第二尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第二尺寸的最小值为单个线程束Warp能够处理的特征块的第一尺寸，所述第二尺寸为所述第一尺寸的倍数，所述第二尺寸的最大值根据共享内存的容量和TB内线程数上限确定。
在一种可能的实现方式中，在所述提取目标图像中的图像特征后，所述方法还包括：
确定单个线程块中的特征块在通道K维度上划分的分组的第三尺寸，以及所述分组的数量；
基于所述分组的数量确定要进行融合处理的第一处理结果的数量；
基于所述第三尺寸和所述第一处理结果的数量生成图形处理器核函数，所述图形处理器核函数还用于对单个线程块中的至少一个分组的至少一个第一处理结果进行融合处理。
根据本公开的一方面，提供了一种图像处理装置，包括：
提取单元，用于提取目标图像中的图像特征；
划分单元，用于在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核；
处理单元，用于利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征；
融合单元，用于将所述多个子卷积特征进行特征融合处理，得到卷积特征，所述卷积特征用于表征对所述图像特征的提取结果。
在一种可能的实现方式中，所述处理单元，用于确定至少一个子卷积核在存储空间中的索引位置；根据所述索引位置，读取至少一个子卷积核中的数据，并行地将读取到的至少一个数据与所述图像特征进行卷积处理，得到多个子卷积特征。
在一种可能的实现方式中，所述装置还包括：
展开单元，用于根据所述图像特征和至少一个子卷积核确定用于进行矩阵乘运算的第一矩阵和第二矩阵，所述第一矩阵和第二矩阵的通道K维度的尺寸为所述图像特征的通道数乘以所述子卷积核的数量；
矩阵划分单元，用于在所述K维度上，将所述第一矩阵和第二矩阵划分为多个特征块。
在一种可能的实现方式中，所述处理单元，用于在图形处理器的多个线程块内并行地进行矩阵乘处理，得到第一处理结果，其中，每个所述线程块内进行至少一个矩阵乘处理；
所述融合单元，用于在所述图形处理器的共享内存中，将单个所述线程块内的至少一个矩阵乘处理得到的第一处理结果进行特征融合，得到至少一个线程块内的第二处理结果，并将所述第二处理结果写入全局存储空间中；将所述全局存储空间中的至少一个第二处理结果进行特征融合，得到卷积特征。
在一种可能的实现方式中，所述装置还包括：
第一尺寸确定单元，用于确定单个线程束Warp中能够处理的特征块的多种第一尺寸，并基于所述第一尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第一尺寸的最大值根据寄存器容量确定，所述第一尺寸的最小值为矩阵乘加运算指令计算的最小矩阵单元的尺寸，所述多种第一尺寸的值为所述最小值的倍数。
在一种可能的实现方式中，所述装置还包括：
第二尺寸确定单元，用于确定单个线程块TB中能够处理的特征块的多种第二尺寸，并基于所述第二尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第二尺寸的最小值为单个线程束Warp能够处理的特征块的第一尺寸，所述第二尺寸为所述第一尺寸的倍数，所述第二尺寸的最大值根据共享内存的容量和TB内线程数上限确定。
在一种可能的实现方式中，所述装置还包括：
第三尺寸确定单元，用于确定单个线程块中的特征块在通道K维度上划分的分组的第三尺寸，以及所述分组的数量；基于所述分组的数量确定要进行融合处理的第一处理结果的数量；基于所述第三尺寸和所述第一处理结果的数量生成图形处理器核函数，所述图形处理器核函数还用于对单个线程块中的至少一个分组的至少一个第一处理结果进行融合处理。
根据本公开的一方面，提供了一种电子设备，包括：处理器；用于存储处理器可执行指令的存储器；其中，所述处理器被配置为调用所述存储器存储的指令，以执行上述方法。
根据本公开的一方面，提供了一种计算机可读存储介质，其上存储有计算机程序指令，所述计算机程序指令被处理器执行时实现上述方法。
根据本公开的一方面，提供了一种计算机程序产品，包括计算机可读代码，或者承载有计算机可读代码的非易失性计算机可读存储介质，当所述计算机可读代码在电子设备的处理器中运行时，所述电子设备中的处理器执行用于实现上述方法。
在本公开实施例中，通过在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核，利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，将所述多个子卷积特征进行特征融合处理，得到卷积特征。由此，通过在通道维度上对卷积核进行第一层拆分，在长和宽的维度上进行第二层拆分，通过两层的拆分，能够尽可能多地对卷积核进行切分，多个子卷积核并行地分别对所述图像特征进行卷积处理，该并行过程可以由多个计算单元并行地执行，充分利用GPU中的处理资源，提高了卷积操作的效率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，而非限制本公开。根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。
图1示出根据本公开实施例的特征图尺寸的示意图。
图2示出根据本公开实施例的矩阵乘运算的卷积过程的示意图。
图3示出根据本公开实施例的图像处理方法的流程图。
图4示出根据本公开实施例的图像处理过程的示意图。
图5示出根据本公开实施例的一种图像处理装置的框图。
图6示出根据本公开实施例的一种电子设备的框图。
图7示出根据本公开实施例的一种电子设备的框图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中术语“至少一种”表示多种中的任意一种或多种中的至少两种的任意组合，例如，包括A、B、C中的至少一种，可以表示包括从A、B和C构成的集合中选择的任意一个或多个元素。
另外，为了更好地说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中， 对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
如背景技术所述，相关技术中的卷积操作的效率有待提高，为了提高卷积操作的效率，可以基于张量计算单元(Tensor Core)进行卷积操作。Tensor Core是一种矩阵乘累加的计算单元，其在一个周期可以完成多次的乘加操作，可以达到非常高的计算性能。针对A100型号的GPU，Tensor Core的int8精度的计算性能甚至可以达到624TOPS。芯片算力的增加主要是为了加速卷积/矩阵乘法一类的高频计算密集型算子，但是也带来了如何高效利用算力的困难，即如何高效地在Tensor Core上实现卷积算子。
典型的卷积神经网络(CNN)由输入层(Input)、卷积层(Conv)、激活函数(Relu)、全连接层(FC)等组成。其中，原始的图像数据经过网络，逐渐抽取出其底层特征，最后形成高级语义特征。
卷积操作就是图像的特征图(Feature Map)与卷积核(Filter Kernel)进行乘加运算，抽取出图像信息的过程。卷积操作是神经网络中最耗时的运算，深度学习模型的大部分时间开销都在卷积算子上，卷积算子的性能对程序性能有着重要影响。
根据特征图(Feature Map)的尺寸大小，可以将卷积类型分为大图少通道类型和小图多通道类型，如图1所示。其中特征图的三个尺寸“长×宽×通道”标注于特征图的上方，如224×224×3、56×56×64等。卷积核尺寸“长×宽”标注于卷积核的下方，如7x7、1x1等。
大图少通道类型：这种类型的卷积一般存在于神经网络的开始阶段，它的特点是特征图的长和宽较大(即大图)，比如224，但是通道数目比较小(即多通道)，比如3。这种卷积类型属于访存密集型运算，Tensor Core的计算能力对于这种类型得不到充分的发挥。
小图多通道类型：这种类型的卷积存在于神经网络的中间和末尾阶段，它的特点是特征图的长和宽较小(即小图)，比如56/28/14等，但是通道数目比较大(即多通道)，比如64/128/256等。这种卷积类型属于计算密集型运算，很适合发挥Tensor Core的计算能力。
目前TensorCore上采用的卷积算法主要是隐式矩阵乘算法。矩阵乘法的计算形式可以表述为两个尺寸为M×K的矩阵A和K×N的矩阵B相乘，A中每一行的第K个元素都与B中对应列的第K个元素对应相乘，得到M×N的矩阵C的过程。
GPU的编程模型往往包含三层：线程网(Grid)、线程块(Thread Block,TB)和线程(Thread)；其中，线程块是任务分配的基本单元，足够多的线程块能保证GPU的硬件计算单元得到充分的发挥。在本公开实施例中，矩阵乘法利用分块技术，将整个大的矩阵乘任务划分成多个小矩阵的乘法任务，然后将每一块小任务分配给不同的线程块来执行。例如，矩阵乘运算会对矩阵C(M×N维度)进行任务划分，每一个线程块计算Mtile×Ntile的小矩阵块，其中，Mtile为M维度特征块的尺寸，Ntile为N维度特征块的尺寸。例如，当M＝N＝1024时，在M和N维度可以按照Mtile＝Ntile＝128进行分块，这样一共产生(1024/128)x(1024/128)＝64个特征块。对于T4型号的GPU来说，至少需要40个线程块才能 用上全部的GPU计算单元SM(Streaming Multiprocessor)。
然而，把小图多通道的卷积类型转换成矩阵乘后，矩阵乘的尺寸如图2所示，矩阵A的M维度和矩阵B的N维度尺寸很小，而累加的K维度的尺寸却很大。例如，M＝N＝256时，M和N维度如果依然使用Mtile＝Ntile＝128进行分块，这样只能划分出4个线程块，大部分GPU的SM处于空闲状态，导致卷积操作的效率有待提高。
在本公开实施例中，通过在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核，利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，将所述多个子卷积特征进行特征融合处理，得到卷积特征。由此，通过在通道维度上对卷积核进行第一层拆分，在长和宽的维度上进行第二层拆分，通过两层的拆分，能够尽可能多地对卷积核进行切分，多个子卷积核并行地分别对所述图像特征进行卷积处理，该并行过程可以由多个计算单元并行地执行，充分利用GPU中的处理资源，提高了卷积操作的效率。
图像处理方法步骤的执行主体可以为硬件执行，或者通过处理器运行计算机可执行代码的方式执行，在一种可能的实现方式中，所述图像处理方法可以由终端设备或服务器等电子设备执行，终端设备可以为用户设备(User Equipment，UE)、移动设备、用户终端、终端、蜂窝电话、无绳电话、个人数字助理(Personal Digital Assistant，PDA)、手持设备、计算设备、车载设备、可穿戴设备等，所述方法可以通过处理器调用存储器中存储的计算机可读指令的方式来实现。
为便于描述，本说明书一个或多个实施例中，图像处理方法的执行主体可以是图形处理器(graphics processing unit，GPU)，后文以执行主体为图形处理器为例，对该方法的实施方式进行介绍。可以理解，该方法的执行主体为GPU只是一种示例性的说明，并不应理解为对该方法的限定。
图3示出根据本公开实施例的图像处理方法的流程图，如图3所示，所述图像处理方法包括：
在步骤S11中，提取目标图像中的图像特征。
图像在计算机技术中的表达可以是一个个像素值组成的矩阵，那么对图像的分析可以是对表征图像像素值的矩阵进行分析。
这里的图像特征可以用来表征图像的像素值，该图像特征可以是图像的像素值组成的矩阵，或者也可以是经多次卷积操作后得到的图像特征，本公开对此不做限定。
在步骤S12中，在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核。
卷积核的具体表现形式可以是一个矩阵，该矩阵中的元素为卷积时的权重，通过该权重，可以通过卷积操作提取想要的图像特征，抑制其它图像特征。
这里对卷积核的划分，具体可以是将卷积核的每一个权重划分为一个子卷积核，或者也可以将不止一个权重划分为一个子卷积核，本公开对子卷积核的划分尺寸不做限定。
对卷积核的拆分可以从两个层面进行拆分，第一层拆分是在通道维度上对卷积核进 行拆分，而第二层拆分是在长和宽的维度上进行拆分，通过两层的拆分，能够尽可能多地对卷积核进行切分。
在步骤S13中，利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征。
利用子卷积核进行卷积处理的过程，即对图像特征进行卷积处理的过程，具体过程此处不做赘述。
在步骤S14中，将所述多个子卷积特征进行特征融合处理，得到卷积特征，所述卷积特征用于表征对所述图像特征的提取结果。
由于多个子卷积核分别对图像特征进行的卷积处理，得到的多个子卷积特征是分开的，因此，可以通过特征融合处理将多个子卷积特征融合在一起。该特征融合处理的过程可以是将多个子卷积特征进行累加，或者可以是对各子卷积特征乘以一定的权重后进行累加，对于具体进行特征融合的过程，此处不做赘述。
那么，针对矩阵乘卷积方式而言，对于小图多通道的卷积类型，虽然矩阵A的M维度和矩阵B的N维度尺寸很小，且累加的K维度的尺寸却很大。然而，由于将卷积核划分为了多个子卷积核，可以在卷积核的维度上进一步分块，来提高并行执行的效率。
例如，当对3×3的卷积核、通道为1024的图像特征进行卷积操作时，第一层对通道划分为8份，那么通道维度的特征块尺寸为1024/8＝256；第二层对3x3卷积核划分为9份，那么子卷积核的尺寸为3×3/9＝1；这两层划分后的可以产生的特征块的数量为8x9＝72份。72份特征块并行进行运算，充分利用GPU中的处理资源，提高了卷积效率。
在本公开实施例中，通过在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核，利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，将所述多个子卷积特征进行特征融合处理，得到卷积特征。由此，通过在通道维度上对卷积核进行第一层拆分，在长和宽的维度上进行第二层拆分，通过两层的拆分，能够尽可能多地对卷积核进行切分，多个子卷积核并行地分别对所述图像特征进行卷积处理，该并行过程可以由多个计算单元并行地执行，充分利用GPU中的处理资源，提高了卷积操作的效率。
在一种可能的实现方式中，所述利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，包括：确定至少一个子卷积核在存储空间中的索引位置；根据所述索引位置，读取至少一个子卷积核中的数据，并行地将读取到的至少一个数据与所述图像特征进行卷积处理，得到多个子卷积特征。
数据在存储空间中存储时会有一个索引值，用来表征数据在存储空间中的存储位置，在本实现方式中，会预先记录子卷积核的索引值，该索引值具体可是卷积核在存储空间中的起始值和终止值。然后直接依据索引值来读取存储空间中的值来跟图像特征进行卷积计算，而无需将卷积核展开为矩阵再进行卷积计算，能够节省内存资源。
在一种可能的实现方式中，在所述将卷积核划分为多个子卷积核后，所述方法还包括：根据所述图像特征和至少一个子卷积核确定用于进行矩阵乘运算的第一矩阵和第二 矩阵，所述第一矩阵和第二矩阵的通道K维度的尺寸为所述图像特征的通道数乘以所述子卷积核的数量；在所述K维度上，将所述第一矩阵和第二矩阵划分为多个特征块。
如前文所述，矩阵乘法的计算形式可以表述为两个尺寸为M×K的矩阵A和K×N的矩阵B相乘，A中每一行的第K个元素都与B中对应列的第K个元素对应相乘，得到M×N的矩阵C的过程。
在显示的矩阵乘卷积中，可以先利用卷积核将M×N的矩阵转化为两个M×K的矩阵A和K×N的矩阵B，具体可以通过im2col算法来实现，此次不做赘述。而针对一个卷积核而言，在一个子卷积核为卷积核中的一个值的情况下，可以利用每一个子卷积核分别将M×N的矩阵(表征图像特征)转换为矩阵A和矩阵B，然后得到的这多个矩阵A可以在K维度上累加作为第一矩阵，得到的这多个矩阵B可以在K维度上累加作为第二矩阵。那么，显然，第一矩阵和第二矩阵的通道K维度的尺寸为所述图像特征的通道数乘以所述子卷积核的数量。
例如，卷积核的尺寸为3×3，每个子卷积核的尺寸为1，那么便有9个子卷积核，在图像特征的矩阵的通道数为1024的情况下，第一矩阵和第二矩阵K维度总的尺寸即为9×1024＝9216。
然后，在K维度上，将第一矩阵和第二矩阵划分为多个特征块，当然，也还可以在矩阵的行列(M和N)维度进行划分，此次不做赘述。具体划分特征块尺寸的实现方式，可参见本公开提供的多种可能的实现方式，此次不做赘述。
在本公开实施例中，基于划分的子卷积核，将第一矩阵和第二矩阵在K维度上的尺寸实现了倍增，那么，在所述K维度上，将所述第一矩阵和第二矩阵划分为多个特征块时，可以划分得到更多的特征块，由此，可以并行地分别对各所述特征块进行矩阵乘运算，得到多个子卷积特征，由于特征块的数量增多，因此，在进行卷积操作时可并行处理的特征块也进一步增多，进一步提高了卷积计算的效率。
在一种可能的实现方式中，所述利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，包括：在图形处理器的多个线程块内并行地进行矩阵乘处理，得到第一处理结果，其中，每个所述线程块内进行至少一个矩阵乘处理；所述将所述多个子卷积特征进行特征融合处理，得到卷积特征，包括：在所述图形处理器的共享内存中，将单个所述线程块内的至少一个矩阵乘处理得到的第一处理结果进行特征融合，得到至少一个线程块内的第二处理结果，并将所述第二处理结果写入全局存储空间中；将所述全局存储空间中的至少一个第二处理结果进行特征融合，得到卷积特征。
在图形处理器中，线程块TB加载在计算单元SM上运行，线程块TB可以并行地执行运算操作，因此，可以由图形处理器的多个TB并行地进行运算操作，每个线程块内进行至少一个运算操作，这样TB中即可得到多个第一处理结果。
单个TB中的特征块在通道K维度上进一步可以划分为一组或多组，即每一个TB中可以对一组或多组特征块进行计算，TB中计算的特征块的组数是2的指数幂，例如可以是1、 2、4等等。那么TB对一组或多组特征块进行计算后，会得到一组或多组第一处理结果，第一处理结果会位于共享内存(Shared Memory，SMem)中，然后通过SMem将同一TB中的第一处理结果进行特征融合，得到各TB内的第二处理结果。
虽然共享内存的大小有限，但是其具备较高的读写速度和带宽，因此，考虑到对单个TB内的第一处理结果进行特征融合所需的运算量并不大，因此，通过SMem对TB内部的第一运算结果进行特征融合，能够提高对第一运算结果进行融合的效率。
在将第一处理结果融合为第二处理结果后，第二处理结果的数量往往较多，因此，可以通过开辟额外的全局存储空间(Global Memory，即GMem)进行特征融合，如图4所示，多个第二处理结果(S 1-S n)在GMem上进行特征融合，最终得到卷积特征S。在GMem上对第二处理结果进行特征融合，由于GMem的存储空间较大，因此其输出效率不会随着特征块数量的增大而降低，能够保证对第二处理结果的输出效率。
在本公开实施例中，在图形处理器的多个线程块内并行地进行卷积处理，在进行特征融合时，可以先在图形处理器的共享内存中，将单个所述线程块内的各矩阵乘处理得到的第一处理结果进行特征融合，得到各线程块内的第二处理结果，并将所述第二处理结果写入全局存储空间中；然后将全局存储空间中的各第二处理结果进行特征融合，得到卷积特征。由此，由于共享内存具备较高的读写速度和带宽，因此通过共享内存对TB内部的第一运算结果进行特征融合，能够提高对第一运算结果进行融合的效率。其次，由于全局存储空间的存储空间较大，因此，通过全局存储空间对线程块之间的第二处理结果进行特征融合，其计算效率不会随着特征块数量的增大而降低，能够保证对第二处理结果的输出效率。从而进一步地提高了卷积任务的并行性，更好地利用了GPU的硬件资源。
在图形处理器中，通过图形处理器核函数kernel来进行特征尺寸切分和卷积核尺寸切分，而由于特征图的尺寸众多，因此，特征块划分尺寸固定的kernel并不能适用于全部的卷积尺寸类型上，在本公开实施例中，尽可能地遍历每一种可能的特征块尺寸来生成卷积kernel，一个卷积kernel对应一种特征块尺寸，由此，可以基于图像特征的尺寸，选择合适的kernel来进行分块，得到多个特征库。
在本公开实施例中，可以确定TB，线程束Warp及K维度的多种可能的特征块尺寸，最终生成对应的多种kernel，方便后期根据图像特征的尺寸来选择合适的kernel。下面对三个维度分别进行详细的说明。
在一种可能的实现方式中，在所述提取目标图像中的图像特征后，所述方法还包括：确定单个线程束Warp中能够处理的特征块的多种第一尺寸，并基于所述第一尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第一尺寸的最大值根据寄存器容量确定，所述第一尺寸的最小值为矩阵乘加运算指令计算的最小矩阵单元的尺寸，所述多种第一尺寸的值为所述最小值的倍数。
在GPU中，会通过下发的矩阵乘加运算(matrix multiply and accumulate，MMA)指令来进行卷积运算，示例性的，一个MMA指令所处理的最小矩阵单元在M×N维度是16 ×8，在K维度是8。
在单个Warp中，其能够处理的最小矩阵单元的尺寸即为MMA指令能够处理的最小矩阵单元的尺寸，而由于指令的运算是以2的指数幂的形式累加，因此单个Warp所能够处理的特征块的尺寸即为最小矩阵单元的尺寸再乘以2的指数幂，N可以为8、16、32、64，M可以为16、32、64、128，那么得到的M×N的值具体如表1所示。
而考虑到寄存器容量的限制，特征块的尺寸也不能无限的增大，其最大值可以根据寄存器容量来确定，由于寄存器容量的限制，寄存器中无法存储128x64的Warp特征块，因此，特征块的第一尺寸的最大值为128×32或64×64，具体如表1所示。
M\N 8 16 32 64
16 16x8 16x16 16x32 16x64
32 32x8 32x16 32x32 32x64
64 64x8 64x16 64x32 64x64
128 128x8 128x16 128x32 \
表1 Warp级的特征块尺寸
在本公开实施例中，可以在Warp维度将所有的特征块的第一尺寸进行遍历，进而基于第一尺寸生成图形处理器核函数kernel，这样得到的kernel可以适用于对各种尺寸的图像特征进行切分，得到的kernel的普适性较高。
在一种可能的实现方式中，在所述提取目标图像中的图像特征后，所述方法还包括：确定单个线程块TB中能够处理的特征块的多种第二尺寸，并基于所述第二尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第二尺寸的最小值为单个线程束Warp能够处理的特征块的第一尺寸，所述第二尺寸为所述第一尺寸的倍数，所述第二尺寸的最大值根据共享内存的容量和TB内线程数上限确定。
一个TB中会包含一个或多个Warp，那么，第二尺寸的最小值即为单个线程束Warp能够处理的特征块的第一尺寸，第二尺寸也可以是第一尺寸的倍数，该倍数为2的指数幂，即2、4。表3中的M TB和N TB的具体值为第一尺寸的倍数。
在一些GPU中，一个TB往往最多可以有1024个线程，即16个Warp，然而，在GPU中，线程数量为128-512个时运算效率较高，因此，往往不会运行16个Warp，因此，为了保证GPU运算效率，一个TB中最多运行8个Warp，即M TB×N TB的最大值为2×4或者4×2，如表2所示。
M TB\N TB 1 2 4
1 1x1 1x2 1x4
2 2x1 2x2 2x4
4 4x1 4x2 \
表2 TB级的特征块尺寸。表中的数字表示相应Warp级特征块尺寸的倍数
在本公开实施例中，可以在TB维度将所有的特征块的第二尺寸进行遍历，进而基于第二尺寸生成图形处理器核函数kernel，这样得到的kernel可以适用于对各种尺寸的图像特征进行切分，得到的kernel的普适性较高。
在一种可能的实现方式中，在所述提取目标图像中的图像特征后，所述方法还包括：确定单个线程块中的特征块在通道K维度上划分的分组的第三尺寸，以及所述分组的数量；基于所述分组的数量确定要进行融合处理的第一处理结果的数量；基于所述第三尺寸和所述第一处理结果的数量生成图形处理器核函数，所述图形处理器核函数还用于对单个线程块中的至少一个分组的至少一个第一处理结果进行融合处理。
如前文所述，在单个Warp中，其能够处理的最小矩阵单元的尺寸即为MMA指令能够处理的最小矩阵单元的尺寸，示例性的，一个MMA指令所处理的最小矩阵单元在M×N维度是16×8，在K维度是8。那么，单个TB中多种可能的K维度的尺寸包括k8、k16、k32、k64等。而TB是由多个Warp组成的，把这些Warp分成多个分组S，不同的组会在K维度的尺寸上进一步切分，切分的尺寸可以是s8、s16、s32等。
例如，1个TB中有8个warp，在TB内在K维度上的尺寸为K128，如果把这8个warp分成2组(每组4个warp)，那么，单个组处理的特征块在K维度尺寸即为s64。
单个TB中分组的数量即为K维度特征块的尺寸除以单个组的K维度尺寸，例如，针对表3中的第二行1×，其分组数为1；第二行2×，其分组数为2；第三行4×，其分组数为4。以k32_s16为例，s16表示分组的尺寸为16，k32表示特征块K维度的尺寸是32，因此，分组数即为2。
K/S 8 16 32
1× k8_s8 k16_s16 k32_s32
2× k16_s8 k32_s16 k64_s32
4× k32_s8 k64_s16 k128_s32
表3 K维度的特征块尺寸及分组尺寸。
由于一个分组会对应一个第一处理结果，因此，分组的数量即可作为第一处理结果的数量，然后基于第一处理结果的数量和第三尺寸即可生成图形处理核函数。
在本公开实施例中，可以在特征块的K维度上对分组的第三尺寸进行遍历，进而基于第三尺寸和特征块的尺寸，确定要进行融合处理的第一处理结果的多种数量，基于第三尺寸和第一处理结果的数量生成图形处理器核函数kernel，这样得到的kernel可以适用于对各种尺寸的分组的第一结果进行融合处理，得到的kernel的普适性较高。
请参阅图4，为本公开实施例的图像处理方法的一个应用场景示意图，在该应用场景中，包含多个GPU计算单元：SM1、SM2……SMn，每一个SM中的TB内对1个特征块进行矩阵乘运算，1个特征块分为2组进行并行处理，分组后得到的第一处理结果在图4中依次标识为S1_0,S1_1,S2_0,S2_1,……Sn_0,Sn_1，第一处理结果位于SMem上，在SMem上进行TB内规约(特征融合处理)，得到第二处理结果，第二处理结果在图4中依次标识为S1,S2,……Sn。得到的第二处理结果会写入GMem中，然后在GMem上进行TB间规约(特征融合处理)处理，得到卷积结果S。
可以理解，本公开提及的上述各个方法实施例，在不违背原理逻辑的情况下，均可以彼此相互结合形成结合后的实施例，限于篇幅，本公开不再赘述。本领域技术人员可 以理解，在具体实施方式的上述方法中，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
此外，本公开还提供了图像处理装置、电子设备、计算机可读存储介质、程序，上述均可用来实现本公开提供的任一种图像处理方法，相应技术方案和描述和参见方法部分的相应记载，不再赘述。
图5示出根据本公开实施例的图像处理装置的框图，如图5所示，所述装置50包括：
提取单元51，用于提取目标图像中的图像特征；
划分单元52，用于在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核；
处理单元53，用于利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征；
融合单元54，用于将所述多个子卷积特征进行特征融合处理，得到卷积特征，所述卷积特征用于表征对所述图像特征的提取结果。
在一种可能的实现方式中，所述处理单元，用于确定至少一个子卷积核在存储空间中的索引位置；根据所述索引位置，读取至少一个子卷积核中的数据，并行地将读取到的至少一个数据与所述图像特征进行卷积处理，得到多个子卷积特征。
在一种可能的实现方式中，所述装置还包括：
展开单元，用于根据所述图像特征和至少一个子卷积核确定用于进行矩阵乘运算的第一矩阵和第二矩阵，所述第一矩阵和第二矩阵的通道K维度的尺寸为所述图像特征的通道数乘以所述子卷积核的数量；
矩阵划分单元，用于在所述K维度上，将所述第一矩阵和第二矩阵划分为多个特征块。
在一种可能的实现方式中，所述处理单元，用于在图形处理器的多个线程块内并行地进行矩阵乘处理，得到第一处理结果，其中，每个所述线程块内进行至少一个矩阵乘处理；
所述融合单元，用于在所述图形处理器的共享内存中，将单个所述线程块内的至少一个矩阵乘处理得到的第一处理结果进行特征融合，得到至少一个线程块内的第二处理结果，并将所述第二处理结果写入全局存储空间中；将所述全局存储空间中的至少一个第二处理结果进行特征融合，得到卷积特征。
在一种可能的实现方式中，所述装置还包括：
第一尺寸确定单元，用于确定单个线程束Warp中能够处理的特征块的多种第一尺寸，并基于所述第一尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第一尺寸的最大值根据寄存器容量确定，所述第一尺寸的最小值为矩阵乘加运算指令计算的最小矩阵单元的尺寸，所述多种第一尺寸的值为所述最小值的倍数。
在一种可能的实现方式中，所述装置还包括：
第二尺寸确定单元，用于确定单个线程块TB中能够处理的特征块的多种第二尺寸，并基于所述第二尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第二尺 寸的最小值为单个线程束Warp能够处理的特征块的第一尺寸，所述第二尺寸为所述第一尺寸的倍数，所述第二尺寸的最大值根据共享内存的容量和TB内线程数上限确定。
在一种可能的实现方式中，所述装置还包括：
第三尺寸确定单元，用于确定单个线程块中的特征块在通道K维度上划分的分组的第三尺寸，以及所述分组的数量；基于所述分组的数量确定要进行融合处理的第一处理结果的数量；基于所述第三尺寸和所述第一处理结果的数量生成图形处理器核函数，所述图形处理器核函数还用于对单个线程块中的至少一个分组的至少一个第一处理结果进行融合处理。
在一些实施例中，本公开实施例提供的装置具有的功能或包含的模块可以用于执行上文方法实施例描述的方法，其具体实现和技术效果可以参照上文方法实施例的描述，为了简洁，这里不再赘述。
本公开实施例还提出一种计算机可读存储介质，其上存储有计算机程序指令，所述计算机程序指令被处理器执行时实现上述方法。计算机可读存储介质可以是易失性或非易失性计算机可读存储介质。
本公开实施例还提出一种电子设备，包括：处理器；用于存储处理器可执行指令的存储器；其中，所述处理器被配置为调用所述存储器存储的指令，以执行上述方法。
本公开实施例还提供了一种计算机程序产品，包括计算机可读代码，或者承载有计算机可读代码的非易失性计算机可读存储介质，当所述计算机可读代码在电子设备的处理器中运行时，所述电子设备中的处理器执行上述方法。
电子设备可以被提供为终端、服务器或其它形态的设备。
图6示出根据本公开实施例的一种电子设备800的框图。例如，电子设备800可以是移动电话，计算机，数字广播终端，消息收发设备，游戏控制台，平板设备，医疗设备，健身设备，个人数字助理等终端。
参照图6，电子设备800可以包括以下一个或多个组件：处理组件802，存储器804，电源组件806，多媒体组件808，音频组件810，输入/输出(I/O)的接口812，传感器组件814，以及通信组件816。
处理组件802通常控制电子设备800的整体操作，诸如与显示，电话呼叫，数据通信，相机操作和记录操作相关联的操作。处理组件802可以包括一个或多个处理器820来执行指令，以完成上述的方法的全部或部分步骤。此外，处理组件802可以包括一个或多个模块，便于处理组件802和其他组件之间的交互。例如，处理组件802可以包括多媒体模块，以方便多媒体组件808和处理组件802之间的交互。
存储器804被配置为存储各种类型的数据以支持在电子设备800的操作。这些数据的示例包括用于在电子设备800上操作的任何应用程序或方法的指令，联系人数据，电话簿数据，消息，图片，视频等。存储器804可以由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器 (EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。
电源组件806为电子设备800的各种组件提供电力。电源组件806可以包括电源管理系统，一个或多个电源，及其他与为电子设备800生成、管理和分配电力相关联的组件。
多媒体组件808包括在所述电子设备800和用户之间的提供一个输出接口的屏幕。在一些实施例中，屏幕可以包括液晶显示器(LCD)和触摸面板(TP)。如果屏幕包括触摸面板，屏幕可以被实现为触摸屏，以接收来自用户的输入信号。触摸面板包括一个或多个触摸传感器以感测触摸、滑动和触摸面板上的手势。所述触摸传感器可以不仅感测触摸或滑动动作的边界，而且还检测与所述触摸或滑动操作相关的持续时间和压力。在一些实施例中，多媒体组件808包括一个前置摄像头和/或后置摄像头。当电子设备800处于操作模式，如拍摄模式或视频模式时，前置摄像头和/或后置摄像头可以接收外部的多媒体数据。每个前置摄像头和后置摄像头可以是一个固定的光学透镜系统或具有焦距和光学变焦能力。
音频组件810被配置为输出和/或输入音频信号。例如，音频组件810包括一个麦克风(MIC)，当电子设备800处于操作模式，如呼叫模式、记录模式和语音识别模式时，麦克风被配置为接收外部音频信号。所接收的音频信号可以被进一步存储在存储器804或经由通信组件816发送。在一些实施例中，音频组件810还包括一个扬声器，用于输出音频信号。
I/O接口812为处理组件802和外围接口模块之间提供接口，上述外围接口模块可以是键盘，点击轮，按钮等。这些按钮可包括但不限于：主页按钮、音量按钮、启动按钮和锁定按钮。
传感器组件814包括一个或多个传感器，用于为电子设备800提供各个方面的状态评估。例如，传感器组件814可以检测到电子设备800的打开/关闭状态，组件的相对定位，例如所述组件为电子设备800的显示器和小键盘，传感器组件814还可以检测电子设备800或电子设备800一个组件的位置改变，用户与电子设备800接触的存在或不存在，电子设备800方位或加速/减速和电子设备800的温度变化。传感器组件814可以包括接近传感器，被配置用来在没有任何的物理接触时检测附近物体的存在。传感器组件814还可以包括光传感器，如互补金属氧化物半导体(CMOS)或电荷耦合装置(CCD)图像传感器，用于在成像应用中使用。在一些实施例中，该传感器组件814还可以包括加速度传感器，陀螺仪传感器，磁传感器，压力传感器或温度传感器。
通信组件816被配置为便于电子设备800和其他设备之间有线或无线方式的通信。电子设备800可以接入基于通信标准的无线网络，如无线网络(WiFi)，第二代移动通信技术(2G)或第三代移动通信技术(3G)，或它们的组合。在一个示例性实施例中，通信组件816经由广播信道接收来自外部广播管理系统的广播信号或广播相关信息。在一个示例性实施例中，所述通信组件816还包括近场通信(NFC)模块，以促进短程通信。例如，在NFC模块可基于射频识别(RFID)技术，红外数据协会(IrDA)技术，超宽带(UWB) 技术，蓝牙(BT)技术和其他技术来实现。
在示例性实施例中，电子设备800可以被一个或多个应用专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理设备(DSPD)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、控制器、微控制器、微处理器或其他电子元件实现，用于执行上述方法。
在示例性实施例中，还提供了一种非易失性计算机可读存储介质，例如包括计算机程序指令的存储器804，上述计算机程序指令可由电子设备800的处理器820执行以完成上述方法。
图7示出根据本公开实施例的一种电子设备1900的框图。例如，电子设备1900可以被提供为一服务器。参照图7，电子设备1900包括处理组件1922，其进一步包括一个或多个处理器，以及由存储器1932所代表的存储器资源，用于存储可由处理组件1922的执行的指令，例如应用程序。存储器1932中存储的应用程序可以包括一个或一个以上的每一个对应于一组指令的模块。此外，处理组件1922被配置为执行指令，以执行上述方法。
电子设备1900还可以包括一个电源组件1926被配置为执行电子设备1900的电源管理，一个有线或无线网络接口1950被配置为将电子设备1900连接到网络，和一个输入输出(I/O)接口1958。电子设备1900可以操作基于存储在存储器1932的操作系统，例如微软服务器操作系统(Windows Server TM)，苹果公司推出的基于图形用户界面操作系统(Mac OS X TM)，多用户多进程的计算机操作系统(Unix TM),自由和开放原代码的类Unix操作系统(Linux TM)，开放原代码的类Unix操作系统(FreeBSD TM)或类似。
在示例性实施例中，还提供了一种非易失性计算机可读存储介质，例如包括计算机程序指令的存储器1932，上述计算机程序指令可由电子设备1900的处理组件1922执行以完成上述方法。
本公开可以是系统、方法和/或计算机程序产品。计算机程序产品可以包括计算机可读存储介质，其上载有用于使处理器实现本公开的各个方面的计算机可读程序指令。
计算机可读存储介质可以是可以保持和存储由指令执行设备使用的指令的有形设备。计算机可读存储介质例如可以是(但不限于)电存储设备、磁存储设备、光存储设备、电磁存储设备、半导体存储设备或者上述的任意合适的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、静态随机存取存储器(SRAM)、便携式压缩盘只读存储器(CD-ROM)、数字多功能盘(DVD)、记忆棒、软盘、机械编码设备、例如其上存储有指令的打孔卡或凹槽内凸起结构、以及上述的任意合适的组合。这里所使用的计算机可读存储介质不被解释为瞬时信号本身，诸如无线电波或者其他自由传播的电磁波、通过波导或其他传输媒介传播的电磁波(例如，通过光纤电缆的光脉冲)、或者通过电线传输的电信号。
这里所描述的计算机可读程序指令可以从计算机可读存储介质下载到各个计算/处 理设备，或者通过网络、例如因特网、局域网、广域网和/或无线网下载到外部计算机或外部存储设备。网络可以包括铜传输电缆、光纤传输、无线传输、路由器、防火墙、交换机、网关计算机和/或边缘服务器。每个计算/处理设备中的网络适配卡或者网络接口从网络接收计算机可读程序指令，并转发该计算机可读程序指令，以供存储在各个计算/处理设备中的计算机可读存储介质中。
用于执行本公开操作的计算机程序指令可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码，所述编程语言包括面向对象的编程语言—诸如Smalltalk、C++等，以及常规的过程式编程语言—诸如“C”语言或类似的编程语言。计算机可读程序指令可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络—包括局域网(LAN)或广域网(WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。在一些实施例中，通过利用计算机可读程序指令的状态信息来个性化定制电子电路，例如可编程逻辑电路、现场可编程门阵列(FPGA)或可编程逻辑阵列(PLA)，该电子电路可以执行计算机可读程序指令，从而实现本公开的各个方面。
这里参照根据本公开实施例的方法、装置(系统)和计算机程序产品的流程图和/或框图描述了本公开的各个方面。应当理解，流程图和/或框图的每个方框以及流程图和/或框图中各方框的组合，都可以由计算机可读程序指令实现。
这些计算机可读程序指令可以提供给通用计算机、专用计算机或其它可编程数据处理装置的处理器，从而生产出一种机器，使得这些指令在通过计算机或其它可编程数据处理装置的处理器执行时，产生了实现流程图和/或框图中的一个或多个方框中规定的功能/动作的装置。也可以把这些计算机可读程序指令存储在计算机可读存储介质中，这些指令使得计算机、可编程数据处理装置和/或其他设备以特定方式工作，从而，存储有指令的计算机可读介质则包括一个制造品，其包括实现流程图和/或框图中的一个或多个方框中规定的功能/动作的各个方面的指令。
也可以把计算机可读程序指令加载到计算机、其它可编程数据处理装置、或其它设备上，使得在计算机、其它可编程数据处理装置或其它设备上执行一系列操作步骤，以产生计算机实现的过程，从而使得在计算机、其它可编程数据处理装置、或其它设备上执行的指令实现流程图和/或框图中的一个或多个方框中规定的功能/动作。
附图中的流程图和框图显示了根据本公开的多个实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，所述模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基 本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
该计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (11)

  1. 一种图像处理方法，其特征在于，包括：
    提取目标图像中的图像特征；
    在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核；
    利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征；
    将所述多个子卷积特征进行特征融合处理，得到卷积特征，所述卷积特征用于表征对所述图像特征的提取结果。
  2. 根据权利要求1所述的方法，其特征在于，所述利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，包括：
    确定至少一个子卷积核在存储空间中的索引位置；
    根据所述索引位置，读取至少一个子卷积核中的数据，并行地将读取到的至少一个数据与所述图像特征进行卷积处理，得到多个子卷积特征。
  3. 根据权利要求1或2所述的方法，其特征在于，在所述将卷积核划分为多个子卷积核后，所述方法还包括：
    根据所述图像特征和至少一个子卷积核确定用于进行矩阵乘运算的第一矩阵和第二矩阵，所述第一矩阵和第二矩阵的通道K维度的尺寸为所述图像特征的通道数乘以所述子卷积核的数量；
    在所述K维度上，将所述第一矩阵和第二矩阵划分为多个特征块。
  4. 根据权利要求1-3任一所述方法，其特征在于，所述利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征，包括：
    在图形处理器的多个线程块内并行地进行矩阵乘处理，得到第一处理结果，其中，所述线程块内进行至少一个矩阵乘处理；
    所述将所述多个子卷积特征进行特征融合处理，得到卷积特征，包括：
    在所述图形处理器的共享内存中，将单个所述线程块内的至少一个矩阵乘处理得到的第一处理结果进行特征融合，得到至少一个线程块内的第二处理结果，并将所述第二处理结果写入全局存储空间中；
    将所述全局存储空间中的至少一个第二处理结果进行特征融合，得到卷积特征。
  5. 根据权利要求1-4任一所述方法，其特征在于，在所述提取目标图像中的图像特征后，所述方法还包括：
    确定单个线程束Warp中能够处理的特征块的多种第一尺寸，并基于所述第一尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第一尺寸的最大值根据寄存器容量确定，所述第一尺寸的最小值为矩阵乘加运算指令计算的最小矩阵单元的尺寸，所 述多种第一尺寸的值为所述最小值的倍数。
  6. 根据权利要求1-5任一所述方法，其特征在于，在所述提取目标图像中的图像特征后，所述方法还包括：
    确定单个线程块TB中能够处理的特征块的多种第二尺寸，并基于所述第二尺寸生成用于进行特征块划分的图形处理器核函数；其中，所述第二尺寸的最小值为单个线程束Warp能够处理的特征块的第一尺寸，所述第二尺寸为所述第一尺寸的倍数，所述第二尺寸的最大值根据共享内存的容量和TB内线程数上限确定。
  7. 根据权利要求1-6任一所述方法，其特征在于，在所述提取目标图像中的图像特征后，所述方法还包括：
    确定单个线程块中的特征块在通道K维度上划分的分组的第三尺寸，以及所述分组的数量；
    基于所述分组的数量确定要进行融合处理的第一处理结果的数量；
    基于所述第三尺寸和所述第一处理结果的数量生成图形处理器核函数，所述图形处理器核函数还用于对单个线程块中的至少一个分组的至少一个第一处理结果进行融合处理。
  8. 一种图像处理装置，其特征在于，包括：
    提取单元，用于提取目标图像中的图像特征；
    划分单元，用于在卷积核的通道维度上以及长和宽的维度上，将卷积核划分为多个子卷积核；
    处理单元，用于利用所述多个子卷积核并行地分别对所述图像特征进行卷积处理，得到多个子卷积特征；
    融合单元，用于将所述多个子卷积特征进行特征融合处理，得到卷积特征，所述卷积特征用于表征对所述图像特征的提取结果。
  9. 一种电子设备，其特征在于，包括：
    处理器；
    用于存储处理器可执行指令的存储器；
    其中，所述处理器被配置为调用所述存储器存储的指令，以执行权利要求1至7中任意一项所述的方法。
  10. 一种计算机可读存储介质，其上存储有计算机程序指令，其特征在于，所述计算机程序指令被处理器执行时实现权利要求1至7中任意一项所述的方法。
  11. 一种计算机程序产品，包括计算机可读代码，或者承载有计算机可读代码的非易失性计算机可读存储介质，当所述计算机可读代码在电子设备的处理器中运行时，所述电子设备中的处理器执行用于实现权利要求1-7中的任一权利要求所述的方法。
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