WO2023277914A1 - Micro-machined ultrasound transducers with insulation layer and methods of manufacture - Google Patents
Micro-machined ultrasound transducers with insulation layer and methods of manufacture Download PDFInfo
- Publication number
- WO2023277914A1 WO2023277914A1 PCT/US2021/039977 US2021039977W WO2023277914A1 WO 2023277914 A1 WO2023277914 A1 WO 2023277914A1 US 2021039977 W US2021039977 W US 2021039977W WO 2023277914 A1 WO2023277914 A1 WO 2023277914A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- soi
- cavity
- mut
- silicon
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000002604 ultrasonography Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 38
- 238000009413 insulation Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 53
- 239000010703 silicon Substances 0.000 claims abstract description 53
- 239000012528 membrane Substances 0.000 claims abstract description 28
- 239000012212 insulator Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 238000005530 etching Methods 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 213
- 235000012431 wafers Nutrition 0.000 description 42
- 238000003384 imaging method Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000000708 deep reactive-ion etching Methods 0.000 description 6
- 230000033001 locomotion Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000004927 fusion Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000002059 diagnostic imaging Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 210000001519 tissue Anatomy 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 241001465754 Metazoa Species 0.000 description 2
- 239000002033 PVDF binder Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000017531 blood circulation Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229920002981 polyvinylidene fluoride Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 210000001835 viscera Anatomy 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- -1 LaNi03 Inorganic materials 0.000 description 1
- XOJVVFBFDXDTEG-UHFFFAOYSA-N Norphytane Natural products CC(C)CCCC(C)CCCC(C)CCCC(C)C XOJVVFBFDXDTEG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000007765 extrusion coating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 210000000056 organ Anatomy 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000007761 roller coating Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001356 surgical procedure Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000001225 therapeutic effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
- B06B1/0607—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using multiple elements
- B06B1/0622—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using multiple elements on one surface
- B06B1/0629—Square array
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
- A61B8/4483—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device characterised by features of the ultrasound transducer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
- B06B1/0688—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction with foil-type piezoelectric elements, e.g. PVDF
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/0292—Electrostatic transducers, e.g. electret-type
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
- B06B2201/70—Specific application
- B06B2201/76—Medical, dental
Definitions
- the present disclosure relates to semi-conductor and micro-electromechanical system (MEMS) technology usable in a medical context, for example, MEMs ultrasound transducers.
- MEMS micro-electromechanical system
- Micromachined ultrasonic transducers offer great potential in many fields, including but not limited to medical imaging, air-coupled imaging, distance monitoring, fingerprint monitoring, non-destructive defect monitoring, backside illumination, bio-MEMS, and diagnosis. Crosstalk is an issue often faced by MUTs.
- SOI wafers enable the manufacture of the most advanced MEMS, complementary metal-oxide-semiconductor (CMOS), power, and radio frequency (RF) components used in consumer, automotive, industrial, and healthcare applications.
- CMOS complementary metal-oxide-semiconductor
- RF radio frequency
- SOI wafers provide high-quality, single-crystalline silicon layers over a high-quality silicon dioxide layer (buried oxide or BOX) which can be used in the design of several MEMS devices.
- SOI wafers provide precise control of several material parameters which enable design and manufacture of unique device configurations.
- Double SOI technology may also improve the functionalities of various microelectromechanical systems (MEMS) devices, such as micromachined ultrasonic transducers (MUTs), including piezoelectric MUTs (pMUTs) and capacitive MUTs (cMUTs).
- MEMS microelectromechanical systems
- MUTs micromachined ultrasonic transducers
- pMUTs piezoelectric MUTs
- cMUTs capacitive MUTs
- Use of double SOI technology may enable designers with more flexibility to size and position cavities (or waveguides) and trenches for etching in the devices’ buried oxide (BOX) and semiconductor layers.
- BOX buried oxide
- a double SOI design may improve acoustic wave transmission (e.g., by increasing wave output power) and reduce crosstalk.
- the multi-SOI process disclosed herein may enable better critical dimension control during the process of etching trenches and cavities in the MUT device, enhancing design flexibility. Additionally, the multi-SOI process may provide more precise alignment tolerances, mitigating effects from alignment errors.
- a multi-silicon on insulator (SOI) micromachined ultrasonic transducer (MUT) device comprises a multi-SOI substrate.
- the device also comprises a MUT having a membrane.
- the device also discloses the MUT affixed to a surface of the multi-SOI substrate.
- the device also discloses the multi-SOI substrate comprising a first SOI layer and at least a second SOI layer disposed above the first SOI layer, the first SOI layer and the second SOI layer each comprising an insulating layer and a semiconducting layer.
- the first SOI layer further comprises a cavity located under the membrane of the MUT. One or more trenches at least partially around a perimeter of the cavity.
- the MUT is a piezoelectric micromachined ultrasound transducer (pMUT).
- the MUT is a capacitive micromachined ultrasound transducer (cMUT).
- the second SOI layer is 40-80 micrometers in height.
- the insulating layer is a buried oxide (BOX) layer.
- the BOX layer is 1-5 micrometers in height.
- the semiconducting layers of the first SOI layer and at least the second SOI layer are handle layers; wherein the cavity is created by etching at least one of the handle layers and the BOX layer.
- the device includes a through silicon via.
- the semiconducting layer is a silicon membrane layer.
- the multi-SOI substrate is a double-SOI substrate.
- the cavity includes a deposited oxide layer.
- the trench is etched to a depth spanning one or more layers of the device.
- the device further includes a handle layer below the first SOI layer.
- the handle layer is a semiconductor layer.
- the semiconducting layer of the second SOI layer includes a metallic coating.
- the cavity is filled with a gas.
- the cavity contains a vacuum.
- the insulating layer comprises a non-oxide insulator.
- a multi-silicon on insulator (SOI) micromachined ultrasonic transducer (MUT) array comprises a multi-SOI substrate.
- the array also comprises a plurality of MUTs each having a membrane.
- the plurality of MUTs was affixed to a surface of the multi-SOI substrate.
- the multi-SOI substrate comprises a second SOI layer disposed above a first SOI layer, the first SOI layer and the second SOI layer each comprising an insulating layer and a semiconducting layer.
- the first SOI layer further comprises a plurality of cavities, each cavity located under a membrane of a MUT of the plurality of MUTs.
- the first SOI layer also comprises one or more trenches at least partially around a perimeter of a cavity of the plurality of cavities of the plurality of MUTs.
- a method of manufacturing a double-silicon on insulator (SOI) micromachined ultrasonic transducer (MUT) array comprises defining at least one trench in a first SOI layer by etching an oxide layer of the first SOI layer to contain a width of the at least one trench.
- the method also comprises applying a photoresist layer to the oxide layer of the first SOI layer.
- the method also comprises defining a cavity in the first SOI layer by pattern etching the photoresist layer and the oxide layer to contain a width of the cavity.
- the method also comprises etching the cavity and the at least one trench.
- the method also comprises applying an oxide layer to the cavity and the at least one trench.
- Fig. 1A is a schematic diagram showing a cross-section of a generalized MUT array attached to an acoustic medium, in accordance with embodiments.
- Fig. IB shows a top view of a MUT array, in accordance with embodiments.
- FIG. 1C is a block diagram of an imaging device, in accordance with embodiments.
- Fig. ID shows a top view of a MUT, in accordance with embodiments.
- Fig. IE shows a cross-sectional view of a MUT, taken along a direction 4-4 in Fig. ID, in accordance with embodiments.
- Fig. 2 is a graph showing amplitude of motion of a MUT array with 128 elements in the azimuth direction, spanning approximately 22 mm, in accordance with embodiments.
- the center two MUTs were actuated, and the other 126 MUTs were monitored for response.
- the grey level indicates positive (towards white) or negative (towards black) diaphragm deflection.
- the two fired elements were eliminated from the plot so that the cross-talk ripples could be visualized.
- the dashed lines 230 approximately represent the imaging cone, defined by wave with a 1,480 m/s velocity.
- Fig. 3 is a graph showing a Fourier transform in space and time (also referred to as an f-k plot). of the data from Fig. 2, representing the data in spatial and frequency domains, in accordance with embodiments.
- the amplitude is plotted in dB relative to the maximum amplitude of the Fourier data, with white data having a higher amplitude black blue data.
- the data circled in between 2 and 4 MHz and 0.5 and 1.5 psec is undesired cross-talk.
- Fig. 4 is an ultrasound image taken with a MUT array similar to that of Figs. 2 and 3, in accordance with embodiments.
- the “spotlight” effect is highlighted by the two arrows, while the “ghosting” artifacts are circled.
- Fig. 5 illustrates a double-SOI MEMS device, in accordance with embodiments.
- Fig. 6 illustrates a double-SOI MEMS device, in accordance with embodiments.
- Fig. 7 illustrates a process for etching cavities and trenches in the “handle” wafer of a double-SOI substrate.
- Fig. 8 illustrates a process for etching cavities and trenches in the “handle” wafer of a double-SOI substrate.
- Described herein is a multi-SOI structure for use as a substrate for microelectromechanical systems (MEMS) manufacturing, especially of micromachined ultrasound transducers (MUTs), including piezoelectric MUTs (pMUTs) and capacitive MUTs (cMUTs).
- MEMS microelectromechanical systems
- MUTs micromachined ultrasound transducers
- pMUTs piezoelectric MUTs
- cMUTs capacitive MUTs
- the multi-SOI structure is a double-SOI structure.
- the multi-SOI structure disclosed may confer many benefits to MUT array designers.
- the depth of the device resulting from adding additional SOI layers, enables buried cavities and trenches to be etched to be longer than in single-SOI structures.
- the disclosed system can enable designers to have flexibility when choosing where to place trenches and how large to make the cavities and trenches in MEMs devices and arrays. This flexibility can enable enhanced ability for a MEMS MUT array to increase the output power of a generated acoustic signal for deep penetration into a subject, and to mitigate the effects of crosstalk from interfacial waves traveling through the array’s silicon substrate.
- Increasing the output power can be performed through the etching of buried cavities, or waveguides, in the multi-SOI substrate.
- the cavities may be etched so that they span multiple layers of the multi-SOI substrate.
- the methods disclosed herein for multi-SOI MEMS device manufacturing may enable precise control of the thickness and depth of the cavities, through multiple iterations of etching and masking.
- a layer of oxide may be applied to the cavity.
- the oxide may be applied by thermally growing the oxide or depositing it (e.g., by Plasma Enhanced Chemical Vapor Deposition (PECVD)).
- PECVD Plasma Enhanced Chemical Vapor Deposition
- a designer may place buried trenches at various locations within the multi-SOI substrate.
- a trench may introduce an impedance mismatch between the substrate of the MEMS device and whatever material is within the cross-talk trench. This impedance mismatch can disrupt cross-talk waves through attenuation, reflection, and scattering.
- Designers may etch trenches to various depths and at various locations near cavities.
- the pattern of trenches etched need not be uniform across a MEMS device (e.g., MUT) array.
- the disclosed system may enable electronic devices to communicate with one another using a through-silicon via (TSV).
- TSV may be a vertical conducting structure to connect multiple silicon dice stacked vertically in a single package.
- a designer may be able to produce vertical electrical connections capable of connecting many devices.
- Using a TSV may increase interconnect and device density, shortening connections between devices, thus reducing electrical losses.
- a TSV may be encoded in the multi-SOI substrate from the top layer of the device to the bottom layer. For example, one may form a recess in the multi-SOI substrate, using a mask to define the width of the recess.
- a conducting material such as a metal, metal alloy, or conductive ceramic compound, such as TiN or doped semiconductor or semiconductor alloys.
- the multi-SOI process disclosed herein may enable better critical dimension control during the process of etching trenches and cavities in the MUT device, enhancing design flexibility. Additionally, the multi-SOI process may provide more precise alignment tolerances, mitigating effects from alignment errors. For example, the multi-SOI process may reduce tolerances necessary to compensate for alignment errors from on the order of 10 micrometers (pm) to on the order of 3 pm. Cavities and trenches in the multi-SOI structure may be etched from the top of an SOI layer, rather than from the bottom, as SOI structures are commonly etched. This may prevent the formation of artifacts, such as tapers, from the etching process.
- FIG. 5 illustrates a double-SOI MEMS device 500, in accordance with an embodiment.
- the device is a pMUT device.
- multi-SOI MEMS devices may have 3, 4, 5, 6, or 10 or more SOI layers.
- the semiconductor used in the embodiment is silicon, in other embodiments, the semiconductor material may be germanium, silicon-germanium, carbon-doped silicon, carbon-doped silicon-germanium, or another material.
- a pMUT array would implement a similar structure repeated in a periodic fashion, but with the trench placement varying spatially.
- the surface layers 510 comprise a piezoelectric layer sandwiched between two conducting layers and are affixed to the double-SOI substrate.
- the conducting layers may comprise electrodes, which may be made of multiple layers comprising SRO (SrRuCh), titanium, and platinum.
- SRO SRO
- the piezoelectric layer can become stressed. This stressing may actuate a membrane below the piezoelectric and conducting layers to create an acoustic output wave.
- the piezoelectric layer may be made of a piezoelectric material such as PZT, KNN, PZT-N, PMN-Pt, AIN, Sc- AIN, ZnO, PVDF, and LiNi03.
- the thicknesses of the piezoelectric layer may vary between 100 nm and 5 pm or possibly more.
- the surface layers 510 may also comprise a multi-layer piezoelectric element (multi-morph), comprising a plurality of piezoelectric sublayers and electrodes.
- the insulating layer 520 may be an oxide layer deposited over the multi-SOI substrate.
- the oxide layer may be silicon dioxide, silicon nitride, or silicon oxy-nitride.
- the insulating layer 520 may be .1 pm to .3 pm thick.
- the insulator may be thermally grown or deposited.
- the second SOI layer 530 may comprise a silicon membrane layer disposed above an insulating layer.
- the insulating layer may be an oxide layer, which may be referred to as a buried oxide layer (BOX). However, the insulating layer may also be composed of a non-oxide insulator, such as sapphire.
- the insulating layer may serve to reduce parasitic capacitance in the MEMS device by physically separating conducting layers from one another, preventing them from accumulating electric charge.
- the silicon membrane layer may facilitate the transmission and receipt of acoustic waves by the pMUT transducer.
- the transducer may transmit an acoustic wave when the piezoelectric layer is stressed, actuating the silicon membrane layer.
- a reflected wave When a reflected wave is incident on the transducer, it may provide pressure to the membrane layer, which can induce a change in charge in the piezoelectric layer.
- the silicon membrane layer may be bonded to the insulating layer using silicon direct or fusion bonding.
- the silicon and oxide layers may be bonded using the following method: a silicon wafer may be oxidized and then implanted with an etch stop layer. Then, the oxidized layer may be bonded to a silicon wafer beneath it. Then, the bonded layers may be annealed. The silicon wafer may be polished and etched down to the etch stop layer. Finally, the etch stop layer may be removed and the top silicon layer further polished.
- the first SOI layer 540 may comprise a silicon layer disposed above an insulating layer, itself disposed above a silicon substrate.
- the first SOI layer may be disposed underneath the second SOI layer.
- the first SOI layer may comprise a cavity and one or more trenches, in addition to silicon and insulating layers similar to those in the second SOI layer.
- the cavity 550 may be sized with specificity to improve performance of the pMUT device.
- the cavity may be etched to a depth spanning the semiconducting layer and insulating layers, as well as cutting into the silicon substrate to a depth.
- a designer may also modify the width of the cavity. Modifying the depth and width of the cavity 550 may serve to shape the output wave produced by the transducer, to provide for better penetration into the acoustic medium. Increasing the number of layers of the multi-SOI devices can increase the depth to which the cavity 550 may be etched.
- the cavity 550 may be in a vacuum, but in other embodiments, the cavity may be filled with a gas at a predetermined pressure.
- a pMUT array may have some cavities filled with vacuums and others filled with gases, to respectively enable freedom of vibrational movement of the membrane in some locations and dampen the vibrational motion of the membrane in other locations.
- the trench 560 may also be sized at the discretion of the designer, as well as placed within the device at the discretion of the designer.
- the trenches may be placed at various locations within the layers of semiconducting material.
- the trenches may also be etched to depths spanning one or more SOI layers of the pMUT device.
- the distribution of trenches in the transducer array need not be uniform. Some individual pMUT elements may have multiple trenches disposed alongside them, where others may only have one trench.
- trenches within the pMUT array may be of various lengths and distances from the surface layers 510, depending on the needs of the double-SOI transducer system.
- the substrate 570 may be a semiconductor layer, e.g., a silicon layer.
- the substrate 570 may also be referred to as a handle layer and may be significantly larger than either of the SOI layers.
- FIG. 6 illustrates a double-SOI MEMS device 600, in accordance with an embodiment.
- the device is a cMUT device.
- a cMUT array would implement a similar structure repeated in a periodic fashion, but with the trench placement varying spatially.
- a cMUT device includes a flexible membrane layer above a cavity formed in a semiconducting substrate.
- the membrane layer and substrate serve as electrodes, and a direct current (DC) bias is applied to them.
- the membrane layer may include a metallic coating.
- the double-SOI MEMS cMUT device may be structured in a similar manner to the double-SOI MEMS pMUT device.
- the device may include, from top to bottom: surface layers 610 (which may comprise one or more electrodes), an insulating layer 620, a second SOI layer 630, a first SOI layer 640, and a semiconducting substrate 670.
- the first SOI layer may comprise the membrane layer, while the second SOI layer may comprise one or more cavities 650 and one or more trenches 660 for acoustic wave generation and shaping and crosstalk elimination.
- MUT micromachined ultrasound transducer
- pMUT piezoelectric micromachined ultrasound transducer
- cMUT capacitive micromachine ultrasonic transducer
- the MUTs can be designed to transmit energy into the acoustic medium to which they are attached.
- the MUTs are represented by the movable diaphragms 101a, 101b, 101c which are formed in or on top of the substrate 100 by cavities 120a, 120b, and 120c.
- the diaphragms 101a, 101b, 101c are coupled acoustically to the semi-infinite acoustic medium 200 at an interface 110.
- the acoustic medium 200 can be any substance, or a plurality of substances; common media include air, water, tissue, electrolytic gel, metal, silicone rubbers used as matching layers to the body, etc.
- the diaphragms lOla-lOlc are excited into motion, primarily in the z- direction.
- the excitation is generally created by a piezoelectric effect (for piezoelectric MUTs (pMUTs)) or a capacitive effect (for capacitive MUTs (cMUTs)).
- pMUTs piezoelectric MUTs
- cMUTs capacitive MUTs
- the motion of the diaphragm creates pressure waves that transmit into the acoustic medium 200.
- the diaphragm motion also creates unwanted waves outside the acoustic medium 200.
- the most common unwanted waves are elastic compression waves that travel within and through the substrate 100, and interfacial waves that travel along the interface 110 between the substrate 100 and the acoustic medium 200, as well as other interfaces attached to the substrate 100.
- All energy radiated outside the acoustic medium 200 is generally unwanted. Not only is it wasted power, but it can interfere with the MUT’s functioning.
- the elastic compression waves will rebound off other surfaces and cause artifacts such as a static image over the medically relevant image formed from the reflected energy from the acoustic medium 200.
- the interfacial waves that travel along the interface 110 will create cross-talk in medical imaging, creating a spot-lighting effect and unwanted ghost images.
- FIG. IB A generalized example of a MUT array 210 is shown in Fig. IB.
- the MUT array 210 comprises a substrate 100 and a plurality of MUTs 101.
- the plurality of MUTs 101 are affixed to a surface of the substrate.
- Each MUT comprises a moveable diaphragm as shown in Fig. 1A.
- each of the MUTs 101 is a pMUT.
- each of the MUTs 101 is a cMUT.
- the MUTs 101 may be arranged in a two-dimensional array 210 arranged in orthogonal directions. That is, the MUTs 101 are be formed into a two-dimensional MxN array 210 with N columns and M rows of MUTs 101.
- the number of columns (N) and the number of rows (M) may be the same or different.
- the array 210 may be curved, e.g., to provide a wider angle of an object being imaged.
- the array may offer different packing such as hexagonal packing, rather than the standard square packing displayed in Fig. IB.
- the array may asymmetrical, e.g., as described in U.S. Patent No. 10,656,007, the entire contents of which are incorporated herein by reference.
- Fig. 2 provides an example of this cross-talk in a MUT array formed from a silicon substrate 100 coupled to a water acoustic medium 200.
- the diagonal ripples 220 represent traveling pressure waves.
- the two dashed lines 230 represent the speed of sound of the water acoustic medium (approximately 1,480 m/s). Ripples and high amplitude data 240 below these lines 230 typically represents good acoustic data.
- the data 250 above the two dashed lines 230 represent various forms of cross-talk.
- Fig. 3 Taking spatial and temporal Fourier transforms of the data in Fig. 2 yields the f-k plot in Fig. 3.
- Fig. 3 we can see that the cross-talk acoustic energy, circled with a dashed line 300, is distributed around 2,000 to 6,000 m/s.
- the longitudinal speed of sound in silicon is approximately 8,800 m/s, while the interfacial wave speed for Rayleigh and Shear waves is between 5,000 and 5,500 m/s. This suggests that the cross-talk energy may be due to a combination of interfacial and bulk waves.
- Fig. 1C is a block diagram of an imaging device 105 with selectively alterable channels 106, 108, controlled by a controller 109, and having imaging computations performed on a computing device 110 according to principles described herein.
- the imaging device 105 may be used to generate an image of internal tissue, bones, blood flow, or organs of human or animal bodies. Accordingly, the imaging device 105 may transmit a signal into the body and receives a reflected signal from the body part being imaged.
- imaging devices may include either pMUTs or cMUTs, which may be referred to as transceivers or imagers, which may be based on photo-acoustic or ultrasonic effects.
- the imaging device 105 can be used to image other objects as well.
- the imaging device 105 can be used in medical imaging; flow measurements in pipes, speaker, and microphone arrays; lithotripsy; localized tissue heating for therapeutic; and highly intensive focused ultrasound (HIFU) surgery.
- HIFU highly intensive focused ultrasound
- the imaging device 105 may be used to get an image of internal organs of an animal as well. Moreover, in addition to imaging internal organs, the imaging device 105 may also be used to determine direction and velocity of blood flow in arteries and veins as in Doppler mode imaging and may also be used to measure tissue stiffness. [071] The imaging device 105 may be used to perform different types of imaging. For example, the imaging device 105 may be used to perform one dimensional imaging, also known as A- Scan, two dimensional imaging, also known as B scan, three dimensional imaging, also known as C scan, and Doppler imaging. The imaging device 105 may be switched to different imaging modes and electronically configured under program control.
- the imaging device 105 includes an array of pMUT or cMUT transducers 210, each transducer 210 including an array of transducer elements (i.e., MUTs) 101.
- the MUTs 101 operate to 1) generate the pressure waves that are passed through the body or other mass and 2) receive reflected waves off the object within the body, or other mass, to be imaged.
- the imaging device 105 may be configured to simultaneously transmit and receive ultrasonic waveforms. For example, certain MUTs 101 may send pressure waves toward the target object being imaged while other MUTs 101 receive the pressure waves reflected from the target object and develop electrical charges in response to the received waves.
- Fig. ID shows a top view of an exemplary MUT 400 (in this example, a pMUT).
- the MUT 400 may be substantially similar to the MUT 101 described herein.
- the MUT may include: a membrane layer 406 suspended from a substrate 402 and disposed over a cavity 404; a bottom electrode (O) 408 disposed on the membrane layer (or, shortly membrane) 406; a piezoelectric layer 410 disposed on the bottom electrode (O) 408; and a top electrode (X) 412 disposed on the piezoelectric layer 410.
- MUTs whether cMUTs or pMUTs, can be efficiently formed on a substrate leveraging various semiconductor wafer manufacturing operations.
- Semiconductor wafers may come in 6 inch, 8 inch, and 12 inch sizes and are capable of housing hundreds of transducer arrays. These semiconductor wafers start as a silicon substrate on which various processing steps are performed.
- An example of such an operation is the formation of S1O2 layers, also known as insulating oxides.
- Various other steps such as the addition of metal layers to serve as interconnects and bond pads are performed to allow connection to other electronics.
- Yet another example of a machine operation is the etching of cavities (e.g., cavity 404 in Fig. IE) in the substrate.
- a first SOI substrate comprising a first SOI layer
- the first SOI layer may comprise a first silicon layer, a buried oxide layer, and a second silicon layer, with the first silicon layer and second silicon layer typically being single-crystal silicon.
- An oxide layer typically silicon dioxide may be deposited over the first silicon layer.
- a cavity and one or more cross-talk trenches may be patterned and etched in the first SOI layer to form a “handle” wafer.
- the trench etch may comprise four steps: (1) etching the oxide layer, (2) etching the first silicon layer via DRIE, (3) etching the BOX (typically via dry RIE etching, or in some cases, via wet etching), and (4) etching the second silicon layer via DRIE to the desired depth.
- an oxide layer may be deposited above the cavity and the trenches and may serve to narrow the trench if desired.
- a second SOI “device” wafer may then be fusion bonded to the “handle” to form the buried trenches and cavity in the double-SOI substrate.
- the “device” wafer may form the second SOI layer of the double-SOI substrate, with the first silicon layer of the first SOI layer forming the second silicon layer of the second SOI layer.
- Most SOI wafers are silicon, meaning that the silicon layers of the “device” and “handle” wafers will typically be single crystal silicon.
- the insulator BOX in this case, is typically a silicon dioxide thermally grown.
- a silicon SOI wafer with single crystal silicon handle and device layers with an oxide BOX may typically be used.
- the device layer may be 5 pm, but typically varies between 100 nm and 100 pm, while the handle layer thickness typically varies between 100 pm and 1000 pm.
- the BOX is typically between 100 nm and 5 pm, but 1 pm may be used, in many cases.
- the backside of the wafer or handle can be thinned via grinding and optionally polished at this point.
- the handle layer is thinned from 500 pm to 300 pm thick. Common thicknesses typically vary between 50 pm and 1000 pm.
- the cavity-side trenches 105 may be patterned and etched.
- the backside of the substrate 100 may be etched typically via DRIE (deep reactive ion etching).
- the cavity etch can be timed.
- the cavity may be etched at the same time as the cavity- side trench 105.
- the etch may stop selectively on the BOX.
- the cavity can be etched via other techniques such as KOH, TMAH, HNA, and RIE.
- the wafer can be considered complete after photoresist strip.
- An insulating layer can then be deposited over the double-SOI substrate.
- the insulating layer is typically some form of S1O2, about 0.1 pm to 3 pm thick. It is commonly deposited via thermal oxidation, PECVD deposition, or by another technique.
- a first metal layer 408 (of Fig. IE) (also referred to as Ml or metal 1) can then be deposited.
- this is a combination of films that adhere to the substrate, prevent diffusion of the piezoelectric, aid the piezoelectric in structured deposition/growth, and which is conductive.
- SRO SrRu03
- these layers are thin, less than 200 nm, with some films 10 to 40 nm. Stress, manufacturing, and cost issues will usually limit this stack to less than 1 pm.
- the conductor (Pt) is typically thicker than the structuring layer (SRO) and adhesion layer (Ti).
- Pt can be replaced with other conductive materials such as Cu, Cr, Ni, Ag, Al, Mo, W, and NiCr. These other materials usually have disadvantages such as poor diffusion barrier, brittleness, or adverse adhesion, and Pt is the most common conductor used.
- the adhesion layer, Ti can be replaced with any common adhesion layers such as TiW, TiN, Cr, Ni, Cr, etc.
- a piezoelectric material 410 can then be deposited.
- suitable piezoelectric materials include: PZT, KNN, PZT-N, PMN-Pt, AIN, Sc- AIN, ZnO,
- the thicknesses of the piezoelectric layer may vary between 100 nm and 5 pm or possibly more.
- a second metal layer 412 (also referred to as M2 or metal 2) can then be deposited.
- This second metal layer 412 may be similar to the first metal layer 408 and may serve similar purposes.
- M2 the same stack as Ml may be used, but in reverse: Ti for adhesion on top of Pt to prevent diffusion on top of SRO for structure.
- the second metal layer or M2412 may then be patterned and etched, stopping on the piezoelectric layer. Etches can be made in many ways herein, for example, via RIE (reactive ion etching), ion mill, wet chemical etching, isotropic gas etching, etc. After patterning and etching, the photoresistor used to pattern M2 may be stripped, via wet and/or dry etching. In many embodiments for manufacturing cMUTs and pMUTs described herein, any number of ways of etching may be used, and the photoresist is typically stripped after most pattern and etch steps. [087] (k) The piezoelectric layer may then be similarly patterned and etched, stopping at the first metal layer or Ml 408. Typically, wet, RIE, and/or ion mill etches are used.
- the first metal layer or Ml 408 may then be similarly patterned and etched, stopping on the dielectric insulating layer.
- An H2 barrier H2 diffusion into the piezoelectric layer can limit its lifetime. To prevent this, an H2 barrier can be used. 40 nm of ALD (atomic layer deposition) aluminum oxide (A1203) may be used to accomplish this. Other suitable materials may include SiC, diamond-like carbon, etc.
- ALD atomic layer deposition
- Al oxide A1203
- a redistribution layer This layer can provide connectivity between Ml and M2 and other connections (e.g., wirebonds, bump bonds, etc.).
- An RDL can be formed by first adding a dielectric such as oxide, etching vias in the dielectric, depositing a conductor (typically Al), and finally patterning the conductor. Additionally, one might add a passivation layer (typically oxide + nitride) to prevent physical scratches, accidental shorting, and/or moisture ingress.
- a first SOI layer typically with a first layer of single crystal silicon, a buried oxide layer, and a single crystal silicon substrate, may be provided.
- the first SOI layer may then be thermally oxidized.
- the cavities may be patterned and etched in the oxide to generate a “handle” wafer. This is typically accomplished through a plasma etch of the oxide or a wet etch (e.g., HF).
- a plasma etch of the oxide or a wet etch (e.g., HF).
- the buried cross-talk trenches may be patterned and etched in the oxide of the “handle” wafer. This is typically accomplished through a plasma etch of the oxide or a wet etch (e.g., HF).
- a “device” wafer comprising a silicon layer and a buried oxide layer, with an additional oxide layer deposited above the silicon layer, may then be fusion bonded to the patterned oxide “handle” wafer.
- the “device” wafer may be patterned and etched (e.g., via DRIE) to correspond to the buried trenches 104 in the “handle” wafer prior to fusion bonding, such that fusion bonding of the “handle” and the “device” wafers forms the buried trenches 104 (e.g., as shown in Fig. 9B).
- the “device” wafer may be ground and polished to the desired diaphragm thickness.
- FIG. 7 illustrates a process 700 for etching cavities and trenches in the “handle” wafer of adouble-SOI substrate.
- the first layer is a 65 pm SOI wafer including a BOX layer of 1 pm.
- the SOI wafer may be between 40 and 80 pm, and the BOX layer may be between 1 and 5 pm.
- the SOI layer has been oxidized.
- Beneath the SOI wafer is a semiconductor substrate, which may be a “handle” wafer 300-700 pm thick.
- a photomask may be used to define the cavity.
- the photomask may define a height and a width of the cavity, or heights and widths of cavities for a MEMS array.
- the cavity may be etched.
- the oxide may be etched, using a wet or a dry etching method.
- the silicon layer of the SOI wafer may be etched using DRIE etching.
- the BOX layer may be again etched using a wet or a dry (e.g., RIE) etching method.
- the silicon substrate may be etched.
- the cavity is etched to a depth of 80 pm +/- 2 pm (65 pm all the way through the first SOI layer and 15 pm into the handle layer).
- the cavity may then be oxidized. Oxidation can keep the cavity shape intact, preserving the ability of the cavity to serve as a waveguide. If the oxide is not applied to the cavity, the cavity may have tapered edges instead of straight edges.
- the first SOI layer may be bonded to a 5 pm SOI wafer (which makes up the second SOI layer).
- the second SOI layer can additionally include an oxide thermally grown or deposited above the silicon layer.
- steps show process 700 in accordance with many embodiments, a person of ordinary skill in the art will recognize many variations based on the teaching described herein.
- the steps may be completed in a different order. Steps may be added or omitted. Some of the steps may comprise sub-steps. Many of the steps and sub-steps may be repeated as often as beneficial.
- the cavity may not be etched into the semiconductor or silicon layer below the top layer of the device. In some embodiments, the cavity may be etched into the top layer. In other embodiments, particularly in embodiments with more than two layers, a cavity may be etched into a layer lower than the layer just below the top layer of the device.
- FIG. 8 illustrates a process 800 for etching cavities and trenches in the “handle” wafer of a double-SOI substrate.
- a trench size This may be performed by using a photomask to determine a location of the trench on the wafer.
- the photomask may be configured to define a particular pattern or configuration of trenches throughout the substrate. For example, the locations on the wafer where transducer elements may be placed may be regularly spaced within the mask, but different configurations of trenches may be placed alongside the spaces designated for the transducer elements.
- operator may etch the oxide layer of the “handle” wafer to define the trench.
- the oxide layer may be dry (e.g., RIE) etched or wet (e.g., hydrofluoric acid (HF)) etched.
- photoresist may be applied to the oxide surface of the wafer, using a spin coating method.
- the photoresist layer may be a polymeric material sensitive to ultraviolet light.
- alternate methods may be used to coat the oxide surface of the wafer, including spraying, roller coating, dip coating, and extrusion coating.
- the photoresist layer may be pattern etched to define a cavity.
- Pattern etching may be performed by exposing the photoresist layer to ultraviolet light through a mask to obtain the desired pattern.
- An infrared aligner may align the mask on the wafer to precisely etch the pattern.
- the cavity may be partially etched, while the trench opening is still protected by the photoresist layer.
- the etching of the cavities and the trenches may be controlled separately.
- an etchant used to etch the cavity may partially etch the trench as well.
- the photoresist may be stripped (e.g., chemically). After the photoresist is stripped, the oxide layer may serve as a hard mask to complete the etching of the trenches and cavities.
- the operator may use oxide as a mask to etch the cavity below the BOX layer, and etch the trench. The operator may then deposit an oxide onto the cavity. Applying an oxide to the cavity enables the cavity to have straight edges, rather than tapered edges, enabling better shaping of an acoustic wave. [0112] In MEMS devices with additional layers, an operator may continue to use below oxide layers as masks to etch deeper cavities and trenches.
- steps show process 800 in accordance with many embodiments, a person of ordinary skill in the art will recognize many variations based on the teaching described herein.
- the steps may be completed in a different order. Steps may be added or omitted. Some of the steps may comprise sub-steps. Many of the steps and sub-steps may be repeated as often as beneficial.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL309826A IL309826A (en) | 2021-06-30 | 2021-06-30 | Micro-machined ultrasound transducers with insulation layer and methods of manufacture |
KR1020247003217A KR20240025678A (en) | 2021-06-30 | 2021-06-30 | Micro-machined ultrasonic transducers with insulating layer and manufacturing methods |
CN202180101283.7A CN117751088A (en) | 2021-06-30 | 2021-06-30 | Micromechanical ultrasonic transducer with insulating layer and method of manufacture |
PCT/US2021/039977 WO2023277914A1 (en) | 2021-06-30 | 2021-06-30 | Micro-machined ultrasound transducers with insulation layer and methods of manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2021/039977 WO2023277914A1 (en) | 2021-06-30 | 2021-06-30 | Micro-machined ultrasound transducers with insulation layer and methods of manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2023277914A1 true WO2023277914A1 (en) | 2023-01-05 |
Family
ID=84690571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2021/039977 WO2023277914A1 (en) | 2021-06-30 | 2021-06-30 | Micro-machined ultrasound transducers with insulation layer and methods of manufacture |
Country Status (4)
Country | Link |
---|---|
KR (1) | KR20240025678A (en) |
CN (1) | CN117751088A (en) |
IL (1) | IL309826A (en) |
WO (1) | WO2023277914A1 (en) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040085858A1 (en) * | 2002-08-08 | 2004-05-06 | Khuri-Yakub Butrus T. | Micromachined ultrasonic transducers and method of fabrication |
US20140220723A1 (en) * | 2012-12-18 | 2014-08-07 | Analog Devices, Inc. | Methods and Structures for Using Diamond in the Production of MEMS |
US9067779B1 (en) * | 2014-07-14 | 2015-06-30 | Butterfly Network, Inc. | Microfabricated ultrasonic transducers and related apparatus and methods |
US20160045935A1 (en) * | 2014-08-18 | 2016-02-18 | Samsung Electronics Co., Ltd. | Capacitive micromachined ultrasonic transducer having nanopillar structure and method of fabricating the same |
US20170232474A1 (en) * | 2015-07-30 | 2017-08-17 | North Carolina State University | Anodically bonded vacuum-sealed capacitive micromachined ultrasonic transducer (cmut) |
US20190316957A1 (en) * | 2018-04-11 | 2019-10-17 | Exo Imaging Inc. | Imaging devices having piezoelectric transceivers |
-
2021
- 2021-06-30 IL IL309826A patent/IL309826A/en unknown
- 2021-06-30 KR KR1020247003217A patent/KR20240025678A/en unknown
- 2021-06-30 CN CN202180101283.7A patent/CN117751088A/en active Pending
- 2021-06-30 WO PCT/US2021/039977 patent/WO2023277914A1/en active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040085858A1 (en) * | 2002-08-08 | 2004-05-06 | Khuri-Yakub Butrus T. | Micromachined ultrasonic transducers and method of fabrication |
US20140220723A1 (en) * | 2012-12-18 | 2014-08-07 | Analog Devices, Inc. | Methods and Structures for Using Diamond in the Production of MEMS |
US9067779B1 (en) * | 2014-07-14 | 2015-06-30 | Butterfly Network, Inc. | Microfabricated ultrasonic transducers and related apparatus and methods |
US20160045935A1 (en) * | 2014-08-18 | 2016-02-18 | Samsung Electronics Co., Ltd. | Capacitive micromachined ultrasonic transducer having nanopillar structure and method of fabricating the same |
US20170232474A1 (en) * | 2015-07-30 | 2017-08-17 | North Carolina State University | Anodically bonded vacuum-sealed capacitive micromachined ultrasonic transducer (cmut) |
US20190316957A1 (en) * | 2018-04-11 | 2019-10-17 | Exo Imaging Inc. | Imaging devices having piezoelectric transceivers |
Also Published As
Publication number | Publication date |
---|---|
IL309826A (en) | 2024-02-01 |
KR20240025678A (en) | 2024-02-27 |
CN117751088A (en) | 2024-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4730162B2 (en) | Ultrasonic transmitting / receiving device, ultrasonic probe, and manufacturing method thereof | |
US7285897B2 (en) | Curved micromachined ultrasonic transducer arrays and related methods of manufacture | |
JP4401958B2 (en) | Micromachined ultrasonic transducer and manufacturing method | |
CN102333485B (en) | Pre-collapsed CMUT with mechanical collapse retention | |
JP7216550B2 (en) | Broadband ultrasonic transducer | |
US20050075572A1 (en) | Focusing micromachined ultrasonic transducer arrays and related methods of manufacture | |
US8858447B2 (en) | Ultrasonic transducer and method of manufacturing the same | |
Wang et al. | Enhancement of the transmission of piezoelectric micromachined ultrasonic transducer with an isolation trench | |
Sadeghpour et al. | Bendable piezoelectric micromachined ultrasound transducer (PMUT) arrays based on silicon-on-insulator (SOI) technology | |
Dausch et al. | 5I-4 Piezoelectric micromachined ultrasound transducer (pMUT) arrays for 3D imaging probes | |
US20220304659A1 (en) | Trenches for the reduction of cross-talk in mut arrays | |
JP6390428B2 (en) | Ultrasonic transducer cell, ultrasonic probe, and control method of ultrasonic transducer cell | |
US20230002213A1 (en) | Micro-machined ultrasound transducers with insulation layer and methods of manufacture | |
Pappalardo et al. | Micromachined ultrasonic transducers | |
Joshi et al. | Fabrication of High-Frequency 2D Flexible pMUT Array | |
WO2023277914A1 (en) | Micro-machined ultrasound transducers with insulation layer and methods of manufacture | |
EP3317026B1 (en) | Ultrasound system and ultrasonic pulse transmission method | |
Baum et al. | An improved design for 2D arrays of capacitive micromachined ultrasound transducers: Modeling, fabrication, and characterization | |
Wang et al. | Fabrication Process and Performance Analysis of AlN based Piezoelectric Micromachined Ultrasonic Transducer with a Suspended Structure | |
CA3154568A1 (en) | Trenches for the reduction of cross-talk in mut arrays | |
Sadeghpour et al. | Klik hier als u tekst wilt invoeren. Bendable Piezoele | |
JP2007274620A (en) | Array probe, array probe device, and method of manufacturing array probe |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21948662 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 309826 Country of ref document: IL |
|
ENP | Entry into the national phase |
Ref document number: 20247003217 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020247003217 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2021948662 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2021948662 Country of ref document: EP Effective date: 20240130 |