WO2023273774A1 - Pd充电电路及pos机 - Google Patents

Pd充电电路及pos机 Download PDF

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Publication number
WO2023273774A1
WO2023273774A1 PCT/CN2022/096349 CN2022096349W WO2023273774A1 WO 2023273774 A1 WO2023273774 A1 WO 2023273774A1 CN 2022096349 W CN2022096349 W CN 2022096349W WO 2023273774 A1 WO2023273774 A1 WO 2023273774A1
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WO
WIPO (PCT)
Prior art keywords
terminal
output
resistor
usb
signal
Prior art date
Application number
PCT/CN2022/096349
Other languages
English (en)
French (fr)
Inventor
周超超
Original Assignee
百富计算机技术（深圳）有限公司
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Publication of WO2023273774A1 publication Critical patent/WO2023273774A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00036—Charger exchanging data with battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/0071—Regulation of charging or discharging current or voltage with a programmable schedule
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters

Definitions

  • the present application belongs to the field of USB charging, and in particular relates to a PD charging circuit and a POS machine.
  • a traditional power delivery protocol (Power Delivery, PD) charging circuit converts multiple Universal Serial Bus (Universal Serial Bus, USB) voltages output by external devices into charging voltages to charge the battery.
  • USB Universal Serial Bus
  • the PD charging circuit has two USB interfaces (the two USB interfaces can transfer two USB voltages output by two external devices respectively) and the battery may be a single battery, a double battery or a four battery, the traditional PD The charging circuit cannot charge.
  • the traditional PD charging circuit cannot meet the charging requirements under the conditions of multi-channel USB voltage supply and charging of batteries with different numbers of cells.
  • the purpose of this application is to provide a PD charging circuit and a Point of Sales (POS) machine, which aims to solve the defect that the traditional PD charging circuit cannot meet the charging demand under the conditions of multi-channel USB voltage supply and charging of batteries with different numbers of cells. .
  • POS Point of Sales
  • the embodiment of this application provides a PD charging circuit, including:
  • the power management circuit is used for connecting with the first device and/or the second device, configured to, when receiving the first USB voltage output by the first device and/or the second USB voltage output by the second device, according to the first A USB voltage and/or the second USB voltage output port identification signal and a power supply voltage; the power supply voltage is used to supply power to each functional circuit;
  • a control circuit connected to the power management circuit, configured to output a first control signal according to the port identification signal;
  • a first switching circuit configured to be connected to the first device and/or the second device, and also connected to the control circuit, configured to forward a first configuration channel interaction signal according to the control signal of the first level enabling the first device to maintain output of the first USB voltage, or forwarding a second configuration channel interaction signal according to the control signal of a second level to enable the second device to maintain output of the second USB voltage;
  • the first configuration channel interaction signal is a half-duplex communication signal between the control circuit and the first device
  • the second configuration channel interaction signal is a communication signal between the control circuit and the second device Half-duplex communication signal between;
  • an energy storage component connected to the control circuit and configured to output a battery status signal
  • the control circuit is further configured to output a second control signal according to the battery status signal
  • the power management circuit is further configured to convert the first USB voltage or the second USB voltage into the power supply voltage and a charging voltage according to the second control signal, and the charging voltage is used for the energy storage components to charge.
  • it also includes:
  • the second switching circuit is connected to the first device and/or the second device, and is also connected to the control circuit, configured to forward the second output of the first device according to the control signal of the first level.
  • a USB data signal or forwarding the second USB data signal output by the second device according to the control signal of the second level;
  • the control circuit is further configured to receive the first USB data signal or the second USB data signal.
  • the second switching circuit includes a first analog switch, a first TVS transistor, a second TVS transistor, a first capacitor, a first resistor, a second resistor, and a third resistor;
  • the first positive data input end of the first analog switch and the first negative data input end of the first analog switch are commonly connected to the first USB data signal input end of the second switching circuit, and the first analog
  • the second positive data input end of the switch and the second negative data input end of the first analog switch are commonly connected to the second USB data signal input end of the second switching circuit, and the positive data input end of the first analog switch
  • the output terminal and the negative data input and output terminal of the first analog switch are commonly connected to the first USB data signal output terminal of the second switching circuit and the second USB data signal output terminal of the second switching circuit, the The selection end of the first analog switch is connected to the first end of the first TVS transistor, the first end of the first capacitor and the first end of the first resistor, and the second end of the first resistor is connected to the first end of the first resistor.
  • the first terminal of the second resistor is commonly connected to the first control signal input terminal of the second switching circuit, the output enabling terminal of the first analog switch is connected to the first terminal of the second TVS transistor and the The first end of the third resistor is connected, the second end of the first TVS tube, the second end of the second TVS tube, the second end of the first capacitor, the second end of the second resistor terminal and the second terminal of the third resistor are commonly connected to the power ground.
  • it also includes:
  • a first USB interface connected to the first device, the power management circuit, the first switching circuit, and the second switching circuit, configured to forward the first USB data signal, the first configuration channel interaction signal as well as the first USB voltage.
  • it also includes:
  • a second USB interface connected to the second device, the power management circuit, the first switching circuit, and the second switching circuit, configured to forward the second USB data signal, the second configuration channel interaction signal as well as the second USB voltage.
  • the first switching circuit includes a second analog switch, a third TVS transistor, a fourth TVS transistor, a second capacitor, a fourth resistor, a fifth resistor, and a sixth resistor;
  • the first positive data input end of the second analog switch and the first negative data input end of the second analog switch are commonly connected to the first configuration channel interaction signal input and output end of the first switching circuit, and the first The second positive data input end of the two analog switches and the second negative data input end of the second analog switch are commonly connected to the second configuration channel interaction signal input and output end of the first switching circuit, and the second analog switch
  • the positive data input and output terminals of the second analog switch and the negative data input and output terminals of the second analog switch are commonly connected to the first configuration channel interaction signal input and output terminals of the first switching circuit and the second configuration channel of the first switching circuit
  • An interactive signal input and output terminal, the selection terminal of the second analog switch U2 is connected to the first terminal of the third TVS transistor, the first terminal of the second capacitor, and the first terminal of the fourth resistor, so The second end of the fourth resistor and the first end of the sixth resistor are commonly connected to the first control signal input end of the first switching circuit, and the output enabling end of the second analog switch is connected to the first
  • the first end of the four TVS tubes is connected to the first end of the fifth resistor, the second end of the third TVS tube, the second end of the fourth TVS tube, and the second end of the second capacitor , the second end of the fifth resistor and the second end of the sixth resistor are commonly connected to the power ground.
  • control circuit includes a microprocessor
  • the first PD configuration channel end of the microprocessor and the second PD configuration channel end of the microprocessor are commonly connected to the first configuration channel interaction signal input and output end of the control circuit and the second PD configuration channel end of the control circuit.
  • Configure channel interaction signal input and output terminals, the peripheral enabling terminal of the microprocessor is connected to the first control signal output terminal of the control circuit, the first serial data terminal of the microprocessor and the microprocessor.
  • the first serial clock terminal of the control circuit is commonly connected to the port identification signal input terminal of the control circuit and the second control signal output terminal of the control circuit, the second serial data terminal of the microprocessor and the microprocessor
  • the second serial clock end of the device is commonly connected to the battery status signal input end of the control circuit, the positive USB data input end of the microprocessor and the negative USB data input end of the microprocessor are commonly connected to the The first USB data signal input terminal of the control circuit and the second USB data signal input terminal of the control circuit.
  • the power management circuit includes a step-down chip, a first inductor, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first regulator transistor , the second Zener tube, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the seventh resistor, the eighth resistor, the ninth resistor, the tenth resistor, the eleventh resistance and the twelfth resistance;
  • the first power supply input end of the step-down chip is connected to the first end of the eleventh resistor
  • the second power input end of the step-down chip is connected to the first end of the twelfth resistor
  • the The second end of the eleventh resistor and the drain of the second field effect transistor are commonly connected to the first USB voltage input end of the power management circuit
  • the second end of the twelfth resistor and the fourth The drains of the field effect transistors are commonly connected to the second USB voltage input terminal of the power management circuit
  • the source of the second field effect transistor is connected to the first end of the eighth resistor, the first end of the seventh capacitor, the positive electrode of the first voltage regulator transistor, and the source of the first field effect transistor
  • the gate of the second field effect transistor is connected to the second end of the eighth resistor, the second end of the seventh capacitor, the negative pole of the first voltage regulator transistor, and the second end of the seventh resistor.
  • the first end is connected to the gate of the first field effect transistor, and the second end of the seventh resistor is connected to the first power drive output end of the step-down chip;
  • the source of the fourth field effect transistor is connected to the first end of the tenth resistor, the first end of the eighth capacitor, the positive electrode of the second voltage regulator transistor, and the source of the third field effect transistor pole connection, the gate of the fourth field effect transistor is connected to the second end of the tenth resistor, the second end of the eighth capacitor, the negative pole of the second voltage regulator transistor, and the second end of the ninth resistor.
  • the first end is connected to the gate of the third field effect transistor, and the second end of the ninth resistor is connected to the second power drive output end of the step-down chip;
  • the drain of the first field effect transistor is connected to the drain of the third field effect transistor, the first end of the ninth capacitor, and the bus power end of the step-down chip;
  • the battery power output end of the step-down chip and the first end of the sixth capacitor are commonly connected to the charging voltage output end of the power management circuit, the system power output end of the step-down chip and the fifth capacitor
  • the first terminal of the step-down chip is commonly connected to the power supply voltage output end of the power management circuit, and the serial data output end of the step-down chip and the serial clock output end of the step-down chip are commonly connected to the output end of the power management circuit.
  • the first soft-start end of the step-down chip is connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the first switch end of the first channel of the step-down chip, the step-down The second switch terminal of the first channel of the pressure chip, the third switch terminal of the first channel of the step-down chip, the fourth switch terminal of the first channel of the step-down chip, the fifth switch terminal of the first channel of the step-down chip
  • the switch terminal is connected to the first terminal of the first inductor
  • the second soft-start terminal of the step-down chip is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the first switch end of the second channel of the step-down chip, the step-down
  • the switch terminal is connected to the second terminal of the first inductor;
  • the second end of the fifth capacitor, the second end of the sixth capacitor and the second end of the ninth capacitor are commonly connected to the power ground.
  • it also includes:
  • a start-up circuit configured to be connected to the first device and/or the second device, and also connected to the control circuit, the first switching circuit and the power management circuit, configured to forward the The first configuration channel interaction signal to enable the first device to output the first USB voltage; and/or when the power supply voltage is not received, forward the second configuration channel interaction signal to enable the second device to output second USB voltage;
  • the startup circuit is further configured to stop forwarding the first configuration channel interaction signal and/or the first configuration channel interaction signal according to the supply voltage.
  • An embodiment of the present application further provides a POS machine, the POS machine including the above PD charging circuit.
  • the embodiment of the present application has the beneficial effect that the first switching circuit forwards the first configuration channel interaction signal or the second configuration channel interaction signal according to the control signal, so that the first device maintains the output of the first USB voltage , or make the second device maintain the output of the second USB voltage, and realize multi-channel USB voltage power supply; and because the control circuit outputs the second control signal according to the battery status signal output by the energy storage component, the power management circuit will output the first USB voltage Or the second USB voltage is converted into a charging voltage; the charging voltage is output according to the state of the battery, and the charging requirements of batteries with different numbers are met; therefore, the charging requirements under the conditions of multi-channel USB voltage supply and charging of batteries with different numbers are met.
  • FIG. 1 is a schematic structural diagram of a PD charging circuit provided by an embodiment of the present application.
  • FIG. 2 is another schematic structural diagram of a PD charging circuit provided by an embodiment of the present application.
  • FIG. 3 is another schematic structural diagram of a PD charging circuit provided by an embodiment of the present application.
  • FIG. 4 is another schematic structural diagram of a PD charging circuit provided by an embodiment of the present application.
  • FIG. 5 is another schematic structural diagram of a PD charging circuit provided by an embodiment of the present application.
  • FIG. 6 is an example circuit schematic diagram of a PD charging circuit provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • FIG. 1 shows a schematic structural diagram of a PD charging circuit provided by a preferred embodiment of the present application. For the convenience of description, only the parts related to this embodiment are shown, and the details are as follows:
  • the above PD charging circuit includes a power management circuit 11 , a control circuit 12 , a first switching circuit 13 and an energy storage component 14 .
  • the power management circuit 11 is configured to be connected to the first device 81 and/or the second device 82, configured to receive the first USB voltage output by the first device 81 and/or the second USB voltage output by the second device 82 , outputting a port identification signal and a power supply voltage according to the first USB voltage and/or the second USB voltage; the power supply voltage is used to supply power to each functional circuit;
  • the control circuit 12 is connected to the power management circuit 11 and is configured to output a first control signal according to the port identification signal;
  • the first switching circuit 13 is used to connect to the first device 81 and/or the second device 82, and is also connected to the control circuit 12, configured to forward the first configuration channel interaction signal according to the control signal of the first level so that the first
  • the device 81 maintains the output of the first USB voltage, or forwards the second configuration channel interaction signal according to the control signal of the second level so that the second device 82 maintains the output of the second USB voltage;
  • the first configuration channel interaction signal is the control circuit 12 A half-duplex communication signal with the first device 81;
  • the second configuration channel interaction signal is a half-duplex communication signal between the control circuit 12 and the second device 82;
  • the energy storage component 14 is connected with the control circuit 12 and configured to output a battery status signal; the energy storage component 14 may be a battery.
  • the control circuit 12 is further configured to output a second control signal according to the battery status signal
  • the power management circuit 11 is further configured to convert the first USB voltage or the second USB voltage into a power supply voltage and a charging voltage according to the second control signal, and the charging voltage is used to charge the energy storage component 14 .
  • the port identification signal can carry the first port information or the second port information;
  • the power management circuit 11 is specifically configured to output the port identification signal carrying the first port signal according to the first USB voltage; output the port identification signal carrying the first port signal according to the second USB voltage; Port identification signal of the second port signal; outputting the port identification signal carrying the first port signal according to the first USB voltage and the second USB voltage.
  • the control circuit 12 is specifically configured to output a control signal of a first level according to the first port information, or output a control signal of a second level according to the second port information.
  • the battery status signal carries battery status information, and the battery status information includes the number of battery cells, battery voltage and battery rated voltage.
  • first device 81 and the second device 82 may be terminal devices, adapters or docking stations respectively.
  • the energy storage component 14 is also configured to output the battery voltage; the power management circuit 11 is also configured to convert the battery voltage into a power supply voltage.
  • the PD charging circuit is powered by the energy storage component 14 .
  • the PD charging circuit further includes a second switching circuit 15 .
  • the second switching circuit 15 is connected to the first device 81 and/or the second device 82, and is also connected to the control circuit 12, configured to forward the first USB data signal output by the first device 81 according to the control signal of the first level, Or forward the second USB data signal output by the second device 82 according to the control signal of the second level.
  • the control circuit 12 is also configured to receive the first USB data signal or the second USB data signal.
  • the signal switching function in the two USB data signal links is realized by the second switching circuit 15 .
  • the PD charging circuit also includes a first USB interface 16 .
  • the first USB interface 16 is connected to the first device 81, the power management circuit 11, the first switching circuit 13 and the second switching circuit 15, configured to forward the first USB data signal, the first configuration channel interaction signal and the first USB voltage .
  • the connection between the PD charging circuit and the external first device 81 is realized.
  • the PD charging circuit also includes a second USB interface 17 .
  • the second USB interface 17 is connected to the second device 82, the power management circuit 11, the first switching circuit 13 and the second switching circuit 15, configured to forward the second USB data signal, the second configuration channel interaction signal and the second USB voltage .
  • the connection between the PD charging circuit and the external second device 82 is realized.
  • the PD charging circuit also includes a startup circuit 18 .
  • the starting circuit 18 is used to connect with the first device 81 and/or the second device 82, and is also connected with the control circuit 12, the first switching circuit 13 and the power management circuit 11, and is configured to forward the first A configuration channel interaction signal to enable the first device 81 to output a first USB voltage; and/or forward a second configuration channel interaction signal to enable the second device 82 to output a second USB voltage when no supply voltage is received;
  • the startup circuit 18 is further configured to stop forwarding the first configuration channel interaction signal and/or the first configuration channel interaction signal according to the supply voltage.
  • the PD charging circuit By starting the circuit 18, the PD charging circuit is powered on. And after power-on, the startup circuit 18 stops working, and the control circuit 12 only communicates with one of the devices for configuration channel interaction signals, which prevents crosstalk caused by multiple configuration channel interaction signals and enhances the stability of the PD charging circuit.
  • FIG. 6 shows an example circuit structure of the PD charging circuit provided by the embodiment of the present application. For the convenience of description, only the parts related to the embodiment of the present application are shown, and the details are as follows:
  • the second switching circuit 15 includes a first analog switch U1, a first transient diode (Transient Voltage Suppressor, TVS) Z1, second TVS transistor Z2, first capacitor C1, first resistor R1, second resistor R2 and third resistor R3.
  • a first analog switch U1 a first transient diode (Transient Voltage Suppressor, TVS) Z1, second TVS transistor Z2, first capacitor C1, first resistor R1, second resistor R2 and third resistor R3.
  • TVS Transient Voltage Suppressor
  • the first positive data input terminal HSD1+ of the first analog switch U1 and the first negative data input terminal HSD1- of the first analog switch U1 are commonly connected to the first USB data signal input terminal of the second switching circuit 15, the first analog switch U1
  • the second positive data input terminal HSD2+ of the first analog switch U1 and the second negative data input terminal HSD2- of the first analog switch U1 are commonly connected to the second USB data signal input terminal of the second switching circuit 15, and the positive data input and output of the first analog switch U1
  • the terminal D+ and the negative data input and output terminal D- of the first analog switch U1 are commonly connected to the first USB data signal output terminal of the second switching circuit 15 and the second USB data signal output terminal of the second switching circuit 15, the first analog
  • the selection terminal SEL of the switch U1 is connected to the first terminal of the first TVS transistor Z1, the first terminal of the first capacitor C1 and the first terminal of the first resistor R1, the second terminal of the first resistor R1 and the second terminal of the second resistor R2
  • the first terminal
  • Realizing the second switching circuit 15 with an analog switch completes the signal switching function in the two USB data signal links, thereby maximizing signal integrity and system reliability and reducing layout space.
  • the first switching circuit 13 includes a second analog switch U2, a third TVS transistor Z3, a fourth TVS transistor Z4, a second capacitor C2, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6.
  • the first positive data input terminal HSD1+ of the second analog switch U2 and the first negative data input terminal HSD1- of the second analog switch U2 are commonly connected to the first configuration channel interaction signal input and output terminals of the first switching circuit 13, and the second analog
  • the second positive data input terminal HSD2+ of the switch U2 and the second negative data input terminal HSD2- of the second analog switch U2 are commonly connected to the second configuration channel interaction signal input and output terminals of the first switching circuit 13, and the second analog switch U2
  • the positive data input and output terminal D+ and the negative data input and output terminal D ⁇ of the second analog switch U2 are commonly connected to the first configuration channel interaction signal input and output terminal of the first switching circuit 13 and the second configuration channel of the first switching circuit 13 to interact Signal input and output terminals
  • the selection terminal SEL of the second analog switch U2 is connected to the first terminal of the third TVS transistor Z3, the first terminal of the second capacitor C2 and the first terminal of the fourth resistor R4, and the first terminal of the fourth resistor R4
  • Realizing the first switching circuit 13 with an analog switch completes the signal switching function in the interactive signal link of the two configuration channels, thereby maximizing signal integrity and system reliability and reducing layout space.
  • the control circuit 12 includes a microprocessor U3.
  • the first PD configuration channel end PD_CC1 of the microprocessor U3 and the second PD configuration channel end PD_CC2 of the microprocessor are jointly connected to the first configuration channel interaction signal input and output end of the control circuit 12 and the second configuration channel interaction of the control circuit 12 Signal input and output terminals, the peripheral enable terminal PERIPHERAL_EN0 of the microprocessor U3 is connected to the first control signal output terminal of the control circuit 12, the first serial data terminal SDA6 of the microprocessor U3 and the first serial data terminal of the microprocessor U3
  • the clock terminal SCL6 is commonly connected to the port identification signal input terminal of the control circuit 12 and the second control signal output terminal of the control circuit 12, the second serial data terminal SDA4 of the microprocessor U3 and the second serial clock of the microprocessor U3
  • the terminal SCL4 is commonly connected to the battery status signal input terminal of the control circuit 12, the positive USB data input terminal USB_DP of the microprocessor U3 and the negative USB data input terminal USB_DM of the microprocessor U3 are commonly
  • the power management circuit 11 includes a step-down chip U4, a first inductor L1, a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a first voltage regulator transistor Z5, The second voltage regulator tube Z6, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12.
  • the first power input terminal VAC1 of the step-down chip U4 is connected to the first end of the eleventh resistor R11
  • the second power input terminal VAC2 of the step-down chip U4 is connected to the first end of the twelfth resistor R12
  • the eleventh resistor The second end of R11 and the drain of the second field effect transistor M2 are connected to the first USB voltage input end of the power management circuit 11, and the second end of the twelfth resistor R12 is connected to the drain of the fourth field effect transistor M4. Connect to the second USB voltage input end of the power management circuit 11 .
  • the source of the second field effect transistor M2 is connected to the first end of the eighth resistor R8, the first end of the seventh capacitor C7, the anode of the first voltage regulator transistor Z5 and the source of the first field effect transistor M1, and the second The gate of the field effect transistor M2 and the second end of the eighth resistor R8, the second end of the seventh capacitor C7, the negative pole of the first voltage regulator transistor Z5, the first end of the seventh resistor R7, and the first field effect transistor M1
  • the gate of the seventh resistor R7 is connected to the gate, and the second end of the seventh resistor R7 is connected to the first power drive output end ACDRV1 of the step-down chip U4.
  • the source of the fourth field effect transistor M4 is connected to the first end of the tenth resistor R10, the first end of the eighth capacitor C8, the anode of the second voltage regulator transistor Z6 and the source of the third field effect transistor M3, and the fourth The gate of the field effect transistor M4, the second end of the tenth resistor R10, the second end of the eighth capacitor C8, the negative pole of the second voltage regulator transistor Z6, the first end of the ninth resistor R9, and the third field effect transistor M3
  • the gate of the ninth resistor R9 is connected to the second end of the ninth resistor R9 and the second power drive output end ACDRV2 of the step-down chip U4.
  • the drain of the first FET M1 is connected to the drain of the third FET M3 , the first terminal of the ninth capacitor C9 and the bus power terminal VBUS of the step-down chip U4 .
  • the battery power output terminal BAT of the step-down chip U4 and the first terminal of the sixth capacitor C6 are jointly connected to the charging voltage output terminal of the power management circuit 11, the system power output terminal SYS of the step-down chip U4 and the first terminal of the fifth capacitor C5 terminals are commonly connected to the power supply voltage output end of the power management circuit 11, the serial data output end SDA of the step-down chip U4 and the serial clock output end SCL of the step-down chip U4 are jointly connected to the port identification signal output end of the power management circuit 11 .
  • the first soft-start terminal BTST1 of the step-down chip U4 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is connected to the first switch terminal SW1_1 of the first channel of the step-down chip U4 and the first end of the step-down chip U4.
  • the first end of the first inductor L1 is connected.
  • the second soft-start terminal BTST2 of the step-down chip U4 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is connected to the first switch end SW2_1 of the second channel of the step-down chip U4 and the first end of the step-down chip U4.
  • the second end of the first inductor L1 is connected.
  • the second terminal of the fifth capacitor C5, the second terminal of the sixth capacitor C6 and the second terminal of the ninth capacitor C9 are commonly connected to the power ground.
  • the first USB voltage and/or the second USB voltage is converted into a power supply voltage and a charging voltage by the step-down chip U2, and the USB voltage is identified to output a port identification signal.
  • the step-down chip U2 identifies the first USB voltage and/or the second USB voltage through the first power input terminal VAC1 and the first power input terminal VAC1, and after identification, outputs a third control signal through the first power drive output terminal ACDRV1 so that The first FET M1 and the second FET M2 conduct and forward the first USB voltage to the bus power terminal VBUS of the step-down chip U4; or output the fourth control signal through the second power supply drive output terminal ACDRV2, so that the first The third FET M3 and the fourth FET M4 are turned on and forward the second USB voltage to the bus power terminal VBUS of the step-down chip U4.
  • the step-down chip U4 converts the first USB voltage or the second USB voltage into a power supply voltage and a charging voltage.
  • the operation of the PD charging circuit can be divided into the following three situations:
  • the PD charging circuit is connected to the first device 81 , and the PD charging circuit is not connected to the second device 82 .
  • the first power supply input terminal VAC1 of the step-down chip U1 receives the first USB voltage output by the first device 81, it outputs a port identification signal and a power supply voltage according to the first USB voltage; the power supply voltage is used to supply power to each functional circuit; wherein , the port identification signal is output from the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 to the first serial data terminal SDA6 of the microprocessor U3 and the first serial data terminal SDA6 of the microprocessor U3 The serial clock terminal SCL6; the power supply voltage is output from the system power supply output terminal SYS of the step-down chip U4.
  • the microprocessor U3 outputs a first control signal of a first level from the peripheral enable terminal PERIPHERAL_EN0 of the microprocessor U3 to the selection terminal SEL of the first analog switch U1 and the selection terminal SEL of the second analog switch U2 according to the port identification signal.
  • the first analog switch U1 forwards the first configuration channel interaction signal according to the control signal of the first level so that the first device 81 maintains the output of the first USB voltage; the energy storage component 14 outputs the battery status signal to the second string of the microprocessor U3
  • the microprocessor U3 outputs the second control signal from the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 to the serial data output terminal of the step-down chip U4 according to the battery status signal SDA and the serial clock output terminal SCL of the step-down chip U4; the step-down chip U4 converts the first USB voltage into a supply voltage and a charging voltage according to the second control signal, and the charging voltage is used to charge the energy storage component 14 .
  • the second analog switch U2 forwards the first USB data signal output by the first device 81 according to the control signal of the first level, and the positive USB data input port USB_DP of the microprocessor U3 and the negative USB data input port USB_DM of the microprocessor U3 receive first USB data signal.
  • the PD charging circuit is not connected to the first device 81 , and the PD charging circuit is connected to the second device 82 .
  • the second power input terminal VAC2 of the step-down chip U1 receives the second USB voltage output by the second device 82, it outputs a port identification signal and a power supply voltage according to the second USB voltage; the power supply voltage is used to supply power to each functional circuit; wherein , the port identification signal is output from the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 to the first serial data terminal SDA6 of the microprocessor U3 and the first serial data terminal SDA6 of the microprocessor U3 The serial clock terminal SCL6; the power supply voltage is output from the system power supply output terminal SYS of the step-down chip U4.
  • the microprocessor U3 outputs the first control signal of the second level from the peripheral enable terminal PERIPHERAL_EN0 of the microprocessor U3 to the selection terminal SEL of the first analog switch U1 and the selection terminal SEL of the second analog switch U2 according to the port identification signal.
  • the first analog switch U1 forwards the second configuration channel interaction signal according to the control signal of the second level so that the second device 82 maintains the output of the second USB voltage;
  • the energy storage component 14 outputs the battery status signal to the second string of the microprocessor U3
  • the microprocessor U3 outputs the second control signal from the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 to the serial data output terminal of the step-down chip U4 according to the battery status signal SDA and the serial clock output terminal SCL of the step-down chip U4; the step-down chip U4 converts the second USB voltage into a power supply voltage and a charging voltage according to the second control signal, and the charging voltage is used to charge the energy storage component 14 .
  • the second analog switch U2 forwards the second USB data signal output by the second device 82 according to the control signal of the second level, and the positive USB data input port USB_DP of the microprocessor U3 and the negative USB data input port USB_DM of the microprocessor U3 receive Second USB data signal.
  • the PD charging circuit is connected to the first device 81 , and the PD charging circuit is connected to the second device 82 .
  • the power supply voltage is used to supply power to each functional circuit; wherein, the port identification signal is from the serial data output terminal SDA of the step-down chip U4 and the step-down chip U4
  • the serial clock output terminal SCL of the microprocessor U3 is output to the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3; the supply voltage is output from the system power supply output terminal SYS of the step-down chip U4.
  • the microprocessor U3 outputs a first control signal of a first level from the peripheral enable terminal PERIPHERAL_EN0 of the microprocessor U3 to the selection terminal SEL of the first analog switch U1 and the selection terminal SEL of the second analog switch U2 according to the port identification signal.
  • the first analog switch U1 forwards the first configuration channel interaction signal according to the control signal of the first level so that the first device 81 maintains the output of the first USB voltage; the energy storage component 14 outputs the battery status signal to the second string of the microprocessor U3
  • the microprocessor U3 outputs the second control signal from the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 to the serial data output terminal of the step-down chip U4 according to the battery status signal SDA and the serial clock output terminal SCL of the step-down chip U4; the step-down chip U4 converts the first USB voltage into a power supply voltage and a charging voltage according to the second control signal, and the charging voltage is used to charge the energy storage component 14 .
  • the second analog switch U2 forwards the first USB data signal output by the first device 81 according to the control signal of the first level, and the positive USB data input port USB_DP of the microprocessor U3 and the negative USB data input port USB_DM of the microprocessor U3 receive first USB data signal.
  • An embodiment of the present application further provides a POS machine, the POS machine including the above PD charging circuit.
  • the power management circuit outputs the port identification signal and the power supply voltage according to the first USB voltage output by the first device and/or the second USB voltage output by the second device; the power supply voltage is used to supply power to each functional circuit; control The circuit outputs the first control signal according to the port identification signal; the first switching circuit forwards the first configuration channel interaction signal according to the control signal of the first level so that the first device maintains the output of the first USB voltage, or according to the control signal of the second level The signal forwards the second configuration channel interaction signal so that the second device maintains the output of the second USB voltage; wherein, the first configuration channel interaction signal is a half-duplex communication signal between the control circuit and the first device; the second configuration channel interaction signal It is a half-duplex communication signal between the control circuit and the second device; the energy storage component outputs a battery status signal; the control circuit outputs a second control signal according to the battery status signal; the power management circuit converts the first USB voltage or The second USB voltage is converted into a power supply voltage and a

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Abstract

一种PD充电电路及POS机，属于USB充电领域，通过电源管理电路根据第一设备输出的第一USB电压和/或第二设备输出的第二USB电压输出端口识别信号和供电电压；控制电路根据端口识别信号输出第一控制信号；第一切换电路根据控制信号转发第一配置通道交互信号以使第一设备维持输出第一USB电压，或转发第二配置通道交互信号以使第二设备维持输出第二USB电压；储能组件输出电池状态信号；控制电路根据电池状态信号输出第二控制信号以使电源管理电路将第一USB电压或第二USB电压转换为供电电压和对储能组件进行充电的充电电压；故满足了在多路USB电压供电和不同节数电池充电的条件下的充电需求。

Description

PD充电电路及POS机 技术领域
本申请属于USB充电领域，尤其涉及一种PD充电电路及POS机。
 背景技术
传统的功率传输协议（Power Delivery，PD）充电电路将外部设备输出的多通用串行总线（Universal Serial Bus，USB）电压转换为充电电压以对电池进行充电。然而， PD充电电路具有两个USB接口（两个USB接口可以分别转接两个外部设备输出的两个USB电压）且电池可能为单节电池、双节电池或四节电池时，传统的PD充电电路无法进行充电。
故传统的PD充电电路在多路USB电压供电和不同节数电池充电的条件下无法满足充电需求。
 技术问题
本申请的目的在于提供一种PD充电电路及销售点（Pointofsales，POS）机，旨在解决传统的PD充电电路在多路USB电压供电和不同节数电池充电的条件下无法满足充电需求的缺陷。
 技术解决方案
本申请实施例提供了一种PD充电电路，包括：
电源管理电路，用于与第一设备和/或第二设备连接，配置为当接收到第一设备输出的第一USB电压和/或第二设备输出的第二USB电压时，根据所述第一USB电压和/或所述第二USB电压输出端口识别信号和供电电压；所述供电电压用于对各个功能电路进行供电；
控制电路，与所述电源管理电路连接，配置为根据所述端口识别信号输出第一控制信号；
第一切换电路，用于与所述第一设备和/或所述第二设备连接，还与所述控制电路连接，配置为根据第一电平的所述控制信号转发第一配置通道交互信号以使所述第一设备维持输出所述第一USB电压，或根据第二电平的所述控制信号转发第二配置通道交互信号以使所述第二设备维持输出所述第二USB电压；其中，所述第一配置通道交互信号为所述控制电路和所述第一设备之间的半双工通信信号；所述第二配置通道交互信号为所述控制电路和所述第二设备之间的半双工通信信号；
储能组件，与所述控制电路连接，配置为输出电池状态信号；
所述控制电路还配置为根据电池状态信号输出第二控制信号；
所述电源管理电路还配置为根据所述第二控制信号将所述第一USB电压或所述第二USB电压转换为所述供电电压和充电电压，所述充电电压用于对所述储能组件进行充电。
在其中一个实施例中，还包括：
第二切换电路，与所述第一设备和/或所述第二设备连接，还与所述控制电路连接，配置为根据第一电平的所述控制信号转发所述第一设备输出的第一USB数据信号，或根据第二电平的所述控制信号转发所述第二设备输出的所述第二USB数据信号；
所述控制电路还配置为接收所述第一USB数据信号或所述第二USB数据信号。
在其中一个实施例中，所述第二切换电路包括第一模拟开关、第一TVS管、第二TVS管、第一电容、第一电阻、第二电阻以及第三电阻；
所述第一模拟开关的第一正极数据输入端和所述第一模拟开关的第一负极数据输入端共同连接至所述第二切换电路的第一USB数据信号输入端，所述第一模拟开关的第二正极数据输入端和所述第一模拟开关的第二负极数据输入端共同连接至所述第二切换电路的第二USB数据信号输入端，所述第一模拟开关的正极数据输入输出端和所述第一模拟开关的负极数据输入输出端共同连接至所述第二切换电路的第一USB数据信号输出端和所述第二切换电路的第二USB数据信号输出端，所述第一模拟开关的选择端与所述第一TVS管的第一端、所述第一电容的第一端以及所述第一电阻的第一端连接，所述第一电阻的第二端和所述第二电阻的第一端共同连接至所述第二切换电路的第一控制信号输入端，所述第一模拟开关的输出使能端与所述第二TVS管的第一端和所述第三电阻的第一端连接，所述第一TVS管的第二端、所述第二TVS管的第二端、所述第一电容的第二端、所述第二电阻的第二端以及所述第三电阻的第二端共接于电源地。
在其中一个实施例中，还包括：
第一USB接口，与所述第一设备、所述电源管理电路、所述第一切换电路以及所述第二切换电路连接，配置为转发所述第一USB数据信号、所述第一配置通道交互信号以及所述第一USB电压。
在其中一个实施例中，还包括：
第二USB接口，与所述第二设备、所述电源管理电路、所述第一切换电路以及所述第二切换电路连接，配置为转发所述第二USB数据信号、所述第二配置通道交互信号以及所述第二USB电压。
在其中一个实施例中，所述第一切换电路包括第二模拟开关、第三TVS管、第四TVS管、第二电容、第四电阻、第五电阻以及第六电阻；
所述第二模拟开关的第一正极数据输入端和所述第二模拟开关的第一负极数据输入端共同连接至所述第一切换电路的第一配置通道交互信号输入输出端，所述第二模拟开关的第二正极数据输入端和所述第二模拟开关的第二负极数据输入端共同连接至所述第一切换电路的第二配置通道交互信号输入输出端，所述第二模拟开关的正极数据输入输出端和所述第二模拟开关的负极数据输入输出端共同连接至所述第一切换电路的第一配置通道交互信号输入输出端和所述第一切换电路的第二配置通道交互信号输入输出端，所述第二模拟开关U2的选择端与所述第三TVS管的第一端、所述第二电容的第一端以及所述第四电阻的第一端连接，所述第四电阻的第二端和所述第六电阻的第一端共同连接至所述第一切换电路的第一控制信号输入端，所述第二模拟开关的输出使能端与所述第四TVS管的第一端和所述第五电阻的第一端连接，所述第三TVS管的第二端、所述第四TVS管的第二端、所述第二电容的第二端、所述第五电阻的第二端以及所述第六电阻的第二端共接于电源地。
在其中一个实施例中，所述控制电路包括微处理器；
所述微处理器的第一PD配置通道端和所述微处理器的第二PD配置通道端共同连接至所述控制电路的第一配置通道交互信号输入输出端和所述控制电路的第二配置通道交互信号输入输出端，所述微处理器的外围使能端连接至所述控制电路的第一控制信号输出端，所述微处理器的第一串行数据端和所述微处理器的第一串行时钟端共同连接至所述控制电路的端口识别信号输入端和所述控制电路的第二控制信号输出端，所述微处理器的第二串行数据端和所述微处理器的第二串行时钟端共同连接至所述控制电路的电池状态信号输入端，所述微处理器的正极USB数据输入端和所述微处理器的负极USB数据输入端共同连接至所述控制电路的第一USB数据信号输输入端和所述控制电路的第二USB数据信号输入端。
在其中一个实施例中，所述电源管理电路包括降压芯片、第一电感、第一场效应管、第二场效应管、第三场效应管、第四场效应管、第一稳压管、第二稳压管、第三电容、第四电容、第五电容、第六电容、第七电容、第八电容、第七电阻、第八电阻、第九电阻、第十电阻、第十一电阻以及第十二电阻；
所述降压芯片的第一电源输入端与所述第十一电阻的第一端连接，所述降压芯片的第二电源输入端与所述第十二电阻的第一端连接，所述第十一电阻的第二端和所述第二场效应管的漏极共同连接至所述电源管理电路的第一USB电压输入端，所述第十二电阻的第二端和所述第四场效应管的漏极共同连接至所述电源管理电路的第二USB电压输入端；
所述第二场效应管的源极与所述第八电阻的第一端、所述第七电容的第一端、所述第一稳压管的正极以及所述第一场效应管的源极连接，所述第二场效应管的栅极与所述第八电阻的第二端、所述第七电容的第二端、所述第一稳压管的负极、所述第七电阻的第一端以及所述第一场效应管的栅极连接，所述第七电阻的第二端与所述降压芯片的第一电源驱动输出端连接；
所述第四场效应管的源极与所述第十电阻的第一端、所述第八电容的第一端、所述第二稳压管的正极以及所述第三场效应管的源极连接，所述第四场效应管的栅极与所述第十电阻的第二端、所述第八电容的第二端、所述第二稳压管的负极、所述第九电阻的第一端以及所述第三场效应管的栅极连接，所述第九电阻的第二端与所述降压芯片的第二电源驱动输出端连接；
所述第一场效应管的漏极与所述第三场效应管的漏极、所述第九电容的第一端以及所述降压芯片的总线电源端连接；
所述降压芯片的电池电源输出端和所述第六电容的第一端共同连接至所述电源管理电路的充电电压输出端，所述降压芯片的系统电源输出端和所述第五电容的第一端共同连接至所述电源管理电路的供电电压输出端，所述降压芯片的串行数据输出端和所述降压芯片的串行时钟输出端共同连接至所述电源管理电路的端口识别信号输出端；
所述降压芯片的第一软启动端与所述第三电容的第一端连接，所述第三电容的第二端与所述降压芯片的第一通道第一开关端、所述降压芯片的第一通道第二开关端、所述降压芯片的第一通道第三开关端、所述降压芯片的第一通道第四开关端、所述降压芯片的第一通道第五开关端以及所述第一电感的第一端连接；
所述降压芯片的第二软启动端与所述第四电容的第一端连接，所述第四电容的第二端与所述降压芯片的第二通道第一开关端、所述降压芯片的第二通道第二开关端、所述降压芯片的第二通道第三开关端、所述降压芯片的第二通道第四开关端、所述降压芯片的第二通道第五开关端以及所述第一电感的第二端连接；
所述第五电容的第二端、所述第六电容的第二端以及所述第九电容的第二端共接于电源地。
在其中一个实施例中，还包括：
启动电路，用于与第一设备和/或第二设备连接，还与所述控制电路、所述第一切换电路以及所述电源管理电路连接，配置为当未接收到供电电压时，转发所述第一配置通道交互信号以使所述第一设备输出第一USB电压；和/或当未接收到所述供电电压时，转发所述第二配置通道交互信号以使所述第二设备输出第二USB电压；
所述启动电路还配置为根据所述供电电压停止转发所述第一配置通道交互信号和/或所述第一配置通道交互信号。
本申请实施例还提供一种POS机，所述POS机包括上述的PD充电电路。
 有益效果
本申请实施例与现有技术相比存在的有益效果是：由于第一切换电路根据控制信号转发第一配置通道交互信号或第二配置通道交互信号，以使第一设备维持输出第一USB电压，或者以使第二设备维持输出第二USB电压，实现了多路USB电压供电；又由于控制电路根据储能组件输出的电池状态信号输出第二控制信号以使电源管理电路将第一USB电压或第二USB电压转换为充电电压；实现了根据电池状态输出充电电压，满足了不同节数电池充电需求；故满足了在多路USB电压供电和不同节数电池充电的条件下的充电需求。
 附图说明
为了更清楚地说明本申请实施例中的技术发明，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的PD充电电路的一种结构示意图；
图2为本申请一实施例提供的PD充电电路的另一种结构示意图；
图3为本申请一实施例提供的PD充电电路的另一种结构示意图；
图4为本申请一实施例提供的PD充电电路的另一种结构示意图；
图5为本申请一实施例提供的PD充电电路的另一种结构示意图；
图6为本申请一实施例提供的PD充电电路的一种示例电路原理图。
 本发明的实施方式
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或者间接在该另一个元件上。当一个元件被称为是“连接于”另一个元件，它可以是直接连接到另一个元件或间接连接至该另一个元件上。
需要理解的是，术语“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
图1示出了本申请较佳实施例提供的PD充电电路的结构示意图，为了便于说明，仅示出了与本实施例相关的部分，详述如下：
上述PD充电电路包括电源管理电路11、控制电路12、第一切换电路13以及储能组件14。
电源管理电路11，用于与第一设备81和/或第二设备82连接，配置为当接收到第一设备81输出的第一USB电压和/或第二设备82输出的第二USB电压时，根据第一USB电压和/或第二USB电压输出端口识别信号和供电电压；供电电压用于对各个功能电路进行供电；
控制电路12，与电源管理电路11连接，配置为根据端口识别信号输出第一控制信号；
第一切换电路13，用于与第一设备81和/或第二设备82连接，还与控制电路12连接，配置为根据第一电平的控制信号转发第一配置通道交互信号以使第一设备81维持输出第一USB电压，或根据第二电平的控制信号转发第二配置通道交互信号以使第二设备82维持输出第二USB电压；其中，第一配置通道交互信号为控制电路12和第一设备81之间的半双工通信信号；第二配置通道交互信号为控制电路12和第二设备82之间的半双工通信信号；
储能组件14，与控制电路12连接，配置为输出电池状态信号；储能组件14可以为电池。
控制电路12还配置为根据电池状态信号输出第二控制信号；
电源管理电路11还配置为根据第二控制信号将第一USB电压或第二USB电压转换为供电电压和充电电压，充电电压用于对储能组件14进行充电。
具体实施中，端口识别信号可以携带第一端口信息或第二端口信息；电源管理电路11具体配置为根据第一USB电压输出携带第一端口信号的端口识别信号；根据第二USB电压输出携带第二端口信号的端口识别信号；根据第一USB电压和第二USB电压输出携带第一端口信号的端口识别信号。
控制电路12具体配置为根据第一端口信息输出第一电平的控制信号，或根据第二端口信息输出第二电平的控制信号。
电池状态信号携带电池状态信息，电池状态信息包括电池节数、电池电压和电池额定电压。
其中，第一设备81和第二设备82可以分别为终端设备、适配器或者扩展坞。
具体实施中，储能组件14还配置为输出电池电压；电源管理电路11还配置为将电池电压转换为供电电压。在没有外接第一设备81和第二设备82时，由储能组件14对PD充电电路进行供电。
如图2所示，PD充电电路还包括第二切换电路15。
第二切换电路15，与第一设备81和/或第二设备82连接，还与控制电路12连接，配置为根据第一电平的控制信号转发第一设备81输出的第一USB数据信号，或根据第二电平的控制信号转发第二设备82输出的第二USB数据信号。
控制电路12还配置为接收第一USB数据信号或第二USB数据信号。
通过第二切换电路15实现了两个USB数据信号链路中的信号切换功能。
如图3所示，PD充电电路还包括第一USB接口16。
第一USB接口16，与第一设备81、电源管理电路11、第一切换电路13以及第二切换电路15连接，配置为转发第一USB数据信号、第一配置通道交互信号以及第一USB电压。
通过第一USB接口16，实现了PD充电电路与外部的第一设备81的连接。
如图4所示，PD充电电路还包括第二USB接口17。
第二USB接口17，与第二设备82、电源管理电路11、第一切换电路13以及第二切换电路15连接，配置为转发第二USB数据信号、第二配置通道交互信号以及第二USB电压。
通过第二USB接口17，实现了PD充电电路与外部的第二设备82的连接。
如图5所示，PD充电电路还包括启动电路18。
启动电路18，用于与第一设备81和/或第二设备82连接，还与控制电路12、第一切换电路13以及电源管理电路11连接，配置为当未接收到供电电压时，转发第一配置通道交互信号以使第一设备81输出第一USB电压；和/或当未接收到供电电压时，转发第二配置通道交互信号以使第二设备82输出第二USB电压；
启动电路18还配置为根据供电电压停止转发第一配置通道交互信号和/或第一配置通道交互信号。
通过启动电路18，实现了PD充电电路的上电。且在上电后使启动电路18停止工作，控制电路12仅与其中一个设备进行配置通道交互信号的通信，防止了多个配置通道交互信号而导致的串扰，增强PD充电电路的稳定性。
图6示出了本申请实施例提供的PD充电电路的一种示例电路结构，为了便于说明，仅示出了与本申请实施例相关的部分，详述如下：
第二切换电路15包括第一模拟开关U1、第一瞬态二极管（Transient Voltage Suppressor，TVS）Z1、第二TVS管Z2、第一电容C1、第一电阻R1、第二电阻R2以及第三电阻R3。
第一模拟开关U1的第一正极数据输入端HSD1+和第一模拟开关U1的第一负极数据输入端HSD1-共同连接至第二切换电路15的第一USB数据信号输入端，第一模拟开关U1的第二正极数据输入端HSD2+和第一模拟开关U1的第二负极数据输入端HSD2-共同连接至第二切换电路15的第二USB数据信号输入端，第一模拟开关U1的正极数据输入输出端D+和第一模拟开关U1的负极数据输入输出端D-共同连接至第二切换电路15的第一USB数据信号输出端和第二切换电路15的第二USB数据信号输出端，第一模拟开关U1的选择端SEL与第一TVS管Z1的第一端、第一电容C1的第一端以及第一电阻R1的第一端连接，第一电阻R1的第二端和第二电阻R2的第一端共同连接至第二切换电路15的第一控制信号输入端，第一模拟开关U1的输出使能端/OE与第二TVS管Z2的第一端和第三电阻R3的第一端连接，第一TVS管Z1的第二端、第二TVS管Z2的第二端、第一电容C1的第二端、第二电阻R2的第二端以及第三电阻R3的第二端共接于电源地。
以模拟开关实现第二切换电路15，完成了两个USB数据信号链路中的信号切换功能，更大限度地提高信号完整性和系统可靠性并减小了布板空间。
第一切换电路13包括第二模拟开关U2、第三TVS管Z3、第四TVS管Z4、第二电容C2、第四电阻R4、第五电阻R5以及第六电阻R6。
第二模拟开关U2的第一正极数据输入端HSD1+和第二模拟开关U2的第一负极数据输入端HSD1-共同连接至第一切换电路13的第一配置通道交互信号输入输出端，第二模拟开关U2的第二正极数据输入端HSD2+和第二模拟开关U2的第二负极数据输入端HSD2-共同连接至第一切换电路13的第二配置通道交互信号输入输出端，第二模拟开关U2的正极数据输入输出端D+和第二模拟开关U2的负极数据输入输出端D-共同连接至第一切换电路13的第一配置通道交互信号输入输出端和第一切换电路13的第二配置通道交互信号输入输出端，第二模拟开关U2的选择端SEL与第三TVS管Z3的第一端、第二电容C2的第一端以及第四电阻R4的第一端连接，第四电阻R4的第二端和第六电阻R6的第一端共同连接至第一切换电路13的第一控制信号输入端，第二模拟开关U2的输出使能端/OE与第四TVS管Z4的第一端和第五电阻R5的第一端连接，第三TVS管Z3的第二端、第四TVS管Z4的第二端、第二电容C2的第二端、第五电阻R5的第二端以及第六电阻R6的第二端共接于电源地。
以模拟开关实现第一切换电路13，完成了两个配置通道交互信号链路中的信号切换功能，更大限度地提高信号完整性和系统可靠性并减小了布板空间。
控制电路12包括微处理器U3。
微处理器U3的第一PD配置通道端PD_CC1和微处理器的第二PD配置通道端PD_CC2共同连接至控制电路12的第一配置通道交互信号输入输出端和控制电路12的第二配置通道交互信号输入输出端，微处理器U3的外围使能端PERIPHERAL_EN0连接至控制电路12的第一控制信号输出端，微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6共同连接至控制电路12的端口识别信号输入端和控制电路12的第二控制信号输出端，微处理器U3的第二串行数据端SDA4和微处理器U3的第二串行时钟端SCL4共同连接至控制电路12的电池状态信号输入端，微处理器U3的正极USB数据输入端USB_DP和微处理器U3的负极USB数据输入端USB_DM共同连接至控制电路12的第一USB数据信号输输入端和控制电路12的第二USB数据信号输入端。
电源管理电路11包括降压芯片U4、第一电感L1、第一场效应管M1、第二场效应管M2、第三场效应管M3、第四场效应管M4、第一稳压管Z5、第二稳压管Z6、第三电容C3、第四电容C4、第五电容C5、第六电容C6、第七电容C7、第八电容C8、第七电阻R7、第八电阻R8、第九电阻R9、第十电阻R10、第十一电阻R11以及第十二电阻R12。
降压芯片U4的第一电源输入端VAC1与第十一电阻R11的第一端连接，降压芯片U4的第二电源输入端VAC2与第十二电阻R12的第一端连接，第十一电阻R11的第二端和第二场效应管M2的漏极共同连接至电源管理电路11的第一USB电压输入端，第十二电阻R12的第二端和第四场效应管M4的漏极共同连接至电源管理电路11的第二USB电压输入端。
第二场效应管M2的源极与第八电阻R8的第一端、第七电容C7的第一端、第一稳压管Z5的正极以及第一场效应管M1的源极连接，第二场效应管M2的栅极与第八电阻R8的第二端、第七电容C7的第二端、第一稳压管Z5的负极、第七电阻R7的第一端以及第一场效应管M1的栅极连接，第七电阻R7的第二端与降压芯片U4的第一电源驱动输出端ACDRV1连接。
第四场效应管M4的源极与第十电阻R10的第一端、第八电容C8的第一端、第二稳压管Z6的正极以及第三场效应管M3的源极连接，第四场效应管M4的栅极与第十电阻R10的第二端、第八电容C8的第二端、第二稳压管Z6的负极、第九电阻R9的第一端以及第三场效应管M3的栅极连接，第九电阻R9的第二端与降压芯片U4的第二电源驱动输出端ACDRV2连接。
第一场效应管M1的漏极与第三场效应管M3的漏极、第九电容C9的第一端以及降压芯片U4的总线电源端VBUS连接。
降压芯片U4的电池电源输出端BAT和第六电容C6的第一端共同连接至电源管理电路11的充电电压输出端，降压芯片U4的系统电源输出端SYS和第五电容C5的第一端共同连接至电源管理电路11的供电电压输出端，降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL共同连接至电源管理电路11的端口识别信号输出端。
降压芯片U4的第一软启动端BTST1与第三电容C3的第一端连接，第三电容C3的第二端与降压芯片U4的第一通道第一开关端SW1_1、降压芯片U4的第一通道第二开关端SW1_2、降压芯片U4的第一通道第三开关端SW1_3、降压芯片U4的第一通道第四开关端SW1_4、降压芯片U4的第一通道第五开关端SW1_5以及第一电感L1的第一端连接。
降压芯片U4的第二软启动端BTST2与第四电容C4的第一端连接，第四电容C4的第二端与降压芯片U4的第二通道第一开关端SW2_1、降压芯片U4的第二通道第二开关端SW2_2、降压芯片U4的第二通道第三开关端SW2_3、降压芯片U4的第二通道第四开关端SW2_4、降压芯片U4的第二通道第五开关端SW2_5以及第一电感L1的第二端连接。
第五电容C5的第二端、第六电容C6的第二端以及第九电容C9的第二端共接于电源地。
通过降压芯片U2将第一USB电压和/或第二USB电压转换为供电电压和充电电压，并识别USB电压以输出端口识别信号。
降压芯片U2通过第一电源输入端VAC1和第一电源输入端VAC1识别第一USB电压和/或第二USB电压，在识别后，通过第一电源驱动输出端ACDRV1输出第三控制信号以使第一场效应管M1和第二场效应管M2导通并转发第一USB电压至降压芯片U4的总线电源端VBUS；或者通过第二电源驱动输出端ACDRV2输出第四控制信号，以使第三场效应管M3和第四场效应管M4导通并转发第二USB电压至降压芯片U4的总线电源端VBUS。降压芯片U4将第一USB电压或第二USB电压转换为供电电压和充电电压。
以下结合工作原理对图6所示的作进一步说明：
作为示例而非限定，PD充电电路工作可以分为以下3种情况：
第一种情况下，PD充电电路与第一设备81连接，且PD充电电路未与第二设备82连接。
降压芯片U1的第一电源输入端VAC1接收到第一设备81输出的第一USB电压时，根据第一USB电压输出端口识别信号和供电电压；供电电压用于对各个功能电路进行供电；其中，端口识别信号从降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL输出至微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6；供电电压从降压芯片U4的系统电源输出端SYS输出。微处理器U3根据端口识别信号从微处理器U3的外围使能端PERIPHERAL_EN0输出第一电平的第一控制信号至第一模拟开关U1的选择端SEL和第二模拟开关U2的选择端SEL。第一模拟开关U1根据第一电平的控制信号转发第一配置通道交互信号以使第一设备81维持输出第一USB电压；储能组件14输出电池状态信号至微处理器U3的第二串行数据端SDA4和微处理器U3的第二串行时钟端SCL4。微处理器U3根据电池状态信号从微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6输出第二控制信号至降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL；降压芯片U4根据第二控制信号将第一USB电压转换为供电电压和充电电压，充电电压用于对储能组件14进行充电。第二模拟开关U2根据第一电平的控制信号转发第一设备81输出的第一USB数据信号，微处理器U3的正极USB数据输入端USB_DP和微处理器U3的负极USB数据输入端USB_DM接收第一USB数据信号。
第二种情况下，PD充电电路未与第一设备81连接，且PD充电电路与第二设备82连接。
降压芯片U1的第二电源输入端VAC2接收到第二设备82输出的第二USB电压时，根据第二USB电压输出端口识别信号和供电电压；供电电压用于对各个功能电路进行供电；其中，端口识别信号从降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL输出至微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6；供电电压从降压芯片U4的系统电源输出端SYS输出。微处理器U3根据端口识别信号从微处理器U3的外围使能端PERIPHERAL_EN0输出第二电平的第一控制信号至第一模拟开关U1的选择端SEL和第二模拟开关U2的选择端SEL。第一模拟开关U1根据第二电平的控制信号转发第二配置通道交互信号以使第二设备82维持输出第二USB电压；储能组件14输出电池状态信号至微处理器U3的第二串行数据端SDA4和微处理器U3的第二串行时钟端SCL4。微处理器U3根据电池状态信号从微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6输出第二控制信号至降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL；降压芯片U4根据第二控制信号将第二USB电压转换为供电电压和充电电压，充电电压用于对储能组件14进行充电。第二模拟开关U2根据第二电平的控制信号转发第二设备82输出的第二USB数据信号，微处理器U3的正极USB数据输入端USB_DP和微处理器U3的负极USB数据输入端USB_DM接收第二USB数据信号。
第三种情况下， PD充电电路与第一设备81连接，且PD充电电路与第二设备82连接。
降压芯片U1的第一电源输入端VAC2接收到第一设备81输出的第一USB电压且降压芯片U1的第二电源输入端VAC2接收到第二设备82输出的第二USB电压时，根据第一USB电压和第二USB电压输出端口识别信号和供电电压；供电电压用于对各个功能电路进行供电；其中，端口识别信号从降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL输出至微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6；供电电压从降压芯片U4的系统电源输出端SYS输出。微处理器U3根据端口识别信号从微处理器U3的外围使能端PERIPHERAL_EN0输出第一电平的第一控制信号至第一模拟开关U1的选择端SEL和第二模拟开关U2的选择端SEL。第一模拟开关U1根据第一电平的控制信号转发第一配置通道交互信号以使第一设备81维持输出第一USB电压；储能组件14输出电池状态信号至微处理器U3的第二串行数据端SDA4和微处理器U3的第二串行时钟端SCL4。微处理器U3根据电池状态信号从微处理器U3的第一串行数据端SDA6和微处理器U3的第一串行时钟端SCL6输出第二控制信号至降压芯片U4的串行数据输出端SDA和降压芯片U4的串行时钟输出端SCL；降压芯片U4根据第二控制信号将第一USB电压转换为供电电压和充电电压，充电电压用于对储能组件14进行充电。第二模拟开关U2根据第一电平的控制信号转发第一设备81输出的第一USB数据信号，微处理器U3的正极USB数据输入端USB_DP和微处理器U3的负极USB数据输入端USB_DM接收第一USB数据信号。
本申请实施例还提供一种POS机，该POS机包括上述的PD充电电路。
本申请实施例通过电源管理电路根据第一设备输出的第一USB电压和/或第二设备输出的第二USB电压输出端口识别信号和供电电压；供电电压用于对各个功能电路进行供电；控制电路根据端口识别信号输出第一控制信号；第一切换电路根据第一电平的控制信号转发第一配置通道交互信号以使第一设备维持输出第一USB电压，或根据第二电平的控制信号转发第二配置通道交互信号以使第二设备维持输出第二USB电压；其中，第一配置通道交互信号为控制电路和第一设备之间的半双工通信信号；第二配置通道交互信号为控制电路和第二设备之间的半双工通信信号；储能组件输出电池状态信号；控制电路根据电池状态信号输出第二控制信号；电源管理电路根据第二控制信号将第一USB电压或第二USB电压转换为供电电压和充电电压，充电电压用于对储能组件进行充电；由于第一切换电路根据控制信号转发第一配置通道交互信号或第二配置通道交互信号，以使第一设备维持输出第一USB电压，或者以使第二设备维持输出第二USB电压，实现了多路USB电压供电；又由于控制电路根据储能组件输出的电池状态信号输出第二控制信号以使电源管理电路将第一USB电压或第二USB电压转换为充电电压；实现了根据电池状态输出充电电压，满足了不同节数电池充电需求；故满足了在多路USB电压供电和不同节数电池充电的条件下的充电需求。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种PD充电电路，其特征在于，包括：
    电源管理电路，用于与第一设备和/或第二设备连接，配置为当接收到第一设备输出的第一USB电压和/或第二设备输出的第二USB电压时，根据所述第一USB电压和/或所述第二USB电压输出端口识别信号和供电电压；所述供电电压用于对各个功能电路进行供电；
    控制电路，与所述电源管理电路连接，配置为根据所述端口识别信号输出第一控制信号；
    第一切换电路，用于与所述第一设备和/或所述第二设备连接，还与所述控制电路连接，配置为根据第一电平的所述控制信号转发第一配置通道交互信号以使所述第一设备维持输出所述第一USB电压，或根据第二电平的所述控制信号转发第二配置通道交互信号以使所述第二设备维持输出所述第二USB电压；其中，所述第一配置通道交互信号为所述控制电路和所述第一设备之间的半双工通信信号；所述第二配置通道交互信号为所述控制电路和所述第二设备之间的半双工通信信号；
    储能组件，与所述控制电路连接，配置为输出电池状态信号；
    所述控制电路还配置为根据电池状态信号输出第二控制信号；
    所述电源管理电路还配置为根据所述第二控制信号将所述第一USB电压或所述第二USB电压转换为所述供电电压和充电电压，所述充电电压用于对所述储能组件进行充电。
  2. 如权利要求1所述的PD充电电路，其特征在于，还包括：
    第二切换电路，与所述第一设备和/或所述第二设备连接，还与所述控制电路连接，配置为根据第一电平的所述控制信号转发所述第一设备输出的第一USB数据信号，或根据第二电平的所述控制信号转发所述第二设备输出的所述第二USB数据信号；
    所述控制电路还配置为接收所述第一USB数据信号或所述第二USB数据信号。
  3. 如权利要求2所述的PD充电电路，其特征在于，所述第二切换电路包括第一模拟开关、第一TVS管、第二TVS管、第一电容、第一电阻、第二电阻以及第三电阻；
    所述第一模拟开关的第一正极数据输入端和所述第一模拟开关的第一负极数据输入端共同连接至所述第二切换电路的第一USB数据信号输入端，所述第一模拟开关的第二正极数据输入端和所述第一模拟开关的第二负极数据输入端共同连接至所述第二切换电路的第二USB数据信号输入端，所述第一模拟开关的正极数据输入输出端和所述第一模拟开关的负极数据输入输出端共同连接至所述第二切换电路的第一USB数据信号输出端和所述第二切换电路的第二USB数据信号输出端，所述第一模拟开关的选择端与所述第一TVS管的第一端、所述第一电容的第一端以及所述第一电阻的第一端连接，所述第一电阻的第二端和所述第二电阻的第一端共同连接至所述第二切换电路的第一控制信号输入端，所述第一模拟开关的输出使能端与所述第二TVS管的第一端和所述第三电阻的第一端连接，所述第一TVS管的第二端、所述第二TVS管的第二端、所述第一电容的第二端、所述第二电阻的第二端以及所述第三电阻的第二端共接于电源地。
  4. 如权利要求2所述的PD充电电路，其特征在于，还包括：
    第一USB接口，与所述第一设备、所述电源管理电路、所述第一切换电路以及所述第二切换电路连接，配置为转发所述第一USB数据信号、所述第一配置通道交互信号以及所述第一USB电压。
  5. 如权利要求2所述的PD充电电路，其特征在于，还包括：
    第二USB接口，与所述第二设备、所述电源管理电路、所述第一切换电路以及所述第二切换电路连接，配置为转发所述第二USB数据信号、所述第二配置通道交互信号以及所述第二USB电压。
  6. 如权利要求1至5任意一项所述的PD充电电路，其特征在于，所述第一切换电路包括第二模拟开关、第三TVS管、第四TVS管、第二电容、第四电阻、第五电阻以及第六电阻；
    所述第二模拟开关的第一正极数据输入端和所述第二模拟开关的第一负极数据输入端共同连接至所述第一切换电路的第一配置通道交互信号输入输出端，所述第二模拟开关的第二正极数据输入端和所述第二模拟开关的第二负极数据输入端共同连接至所述第一切换电路的第二配置通道交互信号输入输出端，所述第二模拟开关的正极数据输入输出端和所述第二模拟开关的负极数据输入输出端共同连接至所述第一切换电路的第一配置通道交互信号输入输出端和所述第一切换电路的第二配置通道交互信号输入输出端，所述第二模拟开关U2的选择端与所述第三TVS管的第一端、所述第二电容的第一端以及所述第四电阻的第一端连接，所述第四电阻的第二端和所述第六电阻的第一端共同连接至所述第一切换电路的第一控制信号输入端，所述第二模拟开关的输出使能端与所述第四TVS管的第一端和所述第五电阻的第一端连接，所述第三TVS管的第二端、所述第四TVS管的第二端、所述第二电容的第二端、所述第五电阻的第二端以及所述第六电阻的第二端共接于电源地。
  7. 如权利要求1至5任意一项所述的PD充电电路，其特征在于，所述控制电路包括微处理器；
    所述微处理器的第一PD配置通道端和所述微处理器的第二PD配置通道端共同连接至所述控制电路的第一配置通道交互信号输入输出端和所述控制电路的第二配置通道交互信号输入输出端，所述微处理器的外围使能端连接至所述控制电路的第一控制信号输出端，所述微处理器的第一串行数据端和所述微处理器的第一串行时钟端共同连接至所述控制电路的端口识别信号输入端和所述控制电路的第二控制信号输出端，所述微处理器的第二串行数据端和所述微处理器的第二串行时钟端共同连接至所述控制电路的电池状态信号输入端，所述微处理器的正极USB数据输入端和所述微处理器的负极USB数据输入端共同连接至所述控制电路的第一USB数据信号输输入端和所述控制电路的第二USB数据信号输入端。
  8. 如权利要求1至5任意一项所述的PD充电电路，其特征在于，所述电源管理电路包括降压芯片、第一电感、第一场效应管、第二场效应管、第三场效应管、第四场效应管、第一稳压管、第二稳压管、第三电容、第四电容、第五电容、第六电容、第七电容、第八电容、第七电阻、第八电阻、第九电阻、第十电阻、第十一电阻以及第十二电阻；
    所述降压芯片的第一电源输入端与所述第十一电阻的第一端连接，所述降压芯片的第二电源输入端与所述第十二电阻的第一端连接，所述第十一电阻的第二端和所述第二场效应管的漏极共同连接至所述电源管理电路的第一USB电压输入端，所述第十二电阻的第二端和所述第四场效应管的漏极共同连接至所述电源管理电路的第二USB电压输入端；
    所述第二场效应管的源极与所述第八电阻的第一端、所述第七电容的第一端、所述第一稳压管的正极以及所述第一场效应管的源极连接，所述第二场效应管的栅极与所述第八电阻的第二端、所述第七电容的第二端、所述第一稳压管的负极、所述第七电阻的第一端以及所述第一场效应管的栅极连接，所述第七电阻的第二端与所述降压芯片的第一电源驱动输出端连接；
    所述第四场效应管的源极与所述第十电阻的第一端、所述第八电容的第一端、所述第二稳压管的正极以及所述第三场效应管的源极连接，所述第四场效应管的栅极与所述第十电阻的第二端、所述第八电容的第二端、所述第二稳压管的负极、所述第九电阻的第一端以及所述第三场效应管的栅极连接，所述第九电阻的第二端与所述降压芯片的第二电源驱动输出端连接；
    所述第一场效应管的漏极与所述第三场效应管的漏极、所述第九电容的第一端以及所述降压芯片的总线电源端连接；
    所述降压芯片的电池电源输出端和所述第六电容的第一端共同连接至所述电源管理电路的充电电压输出端，所述降压芯片的系统电源输出端和所述第五电容的第一端共同连接至所述电源管理电路的供电电压输出端，所述降压芯片的串行数据输出端和所述降压芯片的串行时钟输出端共同连接至所述电源管理电路的端口识别信号输出端；
    所述降压芯片的第一软启动端与所述第三电容的第一端连接，所述第三电容的第二端与所述降压芯片的第一通道第一开关端、所述降压芯片的第一通道第二开关端、所述降压芯片的第一通道第三开关端、所述降压芯片的第一通道第四开关端、所述降压芯片的第一通道第五开关端以及所述第一电感的第一端连接；
    所述降压芯片的第二软启动端与所述第四电容的第一端连接，所述第四电容的第二端与所述降压芯片的第二通道第一开关端、所述降压芯片的第二通道第二开关端、所述降压芯片的第二通道第三开关端、所述降压芯片的第二通道第四开关端、所述降压芯片的第二通道第五开关端以及所述第一电感的第二端连接；
    所述第五电容的第二端、所述第六电容的第二端以及所述第九电容的第二端共接于电源地。
  9. 如权利要求1至5任意一项所述的PD充电电路，其特征在于，还包括：
    启动电路，用于与第一设备和/或第二设备连接，还与所述控制电路、所述第一切换电路以及所述电源管理电路连接，配置为当未接收到供电电压时，转发所述第一配置通道交互信号以使所述第一设备输出第一USB电压；和/或当未接收到所述供电电压时，转发所述第二配置通道交互信号以使所述第二设备输出第二USB电压；
    所述启动电路还配置为根据所述供电电压停止转发所述第一配置通道交互信号和/或所述第一配置通道交互信号。
  10. 一种POS机，其特征在于，所述POS机包括如权利要求1至9任意一项所述的PD充电电路。
PCT/CN2022/096349 2021-06-29 2022-05-31 Pd充电电路及pos机 WO2023273774A1 (zh)

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