WO2023273391A1 - Filtering-coupling integrated circuit, method, and device - Google Patents

Filtering-coupling integrated circuit, method, and device Download PDF

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Publication number
WO2023273391A1
WO2023273391A1 PCT/CN2022/079423 CN2022079423W WO2023273391A1 WO 2023273391 A1 WO2023273391 A1 WO 2023273391A1 CN 2022079423 W CN2022079423 W CN 2022079423W WO 2023273391 A1 WO2023273391 A1 WO 2023273391A1
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Prior art keywords
microstrip line
coupling
line region
filter
terminal
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PCT/CN2022/079423
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French (fr)
Chinese (zh)
Inventor
卢曰海
卢斌斌
宋吉伟
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华为技术有限公司
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Publication of WO2023273391A1 publication Critical patent/WO2023273391A1/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/0138Electrical filters or coupling circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/14Arrangements for reducing ripples from dc input or output

Definitions

  • the present application relates to the field of electronic technology, and in particular to a filter-coupling integration circuit, method, and device.
  • a block diagram of an AP dual-frequency dual-feed system as shown in FIG. 1 usually introduces a digital pre-distortion (Digital pre-distortion, DPD) function in the entire WIFI system.
  • DPD Digital pre-distortion
  • a coupler is added in the link to couple the power output by the power amplifier (power amplifier, PA) to the baseband for pre-distortion processing, so as to offset the distortion caused by the PA operating in the nonlinear region.
  • the PA is located in the front end module (FEM).
  • a filter is usually added at the output end of the PA.
  • the introduction of filters and couplers will increase the area of the single board. On the other hand, it will increase the insertion loss of the link, thereby reducing the output power of the AP and increasing the cost of the entire system.
  • couplers and filters are introduced into the electronic equipment, however, the introduced couplers and filters increase the area of the single board and increase the insertion loss of the electronic equipment.
  • the most commonly used method of combining coupling and filtering is to adopt the coaxial cavity structure as shown in Fig. 4 .
  • the principle of the coaxial cavity structure is that by adjusting the band-pass frequency of the tuning rod cavity, the cavity can be equivalent to an inductance in parallel with a capacitor, thereby forming a resonant stage, realizing the microwave filtering function, and adding a coupling print in the filter Printed circuit board (PCB).
  • PCB Printed circuit board
  • the present application provides a filter-coupling integration circuit, method, and equipment, so as to reduce the single board area of the circuit and reduce the insertion loss of electronic equipment.
  • a filter-coupling circuit is provided, which is used to low-pass filter the first signal input from the input terminal 10 to output the second signal from the output terminal 11, and is also used to filter the first signal Coupled sampling is performed to output a third signal from the coupled terminal 12 .
  • the main signal line of the coupler is moved to the low-pass filtering branch, and the filtering and coupling functions are combined on one device, which reduces the board area and device insertion damage.
  • the filter coupling circuit includes: a first capacitor C2, a first inductor L2, a second capacitor C3, and a second inductor L3, wherein: the first terminal C21 of the first capacitor C2 The ground and the second terminal C22 are respectively connected to the input terminal 10 and the first terminal L21 of the first inductor L2; the first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11.
  • the second end L22 of the first inductance L2 is connected; and the second inductance L3 is coupled to the first inductance L2, and the first end L31 of the second inductance L3 is connected to the coupling end 12, The second end L32 is connected to the load end 13 .
  • one pole of the first capacitor C2 corresponding to the second end C22 is the first microstrip line region C2a, one pole corresponding to the first end C21 is grounded, and the first The microstrip line region C2a is coupled with the ground to form a capacitor.
  • the first microstrip line region C2a is strip-shaped.
  • one pole of the first capacitor C2 corresponding to the second terminal C22 is the second microstrip line region C2d, and one pole corresponding to the first terminal C21 is a third pole connected to the ground.
  • the microstrip line region C2e, the second microstrip line region C2d is coupled with the third microstrip line region C2e to form a capacitor.
  • both the second microstrip line region C2d and the third microstrip line region C2e are elongated.
  • one pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a
  • one pole corresponding to the first end C31 is the ground
  • the fourth The microstrip line region C3a is coupled with the ground to form a capacitor.
  • the fourth microstrip line region C3a is strip-shaped.
  • one pole of the second capacitor C3 corresponding to the second terminal C32 is the fifth microstrip line region C3d, and one pole corresponding to the first terminal C31 is connected to the sixth microstrip line region C3d.
  • the microstrip line region C3e, the fifth microstrip line region C3d is coupled with the sixth microstrip line region C3e to form a capacitor.
  • both the fifth microstrip line region C3d and the sixth microstrip line region C3e are elongated.
  • the first inductance L2 is the seventh microstrip line region L2a
  • the second inductance L3 is the eighth microstrip line region L3a.
  • the seventh microstrip line region L2a is in the shape of a strip, "u” or "v".
  • the seventh microstrip line region L2a can be strip-shaped, "u”-shaped or “v-shaped", so as to meet the needs of the seventh microstrip line region L2a and the eighth microstrip line region L3a. Coupling and/or isolation requirements between.
  • the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be the same as that of the second inductance L2 and the The required coupling degree between the third inductance L3 is positively correlated, and/or, the gap width and/or length between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set as It is positively correlated with the isolation required between the second inductance L2 and the third inductance L3; the distance between the input terminal 10 and the coupling terminal 12 on the eighth microstrip line region L3a is set as It is inversely correlated with the coupling degree required between the second inductance L2 and the third inductance L3, and/or, the input terminal 10 is connected to the load terminal 13 on the eighth microstrip line region L3a The distance therebetween is set to be inversely correlated with the required isolation between the second inductor L2 and the third inductor L3.
  • the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is reasonably set to meet the requirements of the seventh microstrip line region L2a and the eighth microstrip line region L3a Coupling and/or isolation requirements between.
  • the eighth microstrip line region L3a is in the shape of "h", “n”, or “7".
  • the eighth microstrip line area L3a can be in the shape of "h", "n", or "7", so as to meet the needs of the seventh microstrip line area L2a and the eighth microstrip line. Coupling and/or isolation requirements between regions L3a.
  • the first One pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a, one pole corresponding to the first end C31 is the ground, the first microstrip line region C2a and the fourth microstrip line region C3a is located on the first side D1 of the seventh microstrip line region L2a, and the eighth microstrip line region L3a is located on the second side D2 of the seventh microstrip line region L2a; or the eighth microstrip line
  • the region L3a, the first microstrip line region C2a and the fourth microstrip line region C3a are all located on the first side D1 of the seventh microstrip line region L2a.
  • the pole corresponding to the second end C22 of the first capacitor C2 is the second microstrip line region C2d
  • the pole corresponding to the first end C21 is the first pole connected to the ground
  • Three microstrip line areas C2e, one pole of the second capacitor C3 corresponding to the second end C32 is the fifth microstrip line area C3d
  • one pole corresponding to the first end C31 is the sixth microstrip line connected to the ground line region C3e
  • the second microstrip line region C2d, the third microstrip line region C2e, the fifth microstrip line region C3d, and the sixth microstrip line region C3e are located in the seventh microstrip
  • the first side D1 of the line region L2a, the eighth microstrip line region L3a is located at the second side D2 of the seventh microstrip line region L2a; or the second microstrip line region C2d, the third microstrip line region
  • a filter coupling circuit including: a high-pass filter circuit, a filter-coupling integration circuit as described in the first aspect or any implementation of the first aspect; the high-pass filter circuit is used for the The filtering, coupling and unifying circuit provides the high-pass filtered signal, or performs high-pass filtering on the signal output by the filtering, coupling and unifying circuit.
  • the filter coupling circuit further includes: a low-pass filter circuit, an input end of the low-pass filter circuit is connected to the output end 11 of the filter coupling circuit.
  • a filter-coupling method the method is applied to the filter-coupling circuit described in the first aspect or any implementation of the first aspect, and the method includes: The input first signal is low-pass filtered to output the second signal from the output terminal 11 ; and the first signal is coupled and sampled to output the third signal from the coupling terminal 12 .
  • an electronic device including the filter-coupling integration circuit described in the first aspect or any implementation of the first aspect.
  • a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the method described in the third aspect is implemented.
  • a computer program product is provided, which is used to realize the method described in the third aspect when executed on a computing device.
  • Figure 1 is a block diagram of an example AP dual-frequency dual-feed system
  • FIG. 2 is a schematic diagram of a circuit structure in which an existing filter and a coupler are separately arranged;
  • FIG. 3 is a schematic diagram of another existing circuit structure in which a filter and a coupler are separately arranged;
  • FIG. 4 is a schematic structural diagram of the existing coupling-filtering integration realized through the coaxial cavity structure
  • FIG. 5 is a schematic structural diagram of a filter-coupling integration circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a circuit structure of a filter-coupling integration circuit provided by an embodiment of the present application.
  • FIG. 7A is a schematic structural diagram of a filter coupling circuit provided by an embodiment of the present application.
  • FIG. 7B is a schematic structural diagram of another filter coupling circuit provided by the embodiment of the present application.
  • FIG. 8 is a schematic circuit structure diagram of a filter coupling circuit provided in an embodiment of the present application.
  • FIG. 9 is a schematic circuit structure diagram of another filter coupling circuit provided in the embodiment of the present application.
  • FIG. 10 is a schematic circuit structure diagram of a filter coupling circuit provided in an embodiment of the present application.
  • FIG. 11 is a schematic circuit structure diagram of another filter coupling circuit provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of a microstrip line structure of a filter coupling circuit provided in an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a capacitor realized by using a microstrip line
  • FIG. 14 is a schematic diagram of an inductor realized by using a microstrip line
  • FIG. 15 is a schematic diagram of another microstrip line structure of the filter coupling circuit provided by the embodiment of the present application.
  • FIG. 16 is a schematic diagram of another microstrip line structure of the filter coupling circuit provided by the embodiment of the present application.
  • FIG. 17 is a schematic diagram of a simulation result of a filter coupling circuit provided in an embodiment of the present application.
  • FIG. 18 is a schematic flowchart of a coupling filtering method provided by an embodiment of the present application.
  • FIG. 5 it is a schematic structural diagram of a filter-coupling circuit provided by the embodiment of the present application.
  • the circuit 100 is used to low-pass filter the first signal input from the input terminal 10 to output the first signal from the output terminal 11. two signals, and is also used to couple and sample the first signal, so as to output the third signal from the coupling terminal 12 .
  • the first signal may be the signal output by the PA, and the circuit is used to couple the power output by the PA to the baseband for pre-distortion processing, so as to offset the distortion caused by the PA working in the nonlinear region, and to The signal is low-pass filtered to reduce the out-of-band spurs of the PA.
  • FIG. 6 it is a schematic diagram of a circuit structure of a filter coupling integration circuit provided by an embodiment of the present application.
  • the filter coupling integration circuit 100 includes: a first capacitor C2, a first inductor L2, a second capacitor C3 and a first capacitor C3.
  • the first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is respectively connected to the input terminal 10 and the first terminal L21 of the first inductor L2;
  • the first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11 and the second terminal L22 of the first inductor L2;
  • the second inductance L3 is coupled to the first inductance L2 , the first end L31 of the second inductance L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 .
  • the load terminal 13 is generally connected to a matched load, such as a 50 ⁇ resistor.
  • the first capacitor C2, the first inductor L2 and the second capacitor C3 in the circuit 100 are used to low-pass filter the first signal to obtain a second signal, which is passed through the output terminal 11 output the second signal.
  • the first capacitor C2, the first inductor L2 and the second capacitor C3 By changing the values of the first capacitor C2, the first inductor L2 and the second capacitor C3, the high-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of low-pass filtering.
  • the first signal generates alternating magnetic flux through the first inductor L2, so that the second inductor L3 induces a voltage, so that the first inductor L2 and the second inductor L3 realize the coupling function through space or physically, that is, the first inductor in the circuit 100
  • An inductor L2 and a second inductor L3 are used for coupling and sampling the first signal.
  • the degree of isolation and coupling of the filter coupling circuit can be changed by changing the tightness of coupling such as the distance between the first inductor L2 and the second inductor L3.
  • the main signal line of the coupler is moved to the low-pass filter branch, and the filtering and coupling functions are combined on one device, which reduces the area of the single board and reduces the device plug-in. damage.
  • the filter-coupling circuit 100 mentioned above may be a single circuit, or a sub-circuit in a certain circuit.
  • the filter-coupling circuit 100 described above may be a sub-circuit in the filter-coupling circuit described below.
  • the filter coupling circuit may also include more sub-circuits.
  • FIG. 7A it is a schematic structural diagram of a filter coupling circuit provided by an embodiment of the present application.
  • the filter coupling circuit 200 includes the above-mentioned low-pass filter coupling circuit 100 and also includes a high-pass filter circuit 201 .
  • the high-pass filter circuit 201 is respectively connected to the input end 20 of the filter coupling circuit 200 and the input end 10 of the low-pass filter coupling circuit 100 .
  • the high-pass filter circuit 201 is used to provide a high-pass filtered signal for the filter coupling circuit.
  • the high-pass filter circuit 201 is configured to high-pass filter the fourth signal received from the input terminal 20 of the filter coupling circuit 200 to obtain the first signal, which is input to the low-pass filter coupling circuit 100 from the input terminal 10;
  • the low-pass filtering and coupling circuit 100 is used for performing low-pass filtering on the first signal, outputting the second signal through the output terminal 11, and also performing coupling sampling on the first signal, so as to output the sampled first signal from the coupling terminal 12.
  • the coupling terminal 12 can be connected to other circuits.
  • the filter coupling circuit 300 includes a low-pass filter coupling circuit 100 and a high-pass filter circuit 301 .
  • the high-pass filter circuit 301 is respectively connected to the output terminal 11 of the filter coupling circuit 100 and the output terminal 30 of the filter coupling circuit 300 .
  • the high-pass filter circuit 301 performs high-pass filter for the output signal of the filter coupling circuit 100 .
  • the low-pass filter coupling-into-one circuit 100 is used to low-pass filter the first signal input from the input terminal 10 to output the second signal from the output terminal 11 to the high-pass filter circuit 301, and is also used to filter the first signal
  • the signal is coupled and sampled to output a third signal from the coupling end 12;
  • the high-pass filter circuit 301 is used to perform high-pass filtering on the second signal output by the output end 11 of the low-pass filter coupling and integration circuit 100, and pass the output of the filter coupling circuit 300 Terminal 30 outputs the fifth signal.
  • the filtering and coupling functions are combined on one device, which reduces the area of the single board and reduces the device plug-in. damage.
  • the filter coupling circuit as a whole realizes the function of band-pass filtering and also realizes the function of coupling.
  • the filter coupling circuit 800 includes a high-pass filter circuit 201 and a low-pass filter coupling circuit 100 .
  • the high-pass filter circuit 201 is respectively connected to the input end 20 of the filter coupling circuit and the input end 10 of the low-pass filter coupling circuit 100 .
  • the high-pass filter circuit 201 includes a first high-pass filter circuit
  • the first high-pass filter circuit includes a second inductor L1 and a third capacitor C1.
  • the first terminal L11 of the second inductor L1 is connected to the second terminal C12 of the third capacitor C1
  • the second terminal L12 of the second inductor L1 is respectively connected to the input terminal 20 of the filter coupling circuit and the low-pass filter coupling circuit 100
  • the first terminal C11 of the third capacitor C1 is connected to the ground
  • the second terminal C12 of the third capacitor C1 is connected to the first terminal L11 of the second inductor L1.
  • the working principle of the first high-pass filter circuit is: the third signal flows in from the input end 20 of the filter coupling circuit. Utilizing the characteristics of capacitance through AC and inductance against AC, the third inductance L1 and the third capacitor C1 are equivalent to an inductance, and low frequencies are easier to pass through the inductance.
  • the fourth signal is subjected to high-pass filtering to obtain the first signal. By changing the values of the third inductor L1 and the third capacitor C1, the low-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of high-pass filtering.
  • the low-pass filter coupling-in-one circuit 100 includes a first capacitor C2, a first inductor L2, a second capacitor C3, and a second inductor L3, wherein: the first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is respectively connected to the input terminal 10.
  • the first terminal L21 of the first inductor L2 is connected; the first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11 and the second terminal L22 of the first inductor L2; the second inductor L3 is connected to the The first inductor L2 is coupled, the first end L31 of the second inductor L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 .
  • the load terminal 13 is generally connected to a matched load, such as a 50 ⁇ resistor.
  • the working principle of the low-pass filter coupling-in-one circuit 100 is as follows: the first capacitor C2, the first inductance L2 and the second capacitor C3 in the low-pass filter coupling-in-one circuit 100 are used for the A signal is low-pass filtered to obtain a second signal, and the second signal is output through the output terminal 11 .
  • the first capacitor C2, the second capacitor C3, the first inductance L2, and the second inductance L3, the high-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of low-pass filtering.
  • the high-frequency signal (that is, the first signal) generates alternating magnetic flux through the first inductance L2, so that the second inductance L3 induces a voltage, so that the first inductance L2 and the second inductance L3 realize the coupling function through space or physically, That is, the first inductor L2 and the second inductor L3 in the low-pass filter coupling-into-one circuit 100 are used to couple and sample the first signal output by the high-pass filter circuit 201 so as to output the third signal from the coupling terminal 12 .
  • the degree of isolation and coupling of the filter coupling circuit can be changed by changing the tightness of coupling such as the distance between the first inductor L2 and the second inductor L3.
  • the main signal line of the coupler (that is, the second inductor L3) is moved to the filter, and the functions of the filter and the coupler Combined on one device, the size of the entire board is reduced; and the function of the filter and the coupler are combined to reduce the insertion loss on the radio frequency branch; (for example, Figure 2 and Figure 3 include 6 ports P1 to P6, and Figure 8 only includes 4 ports including input terminal 20, output terminal 11, coupling terminal 12 and load terminal 13).
  • the high-pass filter circuit 201 may also include a first high-pass filter circuit connected between the first high-pass filter circuit and the low-pass filter coupling circuit 100, and connected to the first high-pass filter circuit.
  • the filter circuit is connected in parallel with the second high-pass filter circuit.
  • the second high-pass filter circuit includes a fourth inductor L4 and a fourth capacitor C4, the first end L41 of the fourth inductor L4 is connected to the second end C42 of the fourth capacitor C4, and the second end L42 of the fourth inductor L4 is respectively connected to the second end C42 of the fourth capacitor C4.
  • the second terminal L12 of the three inductors L1 is connected to the input terminal 10 of the low-pass filter coupling circuit 100; the first terminal C41 of the fourth capacitor C4 is grounded.
  • the second high-pass filter circuit is used for performing second-order high-pass filter on the third signal.
  • the high-pass filter circuit 201 may also include more parallel-connected high-pass filter circuits, so as to realize higher-order high-pass filter.
  • the filter coupling circuit 900 further includes a low-pass filter circuit 202 .
  • the low-pass filter circuit 202 includes a fifth capacitor C5, a fifth inductor L5 and a sixth capacitor C6. Wherein, the first terminal C51 of the fifth capacitor C5 is grounded, and the second terminal of the fifth capacitor C5 is respectively connected to the output terminal 11 of the low-pass filter coupling-in-one circuit 100 and the first terminal L51 of the fifth inductor L5; the sixth capacitor The first terminal C61 of C6 is grounded, and the second terminal C62 of the sixth capacitor C6 is respectively connected to the second terminal L52 of the fifth inductor L5 and the output terminal 22 of the filter coupling circuit.
  • the low-pass filter circuit is used to perform second-order low-pass filter on the second signal.
  • the filter coupling circuit may also include more low-pass filter circuits connected in series, so as to realize higher-order low-pass filter.
  • the filter coupling circuit may simultaneously have the above-mentioned high-order high-pass filter function and high-order low-pass filter function, or may include one of the high-order high-pass filter function and the high-order low-pass filter function.
  • the filter coupling circuit 1000 includes a low-pass filter coupling circuit 100, and also includes a high-pass filter circuit 301.
  • the high-pass filter circuit 301 is respectively connected to the output end 11 of the low-pass filter coupling circuit 100 and the output end 30 of the filter coupling circuit 1000 .
  • the low-pass filter coupling-into-one circuit 100 includes a first capacitor C2, a first inductor L2, a second capacitor C3, and a second inductor L3, wherein: the first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is connected to the The input end 10 is connected to the first end L21 of the first inductor L2; the first end C31 of the second capacitor C3 is connected to the ground, and the second end C32 is respectively connected to the output end 11 and the second end L22 of the first inductor L2; the second inductor L3 is coupled to the first inductor L2 , the first end L31 of the second inductor L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 .
  • the load terminal 13 is generally connected to a matched load, such as a 50 ⁇ resistor.
  • the working principle of the low-pass filter coupling-in-one circuit 100 is: the first capacitor C2, the first inductance L2, and the second capacitor C3 in the low-pass filter coupling-in-one circuit 100 are used to The first signal is low-pass filtered to obtain a second signal, which is output from the output terminal 11 .
  • the high-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of low-pass filtering.
  • the first signal passes through the first inductance L2 to generate alternating magnetic flux, so that the second inductance L3 induces a voltage, so that the first inductance L2 and the second inductance L3 realize the coupling function through space or physically, that is, low-pass filter coupling
  • the first inductor L2 and the second inductor L3 in a circuit 100 are used to couple and sample the first signal so as to output the third signal from the coupling terminal 12 .
  • the degree of isolation and coupling of the filter coupling circuit can be changed by changing the tightness of coupling such as the distance between the first inductor L2 and the second inductor L3.
  • the high-pass filter circuit 301 includes a first high-pass filter circuit, and the first high-pass filter circuit includes a sixth inductor L6 and a seventh capacitor C7.
  • the first terminal L61 of the sixth inductance L6 is connected to the second terminal C72 of the seventh capacitor, and the second terminal L62 of the sixth inductance L6 is respectively connected to the output terminal 11 of the low-pass filter coupling circuit 100 and the output terminal of the filter coupling circuit. 30 connection; the first terminal C71 of the seventh capacitor is grounded, and the second terminal C72 is connected to the first terminal L61 of the sixth inductor L6.
  • the working principle of the high-pass filter circuit 301 is: using the characteristics of the capacitor passing through the AC and the inductor resisting the AC, the sixth inductance L6 and the seventh capacitor C7 are equivalent to an inductance, and low frequencies are easier to pass through the inductance.
  • the second signal output from the output terminal of the low-pass filtering coupling circuit 100 is subjected to high-pass filtering to obtain a fifth signal, which is output through the output terminal 30 .
  • the sixth inductor L6 and the seventh capacitor C7 By changing the values of the sixth inductor L6 and the seventh capacitor C7, the low-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of high-pass filtering.
  • the main signal line of the coupler (that is, the second inductor L3) is moved to the filter, and the function of the filter and the coupler Combined on one device, the size of the entire board is reduced; and the function of the filter and the coupler are combined to reduce the insertion loss on the radio frequency branch; (for example, Figure 2 and Figure 3 include 6 ports P1 to P6, and Figure 10 only includes 4 ports including input terminal 10, output terminal 30, coupling terminal 12 and load terminal 13).
  • FIG. 11 it is a schematic diagram of a specific circuit structure of another filter coupling circuit provided in the embodiment of the present application.
  • the filter coupling circuit 1100 also includes a low-pass filter circuit 302, and the low-pass filter circuit 302 is connected to the output terminal 11 of the filter coupling circuit 100 .
  • the low-pass filter circuit 302 includes a ninth capacitor C9, an eighth inductor L8 and a tenth capacitor C10.
  • the first terminal C91 of the ninth capacitor C9 is grounded, and the second terminal C92 of the ninth capacitor C9 is respectively connected to the output terminal 11 of the filter coupling circuit 100 and the first terminal L81 of the eighth inductor L8; the tenth capacitor C10
  • the first terminal C101 of the tenth capacitor C10 is connected to the ground, and the second terminal C102 of the tenth capacitor C10 is connected to the second terminal L82 of the eighth inductor L8.
  • the low-pass filter circuit is used to perform second-order low-pass filter on the second signal.
  • the filter coupling circuit may also include more low-pass filter circuits, so as to realize higher-order low-pass filter.
  • the high-pass filtering circuit 301 may further include a second high-pass filtering circuit connected between the first high-pass filtering circuit and the output terminal 30 of the filtering coupling circuit and connected in parallel with the first high-pass filtering circuit.
  • the second high-pass filter circuit includes a seventh inductor L7 and an eighth capacitor C8.
  • the first end L71 of the seventh inductance L7 is connected to the second end C82 of the eighth capacitor C8, and the second end L72 of the seventh inductance L7 is respectively connected to the first end L61 of the sixth inductance L6 and the output end of the filter coupling circuit 30 connection; the first terminal C81 of the eighth capacitor C8 is grounded, and the second terminal C82 of the eighth capacitor C8 is connected to the first terminal L71 of the seventh inductor L7.
  • the second high-pass filter circuit is used to perform a second-order high-pass filter on the fourth signal output by the first high-pass filter circuit to obtain a fifth signal, which is output from the output terminal 30 .
  • the high-pass filter circuit 301 may also include more parallel-connected high-pass filter circuits, so as to realize higher-order high-pass filter.
  • the filter coupling circuit may have the above-mentioned high-order high-pass filter function and high-order low-pass filter function at the same time, or may include one of the high-order high-pass filter function and the high-order low-pass filter function.
  • microstrip lines are a strip line that runs on the surface of the PCB, and uses the discontinuity of the transmission line and its equivalent circuit to realize the construction of capacitive or inductive devices.
  • FIG. 12 a schematic diagram of a corresponding microstrip line structure is shown in FIG. 12 .
  • the filter coupling circuit is set in an AP.
  • This AP works in the 5G frequency band.
  • the inductance value of the third inductor L1 and the capacitance value of the third capacitor C1 in this embodiment are relatively large, and discrete devices can be used (that is, microstrip lines are not used), and L1 and C1 pass through Transmission line connection.
  • the filter coupling circuit shown in FIG. 8 except for the high-pass filter circuit 201 (ie, the third inductor L1 and the third capacitor C1 ), the components in the low-pass filter coupling circuit 100 can all be implemented using microstrip lines.
  • N is a dielectric reference plate (gray part); one surface of N is provided with a metal microstrip line (the part surrounded by the gray part) and/or a metal ground (the part surrounded by the gray part and the gray part). outside the enclosed part).
  • the dielectric reference plate may be a Fr4 (resin material) plate.
  • the dotted-line boxes of different line shapes represent the microstrip line regions corresponding to the first capacitor C2 , the second capacitor C3 , the first inductor L2 , and the second inductor L3 .
  • one pole of the first capacitor C2 corresponding to the second terminal C22 is the first microstrip line region C2a
  • one pole corresponding to the first terminal C21 is ground
  • the first microstrip The stripline region C2a is coupled to ground to form a capacitor.
  • the microstrip line and ground are the two board levels of the capacitor.
  • the first microstrip line region C2a is strip-shaped.
  • one pole of the first capacitor C2 corresponding to the second end C22 is the second microstrip line region C2d
  • one pole corresponding to the first end C21 is the third pole connected to the ground.
  • the microstrip line region C2e, the second microstrip line region C2d and the third microstrip line region C2e are coupled to form a capacitor.
  • the two microstrip lines are the two board levels of the capacitor. Both the second microstrip line region C2d and the third microstrip line region C2e are elongated.
  • one pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a
  • one pole corresponding to the first end C31 is ground
  • the fourth microstrip line Region C3a is coupled to ground to form a capacitor.
  • the microstrip line and ground are the two board levels of the capacitor.
  • the fourth microstrip line region C3a is strip-shaped.
  • one pole of the second capacitor C3 corresponding to the second terminal C32 is the fifth microstrip line region C3d, and one pole corresponding to the first terminal C31 is connected to the sixth microstrip line region C3d.
  • the microstrip line region C3e, the fifth microstrip line region C3d and the sixth microstrip line region C3e are coupled to form a capacitor.
  • the two microstrip lines are the two board levels of the capacitor. Both the fifth microstrip line region C3d and the sixth microstrip line region C3e are elongated.
  • microstrip line regions C2a, C2d, C2e, C3a, C3d or C3e are in the shape of a strip, which may be specifically a rectangle with an aspect ratio greater than a set threshold, or a parallelogram or trapezoid with an aspect ratio greater than a set threshold.
  • the above-mentioned first capacitor C2 can be realized by any one shown in FIG. 13
  • the second capacitor C3 can be realized by any one shown in FIG. 14
  • the above capacitive microstrip line implementations of the first capacitor C2 and the second capacitor C3 can be used in combination. In FIG. 12 , it is described by taking the first microstrip line region C2 a coupled with the ground to form the first capacitor C2 , and the fourth microstrip line region C3 a coupled with the ground to form the second capacitor C3 as an example.
  • the construction of inductive devices can be realized using microstrip line regions of different widths and lengths.
  • the first inductance L2 is the seventh microstrip line region L2a
  • the second inductance L3 is the eighth microstrip line region L3a.
  • the gap width between the seventh microstrip line region L2a and the eighth microstrip line region L3a includes: the first width A1, the second width A2, and the third width A3, the seventh microstrip line region L2a and the eighth microstrip line region
  • the length of the gap between the stripline regions L3a is the length B1.
  • the first microstrip line region C2a and the fourth microstrip line region C3a are located on the first side D1 of the seventh microstrip line region L2a, and the eighth microstrip line region L3a is located on the side of the seventh microstrip line region L2a.
  • Ports 10, 11, 12 and 13 can be connected to the WIFI system through PCB traces or other methods.
  • the coupling degree C of the filter coupling circuit is defined as the logarithm of the ratio of the forward transmission power P3 in the main line coupled to the auxiliary line and the main line incident power P1, and the absolute value of the coupling degree is as follows:
  • S31 in formula (1) is the scattering parameter between the input end 10 and the coupling end 12 .
  • the distance between the input end 10 and the coupling end 12 on the eighth microstrip line area L3a is positively correlated with the scattering parameter between the input end 10 and the coupling end 12, and the distance between the input end 10 and the coupling end 12 The distance between them is inversely correlated with the coupling degree of the filter-coupling circuit.
  • the positive correlation relationship may be a direct proportional relationship
  • the anti-correlation relationship may be an inverse proportional relationship.
  • the smaller S31 is, the greater the coupling degree of the filter coupling circuit is; and the farther the distance between the input terminal 10 and the coupling terminal 12 is , the larger S31 is, the smaller the coupling degree of the filter-coupling circuit is.
  • the first width A1, the second width A2, the third width A3 between the seventh microstrip line region L2a and the eighth microstrip line region L3a, the seventh microstrip line region L2a and the eighth microstrip line region L3a At least one of the lengths B1 is positively correlated with the coupling degree of the filter-coupling circuit.
  • the positive correlation may be a proportional relationship.
  • the way of changing the coupling degree of the filter coupling and unifying circuit is not limited to the above ways.
  • the isolation I of the filter coupling circuit is defined as the decibel ratio of the main line incident power P1 to the output power P4 of the isolated port.
  • the absolute value of the isolation is as follows:
  • S41 in formula (2) is a scattering parameter between the input terminal 10 and the load terminal 13 on the eighth microstrip line region L3a.
  • the distance between the input terminal 10 and the load terminal 13 is positively correlated with the scattering parameter between the input terminal 10 and the load terminal 13, and the distance between the input terminal 10 and the load terminal 13 is inversely related to the isolation of the filter coupling circuit relationship.
  • the positive correlation relationship may be a direct proportional relationship
  • the anti-correlation relationship may be an inverse proportional relationship.
  • the first width A1, the second width A2, the third width A3 of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a, the seventh microstrip line region L2a and the eighth microstrip line region At least one of the lengths B1 of the gaps between the stripline regions L3a is positively correlated with the isolation of the filter-coupling circuit.
  • the positive correlation may be a proportional relationship.
  • the way of changing the isolation of the filtering coupling and combining circuit is not limited to the above ways.
  • the seventh microstrip line area L2a is in the shape of a long strip
  • the eighth microstrip line area L3a is in the shape of "h" which can meet the inductance requirements of the first inductance L2 and the second inductance L3 on the basis of , so that the seventh microstrip line region L2a and the eighth microstrip line region L3a meet the coupling and isolation requirements of the low-pass filter coupling and integration circuit.
  • the eighth microstrip line region L3a may also be in the shape of "n" or "7".
  • the layout and wiring of components can be changed.
  • FIG. 15 another microstrip line structure schematic diagram shown in Figure 15 is different from the microstrip line structure shown in Figure 12 in that the eighth microstrip line region L3a, the first microstrip line region C2a and the The stripline regions C3a are all located on the first side D1 of the seventh microstripline region L2a.
  • the ground between the first microstrip line region C2a and the eighth microstrip line region L3a will increase its isolation so that its coupling can be ignored; and the ground between the fourth microstrip line region C3a and the eighth microstrip line region L3a Grounding between them increases their isolation, making their coupling negligible.
  • the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a has a first width A1 and a second width A2, and the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a The gap between them has a first length B1.
  • the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required coupling degree between the second inductance L2 and the third inductance L3, and/or Or, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required isolation between the second inductor L2 and the third inductor L3.
  • the positive correlation may be a proportional relationship.
  • FIG. 16 another schematic diagram of a microstrip line structure is different from the microstrip line structure shown in FIG. 12 in that the seventh microstrip line region L2a is in the shape of a "v".
  • the two sides of the "v" shape can be stepped or straight with a certain slope, depending on the size of the first inductance L2.
  • the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a has a first width A1 and a second width A2, and the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a The gap between them has a first length B1.
  • the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required coupling degree between the second inductance L2 and the third inductance L3, and/or Or, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required isolation between the second inductor L2 and the third inductor L3.
  • the positive correlation may be a proportional relationship.
  • the seventh microstrip line region L2a can also be in the shape of "u". This application does not list the structure of the seventh microstrip line region L2a one by one. Within the protection scope of this application.
  • Adopting the microstrip line structure to realize the above filter-coupling circuit can reduce the cost of electronic equipment, reduce the size of the filter-coupling circuit, and improve the performance of the filter-coupling circuit.
  • the performance index of the filter-coupling circuit can be characterized by the scatter (S) parameter.
  • the filter-coupling-in-one circuit provided in the embodiment of the present application is simulated using corresponding simulation software, and the S parameters of the filter-coupling-in-one circuit are obtained as shown in FIG. 17 .
  • the abscissa is the frequency, and the unit is gigahertz (GHz); the ordinate is the S parameter value, and the unit is decibel (dB).
  • the return loss S1,1 of port 1 of the device is greater than 17dB in the 5G frequency band (that is, the positions marked by #1, 2, and 3); as shown in the second picture of Figure 17
  • the insertion loss S2,1 of the device is less than 0.62dB in the 5G frequency band (that is, the positions marked by 1, 2, and 3#), and the suppression of the second harmonic of the 5G frequency band is greater than 19dB (that is, the positions marked by 6 and 7# location), the suppression of the 2G frequency band is greater than 38.6dB (that is, the location marked by 4, 5#);
  • the coupling degree is greater than 17.6dB on the 5G frequency , 3# marks); as shown in the fourth picture of Figure 17, the isolation S4,1 is greater than 38.6dB in the 5G frequency band (that is, the positions of 1, 2, 3# marks).
  • the filter-coupling integration circuit designed by the embodiment of the present application has a
  • a filter coupling method is also provided, which is applied to the above-mentioned filter coupling integration circuit shown in FIG. 5 .
  • the method may include the steps of:
  • the first signal may be the signal output by the PA, and the circuit is used to couple the power output by the PA to the baseband for pre-distortion processing, so as to offset the distortion caused by the PA working in the nonlinear region, and to The signal is low-pass filtered to reduce the out-of-band spurs of the PA.
  • the filter coupling method by multiplexing the low-pass filtering branch, the main signal line of the coupler is moved to the low-pass filtering branch, and the filtering and coupling functions are combined on one device, reducing The area of the single board is reduced, and the insertion loss of the device is reduced.
  • the disclosed devices, devices and methods can be implemented in other ways.
  • the division of this unit is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored, or not implement.
  • the mutual coupling, or direct coupling, or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted over a computer-readable storage medium.
  • the computer instructions can be sent from one website site, computer, server, or data center to another via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.)
  • wired such as coaxial cable, optical fiber, digital subscriber line (DSL)
  • wireless such as infrared, wireless, microwave, etc.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the usable medium can be read-only memory (read-only memory, ROM), or random access memory (random access memory, RAM), or magnetic medium, for example, floppy disk, hard disk, magnetic tape, magnetic disk, or optical medium, such as , a digital versatile disc (digital versatile disc, DVD), or a semiconductor medium, for example, a solid state disk (solid state disk, SSD) and the like.
  • read-only memory read-only memory
  • RAM random access memory
  • magnetic medium for example, floppy disk, hard disk, magnetic tape, magnetic disk, or optical medium, such as , a digital versatile disc (digital versatile disc, DVD), or a semiconductor medium, for example, a solid state disk (solid state disk, SSD) and the like.

Abstract

Provided are a filtering-coupling integrated circuit (100), a method, and a device. The filtering-coupling integrated circuit (100) is used to perform low-pass filtering on a first signal inputted from an input end (10) so as to output a second signal from an output end (11), and is also used to perform coupling sampling on the first signal so as to output a third signal from a coupling end (12). By multiplexing a low-pass filtering branch, a main signal line of a coupler is moved to the low-pass filtering branch and filtering and coupling functions are combined on one device, thus reducing the area of a single board and reducing device insertion loss.

Description

滤波耦合合一电路及方法、设备Filter coupling integration circuit, method and device
本申请要求于2021年6月30日提交中国国家知识产权局、申请号202110746880.7、申请名称为“滤波耦合合一电路及方法、设备”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of China on June 30, 2021, with application number 202110746880.7, and the application name is "Filtering and coupling integration circuit and method, device", the entire content of which is incorporated by reference In this application.
技术领域technical field
本申请涉及电子技术领域,尤其涉及一种滤波耦合合一电路及方法、设备。The present application relates to the field of electronic technology, and in particular to a filter-coupling integration circuit, method, and device.
背景技术Background technique
在一些电子设备中,需要同时具备滤波和耦合功能。例如,随着WIFI技术的不断演进,希望接入点(access point,AP)输出更高的功率,提升AP覆盖性能。如图1所示的一种AP双频双馈系统框图,通常会在整个WIFI系统中引入数字预失真(digital pre-distortion,DPD)功能。可选地,链路中会增加耦合器,将功率放大器(power amplifier,PA)输出的功率耦合到基带中进行预失真处理,以抵消PA工作在非线性区带来的失真。其中,PA位于前端模组(front end module,FEM)中。且为了降低PA的带外杂散,使得带外杂散满足空口指标的要求,通常会在PA的输出端增加滤波器。滤波器和耦合器的引入会增加单板的面积,另外一方面会增加链路的插损,从而减小AP的输出功率,同时会使整个系统的成本增加。In some electronic devices, both filtering and coupling functions are required. For example, with the continuous evolution of WIFI technology, it is hoped that the access point (access point, AP) will output higher power to improve the coverage performance of the AP. A block diagram of an AP dual-frequency dual-feed system as shown in FIG. 1 usually introduces a digital pre-distortion (Digital pre-distortion, DPD) function in the entire WIFI system. Optionally, a coupler is added in the link to couple the power output by the power amplifier (power amplifier, PA) to the baseband for pre-distortion processing, so as to offset the distortion caused by the PA operating in the nonlinear region. Wherein, the PA is located in the front end module (FEM). And in order to reduce the out-of-band spurs of the PA so that the out-of-band spurs meet the requirements of the air interface index, a filter is usually added at the output end of the PA. The introduction of filters and couplers will increase the area of the single board. On the other hand, it will increase the insertion loss of the link, thereby reducing the output power of the AP and increasing the cost of the entire system.
如图2和图3所示,在电子设备中引入了耦合器和滤波器,然而,引入的耦合器和滤波器增加了单板的面积,且增加了电子设备的插损。As shown in FIG. 2 and FIG. 3 , couplers and filters are introduced into the electronic equipment, however, the introduced couplers and filters increase the area of the single board and increase the insertion loss of the electronic equipment.
目前最为常用的耦合滤波合一的方法是采用如图4所示的同轴腔体结构。同轴腔体结构的原理是通过调整调谐杆腔体的带通频率,该腔体能够等效成电感并联电容,从而形成一个谐振级,实现微波滤波功能,且在滤波器中加耦合的印制电路板(printed circuit board,PCB)。这种同轴腔体广泛用于基站等高功率场合,但是这种腔体的结构比较大,成本高,且复杂度高,在AP等小功率的场景不适用。At present, the most commonly used method of combining coupling and filtering is to adopt the coaxial cavity structure as shown in Fig. 4 . The principle of the coaxial cavity structure is that by adjusting the band-pass frequency of the tuning rod cavity, the cavity can be equivalent to an inductance in parallel with a capacitor, thereby forming a resonant stage, realizing the microwave filtering function, and adding a coupling print in the filter Printed circuit board (PCB). This kind of coaxial cavity is widely used in high-power applications such as base stations. However, the structure of this cavity is relatively large, the cost is high, and the complexity is high. It is not suitable for low-power scenarios such as APs.
有鉴于此,如何在电子设备中引入滤波和耦合功能后,减少单板面积,降低电子设备的插损,是本申请需要解决的问题。In view of this, how to reduce the area of the single board and the insertion loss of the electronic equipment after introducing filtering and coupling functions into the electronic equipment is a problem to be solved in this application.
发明内容Contents of the invention
本申请提供一种滤波耦合合一电路及方法、设备,以减少电路的单板面积,降低电子设备的插损。The present application provides a filter-coupling integration circuit, method, and equipment, so as to reduce the single board area of the circuit and reduce the insertion loss of electronic equipment.
第一方面,提供了一种滤波耦合合一电路,用于对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号,且还用于对所述第一信号进行耦合采样,以从耦合端12输出第三信号。在该方面中,通过复用低通滤波支路,将耦合器的主信号线移到低通滤波支路上,将滤波和耦合功能合在一个器件上,减少了单板面积,降低了器件插损。In the first aspect, a filter-coupling circuit is provided, which is used to low-pass filter the first signal input from the input terminal 10 to output the second signal from the output terminal 11, and is also used to filter the first signal Coupled sampling is performed to output a third signal from the coupled terminal 12 . In this aspect, by multiplexing the low-pass filtering branch, the main signal line of the coupler is moved to the low-pass filtering branch, and the filtering and coupling functions are combined on one device, which reduces the board area and device insertion damage.
在一种可能的实现中,所述滤波耦合合一电路包括:第一电容C2、第一电感L2、第二 电容C3和第二电感L3,其中:所述第一电容C2的第一端C21接地、第二端C22分别与所述输入端10、所述第一电感L2的第一端L21连接;所述第二电容C3的第一端C31接地、第二端C32分别与所述输出端11、所述第一电感L2的第二端L22连接;以及所述第二电感L3与所述第一电感L2耦合,所述第二电感L3的第一端L31与所述耦合端12连接、第二端L32与负载端13连接。In a possible implementation, the filter coupling circuit includes: a first capacitor C2, a first inductor L2, a second capacitor C3, and a second inductor L3, wherein: the first terminal C21 of the first capacitor C2 The ground and the second terminal C22 are respectively connected to the input terminal 10 and the first terminal L21 of the first inductor L2; the first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11. The second end L22 of the first inductance L2 is connected; and the second inductance L3 is coupled to the first inductance L2, and the first end L31 of the second inductance L3 is connected to the coupling end 12, The second end L32 is connected to the load end 13 .
在又一种可能的实现中,所述第一电容C2与所述第二端C22对应的一极为第一微带线区域C2a、所述第一端C21对应的一极为地,所述第一微带线区域C2a与地耦合形成电容。In yet another possible implementation, one pole of the first capacitor C2 corresponding to the second end C22 is the first microstrip line region C2a, one pole corresponding to the first end C21 is grounded, and the first The microstrip line region C2a is coupled with the ground to form a capacitor.
在又一种可能的实现中,所述第一微带线区域C2a为长条形。In yet another possible implementation, the first microstrip line region C2a is strip-shaped.
在又一种可能的实现中,所述第一电容C2与所述第二端C22对应的一极为第二微带线区域C2d、所述第一端C21对应的一极为与地连通的第三微带线区域C2e,所述第二微带线区域C2d与所述第三微带线区域C2e耦合形成电容。In yet another possible implementation, one pole of the first capacitor C2 corresponding to the second terminal C22 is the second microstrip line region C2d, and one pole corresponding to the first terminal C21 is a third pole connected to the ground. The microstrip line region C2e, the second microstrip line region C2d is coupled with the third microstrip line region C2e to form a capacitor.
在又一种可能的实现中,所述第二微带线区域C2d与所述第三微带线区域C2e均为长条形。In yet another possible implementation, both the second microstrip line region C2d and the third microstrip line region C2e are elongated.
在又一种可能的实现中,所述第二电容C3与所述第二端C32对应的一极为第四微带线区域C3a、所述第一端C31对应的一极为地,所述第四微带线区域C3a与地耦合形成电容。In yet another possible implementation, one pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a, one pole corresponding to the first end C31 is the ground, and the fourth The microstrip line region C3a is coupled with the ground to form a capacitor.
在又一种可能的实现中,所述第四微带线区域C3a为长条形。In yet another possible implementation, the fourth microstrip line region C3a is strip-shaped.
在又一种可能的实现中,所述第二电容C3与所述第二端C32对应的一极为第五微带线区域C3d、所述第一端C31对应的一极为与地连通的第六微带线区域C3e,所述第五微带线区域C3d与所述第六微带线区域C3e耦合形成电容。In yet another possible implementation, one pole of the second capacitor C3 corresponding to the second terminal C32 is the fifth microstrip line region C3d, and one pole corresponding to the first terminal C31 is connected to the sixth microstrip line region C3d. The microstrip line region C3e, the fifth microstrip line region C3d is coupled with the sixth microstrip line region C3e to form a capacitor.
在又一种可能的实现中,所述第五微带线区域C3d与所述第六微带线区域C3e均为长条形。In yet another possible implementation, both the fifth microstrip line region C3d and the sixth microstrip line region C3e are elongated.
在又一种可能的实现中,所述第一电感L2为第七微带线区域L2a,所述第二电感L3为第八微带线区域L3a。In yet another possible implementation, the first inductance L2 is the seventh microstrip line region L2a, and the second inductance L3 is the eighth microstrip line region L3a.
在又一种可能的实现中,所述第七微带线区域L2a为长条形、“u”字形或“v”字形。在该实现中,根据电路布局需要,第七微带线区域L2a可以是长条形、“u”字形或“v”字形,以满足第七微带线区域L2a和第八微带线区域L3a之间的耦合度和/或隔离度需求。In yet another possible implementation, the seventh microstrip line region L2a is in the shape of a strip, "u" or "v". In this implementation, according to the needs of the circuit layout, the seventh microstrip line region L2a can be strip-shaped, "u"-shaped or "v-shaped", so as to meet the needs of the seventh microstrip line region L2a and the eighth microstrip line region L3a. Coupling and/or isolation requirements between.
在又一种可能的实现中,所述第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与所述第二电感L2和所述第三电感L3之间所需要的耦合度成正相关关系,和/或,所述第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与所述第二电感L2和所述第三电感L3之间所需要的隔离度成正相关关系;所述输入端10与第八微带线区域L3a上的耦合端12之间的距离被设置为与所述第二电感L2和所述第三电感L3之间所需要的耦合度成反相关关系,和/或,所述输入端10与所述第八微带线区域L3a上的负载端13之间的距离被设置为与所述第二电感L2和所述第三电感L3之间所需要的隔离度成反相关关系。在该实现中,合理地设置第七微带线区域L2a和第八微带线区域L3a之间的缝隙宽度和/或长度,以满足第七微带线区域L2a和第八微带线区域L3a之间的耦合度和/或隔离度需求。In yet another possible implementation, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be the same as that of the second inductance L2 and the The required coupling degree between the third inductance L3 is positively correlated, and/or, the gap width and/or length between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set as It is positively correlated with the isolation required between the second inductance L2 and the third inductance L3; the distance between the input terminal 10 and the coupling terminal 12 on the eighth microstrip line region L3a is set as It is inversely correlated with the coupling degree required between the second inductance L2 and the third inductance L3, and/or, the input terminal 10 is connected to the load terminal 13 on the eighth microstrip line region L3a The distance therebetween is set to be inversely correlated with the required isolation between the second inductor L2 and the third inductor L3. In this implementation, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is reasonably set to meet the requirements of the seventh microstrip line region L2a and the eighth microstrip line region L3a Coupling and/or isolation requirements between.
在又一种可能的实现中,第八微带线区域L3a为“h”字形、“n”字形、或“7”字形。在该实现中,根据电路布局需要,第八微带线区域L3a可以为“h”字形、“n”字形、或“7”字形,以满 足第七微带线区域L2a和第八微带线区域L3a之间的耦合度和/或隔离度需求。In yet another possible implementation, the eighth microstrip line region L3a is in the shape of "h", "n", or "7". In this implementation, according to the needs of circuit layout, the eighth microstrip line area L3a can be in the shape of "h", "n", or "7", so as to meet the needs of the seventh microstrip line area L2a and the eighth microstrip line. Coupling and/or isolation requirements between regions L3a.
在又一种可能的实现中,当所述第一电容C2与所述第二端C22对应的一极为第一微带线区域C2a、所述第一端C21对应的一极为地,所述第二电容C3与所述第二端C32对应的一极为第四微带线区域C3a、所述第一端C31对应的一极为地,所述第一微带线区域C2a和第四微带线区域C3a位于所述第七微带线区域L2a的第一侧D1,所述第八微带线区域L3a位于所述第七微带线区域L2a的第二侧D2;或所述第八微带线区域L3a、所述第一微带线区域C2a和第四微带线区域C3a均位于所述第七微带线区域L2a的第一侧D1。In yet another possible implementation, when one pole of the first capacitor C2 corresponding to the second terminal C22 is the first microstrip line region C2a, and one pole corresponding to the first terminal C21 is grounded, the first One pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a, one pole corresponding to the first end C31 is the ground, the first microstrip line region C2a and the fourth microstrip line region C3a is located on the first side D1 of the seventh microstrip line region L2a, and the eighth microstrip line region L3a is located on the second side D2 of the seventh microstrip line region L2a; or the eighth microstrip line The region L3a, the first microstrip line region C2a and the fourth microstrip line region C3a are all located on the first side D1 of the seventh microstrip line region L2a.
在又一种可能的实现中,当所述第一电容C2与所述第二端C22对应的一极为第二微带线区域C2d、所述第一端C21对应的一极为与地连通的第三微带线区域C2e,所述第二电容C3与所述第二端C32对应的一极为第五微带线区域C3d、所述第一端C31对应的一极为与地连通的第六微带线区域C3e,所述第二微带线区域C2d、所述第三微带线区域C2e、所述第五微带线区域C3d、所述第六微带线区域C3e位于所述第七微带线区域L2a的第一侧D1,所述第八微带线区域L3a位于所述第七微带线区域L2a的第二侧D2;或所述第二微带线区域C2d、所述第三微带线区域C2e、所述第五微带线区域C3d、所述第六微带线区域C3e和所述第八微带线区域L3a均位于所述第七微带线区域L2a的第一侧D1。In yet another possible implementation, when the pole corresponding to the second end C22 of the first capacitor C2 is the second microstrip line region C2d, and the pole corresponding to the first end C21 is the first pole connected to the ground, Three microstrip line areas C2e, one pole of the second capacitor C3 corresponding to the second end C32 is the fifth microstrip line area C3d, and one pole corresponding to the first end C31 is the sixth microstrip line connected to the ground line region C3e, the second microstrip line region C2d, the third microstrip line region C2e, the fifth microstrip line region C3d, and the sixth microstrip line region C3e are located in the seventh microstrip The first side D1 of the line region L2a, the eighth microstrip line region L3a is located at the second side D2 of the seventh microstrip line region L2a; or the second microstrip line region C2d, the third microstrip line region The strip line region C2e, the fifth microstrip line region C3d, the sixth microstrip line region C3e and the eighth microstrip line region L3a are all located on the first side D1 of the seventh microstrip line region L2a .
第二方面,提供了一种滤波耦合电路,包括:高通滤波电路、如第一方面或第一方面的任一实现所述的滤波耦合合一电路;所述高通滤波电路,用于为所述滤波耦合合一电路提供高通滤波后的信号,或者为所述滤波耦合合一电路输出的信号进行高通滤波。In the second aspect, a filter coupling circuit is provided, including: a high-pass filter circuit, a filter-coupling integration circuit as described in the first aspect or any implementation of the first aspect; the high-pass filter circuit is used for the The filtering, coupling and unifying circuit provides the high-pass filtered signal, or performs high-pass filtering on the signal output by the filtering, coupling and unifying circuit.
在一种可能的实现中,所述滤波耦合电路还包括:低通滤波电路,所述低通滤波电路的输入端与所述滤波耦合合一电路的输出端11相连。In a possible implementation, the filter coupling circuit further includes: a low-pass filter circuit, an input end of the low-pass filter circuit is connected to the output end 11 of the filter coupling circuit.
在又一种可能的实现中,所述高通滤波电路为N阶高通滤波电路,N>=2。In yet another possible implementation, the high-pass filter circuit is an N-order high-pass filter circuit, where N>=2.
第三方面,提供了一种滤波耦合合一方法,所述方法应用于如第一方面或第一方面的任一实现所述的滤波耦合合一电路,所述方法包括:对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号;以及对所述第一信号进行耦合采样,以从耦合端12输出第三信号。In the third aspect, there is provided a filter-coupling method, the method is applied to the filter-coupling circuit described in the first aspect or any implementation of the first aspect, and the method includes: The input first signal is low-pass filtered to output the second signal from the output terminal 11 ; and the first signal is coupled and sampled to output the third signal from the coupling terminal 12 .
第四方面,提供了一种电子设备,包括如第一方面或第一方面的任一实现所述的滤波耦合合一电路。In a fourth aspect, an electronic device is provided, including the filter-coupling integration circuit described in the first aspect or any implementation of the first aspect.
第五方面,提供了一种计算机可读存储介质,其上存储有计算机程序,该程序被处理器执行时实现第三方面所述的方法。In a fifth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method described in the third aspect is implemented.
第六方面,提供了一种计算机程序产品,用于当在计算设备上执行时,实现第三方面所述的方法。In a sixth aspect, a computer program product is provided, which is used to realize the method described in the third aspect when executed on a computing device.
附图说明Description of drawings
图1为示例的AP双频双馈系统框图;Figure 1 is a block diagram of an example AP dual-frequency dual-feed system;
图2为现有的一种滤波器和耦合器分开设置的电路结构示意图;FIG. 2 is a schematic diagram of a circuit structure in which an existing filter and a coupler are separately arranged;
图3为现有的另一种滤波器和耦合器分开设置的电路结构示意图;FIG. 3 is a schematic diagram of another existing circuit structure in which a filter and a coupler are separately arranged;
图4为现有的通过同轴腔体结构实现的耦合滤波合一的结构示意图;FIG. 4 is a schematic structural diagram of the existing coupling-filtering integration realized through the coaxial cavity structure;
图5为本申请实施例提供的一种滤波耦合合一电路的结构示意图;FIG. 5 is a schematic structural diagram of a filter-coupling integration circuit provided by an embodiment of the present application;
图6为本申请实施例提供的一种滤波耦合合一电路的电路结构示意图;FIG. 6 is a schematic diagram of a circuit structure of a filter-coupling integration circuit provided by an embodiment of the present application;
图7A为本申请实施例提供的一种滤波耦合电路的结构示意图;FIG. 7A is a schematic structural diagram of a filter coupling circuit provided by an embodiment of the present application;
图7B为本申请实施例提供的另一种滤波耦合电路的结构示意图;FIG. 7B is a schematic structural diagram of another filter coupling circuit provided by the embodiment of the present application;
图8为本申请实施例提供的一种滤波耦合电路的电路结构示意图;FIG. 8 is a schematic circuit structure diagram of a filter coupling circuit provided in an embodiment of the present application;
图9为本申请实施例提供的另一种滤波耦合电路的电路结构示意图;FIG. 9 is a schematic circuit structure diagram of another filter coupling circuit provided in the embodiment of the present application;
图10为本申请实施例提供的一种滤波耦合电路的电路结构示意图;FIG. 10 is a schematic circuit structure diagram of a filter coupling circuit provided in an embodiment of the present application;
图11为本申请实施例提供的又一种滤波耦合电路的电路结构示意图;FIG. 11 is a schematic circuit structure diagram of another filter coupling circuit provided by the embodiment of the present application;
图12为本申请实施例提供的滤波耦合电路的一种微带线结构示意图;FIG. 12 is a schematic diagram of a microstrip line structure of a filter coupling circuit provided in an embodiment of the present application;
图13为采用微带线实现的电容的示意图;FIG. 13 is a schematic diagram of a capacitor realized by using a microstrip line;
图14为采用微带线实现的电感的示意图;FIG. 14 is a schematic diagram of an inductor realized by using a microstrip line;
图15为本申请实施例提供的滤波耦合电路的另一种微带线结构示意图;FIG. 15 is a schematic diagram of another microstrip line structure of the filter coupling circuit provided by the embodiment of the present application;
图16为本申请实施例提供的滤波耦合电路的又一种微带线结构示意图;FIG. 16 is a schematic diagram of another microstrip line structure of the filter coupling circuit provided by the embodiment of the present application;
图17为本申请实施例提供的滤波耦合电路的仿真结果示意图;FIG. 17 is a schematic diagram of a simulation result of a filter coupling circuit provided in an embodiment of the present application;
图18为本申请实施例提供的一种耦合滤波方法的流程示意图。FIG. 18 is a schematic flowchart of a coupling filtering method provided by an embodiment of the present application.
具体实施方式detailed description
下面结合本申请实施例中的附图对本申请实施例进行描述。Embodiments of the present application are described below with reference to the drawings in the embodiments of the present application.
在以下描述中,为了提供对本申请的透彻理解阐述了大量特定细节。然而,对于本领域普通技术人员显而易见的是:不必采用这些特定细节来实行本发明。在其他实例中,为了避免混淆本申请,未具体描述公知的结构、电路、材料或方法。In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application. It will be apparent, however, to one of ordinary skill in the art that these specific details need not be employed to practice the present invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail in order to avoid obscuring the application.
在整个说明书中,对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着:结合该实施例或示例描述的特定特征、结构或特性被包含在本申请至少一个实施例中。因此,在整个说明书的各个地方出现的短语“一个实施例”、“实施例”、“一个示例”或“示例”不一定都指同一实施例或示例。此外,可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外,本领域普通技术人员应当理解,在此提供的示图都是为了说明的目的,并且示图不一定是按比例绘制的。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。Throughout this specification, reference to "one embodiment," "an embodiment," "an example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in the present application. In at least one embodiment. Thus, appearances of the phrases "one embodiment," "an embodiment," "an example," or "example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, particular features, structures or characteristics may be combined in any suitable combination and/or subcombination in one or more embodiments or examples. Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
在本申请的描述中,需要理解的是,术语“前”、“后”、“左”、“右”、“上”、“下”、“竖直”、“水平”、“高”、“低”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请保护范围的限制。In the description of this application, it is to be understood that the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", The orientation or positional relationship indicated by "low", "inner", "outer" and so on is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, rather than indicating or implying the referred device Or elements must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the scope of protection of the present application.
实施例Example
如图5所示,为本申请实施例提供的一种滤波耦合合一电路的结构示意图,该电路100用于对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号,且还用于对第一信号进行耦合采样,以从耦合端12输出第三信号。As shown in FIG. 5 , it is a schematic structural diagram of a filter-coupling circuit provided by the embodiment of the present application. The circuit 100 is used to low-pass filter the first signal input from the input terminal 10 to output the first signal from the output terminal 11. two signals, and is also used to couple and sample the first signal, so as to output the third signal from the coupling terminal 12 .
例如,该第一信号可以是PA输出的信号,该电路用于对PA输出的功率耦合到基带中进行预失真处理,以抵消PA工作在非线性区带来的失真,还用于对PA输出的信号进行低通滤 波,降低PA的带外杂散。For example, the first signal may be the signal output by the PA, and the circuit is used to couple the power output by the PA to the baseband for pre-distortion processing, so as to offset the distortion caused by the PA working in the nonlinear region, and to The signal is low-pass filtered to reduce the out-of-band spurs of the PA.
如图6所示,为本申请实施例提供的一种滤波耦合合一电路的电路结构示意图,该滤波耦合合一电路100包括:第一电容C2、第一电感L2、第二电容C3和第二电感L3,其中:As shown in FIG. 6 , it is a schematic diagram of a circuit structure of a filter coupling integration circuit provided by an embodiment of the present application. The filter coupling integration circuit 100 includes: a first capacitor C2, a first inductor L2, a second capacitor C3 and a first capacitor C3. Two inductors L3, where:
第一电容C2的第一端C21接地、第二端C22分别与输入端10、第一电感L2的第一端L21连接;The first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is respectively connected to the input terminal 10 and the first terminal L21 of the first inductor L2;
第二电容C3的第一端C31接地、第二端C32分别与输出端11、第一电感L2的第二端L22连接;The first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11 and the second terminal L22 of the first inductor L2;
第二电感L3与第一电感L2耦合,第二电感L3的第一端L31与耦合端12连接、第二端L32与负载端13连接。其中,负载端13一般接匹配的负载,例如50Ω电阻。The second inductance L3 is coupled to the first inductance L2 , the first end L31 of the second inductance L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 . Wherein, the load terminal 13 is generally connected to a matched load, such as a 50Ω resistor.
利用高频更容易通过电容的特性,该电路100中的第一电容C2、第一电感L2和第二电容C3用于对第一信号进行低通滤波,得到第二信号,并通过输出端11输出第二信号。通过改变第一电容C2、第一电感L2和第二电容C3的值可以抑制PA带外杂散的高频部分,从而实现低通滤波的功能。Utilizing the characteristic that high frequencies are easier to pass through capacitors, the first capacitor C2, the first inductor L2 and the second capacitor C3 in the circuit 100 are used to low-pass filter the first signal to obtain a second signal, which is passed through the output terminal 11 output the second signal. By changing the values of the first capacitor C2, the first inductor L2 and the second capacitor C3, the high-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of low-pass filtering.
第一信号通过第一电感L2产生交变的磁通,使得第二电感L3感应出电压,从而第一电感L2和第二电感L3通过空间或者物理上实现耦合的功能,即电路100中的第一电感L2和第二电感L3用于对第一信号进行耦合采样。通过改变第一电感L2和第二电感L3之间的距离等耦合紧密程度可以改变滤波耦合电路的隔离度和耦合度。The first signal generates alternating magnetic flux through the first inductor L2, so that the second inductor L3 induces a voltage, so that the first inductor L2 and the second inductor L3 realize the coupling function through space or physically, that is, the first inductor in the circuit 100 An inductor L2 and a second inductor L3 are used for coupling and sampling the first signal. The degree of isolation and coupling of the filter coupling circuit can be changed by changing the tightness of coupling such as the distance between the first inductor L2 and the second inductor L3.
本实施例中,通过复用低通滤波支路,将耦合器的主信号线移到低通滤波支路上,将滤波和耦合功能合在一个器件上,减少了单板面积,降低了器件插损。In this embodiment, by multiplexing the low-pass filter branch, the main signal line of the coupler is moved to the low-pass filter branch, and the filtering and coupling functions are combined on one device, which reduces the area of the single board and reduces the device plug-in. damage.
上述滤波耦合合一电路100可以是一个单独的电路,也可以是某个电路中的一个子电路。例如,上述滤波耦合合一电路100可以是下述滤波耦合电路中的一个子电路。该滤波耦合电路还可以包括更多的子电路。The filter-coupling circuit 100 mentioned above may be a single circuit, or a sub-circuit in a certain circuit. For example, the filter-coupling circuit 100 described above may be a sub-circuit in the filter-coupling circuit described below. The filter coupling circuit may also include more sub-circuits.
如图7A所示,为本申请实施例提供的一种滤波耦合电路的结构示意图,该滤波耦合电路200包括上述低通滤波耦合合一电路100,还包括高通滤波电路201。可选地,在图7A中,高通滤波电路201分别与滤波耦合电路200的输入端20、低通滤波耦合合一电路100的输入端10连接。高通滤波电路201用于为滤波耦合合一电路提供高通滤波后的信号。可选地,高通滤波电路201用于对从滤波耦合电路200的输入端20接收到的第四信号进行高通滤波,得到第一信号,从输入端10输入到低通滤波耦合合一电路100;低通滤波耦合合一电路100用于对第一信号进行低通滤波,通过输出端11输出第二信号,以及还用于对第一信号进行耦合采样,以从耦合端12输出采样到的第三信号。耦合端12可以连接到其它电路。As shown in FIG. 7A , it is a schematic structural diagram of a filter coupling circuit provided by an embodiment of the present application. The filter coupling circuit 200 includes the above-mentioned low-pass filter coupling circuit 100 and also includes a high-pass filter circuit 201 . Optionally, in FIG. 7A , the high-pass filter circuit 201 is respectively connected to the input end 20 of the filter coupling circuit 200 and the input end 10 of the low-pass filter coupling circuit 100 . The high-pass filter circuit 201 is used to provide a high-pass filtered signal for the filter coupling circuit. Optionally, the high-pass filter circuit 201 is configured to high-pass filter the fourth signal received from the input terminal 20 of the filter coupling circuit 200 to obtain the first signal, which is input to the low-pass filter coupling circuit 100 from the input terminal 10; The low-pass filtering and coupling circuit 100 is used for performing low-pass filtering on the first signal, outputting the second signal through the output terminal 11, and also performing coupling sampling on the first signal, so as to output the sampled first signal from the coupling terminal 12. Three signals. The coupling terminal 12 can be connected to other circuits.
如图7B所示,为本申请实施例提供的另一种滤波耦合电路的结构示意图,该滤波耦合电路300包括低通滤波耦合合一电路100,还包括高通滤波电路301。可选地,在图7B中,高通滤波电路301分别与滤波耦合合一电路100的输出端11、滤波耦合电路300的输出端30连接。高通滤波电路301为滤波耦合合一电路100输出的信号进行高通滤波。可选地,低通滤波耦合合一电路100用于对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号给高通滤波电路301,以及还用于对第一信号进行耦合采样,以从耦合端12输出第三信号;高通滤波电路301用于对低通滤波耦合合一电路100的输出端11输出的第二信号进行高通滤波,通过滤波耦合电路300的输出端30输出第五信号。As shown in FIG. 7B , which is a schematic structural diagram of another filter coupling circuit provided by the embodiment of the present application, the filter coupling circuit 300 includes a low-pass filter coupling circuit 100 and a high-pass filter circuit 301 . Optionally, in FIG. 7B , the high-pass filter circuit 301 is respectively connected to the output terminal 11 of the filter coupling circuit 100 and the output terminal 30 of the filter coupling circuit 300 . The high-pass filter circuit 301 performs high-pass filter for the output signal of the filter coupling circuit 100 . Optionally, the low-pass filter coupling-into-one circuit 100 is used to low-pass filter the first signal input from the input terminal 10 to output the second signal from the output terminal 11 to the high-pass filter circuit 301, and is also used to filter the first signal The signal is coupled and sampled to output a third signal from the coupling end 12; the high-pass filter circuit 301 is used to perform high-pass filtering on the second signal output by the output end 11 of the low-pass filter coupling and integration circuit 100, and pass the output of the filter coupling circuit 300 Terminal 30 outputs the fifth signal.
本实施例中,通过复用低通滤波支路,将耦合器的主信号线移到低通滤波支路上,将滤波和耦合功能合在一个器件上,减少了单板面积,降低了器件插损。上述滤波耦合电路整体实现了带通滤波的功能,且还实现了耦合的功能。In this embodiment, by multiplexing the low-pass filter branch, the main signal line of the coupler is moved to the low-pass filter branch, and the filtering and coupling functions are combined on one device, which reduces the area of the single board and reduces the device plug-in. damage. The filter coupling circuit as a whole realizes the function of band-pass filtering and also realizes the function of coupling.
下面描述滤波耦合电路的具体电路实现:The specific circuit implementation of the filter coupling circuit is described below:
对应图7A所示的结构,如图8所示,为本申请实施例提供的一种滤波耦合电路的电路结构示意图,该滤波耦合电路800包括高通滤波电路201以及低通滤波耦合合一电路100。高通滤波电路201分别与滤波耦合电路的输入端20、低通滤波耦合合一电路100的输入端10连接。Corresponding to the structure shown in FIG. 7A , as shown in FIG. 8 , it is a schematic diagram of the circuit structure of a filter coupling circuit provided by the embodiment of the present application. The filter coupling circuit 800 includes a high-pass filter circuit 201 and a low-pass filter coupling circuit 100 . The high-pass filter circuit 201 is respectively connected to the input end 20 of the filter coupling circuit and the input end 10 of the low-pass filter coupling circuit 100 .
其中,高通滤波电路201包括第一高通滤波电路,该第一高通滤波电路包括第二电感L1和第三电容C1。其中:第二电感L1的第一端L11与第三电容C1的第二端C12连接,第二电感L1的第二端L12分别与滤波耦合电路的输入端20、低通滤波耦合合一电路100的输入端10连接;第三电容C1的第一端C11接地,第三电容C1的第二端C12连接第二电感L1的第一端L11。Wherein, the high-pass filter circuit 201 includes a first high-pass filter circuit, and the first high-pass filter circuit includes a second inductor L1 and a third capacitor C1. Wherein: the first terminal L11 of the second inductor L1 is connected to the second terminal C12 of the third capacitor C1, and the second terminal L12 of the second inductor L1 is respectively connected to the input terminal 20 of the filter coupling circuit and the low-pass filter coupling circuit 100 The first terminal C11 of the third capacitor C1 is connected to the ground, and the second terminal C12 of the third capacitor C1 is connected to the first terminal L11 of the second inductor L1.
第一高通滤波电路的工作原理为:第三信号从滤波耦合电路的输入端20流入。利用电容通交流、电感阻交流的特性,第三电感L1和第三电容C1等效为一个电感,低频更容易通过电感,第一高通滤波电路用于对从滤波耦合电路的输入端20接收到的第四信号进行高通滤波,得到第一信号。通过改变第三电感L1和第三电容C1的值可以抑制PA带外杂散的低频部分,从而实现高通滤波的功能。The working principle of the first high-pass filter circuit is: the third signal flows in from the input end 20 of the filter coupling circuit. Utilizing the characteristics of capacitance through AC and inductance against AC, the third inductance L1 and the third capacitor C1 are equivalent to an inductance, and low frequencies are easier to pass through the inductance. The fourth signal is subjected to high-pass filtering to obtain the first signal. By changing the values of the third inductor L1 and the third capacitor C1, the low-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of high-pass filtering.
低通滤波耦合合一电路100包括第一电容C2、第一电感L2、第二电容C3和第二电感L3,其中:第一电容C2的第一端C21接地、第二端C22分别与输入端10、第一电感L2的第一端L21连接;第二电容C3的第一端C31接地、第二端C32分别与输出端11、第一电感L2的第二端L22连接;第二电感L3与第一电感L2耦合,第二电感L3的第一端L31与耦合端12连接、第二端L32与负载端13连接。其中,负载端13一般接匹配的负载,例如50Ω电阻。The low-pass filter coupling-in-one circuit 100 includes a first capacitor C2, a first inductor L2, a second capacitor C3, and a second inductor L3, wherein: the first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is respectively connected to the input terminal 10. The first terminal L21 of the first inductor L2 is connected; the first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11 and the second terminal L22 of the first inductor L2; the second inductor L3 is connected to the The first inductor L2 is coupled, the first end L31 of the second inductor L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 . Wherein, the load terminal 13 is generally connected to a matched load, such as a 50Ω resistor.
低通滤波耦合合一电路100工作原理为:利用高频更容易通过电容的特性,低通滤波耦合合一电路100中的第一电容C2、第一电感L2和第二电容C3用于对第一信号进行低通滤波,得到第二信号,并通过输出端11输出第二信号。通过改变第一电容C2、第二电容C3、第一电感L2、第二电感L3的值可以抑制PA带外杂散的高频部分,从而实现低通滤波的功能。The working principle of the low-pass filter coupling-in-one circuit 100 is as follows: the first capacitor C2, the first inductance L2 and the second capacitor C3 in the low-pass filter coupling-in-one circuit 100 are used for the A signal is low-pass filtered to obtain a second signal, and the second signal is output through the output terminal 11 . By changing the values of the first capacitor C2, the second capacitor C3, the first inductance L2, and the second inductance L3, the high-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of low-pass filtering.
高频信号(即第一信号)通过第一电感L2产生交变的磁通,使得第二电感L3感应出电压,从而第一电感L2和第二电感L3通过空间或者物理上实现耦合的功能,即低通滤波耦合合一电路100中的第一电感L2和第二电感L3用于对高通滤波电路201输出的第一信号进行耦合采样,以从耦合端12输出第三信号。通过改变第一电感L2和第二电感L3之间的距离等耦合紧密程度可以改变滤波耦合电路的隔离度和耦合度。The high-frequency signal (that is, the first signal) generates alternating magnetic flux through the first inductance L2, so that the second inductance L3 induces a voltage, so that the first inductance L2 and the second inductance L3 realize the coupling function through space or physically, That is, the first inductor L2 and the second inductor L3 in the low-pass filter coupling-into-one circuit 100 are used to couple and sample the first signal output by the high-pass filter circuit 201 so as to output the third signal from the coupling terminal 12 . The degree of isolation and coupling of the filter coupling circuit can be changed by changing the tightness of coupling such as the distance between the first inductor L2 and the second inductor L3.
通过复用第一电容C2、第一电感L2和第二电容C3这一射频支路,将耦合器的主信号线(即第二电感L3)移到滤波器上,将滤波器和耦合器功能合在一个器件上,缩小了整个单板的尺寸;且将滤波器和耦合器功能合一,降低了射频支路上的插损;另外,将滤波器和耦合器功能合一,还可以减少器件的端口数(例如,图2和图3中包括P1~P6共6个端口,图 8中则仅包括输入端20、输出端11、耦合端12和负载端13共4个端口)。By multiplexing the RF branch of the first capacitor C2, the first inductor L2, and the second capacitor C3, the main signal line of the coupler (that is, the second inductor L3) is moved to the filter, and the functions of the filter and the coupler Combined on one device, the size of the entire board is reduced; and the function of the filter and the coupler are combined to reduce the insertion loss on the radio frequency branch; (for example, Figure 2 and Figure 3 include 6 ports P1 to P6, and Figure 8 only includes 4 ports including input terminal 20, output terminal 11, coupling terminal 12 and load terminal 13).
如图9所示,为本申请实施例提供的又一种滤波耦合电路的具体的电路结构示意图。与图8所示的电路的不同在于,在该滤波耦合电路900中,高通滤波电路201还可以包括连接于第一高通滤波电路与低通滤波耦合合一电路100之间、且与第一高通滤波电路并联的第二高通滤波电路。该第二高通滤波电路包括第四电感L4和第四电容C4,第四电感L4的第一端L41与第四电容C4的第二端C42连接,第四电感L4的第二端L42分别与第三电感L1的第二端L12、低通滤波耦合合一电路100的输入端10连接;第四电容C4的第一端C41接地。第二高通滤波电路用于对第三信号进行二阶高通滤波。当然,该高通滤波电路201还可以包括更多并联的高通滤波电路,以实现更高阶的高通滤波。As shown in FIG. 9 , it is a schematic diagram of a specific circuit structure of another filter coupling circuit provided in the embodiment of the present application. The difference from the circuit shown in FIG. 8 is that, in the filter coupling circuit 900, the high-pass filter circuit 201 may also include a first high-pass filter circuit connected between the first high-pass filter circuit and the low-pass filter coupling circuit 100, and connected to the first high-pass filter circuit. The filter circuit is connected in parallel with the second high-pass filter circuit. The second high-pass filter circuit includes a fourth inductor L4 and a fourth capacitor C4, the first end L41 of the fourth inductor L4 is connected to the second end C42 of the fourth capacitor C4, and the second end L42 of the fourth inductor L4 is respectively connected to the second end C42 of the fourth capacitor C4. The second terminal L12 of the three inductors L1 is connected to the input terminal 10 of the low-pass filter coupling circuit 100; the first terminal C41 of the fourth capacitor C4 is grounded. The second high-pass filter circuit is used for performing second-order high-pass filter on the third signal. Certainly, the high-pass filter circuit 201 may also include more parallel-connected high-pass filter circuits, so as to realize higher-order high-pass filter.
另外,为了增加对高频的抑制程度,该滤波耦合电路900还包括低通滤波电路202。该低通滤波电路202包括第五电容C5、第五电感L5和第六电容C6。其中,第五电容C5的第一端C51接地,第五电容C5的第二端分别与低通滤波耦合合一电路100的输出端11、第五电感L5的第一端L51连接;第六电容C6的第一端C61接地,第六电容C6的第二端C62分别与第五电感L5的第二端L52、滤波耦合电路的输出端22连接。该低通滤波电路用于对第二信号进行二阶低通滤波。当然,该滤波耦合电路还可以包括更多串联的低通滤波电路,以实现更高阶的低通滤波。In addition, in order to increase the degree of high-frequency suppression, the filter coupling circuit 900 further includes a low-pass filter circuit 202 . The low-pass filter circuit 202 includes a fifth capacitor C5, a fifth inductor L5 and a sixth capacitor C6. Wherein, the first terminal C51 of the fifth capacitor C5 is grounded, and the second terminal of the fifth capacitor C5 is respectively connected to the output terminal 11 of the low-pass filter coupling-in-one circuit 100 and the first terminal L51 of the fifth inductor L5; the sixth capacitor The first terminal C61 of C6 is grounded, and the second terminal C62 of the sixth capacitor C6 is respectively connected to the second terminal L52 of the fifth inductor L5 and the output terminal 22 of the filter coupling circuit. The low-pass filter circuit is used to perform second-order low-pass filter on the second signal. Certainly, the filter coupling circuit may also include more low-pass filter circuits connected in series, so as to realize higher-order low-pass filter.
该滤波耦合电路可以同时具有上述高阶高通滤波功能和高阶低通滤波功能,也可以包括高阶高通滤波功能和高阶低通滤波功能中的其中一个功能。The filter coupling circuit may simultaneously have the above-mentioned high-order high-pass filter function and high-order low-pass filter function, or may include one of the high-order high-pass filter function and the high-order low-pass filter function.
通过增加耦合和滤波合一器件的阶数,改变整个器件的传输特性,从而改善滤波器的回损、插损以及耦合器的方向性等指标,增加了整个器件的自由度,为耦合和滤波合一器件在其他场景的运用提供了可能。By increasing the order of the coupling and filtering integrated device, the transmission characteristics of the entire device are changed, thereby improving the return loss of the filter, the insertion loss, and the directivity of the coupler, etc., increasing the degree of freedom of the entire device, providing for coupling and filtering The application of integrated devices in other scenarios provides the possibility.
对应图7B所示的结构,如图10所示,为本申请实施例提供的又一种滤波耦合电路的电路结构示意图,该滤波耦合电路1000包括低通滤波耦合合一电路100,还包括高通滤波电路301。高通滤波电路301分别与低通滤波耦合合一电路100的输出端11、滤波耦合电路1000的输出端30连接。Corresponding to the structure shown in FIG. 7B, as shown in FIG. 10, it is a schematic diagram of the circuit structure of another filter coupling circuit provided by the embodiment of the present application. The filter coupling circuit 1000 includes a low-pass filter coupling circuit 100, and also includes a high-pass filter circuit 301. The high-pass filter circuit 301 is respectively connected to the output end 11 of the low-pass filter coupling circuit 100 and the output end 30 of the filter coupling circuit 1000 .
其中,低通滤波耦合合一电路100包括第一电容C2、第一电感L2、第二电容C3和第二电感L3,其中:第一电容C2的第一端C21接地、第二端C22分别与输入端10、第一电感L2的第一端L21连接;第二电容C3的第一端C31接地、第二端C32分别与输出端11、第一电感L2的第二端L22连接;第二电感L3与第一电感L2耦合,第二电感L3的第一端L31与耦合端12连接、第二端L32与负载端13连接。其中,负载端13一般接匹配的负载,例如50Ω电阻。Wherein, the low-pass filter coupling-into-one circuit 100 includes a first capacitor C2, a first inductor L2, a second capacitor C3, and a second inductor L3, wherein: the first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is connected to the The input end 10 is connected to the first end L21 of the first inductor L2; the first end C31 of the second capacitor C3 is connected to the ground, and the second end C32 is respectively connected to the output end 11 and the second end L22 of the first inductor L2; the second inductor L3 is coupled to the first inductor L2 , the first end L31 of the second inductor L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 . Wherein, the load terminal 13 is generally connected to a matched load, such as a 50Ω resistor.
低通滤波耦合合一电路100的工作原理为:利用高频更容易通过电容的特性,低通滤波耦合合一电路100中的第一电容C2、第一电感L2、第二电容C3用于对第一信号进行低通滤波,得到第二信号,从输出端11输出。通过改变第一电容C2、第一电感L2、第二电容C3的值可以抑制PA带外杂散的高频部分,从而实现低通滤波的功能。The working principle of the low-pass filter coupling-in-one circuit 100 is: the first capacitor C2, the first inductance L2, and the second capacitor C3 in the low-pass filter coupling-in-one circuit 100 are used to The first signal is low-pass filtered to obtain a second signal, which is output from the output terminal 11 . By changing the values of the first capacitor C2, the first inductor L2, and the second capacitor C3, the high-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of low-pass filtering.
第一信号通过第一电感L2产生交变的磁通,使得第二电感L3感应出电压,从而第一电感L2和第二电感L3通过空间或者物理上实现耦合的功能,即低通滤波耦合合一电路100中的第一电感L2和第二电感L3用于对第一信号进行耦合采样,以从耦合端12输出第三信号。 通过改变第一电感L2和第二电感L3之间的距离等耦合紧密程度可以改变滤波耦合电路的隔离度和耦合度。The first signal passes through the first inductance L2 to generate alternating magnetic flux, so that the second inductance L3 induces a voltage, so that the first inductance L2 and the second inductance L3 realize the coupling function through space or physically, that is, low-pass filter coupling The first inductor L2 and the second inductor L3 in a circuit 100 are used to couple and sample the first signal so as to output the third signal from the coupling terminal 12 . The degree of isolation and coupling of the filter coupling circuit can be changed by changing the tightness of coupling such as the distance between the first inductor L2 and the second inductor L3.
高通滤波电路301包括第一高通滤波电路,该第一高通滤波电路包括第六电感L6和第七电容C7。第六电感L6的第一端L61与第七电容的第二端C72连接,第六电感L6的第二端L62分别与低通滤波耦合合一电路100的输出端11、滤波耦合电路的输出端30连接;第七电容的第一端C71接地、第二端C72与第六电感L6的第一端L61连接。The high-pass filter circuit 301 includes a first high-pass filter circuit, and the first high-pass filter circuit includes a sixth inductor L6 and a seventh capacitor C7. The first terminal L61 of the sixth inductance L6 is connected to the second terminal C72 of the seventh capacitor, and the second terminal L62 of the sixth inductance L6 is respectively connected to the output terminal 11 of the low-pass filter coupling circuit 100 and the output terminal of the filter coupling circuit. 30 connection; the first terminal C71 of the seventh capacitor is grounded, and the second terminal C72 is connected to the first terminal L61 of the sixth inductor L6.
高通滤波电路301的工作原理为:利用电容通交流、电感阻交流的特性,第六电感L6和第七电容C7等效为一个电感,低频更容易通过电感,第一高通滤波电路用于对从低通滤波耦合合一电路100的输出端输出的第二信号进行高通滤波,得到第五信号,并通过输出端30输出。通过改变第六电感L6和第七电容C7的值可以抑制PA带外杂散的低频部分,从而实现高通滤波的功能。The working principle of the high-pass filter circuit 301 is: using the characteristics of the capacitor passing through the AC and the inductor resisting the AC, the sixth inductance L6 and the seventh capacitor C7 are equivalent to an inductance, and low frequencies are easier to pass through the inductance. The second signal output from the output terminal of the low-pass filtering coupling circuit 100 is subjected to high-pass filtering to obtain a fifth signal, which is output through the output terminal 30 . By changing the values of the sixth inductor L6 and the seventh capacitor C7, the low-frequency part of the out-of-band spurs of the PA can be suppressed, thereby realizing the function of high-pass filtering.
通过复用第一电容C2、第一电感L2、第二电容C3这一射频支路,将耦合器的主信号线(即第二电感L3)移到滤波器上,将滤波器和耦合器功能合在一个器件上,缩小了整个单板的尺寸;且将滤波器和耦合器功能合一,降低了射频支路上的插损;另外,将滤波器和耦合器功能合一,还可以减少器件的端口数(例如,图2和图3中包括P1~P6共6个端口,图10中则仅包括输入端10、输出端30、耦合端12和负载端13共4个端口)。By multiplexing the radio frequency branch of the first capacitor C2, the first inductor L2, and the second capacitor C3, the main signal line of the coupler (that is, the second inductor L3) is moved to the filter, and the function of the filter and the coupler Combined on one device, the size of the entire board is reduced; and the function of the filter and the coupler are combined to reduce the insertion loss on the radio frequency branch; (for example, Figure 2 and Figure 3 include 6 ports P1 to P6, and Figure 10 only includes 4 ports including input terminal 10, output terminal 30, coupling terminal 12 and load terminal 13).
如图11所示,为本申请实施例提供的又一种滤波耦合电路的具体的电路结构示意图。与图10所示的电路的不同在于,为了增加对高频的抑制程度,该滤波耦合电路1100还包括低通滤波电路302,低通滤波电路302与滤波耦合合一电路100的输出端11连接。该低通滤波电路302包括第九电容C9、第八电感L8和第十电容C10。其中,第九电容C9的第一端C91接地,第九电容C9的第二端C92分别与滤波耦合合一电路100的输出端11以及第八电感L8的第一端L81连接;第十电容C10的C101第一端接地,第十电容C10的第二端C102与第八电感L8的第二端L82连接。该低通滤波电路用于对第二信号进行二阶低通滤波。当然,该滤波耦合电路还可以包括更多的低通滤波电路,以实现更高阶的低通滤波。As shown in FIG. 11 , it is a schematic diagram of a specific circuit structure of another filter coupling circuit provided in the embodiment of the present application. The difference from the circuit shown in FIG. 10 is that, in order to increase the degree of suppression of high frequencies, the filter coupling circuit 1100 also includes a low-pass filter circuit 302, and the low-pass filter circuit 302 is connected to the output terminal 11 of the filter coupling circuit 100 . The low-pass filter circuit 302 includes a ninth capacitor C9, an eighth inductor L8 and a tenth capacitor C10. Wherein, the first terminal C91 of the ninth capacitor C9 is grounded, and the second terminal C92 of the ninth capacitor C9 is respectively connected to the output terminal 11 of the filter coupling circuit 100 and the first terminal L81 of the eighth inductor L8; the tenth capacitor C10 The first terminal C101 of the tenth capacitor C10 is connected to the ground, and the second terminal C102 of the tenth capacitor C10 is connected to the second terminal L82 of the eighth inductor L8. The low-pass filter circuit is used to perform second-order low-pass filter on the second signal. Certainly, the filter coupling circuit may also include more low-pass filter circuits, so as to realize higher-order low-pass filter.
另外,在该滤波耦合电路1100中,高通滤波电路301还可以包括连接于第一高通滤波电路与滤波耦合电路的输出端30之间、且与第一高通滤波电路并联的第二高通滤波电路。该第二高通滤波电路包括第七电感L7和第八电容C8。其中,第七电感L7的第一端L71与第八电容C8的第二端C82连接,第七电感L7的第二端L72分别与第六电感L6的第一端L61、滤波耦合电路的输出端30连接;第八电容C8的第一端C81接地,第八电容C8的第二端C82与第七电感L7的第一端L71连接。第二高通滤波电路用于对第一高通滤波电路输出的第四信号进行二阶高通滤波,得到第五信号,并从输出端30输出。当然,该高通滤波电路301还可以包括更多并联的高通滤波电路,以实现更高阶的高通滤波。In addition, in the filtering coupling circuit 1100, the high-pass filtering circuit 301 may further include a second high-pass filtering circuit connected between the first high-pass filtering circuit and the output terminal 30 of the filtering coupling circuit and connected in parallel with the first high-pass filtering circuit. The second high-pass filter circuit includes a seventh inductor L7 and an eighth capacitor C8. Wherein, the first end L71 of the seventh inductance L7 is connected to the second end C82 of the eighth capacitor C8, and the second end L72 of the seventh inductance L7 is respectively connected to the first end L61 of the sixth inductance L6 and the output end of the filter coupling circuit 30 connection; the first terminal C81 of the eighth capacitor C8 is grounded, and the second terminal C82 of the eighth capacitor C8 is connected to the first terminal L71 of the seventh inductor L7. The second high-pass filter circuit is used to perform a second-order high-pass filter on the fourth signal output by the first high-pass filter circuit to obtain a fifth signal, which is output from the output terminal 30 . Certainly, the high-pass filter circuit 301 may also include more parallel-connected high-pass filter circuits, so as to realize higher-order high-pass filter.
该滤波耦合电路可以同时上述高阶高通滤波功能和高阶低通滤波功能,也可以包括高阶高通滤波功能和高阶低通滤波功能中的其中一个功能。The filter coupling circuit may have the above-mentioned high-order high-pass filter function and high-order low-pass filter function at the same time, or may include one of the high-order high-pass filter function and the high-order low-pass filter function.
通过增加耦合和滤波合一器件的阶数,改变整个器件的传输特性,从而改善滤波器的回损、插损以及耦合器的方向性等指标,增加了整个器件的自由度,为耦合和滤波合一器件在其他场景的运用提供了可能。By increasing the order of the coupling and filtering integrated device, the transmission characteristics of the entire device are changed, thereby improving the return loss of the filter, the insertion loss, and the directivity of the coupler, etc., increasing the degree of freedom of the entire device, providing for coupling and filtering The application of integrated devices in other scenarios provides the possibility.
为了兼顾滤波器性能指标、耦合器性能指标、单板尺寸和成本等多方面因素,上述带通 滤波和耦合模块中的部分或全部元件可以采用微带线实现。微带线是走在PCB表面的带状走线,利用传输线的不连续性及其等效电路实现电容或电感器件的构造。In order to take into account various factors such as filter performance index, coupler performance index, single board size and cost, some or all components in the above-mentioned band-pass filtering and coupling module can be realized by using microstrip lines. The microstrip line is a strip line that runs on the surface of the PCB, and uses the discontinuity of the transmission line and its equivalent circuit to realize the construction of capacitive or inductive devices.
以图8所示的滤波耦合电路为例,其对应的一种微带线结构示意图如图12所示。其中,假设该滤波耦合电路设置在一AP中。该AP工作在5G频带。为了达到滤除2.4G频带上的信号,本实施例中第三电感L1的感值和第三电容C1的容值较大,可以使用分立器件(即不采用微带线),L1和C1通过传输线连接。那么,对于图8所示的滤波耦合电路,除高通滤波电路201(即第三电感L1和第三电容C1)外,低通滤波耦合合一电路100中的元件均可以采用微带线实现。Taking the filter coupling circuit shown in FIG. 8 as an example, a schematic diagram of a corresponding microstrip line structure is shown in FIG. 12 . Wherein, it is assumed that the filter coupling circuit is set in an AP. This AP works in the 5G frequency band. In order to filter out signals on the 2.4G frequency band, the inductance value of the third inductor L1 and the capacitance value of the third capacitor C1 in this embodiment are relatively large, and discrete devices can be used (that is, microstrip lines are not used), and L1 and C1 pass through Transmission line connection. Then, for the filter coupling circuit shown in FIG. 8 , except for the high-pass filter circuit 201 (ie, the third inductor L1 and the third capacitor C1 ), the components in the low-pass filter coupling circuit 100 can all be implemented using microstrip lines.
可选地,在图12中,N为介质参考板(灰色部分);N的一个表面设置有金属微带线(灰色部分所围成的部分)和/或金属地(灰色部分及灰色部分所围成的部分之外的部分)。介质参考板可以为Fr4(树脂材料)板材。图12中,分别用不同线条形状的虚线框表示第一电容C2、第二电容C3、第一电感L2、第二电感L3对应的微带线区域。Optionally, in FIG. 12, N is a dielectric reference plate (gray part); one surface of N is provided with a metal microstrip line (the part surrounded by the gray part) and/or a metal ground (the part surrounded by the gray part and the gray part). outside the enclosed part). The dielectric reference plate may be a Fr4 (resin material) plate. In FIG. 12 , the dotted-line boxes of different line shapes represent the microstrip line regions corresponding to the first capacitor C2 , the second capacitor C3 , the first inductor L2 , and the second inductor L3 .
其中,在一个实现中,如图13的左图所示,第一电容C2与第二端C22对应的一极为第一微带线区域C2a、第一端C21对应的一极为地,第一微带线区域C2a与地耦合形成电容。微带线和地为电容的两个板级。第一微带线区域C2a为长条形。Wherein, in one implementation, as shown in the left diagram of FIG. 13 , one pole of the first capacitor C2 corresponding to the second terminal C22 is the first microstrip line region C2a, one pole corresponding to the first terminal C21 is ground, and the first microstrip The stripline region C2a is coupled to ground to form a capacitor. The microstrip line and ground are the two board levels of the capacitor. The first microstrip line region C2a is strip-shaped.
在另一个实现中,如图13的右图所示,第一电容C2与第二端C22对应的一极为第二微带线区域C2d、第一端C21对应的一极为与地连通的第三微带线区域C2e,第二微带线区域C2d与第三微带线区域C2e耦合形成电容。两根微带线为电容的两个板级。第二微带线区域C2d与第三微带线区域C2e均为长条形。In another implementation, as shown in the right figure of FIG. 13 , one pole of the first capacitor C2 corresponding to the second end C22 is the second microstrip line region C2d, and one pole corresponding to the first end C21 is the third pole connected to the ground. The microstrip line region C2e, the second microstrip line region C2d and the third microstrip line region C2e are coupled to form a capacitor. The two microstrip lines are the two board levels of the capacitor. Both the second microstrip line region C2d and the third microstrip line region C2e are elongated.
在一个实现中,如图14的左图所示,第二电容C3与第二端C32对应的一极为第四微带线区域C3a、第一端C31对应的一极为地,第四微带线区域C3a与地耦合形成电容。微带线和地为电容的两个板级。第四微带线区域C3a为长条形。In one implementation, as shown in the left diagram of FIG. 14 , one pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a, one pole corresponding to the first end C31 is ground, and the fourth microstrip line Region C3a is coupled to ground to form a capacitor. The microstrip line and ground are the two board levels of the capacitor. The fourth microstrip line region C3a is strip-shaped.
在另一个实现中,如图14的右图所示,第二电容C3与第二端C32对应的一极为第五微带线区域C3d、第一端C31对应的一极为与地连通的第六微带线区域C3e,第五微带线区域C3d与第六微带线区域C3e耦合形成电容。两根微带线为电容的两个板级。第五微带线区域C3d与第六微带线区域C3e均为长条形。In another implementation, as shown in the right figure of FIG. 14 , one pole of the second capacitor C3 corresponding to the second terminal C32 is the fifth microstrip line region C3d, and one pole corresponding to the first terminal C31 is connected to the sixth microstrip line region C3d. The microstrip line region C3e, the fifth microstrip line region C3d and the sixth microstrip line region C3e are coupled to form a capacitor. The two microstrip lines are the two board levels of the capacitor. Both the fifth microstrip line region C3d and the sixth microstrip line region C3e are elongated.
上述微带线区域C2a、C2d、C2e、C3a、C3d或C3e为长条形,具体可以是长宽比大于设定阈值的长方形,或长高比大于设定阈值的平行四边形、梯形等。The above-mentioned microstrip line regions C2a, C2d, C2e, C3a, C3d or C3e are in the shape of a strip, which may be specifically a rectangle with an aspect ratio greater than a set threshold, or a parallelogram or trapezoid with an aspect ratio greater than a set threshold.
上述第一电容C2可以采用图13所示的任一种实现,第二电容C3可以采用图14所示的任一种实现。第一电容C2和第二电容C3的上述电容微带线实现可以组合使用。在图12中,以第一微带线区域C2a与地耦合形成第一电容C2、以及第四微带线区域C3a与地耦合形成第二电容C3为例进行描述。The above-mentioned first capacitor C2 can be realized by any one shown in FIG. 13 , and the second capacitor C3 can be realized by any one shown in FIG. 14 . The above capacitive microstrip line implementations of the first capacitor C2 and the second capacitor C3 can be used in combination. In FIG. 12 , it is described by taking the first microstrip line region C2 a coupled with the ground to form the first capacitor C2 , and the fourth microstrip line region C3 a coupled with the ground to form the second capacitor C3 as an example.
可以使用不同宽度和长度的微带线区域实现电感器件的构造。第一电感L2为第七微带线区域L2a,第二电感L3为第八微带线区域L3a。第七微带线区域L2a与第八微带线区域L3a之间的缝隙宽度包括:第一宽度A1、第二宽度A2、第三宽度A3,第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙长度为长度B1。The construction of inductive devices can be realized using microstrip line regions of different widths and lengths. The first inductance L2 is the seventh microstrip line region L2a, and the second inductance L3 is the eighth microstrip line region L3a. The gap width between the seventh microstrip line region L2a and the eighth microstrip line region L3a includes: the first width A1, the second width A2, and the third width A3, the seventh microstrip line region L2a and the eighth microstrip line region The length of the gap between the stripline regions L3a is the length B1.
在图12中,第一微带线区域C2a和第四微带线区域C3a位于第七微带线区域L2a的第一侧D1,第八微带线区域L3a位于第七微带线区域L2a的第二侧D2。In FIG. 12, the first microstrip line region C2a and the fourth microstrip line region C3a are located on the first side D1 of the seventh microstrip line region L2a, and the eighth microstrip line region L3a is located on the side of the seventh microstrip line region L2a. Second side D2.
可以通过PCB走线或者其他方式将端口10、11、12和13连接到WIFI系统中。 Ports 10, 11, 12 and 13 can be connected to the WIFI system through PCB traces or other methods.
其中,滤波耦合合一电路的耦合度C的定义为主线耦合到副线中正向传输功率P3与主线入射功率P1之比的对数,耦合度的绝对值如下所示:Among them, the coupling degree C of the filter coupling circuit is defined as the logarithm of the ratio of the forward transmission power P3 in the main line coupled to the auxiliary line and the main line incident power P1, and the absolute value of the coupling degree is as follows:
C=|10lg(P3/P1)|=10lg(P1/P3)=-20lg|S31|             (1)C=|10lg(P3/P1)|=10lg(P1/P3)=-20lg|S31| (1)
式(1)中的S31为输入端10与耦合端12之间的散射参数。S31 in formula (1) is the scattering parameter between the input end 10 and the coupling end 12 .
本实施例中,输入端10和第八微带线区域L3a上的耦合端12之间的距离与输入端10和耦合端12之间的散射参数成正相关关系,输入端10和耦合端12之间的距离与滤波耦合合一电路的耦合度成反相关关系。其中,该正相关关系可以是正比关系,该反相关关系可以是反比关系。具体地,当输入端10和耦合端12之间的距离越近时,S31越小,滤波耦合合一电路的耦合度就越大;而输入端10和耦合端12之间的距离越远时,S31越大,滤波耦合合一电路的耦合度就越小。In this embodiment, the distance between the input end 10 and the coupling end 12 on the eighth microstrip line area L3a is positively correlated with the scattering parameter between the input end 10 and the coupling end 12, and the distance between the input end 10 and the coupling end 12 The distance between them is inversely correlated with the coupling degree of the filter-coupling circuit. Wherein, the positive correlation relationship may be a direct proportional relationship, and the anti-correlation relationship may be an inverse proportional relationship. Specifically, when the distance between the input terminal 10 and the coupling terminal 12 is closer, the smaller S31 is, the greater the coupling degree of the filter coupling circuit is; and the farther the distance between the input terminal 10 and the coupling terminal 12 is , the larger S31 is, the smaller the coupling degree of the filter-coupling circuit is.
另外,第七微带线区域L2a与第八微带线区域L3a之间的第一宽度A1、第二宽度A2、第三宽度A3、第七微带线区域L2a与第八微带线区域L3a之间的长度B1中的至少一个与滤波耦合合一电路的耦合度成正相关关系。其中,该正相关关系可以是正比关系。In addition, the first width A1, the second width A2, the third width A3 between the seventh microstrip line region L2a and the eighth microstrip line region L3a, the seventh microstrip line region L2a and the eighth microstrip line region L3a At least one of the lengths B1 is positively correlated with the coupling degree of the filter-coupling circuit. Wherein, the positive correlation may be a proportional relationship.
当然,改变滤波耦合合一电路的耦合度的方式并不局限于以上方式。Certainly, the way of changing the coupling degree of the filter coupling and unifying circuit is not limited to the above ways.
滤波耦合合一电路的隔离度I的定义为主线入射功率P1与隔离端口的输出功率P4之比的分贝数,隔离度的绝对值如下所示:The isolation I of the filter coupling circuit is defined as the decibel ratio of the main line incident power P1 to the output power P4 of the isolated port. The absolute value of the isolation is as follows:
I=10lg(P1/P4)=-20lg|S41|                 (2)I=10lg(P1/P4)=-20lg|S41| (2)
式(2)中的S41为输入端10和第八微带线区域L3a上的负载端13之间的散射参数。输入端10和负载端13之间的距离与输入端10和负载端13之间的散射参数成正相关关系,输入端10和负载端13之间的距离与滤波耦合合一电路的隔离度成反相关关系。其中,该正相关关系可以是正比关系,该反相关关系可以是反比关系。具体地,输入端10和负载端13之间的距离越近时,S41越小,滤波耦合合一电路的隔离度越大,而输入端10和负载端13之间的距离越远时,S41越大,滤波耦合合一电路的隔离度就越小。S41 in formula (2) is a scattering parameter between the input terminal 10 and the load terminal 13 on the eighth microstrip line region L3a. The distance between the input terminal 10 and the load terminal 13 is positively correlated with the scattering parameter between the input terminal 10 and the load terminal 13, and the distance between the input terminal 10 and the load terminal 13 is inversely related to the isolation of the filter coupling circuit relationship. Wherein, the positive correlation relationship may be a direct proportional relationship, and the anti-correlation relationship may be an inverse proportional relationship. Specifically, when the distance between the input terminal 10 and the load terminal 13 is closer, S41 is smaller, and the isolation of the filter coupling circuit is larger, and when the distance between the input terminal 10 and the load terminal 13 is farther, S41 The larger the value, the smaller the isolation of the filter-coupling circuit.
另外,第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙的第一宽度A1、第二宽度A2、第三宽度A3、第七微带线区域L2a与第八微带线区域L3a之间的缝隙的长度B1中的至少一个与滤波耦合合一电路的隔离度成正相关关系。其中,该正相关关系可以是正比关系。In addition, the first width A1, the second width A2, the third width A3 of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a, the seventh microstrip line region L2a and the eighth microstrip line region At least one of the lengths B1 of the gaps between the stripline regions L3a is positively correlated with the isolation of the filter-coupling circuit. Wherein, the positive correlation may be a proportional relationship.
当然,改变滤波耦合合一电路的隔离度的方式并不局限于以上方式。Certainly, the way of changing the isolation of the filtering coupling and combining circuit is not limited to the above ways.
在图12中,第七微带线区域L2a为长条形,第八微带线区域L3a为“h”字形,可以在满足第一电感L2和第二电感L3自身的感值要求的基础上,使得第七微带线区域L2a和第八微带线区域L3a满足低通滤波耦合合一电路的耦合度和隔离度要求。另外,第八微带线区域L3a还可以为“n”字形或“7”字形。In Fig. 12, the seventh microstrip line area L2a is in the shape of a long strip, and the eighth microstrip line area L3a is in the shape of "h", which can meet the inductance requirements of the first inductance L2 and the second inductance L3 on the basis of , so that the seventh microstrip line region L2a and the eighth microstrip line region L3a meet the coupling and isolation requirements of the low-pass filter coupling and integration circuit. In addition, the eighth microstrip line region L3a may also be in the shape of "n" or "7".
为了进一步缩小整个滤波耦合合一电路的尺寸,可以改变元器件的布局布线。In order to further reduce the size of the entire filter-coupling circuit, the layout and wiring of components can be changed.
例如,如图15所示的另一种微带线结构示意图,与图12所示的微带线结构不同的是,第八微带线区域L3a、第一微带线区域C2a和第四微带线区域C3a均位于第七微带线区域L2a的第一侧D1。这里,第一微带线区域C2a和第八微带线区域L3a之间的地会增大其隔离,从而可以忽略其耦合;以及第四微带线区域C3a和第八微带线区域L3a之间的地会增大其隔离, 从而可以忽略其耦合。第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙具有第一宽度A1和第二宽度A2,第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙具有第一长度B1。第七微带线区域L2a与第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与第二电感L2和第三电感L3之间所需要的耦合度成正相关关系,和/或,第七微带线区域L2a与第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与第二电感L2和第三电感L3之间所需要的隔离度成正相关关系。其中,该正相关关系可以是正比关系。For example, another microstrip line structure schematic diagram shown in Figure 15 is different from the microstrip line structure shown in Figure 12 in that the eighth microstrip line region L3a, the first microstrip line region C2a and the The stripline regions C3a are all located on the first side D1 of the seventh microstripline region L2a. Here, the ground between the first microstrip line region C2a and the eighth microstrip line region L3a will increase its isolation so that its coupling can be ignored; and the ground between the fourth microstrip line region C3a and the eighth microstrip line region L3a Grounding between them increases their isolation, making their coupling negligible. The gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a has a first width A1 and a second width A2, and the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a The gap between them has a first length B1. The width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required coupling degree between the second inductance L2 and the third inductance L3, and/or Or, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required isolation between the second inductor L2 and the third inductor L3. Wherein, the positive correlation may be a proportional relationship.
又例如,如图16所示的又一种微带线结构示意图,与图12所示的微带线结构不同的是,第七微带线区域L2a为“v”字形。其中,“v”字形的两边可以是阶梯形或有一定斜度的直线,根据第一电感L2的大小而定。第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙具有第一宽度A1和第二宽度A2,第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙具有第一长度B1。第七微带线区域L2a与第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与第二电感L2和第三电感L3之间所需要的耦合度成正相关关系,和/或,第七微带线区域L2a与第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与第二电感L2和第三电感L3之间所需要的隔离度成正相关关系。其中,该正相关关系可以是正比关系。For another example, as shown in FIG. 16 , another schematic diagram of a microstrip line structure is different from the microstrip line structure shown in FIG. 12 in that the seventh microstrip line region L2a is in the shape of a "v". Wherein, the two sides of the "v" shape can be stepped or straight with a certain slope, depending on the size of the first inductance L2. The gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a has a first width A1 and a second width A2, and the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a The gap between them has a first length B1. The width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required coupling degree between the second inductance L2 and the third inductance L3, and/or Or, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be positively correlated with the required isolation between the second inductor L2 and the third inductor L3. Wherein, the positive correlation may be a proportional relationship.
此外,第七微带线区域L2a还可以是“u”字形,本申请不一一列举第七微带线区域L2a的结构,根据本申请的微带线结构原理实现的微带线区域结构都在本申请的保护范围内。In addition, the seventh microstrip line region L2a can also be in the shape of "u". This application does not list the structure of the seventh microstrip line region L2a one by one. Within the protection scope of this application.
以上是以图8所示的滤波耦合合一电路为例示例了该滤波耦合合一电路的微带线的构造,同理,也可以根据微带线构造电容和电感的原理,构造图9~图11所示的滤波耦合合一电路的微带线结构。The above is an example of the filter-coupling circuit shown in Figure 8 to illustrate the structure of the microstrip line of the filter-coupling circuit. Similarly, it is also possible to construct the microstrip line according to the principle of microstrip line construction of capacitance and inductance, as shown in Figure 9- The microstrip line structure of the filter coupling integration circuit shown in Fig. 11 .
采用微带线结构实现上述滤波耦合合一电路,可以降低电子设备的成本,减小滤波耦合合一电路的尺寸,提高滤波耦合合一电路的性能。Adopting the microstrip line structure to realize the above filter-coupling circuit can reduce the cost of electronic equipment, reduce the size of the filter-coupling circuit, and improve the performance of the filter-coupling circuit.
滤波耦合合一电路的性能指标可以通过散射(scatter,S)参数进行表征。对本申请实施例提供的滤波耦合合一电路采用相应的仿真软件进行仿真,得到滤波耦合合一电路的S参数如图17所示。其中,横坐标为频率,单位为千兆赫兹(GHz);纵坐标为S参数值,单位为分贝(dB)。其中,如图17的第1幅图所示,器件的1端口的回损S1,1在5G频带上大于17dB(即1、2、3#标识的位置);如图17的第2幅图所示,器件的插损S2,1在5G频带上小于0.62dB(即1、2、3#标识的位置),且对5G频带二次谐波的抑制大于19dB(即6、7#标识的位置),对2G频带的抑制大于38.6dB(即4、5#标识的位置);如图17的第3幅图所示,耦合度在5G频带上S3,1大于17.6dB(即1、2、3#标识的位置);如图17的第4幅图所示,隔离度S4,1在5G频带上大于38.6dB(即1、2、3#标识的位置)。综上,采用本申请实施例所设计的滤波耦合合一电路具有较好的射频指标,能满足相应的需求。The performance index of the filter-coupling circuit can be characterized by the scatter (S) parameter. The filter-coupling-in-one circuit provided in the embodiment of the present application is simulated using corresponding simulation software, and the S parameters of the filter-coupling-in-one circuit are obtained as shown in FIG. 17 . Wherein, the abscissa is the frequency, and the unit is gigahertz (GHz); the ordinate is the S parameter value, and the unit is decibel (dB). Among them, as shown in the first picture of Figure 17, the return loss S1,1 of port 1 of the device is greater than 17dB in the 5G frequency band (that is, the positions marked by #1, 2, and 3); as shown in the second picture of Figure 17 As shown, the insertion loss S2,1 of the device is less than 0.62dB in the 5G frequency band (that is, the positions marked by 1, 2, and 3#), and the suppression of the second harmonic of the 5G frequency band is greater than 19dB (that is, the positions marked by 6 and 7# location), the suppression of the 2G frequency band is greater than 38.6dB (that is, the location marked by 4, 5#); as shown in the third picture of Figure 17, the coupling degree is greater than 17.6dB on the 5G frequency , 3# marks); as shown in the fourth picture of Figure 17, the isolation S4,1 is greater than 38.6dB in the 5G frequency band (that is, the positions of 1, 2, 3# marks). To sum up, the filter-coupling integration circuit designed by the embodiment of the present application has a better radio frequency index and can meet corresponding requirements.
如图18所示,还提供了一种滤波耦合方法,应用于上述图5所示的滤波耦合合一电路。As shown in FIG. 18 , a filter coupling method is also provided, which is applied to the above-mentioned filter coupling integration circuit shown in FIG. 5 .
该方法可以包括以下步骤:The method may include the steps of:
S1801.对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号。S1801. Low-pass filter the first signal input from the input terminal 10 to output the second signal from the output terminal 11.
S1802.对第一信号进行耦合采样,以从耦合端12输出第三信号。S1802. Perform coupling sampling on the first signal, so as to output a third signal from the coupling end 12.
例如,该第一信号可以是PA输出的信号,该电路用于对PA输出的功率耦合到基带中进行预失真处理,以抵消PA工作在非线性区带来的失真,还用于对PA输出的信号进行低通滤波,降低PA的带外杂散。For example, the first signal may be the signal output by the PA, and the circuit is used to couple the power output by the PA to the baseband for pre-distortion processing, so as to offset the distortion caused by the PA working in the nonlinear region, and to The signal is low-pass filtered to reduce the out-of-band spurs of the PA.
根据本申请实施例提供的一种滤波耦合方法,通过复用低通滤波的支路,将耦合器的主信号线移到低通滤波支路上,将滤波和耦合功能合在一个器件上,减少了单板面积,降低了器件插损。According to a filter coupling method provided by the embodiment of the present application, by multiplexing the low-pass filtering branch, the main signal line of the coupler is moved to the low-pass filtering branch, and the filtering and coupling functions are combined on one device, reducing The area of the single board is reduced, and the insertion loss of the device is reduced.
所属领域的技术人员可以清楚地了解到,为描述的方便和简洁,上述描述的方法的具体工作过程,可以参考前述装置实施例中的描述,在此不再赘述。Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the method described above can refer to the description in the foregoing device embodiments, and details are not repeated here.
在本申请所提供的几个实施例中,应该理解到,所揭露的设备、装置和方法,可以通过其它的方式实现。例如,该单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如,多个单元或组件可以结合或者可以集成到另一个系统,或一些特征可以忽略,或不执行。所显示或讨论的相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。In the several embodiments provided in this application, it should be understood that the disclosed devices, devices and methods can be implemented in other ways. For example, the division of this unit is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored, or not implement. The mutual coupling, or direct coupling, or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。A unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
在上述实施例中,可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时,可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行该计算机程序指令时,全部或部分地产生按照本申请实施例的流程或功能。该计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。该计算机指令可以存储在计算机可读存储介质中,或者通过该计算机可读存储介质进行传输。该计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line,DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。该计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。该可用介质可以是只读存储器(read-only memory,ROM),或随机存取存储器(random access memory,RAM),或磁性介质,例如,软盘、硬盘、磁带、磁碟、或光介质,例如,数字通用光盘(digital versatile disc,DVD)、或者半导体介质,例如,固态硬盘(solid state disk,SSD)等。In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer instructions can be sent from one website site, computer, server, or data center to another via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) A website site, computer, server or data center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The usable medium can be read-only memory (read-only memory, ROM), or random access memory (random access memory, RAM), or magnetic medium, for example, floppy disk, hard disk, magnetic tape, magnetic disk, or optical medium, such as , a digital versatile disc (digital versatile disc, DVD), or a semiconductor medium, for example, a solid state disk (solid state disk, SSD) and the like.

Claims (20)

  1. 一种滤波耦合合一电路,其特征在于,用于对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号,且还用于对所述第一信号进行耦合采样,以从耦合端12输出第三信号。A filter-coupling circuit, characterized in that it is used to low-pass filter the first signal input from the input terminal 10 to output the second signal from the output terminal 11, and is also used to couple the first signal sampled to output a third signal from the coupled terminal 12.
  2. 如权利要求1所述的滤波耦合合一电路,其特征在于,所述滤波耦合合一电路包括:第一电容C2、第一电感L2、第二电容C3和第二电感L3,其中:The filter coupling unification circuit according to claim 1, wherein the filter coupling unification circuit comprises: a first capacitor C2, a first inductance L2, a second capacitor C3 and a second inductance L3, wherein:
    所述第一电容C2的第一端C21接地、第二端C22分别与所述输入端10、所述第一电感L2的第一端L21连接;The first terminal C21 of the first capacitor C2 is grounded, and the second terminal C22 is respectively connected to the input terminal 10 and the first terminal L21 of the first inductor L2;
    所述第二电容C3的第一端C31接地、第二端C32分别与所述输出端11、所述第一电感L2的第二端L22连接;The first terminal C31 of the second capacitor C3 is grounded, and the second terminal C32 is respectively connected to the output terminal 11 and the second terminal L22 of the first inductor L2;
    所述第二电感L3与所述第一电感L2耦合,所述第二电感L3的第一端L31与所述耦合端12连接、第二端L32与负载端13连接。The second inductance L3 is coupled to the first inductance L2 , the first end L31 of the second inductance L3 is connected to the coupling end 12 , and the second end L32 is connected to the load end 13 .
  3. 如权利要求2所述的滤波耦合合一电路,其特征在于,所述第一电容C2与所述第二端C22对应的一极为第一微带线区域C2a、所述第一端C21对应的一极为地,所述第一微带线区域C2a与地耦合形成电容。The filtering and coupling circuit according to claim 2, characterized in that, one pole of the first capacitor C2 corresponding to the second end C22 is the first microstrip line region C2a, and the pole corresponding to the first end C21 One pole is ground, and the first microstrip line region C2a is coupled with ground to form a capacitor.
  4. 如权利要求3所述的滤波耦合合一电路,其特征在于,所述第一微带线区域C2a为长条形。The filter-coupling circuit according to claim 3, wherein the first microstrip line region C2a is strip-shaped.
  5. 如权利要求2所述的滤波耦合合一电路,其特征在于:The filtering and coupling circuit according to claim 2, characterized in that:
    所述第一电容C2与所述第二端C22对应的一极为第二微带线区域C2d、所述第一端C21对应的一极为与地连通的第三微带线区域C2e,所述第二微带线区域C2d与所述第三微带线区域C2e耦合形成电容。One pole of the first capacitor C2 corresponding to the second terminal C22 is the second microstrip line region C2d, and one pole corresponding to the first terminal C21 is the third microstrip line region C2e connected to the ground. The second microstrip line region C2d is coupled with the third microstrip line region C2e to form a capacitor.
  6. 如权利要求5所述的滤波耦合合一电路,其特征在于,所述第二微带线区域C2d与所述第三微带线区域C2e均为长条形。The filter-coupling circuit according to claim 5, wherein the second microstrip line region C2d and the third microstrip line region C2e are both strip-shaped.
  7. 如权利要求3-6任一所述的滤波耦合合一电路,其特征在于:The filter-coupling circuit according to any one of claims 3-6, characterized in that:
    所述第二电容C3与所述第二端C32对应的一极为第四微带线区域C3a、所述第一端C31对应的一极为地,所述第四微带线区域C3a与地耦合形成电容。One pole of the second capacitor C3 corresponding to the second end C32 is the fourth microstrip line region C3a, and one pole corresponding to the first end C31 is the ground, and the fourth microstrip line region C3a is coupled with the ground to form a capacitance.
  8. 如权利要求7所述的滤波耦合合一电路,其特征在于,所述第四微带线区域C3a为长条形。The filter-coupling-integration circuit according to claim 7, wherein the fourth microstrip line region C3a is strip-shaped.
  9. 如权利要求7或8所述的滤波耦合合一电路,其特征在于:The filtering and coupling circuit according to claim 7 or 8, characterized in that:
    所述第二电容C3与所述第二端C32对应的一极为第五微带线区域C3d、所述第一端C31对应的一极为与地连通的第六微带线区域C3e,所述第五微带线区域C3d与所述第六微带线区域C3e耦合形成电容。One pole of the second capacitor C3 corresponding to the second end C32 is the fifth microstrip line region C3d, and one pole corresponding to the first end C31 is the sixth microstrip line region C3e connected to the ground. The fifth microstrip line region C3d is coupled with the sixth microstrip line region C3e to form a capacitor.
  10. 如权利要求9所述的滤波耦合合一电路,其特征在于,所述第五微带线区域C3d与所述第六微带线区域C3e均为长条形。The filter-coupling circuit according to claim 9, wherein the fifth microstrip line region C3d and the sixth microstrip line region C3e are both strip-shaped.
  11. 如权利要求2-10任一所述的滤波耦合合一电路,其特征在于,所述第一电感L2为第七微带线区域L2a,所述第二电感L3为第八微带线区域L3a。The filtering and coupling circuit according to any one of claims 2-10, wherein the first inductance L2 is the seventh microstrip line region L2a, and the second inductance L3 is the eighth microstrip line region L3a .
  12. 如权利要求11所述的滤波耦合合一电路,其特征在于,所述第七微带线区域L2a为长条形、“u”字形或“v”字形。The filter-coupling circuit according to claim 11, wherein the seventh microstrip line area L2a is strip-shaped, "u"-shaped or "v-shaped".
  13. 根据权利要求11或12所述的滤波耦合合一电路,其特征在于:According to claim 11 or 12 described filter coupling integration circuit, it is characterized in that:
    所述第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与所述第二电感L2和所述第三电感L3之间所需要的耦合度成正相关关系,和/或,所述第七微带线区域L2a与所述第八微带线区域L3a之间的缝隙宽度和/或长度被设置为与所述第二电感L2和所述第三电感L3之间所需要的隔离度成正相关关系;The width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be the same as that required between the second inductance L2 and the third inductance L3 The degree of coupling is positively correlated, and/or, the width and/or length of the gap between the seventh microstrip line region L2a and the eighth microstrip line region L3a is set to be the same as the second inductance L2 and the The required isolation between the third inductors L3 is positively correlated;
    所述输入端10与第八微带线区域L3a上的耦合端12之间的距离被设置为与所述第二电感L2和所述第三电感L3之间所需要的耦合度成反相关关系,和/或,所述输入端10与所述第八微带线区域L3a上的负载端13之间的距离被设置为与所述第二电感L2和所述第三电感L3之间所需要的隔离度成反相关关系。The distance between the input terminal 10 and the coupling terminal 12 on the eighth microstrip line region L3a is set to be inversely correlated with the required coupling degree between the second inductance L2 and the third inductance L3 , and/or, the distance between the input terminal 10 and the load terminal 13 on the eighth microstrip line region L3a is set to be equal to the required distance between the second inductance L2 and the third inductance L3 The degree of isolation is inversely correlated.
  14. 如权利要求11-13任一所述的滤波耦合合一电路,其特征在于,第八微带线区域L3a为“h”字形、“n”字形、或“7”字形。The filter-coupling circuit according to any one of claims 11-13, characterized in that the eighth microstrip line region L3a is in the shape of "h", "n" or "7".
  15. 根据权利要求11-14任一所述的滤波耦合合一电路,其特征在于:According to any one of claims 11-14, the filter coupling circuit is characterized in that:
    当所述第一电容C2与所述第二端C22对应的一极为第一微带线区域C2a、所述第一端C21对应的一极为地,所述第二电容C3与所述第二端C32对应的一极为第四微带线区域C3a、所述第一端C31对应的一极为地,所述第一微带线区域C2a和第四微带线区域C3a位于所述第七微带线区域L2a的第一侧D1,所述第八微带线区域L3a位于所述第七微带线区域L2a的第二侧D2;或When the pole of the first capacitor C2 corresponding to the second terminal C22 is the first microstrip line region C2a, and the pole corresponding to the first terminal C21 is grounded, the second capacitor C3 and the second terminal One pole corresponding to C32 is the fourth microstrip line region C3a, one pole corresponding to the first end C31 is ground, the first microstrip line region C2a and the fourth microstrip line region C3a are located on the seventh microstrip line the first side D1 of the region L2a, the eighth microstrip line region L3a is located on the second side D2 of the seventh microstrip line region L2a; or
    所述第八微带线区域L3a、所述第一微带线区域C2a和第四微带线区域C3a均位于所述第七微带线区域L2a的第一侧D1。The eighth microstrip line region L3a, the first microstrip line region C2a and the fourth microstrip line region C3a are all located on the first side D1 of the seventh microstrip line region L2a.
  16. 一种滤波耦合电路,其特征在于,包括:高通滤波电路和如权利要求1-15任一所述的滤波耦合合一电路;A filter coupling circuit, characterized in that it comprises: a high-pass filter circuit and a filter coupling integration circuit according to any one of claims 1-15;
    所述高通滤波电路,用于为所述滤波耦合合一电路提供高通滤波后的信号,或者为所述滤波耦合合一电路输出的信号进行高通滤波。The high-pass filter circuit is used to provide the high-pass filtered signal for the filter coupling and unification circuit, or perform high-pass filtering for the signal output by the filter coupling and unification circuit.
  17. 如权利要求16所述的滤波耦合电路,其特征在于,所述滤波耦合电路还包括:低通滤波电路,所述低通滤波电路的输入端与所述滤波耦合合一电路的输出端11相连。The filter coupling circuit according to claim 16, wherein the filter coupling circuit further comprises: a low-pass filter circuit, the input terminal of the low-pass filter circuit is connected to the output terminal 11 of the filter coupling circuit .
  18. 如权利要求16或17所述的滤波耦合合一电路,其特征在于,所述高通滤波电路为N阶高通滤波电路,N>=2。The filter-coupling integration circuit according to claim 16 or 17, characterized in that, the high-pass filter circuit is an N-order high-pass filter circuit, N>=2.
  19. 一种滤波耦合合一方法,其特征在于,所述方法应用于权利要求1-15任一所述的滤波耦合合一电路,所述方法包括:A filter coupling integration method, characterized in that the method is applied to the filter coupling integration circuit described in any one of claims 1-15, the method comprising:
    对从输入端10输入的第一信号进行低通滤波以从输出端11输出第二信号;performing low-pass filtering on the first signal input from the input terminal 10 to output the second signal from the output terminal 11;
    对所述第一信号进行耦合采样,以从耦合端12输出第三信号。Coupling sampling is performed on the first signal to output a third signal from the coupling terminal 12 .
  20. 一种电子设备,其特征在于,包括如权利要求1-15任一所述的滤波耦合合一电路。An electronic device, characterized in that it comprises the filter-coupling-integration circuit according to any one of claims 1-15.
PCT/CN2022/079423 2021-06-30 2022-03-04 Filtering-coupling integrated circuit, method, and device WO2023273391A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001177304A (en) * 1999-12-20 2001-06-29 Saito Kiyouchiyou Tokushu Kiki Kk Polar type band pass filter
US20060121874A1 (en) * 2003-05-12 2006-06-08 Epcos Ag Low-loss transmitter module
WO2014050623A1 (en) * 2012-09-26 2014-04-03 太陽誘電株式会社 Directional coupling circuit device
CN109560360A (en) * 2018-12-11 2019-04-02 深圳飞骧科技有限公司 A kind of directional coupler

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001177304A (en) * 1999-12-20 2001-06-29 Saito Kiyouchiyou Tokushu Kiki Kk Polar type band pass filter
US20060121874A1 (en) * 2003-05-12 2006-06-08 Epcos Ag Low-loss transmitter module
WO2014050623A1 (en) * 2012-09-26 2014-04-03 太陽誘電株式会社 Directional coupling circuit device
CN109560360A (en) * 2018-12-11 2019-04-02 深圳飞骧科技有限公司 A kind of directional coupler

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