WO2023249821A1 - Adaptateurs de quantification - Google Patents

Adaptateurs de quantification Download PDF

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Publication number
WO2023249821A1
WO2023249821A1 PCT/US2023/024877 US2023024877W WO2023249821A1 WO 2023249821 A1 WO2023249821 A1 WO 2023249821A1 US 2023024877 W US2023024877 W US 2023024877W WO 2023249821 A1 WO2023249821 A1 WO 2023249821A1
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learnable
quantization
ann
transformer
model
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PCT/US2023/024877
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English (en)
Inventor
Minseop Park
Jaeseong YOU
Simyung CHANG
Markus Nagel
Chirag Sureshbhai Patel
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Qualcomm Incorporated
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Publication of WO2023249821A1 publication Critical patent/WO2023249821A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/088—Non-supervised learning, e.g. competitive learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/09—Supervised learning

Definitions

  • aspects of the present disclosure generally relate to quantization in artificial neural networks.
  • Artificial neural networks may comprise interconnected groups of artificial neurons (e.g., neuron models).
  • the artificial neural network may be a computational device or be represented as a method to be performed by a computational device.
  • Convolutional neural networks are a type of feed-forward artificial neural network.
  • Convolutional neural networks may include collections of neurons that each have a receptive field and that collectively tile an input space.
  • Convolutional neural networks such as deep convolutional neural networks (DCNs) have numerous applications.
  • these neural network architectures are used in various technologies, such as image recognition, speech recognition, acoustic scene classification, keyword spotting, autonomous driving, and other classification tasks.
  • Edge devices such as smartphones are widely used. Given the many useful applications of neural networks, there is increasing demand for use of edge devices and for personalized services for such edge devices. However, edge devices have limited computational resources and generalized models may utilize more complex networks and computational resources.
  • a processor-implemented method includes receiving an artificial neural network (ANN) model, the ANN model having a number of channels of target activations.
  • the method further includes incorporating a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN.
  • the quantization module scales a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • the method may still further includes operating the adapted ANN model to generate an inference based on the learnable quantization module parameter.
  • Another aspect of the present disclosure is directed to an apparatus including means for receiving an artificial neural network (ANN) model, the ANN model having a number of channels of target activations.
  • the apparatus further includes means for incorporating a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN.
  • the quantization module scales a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • the apparatus may still further include means for operating the adapted ANN model to generate an inference based on the learnable quantization module parameter.
  • a non-transitory computer- readable medium with non-transitory program code recorded thereon is disclosed.
  • the program code is executed by a processor and includes program code to receive an artificial neural network (ANN) model, the ANN model having a number of channels of target activations.
  • the program code further includes program code to incorporate a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN.
  • the quantization module scales a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • the program code may still further include program code to operate the adapted ANN model to generate an inference based on the learnable quantization module parameter.
  • Another aspect of the present disclosure is directed to an apparatus having a memory and one or more processors coupled to the memory.
  • the processor(s) is configured to receive an artificial neural network (ANN) model, the ANN model having a number of channels of target activations.
  • the processor(s) is further configured to incorporate a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN.
  • the quantization module scales a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • the processor(s) may still further be configured to operate the adapted ANN model to generate an inference based on the learnable quantization module parameter.
  • FIGURE 1 illustrates an example implementation of a neural network using a system-on-a-chip (SOC), including a general-purpose processor in accordance with certain aspects of the present disclosure.
  • SOC system-on-a-chip
  • FIGURES 2A, 2B, and 2C are diagrams illustrating a neural network in accordance with various aspects of the present disclosure.
  • FIGURE 2D is a diagram illustrating an exemplary deep convolutional network (DCN) in accordance with various aspects of the present disclosure.
  • FIGURE 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) in accordance with various aspects of the present disclosure.
  • DCN deep convolutional network
  • FIGURE 4 is a block diagram illustrating an exemplary software architecture that may modularize artificial intelligence (Al) functions, in accordance with various aspects of the present disclosure.
  • FIGURE 5 is a block diagram illustrating an example implementation of a quadapter module in an artificial neural network (ANN), in accordance with various aspects of the present disclosure.
  • ANN artificial neural network
  • FIGURE 6 is a diagram illustrating example pseudocode for training a quadapter module, in accordance with various aspects of the present disclosure.
  • FIGURE 7 is a flow diagram illustrating a processor-implemented method for adaptive quantization in an artificial neural network (ANN), in accordance with various aspects of the present disclosure.
  • ANN artificial neural network
  • transformer architectures such as (but not limited to) bi-directional encoder representations from transformers (BERT), robustly optimized BERT approach (RoBERTa), XLNet, Transformer-XL, and the generative pre-trained transformer (GPT) family of transformers (e.g., GPT-2, GPT-3, GPT-4, etc.), language models may be pre-trained from large corpora of unlabeled text. Accordingly, such transformer architectures have become popular building blocks in conventional NLP pipelines, as well as in other areas such as computer vision and audio processing.
  • transformer-based models may be extremely large, sometimes exceeding billions of parameters, for example.
  • efficient deployment of such transformer-based models on resource-constrained embedded systems including mobile devices (e.g., smartphones) and Internet of Things (loT) devices, and even some systems in data centers, is challenging due to increased latency, energy consumption, and a prohibitively large memory footprint.
  • neural network quantization reduces memory consumption by using low-bit precision for weight and activation tensors.
  • neural network quantization may reduce inference time and improve energy efficiency by employing low-bit fixed-point arithmetic instead of floating-point arithmetic.
  • Quantization may introduce additional noise in the neural network that may lead to a reduction in the model’s accuracy as well as an increase in computational complexity. For instance, transformer models may have numerous outliers in their activations. These activation outliers may lead to a larger quantization error.
  • Some conventional approaches attempt to address the large quantization error by applying quantization-aware training (QAT).
  • QAT involves a fine-tuning process based on the training dataset and training pipeline identical to the original model.
  • QAT procedures may incur overfitting because QAT changes the parameters of the pretrained model when adapting to an unfamiliar distribution or domain.
  • many pre-trained language models may not grant access to the training dataset and pipeline forcing users to rely on arbitrary datasets and training pipelines for fine-tuning, which may also result in the model overfitting to the fine-tuning data.
  • aspects of the present disclosure are directed to an adapter for improved quantization in neural network models.
  • a quantization adapter (quadapter) module may adapt to a domain shift resulting from quantization while preserving the initial model parameters.
  • quantization-aware training and/or post-training quantization may also be applied. Accordingly, aspects of the present disclosure may beneficially reduce, and in some aspects, prevent overfitting when fine-tuning data for QAT, and improve quantization performance in data-scarce environments, as well as for in distribution settings.
  • FIGURE 1 illustrates an example implementation of a system-on-a-chip (SOC) 100, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for adaptive quantization in an artificial neural network.
  • Variables e.g., neural signals and synaptic weights
  • system parameters associated with a computational device e.g., neural network with weights
  • delays e.g., frequency bin information, and task information
  • NPU neural processing unit
  • NPU neural processing unit
  • GPU graphics processing unit
  • DSP digital signal processor
  • Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or may be loaded from a memory block 118.
  • the SOC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104, a DSP 106, a connectivity block 110, which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures.
  • the NPU 108 is implemented in the CPU 102, DSP 106, and/or GPU 104.
  • the SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and/or navigation module 120, which may include a global positioning system.
  • the SOC 100 may be based on an ARM instruction set.
  • the instructions loaded into the general -purpose processor 102 may include code to receive an artificial neural network (ANN) model, the ANN model having a plurality of channels of target activations.
  • the general -purpose processor 102 may also include code to incorporate a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN.
  • the quantization module scales a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • the general -purpose processor 102 may further include code to operate the adapted ANN model to generate an inference based on the learnable quantization module parameter.
  • Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning.
  • a shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs.
  • Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise. Deep learning architectures, in contrast, may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new types of features that a human might not have considered.
  • a deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For instance, higher layers may learn to represent complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases.
  • Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure.
  • the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes.
  • Neural networks may be designed with a variety of connectivity patterns.
  • feed-forward networks information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers.
  • a hierarchical representation may be built up in successive layers of a feed-forward network, as described above.
  • Neural networks may also have recurrent or feedback (also called top- down) connections. In a recurrent connection, the output from a neuron in a given layer may be communicated to another neuron in the same layer.
  • a recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence.
  • a connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection.
  • a network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.
  • FIGURE 2A illustrates an example of a fully connected neural network 202.
  • a neuron in a first layer may communicate its output to every neuron in a second layer, so that each neuron in the second layer will receive input from every neuron in the first layer.
  • FIGURE 2B illustrates an example of a locally connected neural network 204.
  • a neuron in a first layer may be connected to a limited number of neurons in the second layer.
  • a locally connected layer of the locally connected neural network 204 may be configured so that each neuron in a layer will have the same or a similar connectivity pattern, but with connections strengths that may have different values (e.g., 210, 212, 214, and 216).
  • the locally connected connectivity pattern may give rise to spatially distinct receptive fields in a higher layer because the higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the network.
  • FIGURE 2C illustrates an example of a convolutional neural network 206.
  • the convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208).
  • Convolutional neural networks may be well suited to problems in which the spatial location of inputs is meaningful.
  • FIGURE 2D illustrates a detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capturing device 230, such as a car-mounted camera.
  • the DCN 200 of the current example may be trained to identify traffic signs and a number provided on the traffic sign.
  • the DCN 200 may be trained for other tasks, such as identifying lane markings or identifying traffic lights.
  • the DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222.
  • the DCN 200 may include a feature extraction section and a classification section.
  • a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218.
  • the convolutional kernel for the convolutional layer 232 may be a 5x5 kernel that generates 28x28 feature maps.
  • the convolutional kernels may also be referred to as filters or convolutional filters.
  • the first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220.
  • the max pooling layer reduces the size of the first set of feature maps 218. That is, a size of the second set of feature maps 220, such as 14x14, is less than the size of the first set of feature maps 218, such as 28x28.
  • the reduced size provides similar information to a subsequent layer while reducing memory consumption.
  • the second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).
  • the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number that corresponds to a possible feature of the image 226, such as “sign,” “60,” and “100.” A softmax function (not shown) may convert the numbers in the second feature vector 228 to a probability. As such, an output 222 of the DCN 200 may be a probability of the image 226 including one or more features.
  • the probabilities in the output 222 for “sign” and “60” are higher than the probabilities of the others of the output 222, such as “30,” “40,” “50,” “70,” “80,” “90,” and “100”.
  • the output 222 produced by the DCN 200 may likely be incorrect.
  • an error may be calculated between the output 222 and a target output.
  • the target output is the ground truth of the image 226 (e.g., “sign” and “60”).
  • the weights of the DCN 200 may then be adjusted so the output 222 of the DCN 200 is more closely aligned with the target output.
  • a learning algorithm may compute a gradient vector for the weights.
  • the gradient may indicate an amount that an error would increase or decrease if the weight were adjusted.
  • the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer.
  • the gradient may depend on the value of the weights and on the computed error gradients of the higher layers.
  • the weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as “back propagation” as it involves a “backward pass” through the neural network.
  • the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient.
  • This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level.
  • the DCN 200 may be presented with new images and a forward pass through the DCN 200 may yield an output 222 that may be considered an inference or a prediction of the DCN 200.
  • Deep belief networks are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs).
  • RBM Restricted Boltzmann Machines
  • An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning.
  • the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors
  • the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.
  • DCNs are networks of convolutional networks, configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.
  • DCNs may be feed-forward networks.
  • the connections from a neuron in a first layer of a DCN to a group of neurons in the next higher layer are shared across the neurons in the first layer.
  • the feed-forward and shared connections of DCNs may be exploited for fast processing.
  • the computational burden of a DCN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.
  • each layer of a convolutional network may be considered a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information.
  • the outputs of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e.g., 220) receiving input from a range of neurons in the previous layer (e.g., feature maps 218) and from each of the multiple channels.
  • the values in the feature map may be further processed with a non-linearity, such as a rectification, max(0, x). Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.
  • a non-linearity such as a rectification, max(0, x).
  • Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.
  • the performance of deep learning architectures may increase as more labeled data points become available or as computational power increases. Modem deep neural networks are routinely trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms may further boost the performance of deep learning. Rectified linear units may reduce a training issue known as vanishing gradients. New training techniques may reduce over-fitting and thus enable larger models to achieve better generalization. Encapsulation techniques may abstract data in a given receptive field and further boost overall performance.
  • FIGURE 3 is a block diagram illustrating a deep convolutional network (DCN) 350.
  • the deep convolutional network 350 may include multiple different types of layers based on connectivity and weight sharing.
  • the deep convolutional network 350 includes the convolution blocks 354A, 354B.
  • Each of the convolution blocks 354A, 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.
  • CONV convolution layer
  • LNorm normalization layer
  • MAX POOL max pooling layer
  • the convolution layers 356 may include one or more convolutional filters, which may be applied to the input data to generate a feature map.
  • the normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition.
  • the max pooling layers 360 may provide down sampling aggregation over space for local invariance and dimensionality reduction.
  • the parallel filter banks for example, of a deep convolutional network may be loaded on a CPU 102 or GPU 104 of an SOC 100 (e.g., FIGURE 1) to achieve high performance and low power consumption.
  • the parallel filter banks may be loaded on the DSP 106 or an ISP 116 of an SOC 100.
  • the deep convolutional network 350 may access other processing blocks that may be present on the SOC 100, such as sensor processor 114 and navigation module 120, dedicated, respectively, to sensors and navigation.
  • the deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2).
  • the deep convolutional network 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350 are weights (not shown) that are to be updated.
  • LR logistic regression
  • each of the layers may serve as an input of a succeeding one of the layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn hierarchical feature representations from input data 352 (e.g., images, audio, video, sensor data and/or other input data) supplied at the first of the convolution blocks 354A.
  • the output of the deep convolutional network 350 is a classification score 366 for the input data 352.
  • the classification score 366 may be a set of probabilities, where each probability is the probability of the input data including a feature from a set of features.
  • FIGURE 4 is a block diagram illustrating an exemplary software architecture 400 that may modularize artificial intelligence (Al) functions.
  • applications may be designed that may cause various processing blocks of a system-on-a-chip (SoC) 420 (for example a CPU 422, a DSP 424, a GPU 426 and/or an NPU 428) (which may be similar to SoC 100 of FIGURE 1) to support adaptive quantization for an Al application 402, according to aspects of the present disclosure.
  • SoC system-on-a-chip
  • the architecture 400 may, for example, be included in a computational device, such as a smartphone.
  • the Al application 402 may be configured to call functions defined in a user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location at which the computational device including the architecture 400 currently operates.
  • the Al application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake.
  • the Al application 402 may make a request to compiled program code associated with a library defined in an Al function application programming interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide an inference response based on video and positioning data, for example.
  • API Al function application programming interface
  • the Al application 402 may cause the run-time engine 408, for example, to request an inference at a particular time interval or triggered by an event detected by the user interface of the Al application 402.
  • the run-time engine 408 may in turn send a signal to an operating system in an operating system (OS) space, such as a Linux Kernel 412, running on the SoC 420.
  • OS operating system
  • the operating system may cause a continuous relaxation of quantization to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof.
  • the CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver 414, 416, or 418 for, respectively, the DSP 424, the GPU 426, or the NPU 428.
  • a driver such as a driver 414, 416, or 418 for, respectively, the DSP 424, the GPU 426, or the NPU 428.
  • the deep neural network may be configured to run on a combination of processing blocks, such as the CPU 422, the DSP 424, and the GPU 426, or may be run on the NPU 428.
  • the Al application 402 may be configured to call functions defined in the user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location in which the computational device including the architecture 400 currently operates.
  • the Al application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake.
  • the Al application 402 may make a request to compiled program code associated with a library defined in a SceneDetect application programming interface (API) 406 to provide an estimate of the current scene. This request may ultimately rely on the output of a differential neural network configured to provide scene estimates based on video and positioning data, for example.
  • API Application programming interface
  • the run-time engine 408, which may be compiled code of a Runtime Framework, may be further accessible to the Al application 402.
  • the Al application 402 may cause the run-time engine 408, for example, to request a scene estimate at a particular time interval or triggered by an event detected by the user interface of the Al application 402.
  • the run-time engine 408 may in turn send a signal to the operating system 410, such as the Kernel 412, running on the SoC 420.
  • the operating system 410 may cause a computation to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof.
  • the CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as the driver 414-418 for the DSP 424, for the GPU 426, or for the NPU 428.
  • the differential neural network may be configured to run on a combination of processing blocks, such as the CPU 422 and the GPU 426, or may be run on the NPU 428.
  • an artificial neural network may be adapted by incorporating a quantization adapter module (the quantization adapter module may be referred to as a “quadapter”).
  • a quadapter may linearly scale the input channels of the ANN and revert after quantization. As such, the identity relation may be maintained to enable retention of the model parameters.
  • the quadapter may include a set of learnable parameters and may be configured to perform a linear scaling before or after a quantizer Q for a target activation. That is, the quadapter may linearly scale the input channels of the ANN and revert them back after quantization. In doing so, an identity relationship between quantization parameters may enable model parameters to be maintained. Instead, only a set of learnable quantization parameters are adapted.
  • a quadapter module output y may be defined as follows:
  • ⁇ 2 0i and ⁇ 2e 2 are the weight quantizers and Q 0a is the activation quantizer.
  • the quantization (quadapter) parameter a may be trained during a training phase and fused (e.g., fixed) during an inference phase.
  • W. and b.' represent fused weights and biases of a first linear layer.
  • W 2 represents fused weights of a second layer at the inference time (e.g., as in Equation 3).
  • the forward scaling and the inverse scaling may correspond across three nested quantizers that may be strongly nonlinear operations. Therefore, the quadapter parameter a should be learned rather than set analytically because a single analytical solution may not be sufficient to balance the quantization burden between the two layers.
  • FIGURE 5 is a block diagram illustrating an example implementation 500 of a quadapter module 502 in an artificial neural network (ANN), in accordance with various aspects of the present disclosure.
  • the quadapter module 502 is configured, as described, to apply the quadapter parameter a to weights and biases of a preceding linear layer (e.g., layer normalization (LN) layer).
  • the quadapter module 502 may also apply an inverse of the quadapter parameter a to weights of the succeeding layer (e.g., a fully-connected (FC) layer).
  • the quantizer parameter Q may apply a quantization process to weights and activations of each layer of the ANN.
  • the quadapter module 502 is inserted in an ANN 504.
  • the ANN 504 has a transformer architecture.
  • the quadapter module 502 may be included in other types of ANNs.
  • a single transformer block is shown in FIGURE 5.
  • the ANN 504 may include multiple transformer blocks.
  • One or more instances of the quadapter module 502 may be incorporated into the ANN 504.
  • a first quadapter module 502a may be inserted between a first LN layer 506a and an attention layer 508.
  • a second quadapter module 502b may be inserted between a second LN layer 506b and a multilayer perceptron (MLP) layer 510.
  • MLP multilayer perceptron
  • a quadapter module 502 may also be included between a final LN layer and a final logit projection.
  • FIGURE 6 is a diagram illustrating example pseudocode 600 for training a quadapter module, in accordance with various aspects of the present disclosure.
  • the learning of a quadapter module may be conducted in two phases: a block-wise calibration phase 602 and an end-to-end fine-tuning phase 604.
  • each of the quadapter module instances e.g., 502a, 502b
  • each quadapter module may be trained independently on a per-quadapter module basis.
  • the local objective for each block may, for example, be the L2 loss: arg
  • the quadapter parameters a are learned by minimizing the block-wise quantization error with the calibration data for quantization.
  • the quadapter module output y may be computed in a dynamic quantization mode, where the statistics are obtained per batch.
  • the quantization parameters Q minimum/maximum may be computed dynamically in every batch considering the effect of the quadapter parameters.
  • a quadapter module (e.g., 502a, 502b) resulting from the block-wise calibration phase 602 is a post-training quantization (PTQ) approach that is independent of the end-to- end fine-tuning phase 604.
  • PTQ post-training quantization
  • the end-to-end fine-tuning phase 604 may begin with more accommodating quantization parameters (e.g., less extreme minimum/maximum statistics) because more moderate values may be produced in contrast to more extreme outliers during the blockwise calibration phase 602. As a result, the fine-tuning process may converge more quickly.
  • the statistics for quantization may be computed as in a static quantization based on the same calibration data as in the block-wise calibration phase 602.
  • the quadapter module e.g., 502a, 502b
  • the quadapter module may then be trained to minimize the end-to-end task loss using a training data set.
  • the quantization parameters may be jointly learned while the ANN model parameters (e.g., weights) may be fixed.
  • FIGURE 7 is a flow diagram illustrating a processor-implemented method 700 for adaptive quantization in an artificial neural network, in accordance with various aspects of the present disclosure.
  • the processor-implemented method 700 may be performed by a processor such as CPU 102, GPU 104, or NPU 108, for example.
  • the processor receives an artificial neural network (ANN) model.
  • the ANN model has multiple channels of target activations.
  • the ANN may comprise a transformer neural network such as (but not limited to) bi-directional encoder representations from transformers (BERT), a robustly optimized BERT approach (RoBERTa)-based transformer, an XLNet-based transformer, Transformer-XL-based transformer, or a generative pre-trained transformer (GPT), for instance.
  • the ANN model may comprise a pre-trained model.
  • the processor incorporates a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN.
  • the quantization module scales a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • the quadapter module 502a may be inserted between the first LN layer 506a and the attention layer 508 of the ANN 504.
  • the processor may optionally operate the adapted ANN model to generate an inference based on the learnable quantization module parameter.
  • the adapted ANN model may operate to generate the inference based on a learnable quantization parameter.
  • the quantization parameter may be determined based on a task loss of the adapted ANN model.
  • a processor-implemented method comprising: receiving an artificial neural network (ANN) model, the ANN model having a plurality of channels of target activations; and incorporating a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • ANN artificial neural network
  • the processor-implemented method of any of clauses 1-5 in which the ANN model comprises a transformer neural network model.
  • the transformer neural network model comprises one of a bi-directional encoder representations from transformers (BERT), a robustly optimized BERT approach (RoBERTa)-based transformer, an XLNet-based transformer, a Transformer-XL-based transformer, or a generative pre-trained transformer (GPT).
  • An apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor configured: to receive an artificial neural network (ANN) model, the ANN model having a plurality of channels of target activations; and to incorporate a quantization module between a first linear layer of the ANN and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • ANN artificial neural network
  • the at least one processor is further configured to scale a target activation in each channel of the plurality of channels of target activations based on a learnable quantization parameter.
  • the transformer neural network model comprises one of a bi-directional encoder representations from transformers (BERT), a robustly optimized BERT approach (RoBERT a)-based transformer, an XLNet-based transformer, a Transformer-XL-based transformer, or a generative pretrained transformer (GPT).
  • a non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor and comprising: program code to receive an artificial neural network (ANN) model, the ANN model having a plurality of channels of target activations; and program code to incorporate a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • ANN artificial neural network
  • An apparatus comprising: means for receiving an artificial neural network (ANN) model, the ANN model having a plurality of channels of target activations; and means for incorporating a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on a learnable quantization module parameter and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameter.
  • ANN artificial neural network
  • the ANN model comprises a transformer neural network model.
  • the transformer neural network model comprises one of a bi-directional encoder representations from transformers (BERT), a robustly optimized BERT approach (RoBERT a)-based transformer, an XLNet-based transformer, a Transformer-XL-based transformer, or a generative pretrained transformer (GPT).
  • the receiving means, incorporating means, operating means, determining means, scaling means, and/or training means may be the GPU 104, program memory associated with the GPU 104, fully connected layers 362, NPU 428, and/or the routing connection processing unit 216 configured to perform the functions recited.
  • the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.
  • the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions.
  • the means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor.
  • ASIC application specific integrated circuit
  • determining encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining and the like. Additionally, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing, and the like. [0079] As used, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array signal
  • PLD programmable logic device
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • a software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth.
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • registers a hard disk, a removable disk, a CD-ROM and so forth.
  • a software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media.
  • a storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • the methods disclosed comprise one or more steps or actions for achieving the described method.
  • the method steps and/or actions may be interchanged with one another without departing from the scope of the claims.
  • the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
  • an example hardware configuration may comprise a processing system in a device.
  • the processing system may be implemented with a bus architecture.
  • the bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints.
  • the bus may link together various circuits including a processor, machine-readable media, and a bus interface.
  • the bus interface may be used to connect a network adapter, among other things, to the processing system via the bus.
  • the network adapter may be used to implement signal processing functions.
  • a user interface e.g., keypad, display, mouse, joystick, etc.
  • the bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.
  • the processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media.
  • the processor may be implemented with one or more general-purpose and/or specialpurpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software.
  • Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof.
  • RAM random access memory
  • ROM read only memory
  • PROM programmable read-only memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable Read-only memory
  • registers magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof.
  • the machine-readable media may be embodied in a computer-program product.
  • the computer-program product may comprise packaging materials.
  • the machine-readable media may be part of the processing system separate from the processor.
  • the machine-readable media, or any portion thereof may be external to the processing system.
  • the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface.
  • the machine-readable media, or any portion thereof may be integrated into the processor, such as the case may be with cache and/or general register files.
  • the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.
  • the processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture.
  • the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described.
  • the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure.
  • ASIC application specific integrated circuit
  • FPGAs field programmable gate arrays
  • PLDs programmable logic devices
  • controllers state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure.
  • the machine-readable media may comprise a number of software modules.
  • the software modules include instructions that, when executed by the processor, cause the processing system to perform various functions.
  • the software modules may include a transmission module and a receiving module.
  • Each software module may reside in a single storage device or be distributed across multiple storage devices.
  • a software module may be loaded into RAM from a hard drive when a triggering event occurs.
  • the processor may load some of the instructions into cache to increase access speed.
  • One or more cache lines may then be loaded into a general register file for execution by the processor.
  • Computer- readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage medium may be any available medium that can be accessed by a computer.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium.
  • computer-readable media may comprise non-transitory computer- readable media (e.g., tangible media).
  • computer-readable media may comprise transitory computer- readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.
  • certain aspects may comprise a computer program product for performing the operations presented.
  • a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described.
  • the computer program product may include packaging material.
  • modules and/or other appropriate means for performing the methods and techniques described can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable.
  • a user terminal and/or base station can be coupled to a server to facilitate the transfer of means for performing the methods described.
  • various methods described can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device.
  • storage means e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.
  • CD compact disc
  • floppy disk etc.
  • any other suitable technique for providing the methods and techniques described to a device can be utilized.

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Abstract

Un procédé mis en œuvre par processeur de quantification adaptative dans un réseau de neurones artificiels (ANN) comprend la réception d'un modèle ANN. Le modèle ANN comporte de multiples canaux d'activations cibles. Un module de quantification est incorporé entre une première couche linéaire de l'ANN et une seconde couche linéaire de l'ANN pour générer un ANN adapté. Le module de quantification met à l'échelle un premier ensemble de pondérations et de biais de la première couche linéaire sur la base d'un paramètre de module de quantification pouvant être appris et met à l'échelle un second ensemble de pondérations de la seconde couche linéaire sur la base d'un inverse du paramètre de module de quantification pouvant être appris.
PCT/US2023/024877 2022-06-24 2023-06-08 Adaptateurs de quantification WO2023249821A1 (fr)

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US18/330,990 US20230419087A1 (en) 2022-06-24 2023-06-07 Adapters for quantization
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200302299A1 (en) * 2019-03-22 2020-09-24 Qualcomm Incorporated Systems and Methods of Cross Layer Rescaling for Improved Quantization Performance

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US20200302299A1 (en) * 2019-03-22 2020-09-24 Qualcomm Incorporated Systems and Methods of Cross Layer Rescaling for Improved Quantization Performance

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LI ZHEXIN ET AL: "Fixed-point Quantization for Vision Transformer", 2021 CHINA AUTOMATION CONGRESS (CAC), IEEE, 22 October 2021 (2021-10-22), pages 7282 - 7287, XP034100275, DOI: 10.1109/CAC53003.2021.9728246 *
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