WO2023059723A1 - Compression de modèle par analyse en composantes principales parcimonieuse quantifiée - Google Patents

Compression de modèle par analyse en composantes principales parcimonieuse quantifiée Download PDF

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WO2023059723A1
WO2023059723A1 PCT/US2022/045785 US2022045785W WO2023059723A1 WO 2023059723 A1 WO2023059723 A1 WO 2023059723A1 US 2022045785 W US2022045785 W US 2022045785W WO 2023059723 A1 WO2023059723 A1 WO 2023059723A1
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matrix
layer
latent
codebook
weight tensor
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PCT/US2022/045785
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English (en)
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Andrey Kuzmin
Marinus Willem VAN BAALEN
Markus Nagel
Arash BEHBOODI
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Qualcomm Incorporated
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Publication of WO2023059723A1 publication Critical patent/WO2023059723A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/084—Backpropagation, e.g. using gradient descent

Definitions

  • aspects of the present disclosure generally relate to compressing a neural network model.
  • Artificial neural networks may comprise interconnected groups of artificial neurons (e.g., neuron models).
  • the artificial neural network may be a computational device or represented as a method to be performed by a computational device.
  • Convolutional neural networks such as deep convolutional neural networks, are a type of feed-forward artificial neural network.
  • Convolutional neural networks may include layers of neurons that may be configured in a tiled receptive field.
  • Deep neural networks such as deep convolutional neural networks
  • deep neural networks consume a large amount of resources, such as computational, power, and/or memory resources.
  • Transferring weight data in deep neural networks may be a significant contributor to both inference time resource consumption and latency.
  • processing cores of a device associated with the deep neural network may be idle as weights of the deep neural network are transferred from off-chip to on-chip memory of the device.
  • a processor-implemented method includes retrieving, for a layer of an artificial neural network, a codebook matrix representing a codebook and a latent matrix representing linear coefficients.
  • the processor-implemented method further includes determining, for the layer, the weight tensor based on a product of the codebook matrix and the latent matrix.
  • the processor- implemented method still further includes processing, at the layer, an input based on the weight tensor.
  • Another aspect of the present disclosure is directed to an apparatus including means for retrieving, for a layer an artificial neural network, a codebook matrix representing a codebook and a latent matrix representing linear coefficients.
  • the apparatus further includes means for determining, for the layer, the weight tensor based on a product of the codebook matrix and the latent matrix.
  • the apparatus still further includes means for processing, at the layer, an input based on the weight tensor.
  • a non-transitory computer- readable medium with non-transitory program code recorded thereon is disclosed.
  • the program code is executed by a processor and includes program code to retrieve, for a layer of a set of layers of an artificial neural network, a codebook matrix representing a codebook and a latent matrix representing linear coefficients.
  • the program code further includes program code to determine, for the layer, the weight tensor based on a product of the codebook matrix and the latent matrix.
  • the program code still further includes program code to process, at the layer, an input based on the weight tensor.
  • Another aspect of the present disclosure is directed to an apparatus having a processor, and a memory coupled with the processor and storing instructions operable, when executed by the processor, to cause the apparatus to retrieve, for a layer of an artificial neural network, a codebook matrix representing a codebook and a latent matrix representing linear coefficients. Execution of the instructions also cause the apparatus to determine, for the layer, the weight tensor based on a product of the codebook matrix and the latent matrix. Execution of the instructions further cause the apparatus to process, at the layer, an input based on the weight tensor. [0009] Aspects generally include a method, apparatus, system, computer program product, non-transitory computer-readable medium, user equipment, base station, wireless communications device, and processing system as substantially described with reference to and as illustrated by the accompanying drawings and specification.
  • FIGURE 1 illustrates an example implementation of designing a neural network using a system-on-a-chip (SOC), including a general-purpose processor, in accordance with certain aspects of the present disclosure.
  • SOC system-on-a-chip
  • FIGURES 2A, 2B, and 2C are diagrams illustrating a neural network, in accordance with aspects of the present disclosure.
  • FIGURE 2D is a diagram illustrating an exemplary deep convolutional network (DCN), in accordance with aspects of the present disclosure.
  • FIGURE 3 is a block diagram illustrating an exemplary deep convolutional network (DCN), in accordance with aspects of the present disclosure.
  • FIGURE 4 is a block diagram illustrating an example of approximating an original weight tensor, in accordance with various aspects of the present disclosure.
  • FIGURE 5 illustrates a flow diagram illustrating an example process for an artificial neural network, in accordance with some aspects of the present disclosure.
  • Deep neural networks may be used in a variety of tasks on a variety of devices.
  • DNNs consume a large amount of resources of a device, such as computational, power, and/or memory resources. Therefore, deployment of a DNN on some devices remains challenging due to limited resources of such devices.
  • edge devices such as mobile devices and Internet-of-Things (loT) devices may be subject to computational and memory constraints.
  • LoT Internet-of-Things
  • it may be difficult to deploy a DNN on an edge device because an amount of computational power and/or memory use of the DNN may be greater than an amount of computational power and/or memory available at the edge device.
  • a DNN deployed on a cloud computing system may not be subject to computational and memory constraints.
  • cloud computing systems may increase latency of the DNN and/or increase power consumption associated with the DNN.
  • DNNs may also be referred to as deep networks or deep convolutional neural networks.
  • transferring weight data contributes to power consumption and latency during inference.
  • one or more processing cores of a device may be idle as weights are being transferred from off-chip of the device to on-chip memory of the device during a weight data transfer. It may be desirable to reduce resources used by an artificial neural network to decrease power consumption and latency.
  • the resources may include memory resources and/or computational resources of a device used to deploy the DNN.
  • Various aspects disclosed relate generally to tensor factorization. Some aspects more specifically relate to factorizing an original weight tensor to a codebook matrix (e.g., a dense matrix) and a latent matrix (e.g., a sparse matrix), such that the matrix product closely approximates the original weight tensor.
  • a codebook matrix e.g., a dense matrix
  • a latent matrix e.g., a sparse matrix
  • the matrix product may be computed, and the result may be used for computations at a layer associated with the original weight tensor.
  • a matrix product may be computed per layer, as each layer processes an input.
  • multiple matrix products may be computed prior to processing an input at the layers of the neural network. In such examples, each layer may be associated with a respective matrix product of the multiple matrix products.
  • the described techniques may reduce latency by reducing an amount of weight data transfers.
  • cores that may have been idle during a weight data transfer may be allocated to generating layer weights, for each layer, based on a matrix product corresponding to an original weight associated with the layer.
  • FIGURE 1 illustrates an example implementation of a system-on-a-chip (SOC) 100, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for generating a weight tensor based on a dense quantized matrix and a sparse quantized matrix, in accordance with certain aspects of the present disclosure.
  • SOC system-on-a-chip
  • Variables e.g., neural signals and synaptic weights
  • system parameters associated with a computational device e.g., neural network with weights
  • delays e.g., frequency bin information, and task information
  • NPU neural processing unit
  • GPU graphics processing unit
  • DSP digital signal processor
  • Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or may be loaded from a memory block 118.
  • the SOC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104, a DSP 106, a connectivity block 110, which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures.
  • the NPU is implemented in the CPU, DSP, and/or GPU.
  • the SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and/or navigation module 120, which may include a global positioning system.
  • ISPs image signal processors
  • the SOC 100 may be based on an ARM instruction set.
  • the instructions loaded into the general -purpose processor 102 may comprise code to generate, during training of the ANN, the weight tensor based on a transformation of an original weight tensor from a four-dimensional weight tensor to a two-dimensional weight tensor; code to factorize, during the training, the weight tensor to a dense matrix and a sparse matrix; code to quantize, during the training, the dense matrix and the sparse matrix to generate the dense quantized matrix and the sparse quantized matrix; and code to sparsify the sparse quantized matrix.
  • the instructions loaded into the general-purpose processor 102 may also comprise code to retrieve, for a layer of a set of layers of the ANN, a dense quantized matrix comprising a codebook and a sparse quantized matrix comprising linear coefficients, the dense quantized matrix and the sparse quantized matrix associated with a weight tensor of the layer; code to determine, for the layer of the set of layers, the weight tensor based on a product of the dense quantized matrix and the sparse quantized matrix; and code to process, at the layer, an input based on the weight tensor
  • Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data.
  • deep learning addresses a major bottleneck of traditional machine learning.
  • a shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs.
  • Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise.
  • Deep learning architectures may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new types of features that a human might not have considered.
  • a deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data For instance, higher layers may learn to represent complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases.
  • Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure.
  • the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes.
  • Neural networks may be designed with a variety of connectivity patterns.
  • feed-forward networks information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers.
  • a hierarchical representation may be built up in successive layers of a feed-forward network.
  • Neural networks may also have recurrent or feedback (also called top-down) connections.
  • a recurrent connection the output from a neuron in a given layer may be communicated to another neuron in the same layer.
  • a recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence.
  • a connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection.
  • a network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.
  • FIGURE 2A illustrates an example of a fully connected neural network 202.
  • a neuron in a first layer may communicate its output to every neuron in a second layer, so that each neuron in the second layer will receive input from every neuron in the first layer.
  • FIGURE 2B illustrates an example of a locally connected neural network 204.
  • a neuron in a first layer may be connected to a limited number of neurons in the second layer.
  • a locally connected layer of the locally connected neural network 204 may be configured so that each neuron in a layer will have the same or a similar connectivity pattern, but with connections strengths that may have different values (e.g., 210, 212, 214, and 216).
  • the locally connected connectivity pattern may give rise to spatially distinct receptive fields in a higher layer, because the higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the network.
  • FIGURE 2C illustrates an example of a convolutional neural network 206.
  • the convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208).
  • Convolutional neural networks may be well suited to problems in which the spatial location of inputs is meaningful.
  • FIGURE 2D illustrates a detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capturing device 230, such as a car-mounted camera.
  • the DCN 200 of the current example may be trained to identify traffic signs and a number provided on the traffic sign.
  • the DCN 200 may be trained for other tasks, such as identifying lane markings or identifying traffic lights.
  • the DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222.
  • the DCN 200 may include a feature extraction section and a classification section.
  • a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218.
  • the convolutional kernel for the convolutional layer 232 may be a 5x5 kernel that generates 28x28 feature maps.
  • the convolutional kernels may also be referred to as filters or convolutional filters.
  • the first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220.
  • the max pooling layer reduces the size of the first set of feature maps 218. That is, a size of the second set of feature maps 220, such as 14x14, is less than the size of the first set of feature maps 218, such as 28x28.
  • the reduced size provides similar information to a subsequent layer while reducing memory consumption.
  • the second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).
  • the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number that corresponds to a possible feature of the image 226, such as “sign,” “60,” and “100.” A softmax function (not shown) may convert the numbers in the second feature vector 228 to a probability. As such, an output 222 of the DCN 200 is a probability of the image 226 including one or more features.
  • the probabilities in the output 222 for “sign” and “60” are higher than the probabilities of the others of the output 222, such as “30,” “40,” “50,” “70,” “80,” “90,” and “100”.
  • the output 222 produced by the DCN 200 is likely to be incorrect.
  • an error may be calculated between the output 222 and a target output.
  • the target output is the ground truth of the image 226 (e.g., “sign” and “60”).
  • the weights of the DCN 200 may then be adjusted so the output 222 of the DCN 200 is more closely aligned with the target output.
  • a learning algorithm may compute a gradient vector for the weights.
  • the gradient may indicate an amount that an error would increase or decrease if the weight were adjusted.
  • the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer.
  • the gradient may depend on the value of the weights and on the computed error gradients of the higher layers.
  • the weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as “back propagation” as it involves a “backward pass” through the neural network.
  • the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient.
  • This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level.
  • the DCN may be presented with new images (e.g., the speed limit sign of the image 226) and a forward pass through the network may yield an output 222 that may be considered an inference or a prediction of the DCN.
  • Deep belief networks are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs).
  • RBM Restricted Boltzmann Machines
  • An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning.
  • the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors
  • the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.
  • DCNs Deep convolutional networks
  • DCNs are networks of convolutional networks, configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.
  • DCNs may be feed-forward networks.
  • the connections from a neuron in a first layer of a DCN to a group of neurons in the next higher layer are shared across the neurons in the first layer.
  • the feed-forward and shared connections of DCNs may be exploited for fast processing.
  • the computational burden of a DCN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.
  • the processing of each layer of a convolutional network may be considered a spatially invariant template or basis projection.
  • the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information.
  • the outputs of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e g., 220) receiving input from a range of neurons in the previous layer (e.g., feature maps 218) and from each of the multiple channels.
  • the values in the feature map may be further processed with a non-linearity, such as a rectification, max(0, x). Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.
  • the performance of deep learning architectures may increase as more labeled data points become available or as computational power increases. Modem deep neural networks are routinely trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms may further boost the performance of deep learning. Rectified linear units may reduce a training issue known as vanishing gradients. New training techniques may reduce over-fitting and thus enable larger models to achieve better generalization. Encapsulation techniques may abstract data in a given receptive field and further boost overall performance.
  • FIGURE 3 is a block diagram illustrating a deep convolutional network 350.
  • the deep convolutional network 350 may include multiple different types of layers based on connectivity and weight sharing.
  • the deep convolutional network 350 includes the convolution blocks 354A, 354B.
  • Each of the convolution blocks 354A, 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.
  • CONV convolution layer
  • LNorm normalization layer
  • MAX POOL max pooling layer
  • the convolution layers 356 may include one or more convolutional filters, which may be applied to the input data to generate a feature map. Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not so limiting, and instead, any number of the convolution blocks 354A, 354B may be included in the deep convolutional network 350 according to design preference.
  • the normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition.
  • the max pooling layer 360 may provide down sampling aggregation over space for local invariance and dimensionality reduction.
  • the parallel filter banks for example, of a deep convolutional network may be loaded on a CPU 102 or GPU 104 of an SOC 100 to achieve high performance and low power consumption.
  • the parallel filter banks may be loaded on the DSP 106 or an ISP 116 of an SOC 100.
  • the deep convolutional network 350 may access other processing blocks that may be present on the SOC 100, such as sensor processor 114 and navigation module 120, dedicated, respectively, to sensors and navigation.
  • the deep convolutional network 350 may also include one or more fully connected layers 362 (FC 1 and FC2).
  • the deep convolutional network 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350 are weights (not shown) that are to be updated.
  • LR logistic regression
  • each of the layers may serve as an input of a succeeding one of the layers (e g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn hierarchical feature representations from input data 352 (e.g., images, audio, video, sensor data and/or other input data) supplied at the first of the convolution blocks 354A.
  • the output of the deep convolutional network 350 is a classification score 366 for the input data 352.
  • the classification score 366 may be a set of probabilities, where each probability is the probability of the input data, including a feature from a set of features.
  • DNNs deep neural networks
  • edge devices such as mobile devices and Internet-of-Things (loT) devices may be subject to computational and memory constraints Therefore, it may be difficult to deploy a DNN on an edge device because an amount of resources, such as computational power and/or memory resources, used by the DNN may be greater than an amount of resources available at the edge device.
  • a DNN deployed on cloud computing systems may not be subject to computational and memory constraints. Still, cloud computing systems may increase latency of the DNN and/or increase an amount of power consumed by the DNN.
  • transferring weight data may increase power consumption and latency during inference.
  • one or more processing cores of a device may be idle as weight data is transferred from off-chip (e.g., DRAM) of the device to on-chip memory (e.g., tightly coupled memory (TCM) or SRAM) of the device during the transfer of the weight data. It may be desirable to reduce resources used by a DNN to decrease power consumption and/or latency.
  • the resources may include memory resources and/or computational resources, such as a processor resources.
  • weight tensors may be factorized based on a sparse principal component analysis (PCA) technique.
  • PCA is an example of a data-processing and dimension-reduction technique that seeks linear combinations of original variables, such that derived variables may capture maximal variance.
  • a singular value decomposition (SVD) of a data matrix may be used to determine the PCA.
  • data X may be represented by an n x p matrix, where a parameter n represents a number of observations and a parameter p represents a number of variables.
  • PCAs may be difficult to interpret because components may be linear combinations of variables p.
  • Sparse PCA may be specified to achieve a dimensionality reduction while also reducing a number of variables.
  • Some aspects more specifically relate to identifying a factorization of a codebook matrix C and a latent matrix Z associated with an original weight tensor W, such that the matrix product CZ approximates the original weight tensor W.
  • the values of latent matrix Z may be multi-bit.
  • the latent matrix Z may be an example of a sparse quantized matrix and the codebook matrix C may be an example of a dense quantized matrix. Additionally, the latent quantized matrix Z may represent linear coefficients of an approximation of the weight tensor W .
  • the matrix product CZ may be computed during inference, and the result may be used for computations at a layer associated with the original weight tensor.
  • a matrix product may be computed per layer, as each layer processes an input.
  • multiple matrix products may be computed prior to processing an input at the layers of the neural network.
  • each layer may be associated with a respective matrix product of the multiple matrix products.
  • FIGURE 4 is a block diagram illustrating an example of approximating an original weight tensor W in accordance with various aspects of the present disclosure.
  • the original weight tensor W where W E ⁇ FmxFoutxHxw o p a convoiu tional layer may be reshaped to a dense matrix W 400, where W E JR NxD .
  • the dense matrix W 400 may also be referred to as a weight matrix.
  • the dense matrix W 400 may be in a float32 format.
  • F in represents a number of input channels
  • F out represents a number of output channels
  • H and W represent spatial dimensions of a filter.
  • the decomposition of every column of the dense matrix W 400 may be a linear combination of k codebook vectors (columns of the codebook matrix C 402):: where C.j is the j-th column of the codebook matrix C 402.
  • the quantiziation operation for the codebook matrix C 402 and the latent matrix latent matrix Z may be defined as follows:
  • the dense matrix W 400 may be factorized into a codebook matrix C 402 associated with a codebook, and a latent matrix Z 404 (Z E IR fcxN ) associated with a linear coefficient, such that the dense matrix W 400 is a product of the codebook matrix C 402 and the latent matrix Z 404 (e.g., W — CZ).
  • the codebook matrix C 402 and the latent matrix Z 404 may be stored instead of storing a full weight tensor W, thereby reducing a memory footprint of a DNN.
  • PCA principle component analysis
  • the codebook matrix C 402 and the latent matrix Z 404 may be quantized to bitwidths B c and B z , respectively, with B c , B z « 32. That is, the bitwidths B c and B z define a compression rate of the codebook matrix C 402 and the latent matrix Z 404.
  • a number of zero values may be greater than a number of non-zero values.
  • a zero mean version of the original weight tensor W may be factorized.
  • dimensions of the dense matrix W 400 may be [d x n], where d « n.
  • Dimensions of the codebook matrix C 402 may be [d x k], where d » k
  • dimensions of the latent matrix Z 404 may be [k x n]/
  • a weight tensor W may be reshaped into a dense matrix W 400.
  • the dense matrix W 400 may be factorized into a codebook matrix C 402 and a latent matrix Z 404 using a floating point implementation of principle component analysis (PCA). Scales shared per row for the codebook matrix C 402 and per column for the latent matrix Z 404 may be quantized as follows:
  • the variable b represents a bit-width
  • the variable i represents a row
  • the variable j represents a column.
  • the variable s £ represents a quantization scale
  • the variable ⁇ 5i represents a quantization scale.
  • the clamp() function may be defined as:
  • the quantization scales s £ and ⁇ 5i may be determined as follows: [0062] During training, the dense quantized matrix C and the sparse quantized matrix Z may be optimized based on input data samples, per layer, to compensate for quantization. In some examples, a straight-through estimator may be used for training quantized weights. That is, during training, the values of the dense quantized matrix C and the latent quantized matrix Z may be adjusted, rather than the values of a weight matrix. The latent quantized matrix Z may be stored in a compressed sparse format to reduce a size of a layer (e.g., reduce memory use). In some examples, magnitude pruning or L0 norm minimization may be used for the sparsification.
  • any unstructured sparsification method may be used.
  • the network may be fine-tuned end- to-end using back-propagation and the original dataset to recover the error after the compression.
  • a straight-through estimator may be used for quantized factors.
  • the dense quantized matrix C and the sparse quantized matrix Z may be stored, per layer, in memory.
  • the dense quantized matrix C and the sparse quantized matrix Z may be loaded from memory. Furthermore, a weight tensor W may be estimated based on a product of the dense quantized matrix C and the sparse quantized matrix Z. The neural network may then proceed with the layer computations based on weights obtained from the reconstructed weight tensor W. In some examples, the weight tensor W may be reconstructed per layer to reduce overall memory use. In other examples, all weight tensors W (e g., for each layer of the neural network) may be reconstructed prior to performing the inference at the neural network.
  • FIGURE 5 is a flow diagram illustrating an example process 500 for an artificial neural network (ANN), in accordance with some aspects of the present disclosure.
  • the example process 500 is an example of generating a weight tensor for one or more layers of the artificial neural network based on a codebook matrix and a latent matrix associated with each layer of the one or more layers.
  • the process 500 may be for an artificial neural network, such as the DCN 200 or the DCN 350 described with reference to FIGURES 2 and 3, respectively.
  • the ANN retrieves, for a layer of the ANN, a codebook matrix representing a codebook and a latent matrix representing linear coefficients.
  • the codebook matrix and the latent matrix may be stored in a memory associated with a device that implements the ANN.
  • the layer may be a convolutional layer or a fully connected layer.
  • the ANN may be a deep convolutional neural network.
  • the ANN determines, for the layer, the weight tensor based on a product of the codebook matrix and the latent matrix.
  • the ANN processes, at the layer, an input based on the weight tensor.
  • the input may be processed by performing a convolution based on weights associated with the weight tensor.
  • the process 500 described in blocks 502, 504, and 506 may be repeated for each remaining layer of the set of layers based on a codebook matrix and a latent matrix associated with a weight tensor of each remaining layer of the set of layers. In other examples, the process 500 may be performed for all layers of the ANN upon initializing the ANN, or prior to processing an input to the ANN.
  • a processor-implemented method comprising: retrieving, for a layer of an artificial neural network (ANN), a codebook matrix representing a codebook and a latent matrix representing linear coefficients; determining, for the layer of the set of layers, the weight tensor based on a product of the codebook matrix and the latent matrix; and processing, at the layer, an input based on the weight tensor.
  • ANN artificial neural network
  • Clause 2 The processor-implemented method of Clause 1, further comprising repeating the retrieving, the determining, and the processing for each remaining layer of the set of layers based on a codebook matrix and a latent matrix associated with a weight tensor of each remaining layer of the set of layers.
  • Clause 3 The processor-implemented method of any one of Clauses 1-2, in which processing the input comprises performing a convolution based on weights associated with the weight tensor.
  • Clause 4 The processor-implemented method of any one of Clauses 1-3, further comprising: generating, during training of the ANN, the weight tensor based on a transformation of an original weight tensor from a four-dimensional weight tensor to a two-dimensional weight tensor; factorizing, during the training, the weight tensor to a dense matrix and a sparse matrix; and quantizing, during the training, the dense matrix and the sparse matrix to generate the dense quantized matrix and the sparse quantized matrix.
  • Clause 5 The processor-implemented method of Clause 4, further comprising factorizing the weight tensor to the codebook matrix and the latent matrix based on a floating point implementation for principal component analysis (PC A).
  • PC A principal component analysis
  • Clause 6 The processor-implemented method of any one of clauses 4-5, further comprising optimizing, during the training, the codebook matrix and the latent matrix on training data based on the quantizing.
  • Clause 7 The processor-implemented method of any one of Clauses 4-6, in which a compression rate of a factorization associated with the codebook matrix is different from a compression rate of a factorization associated with the latent matrix.
  • Clause 8 The processor-implemented method of any one of Clauses 1-7, in which the codebook matrix and the latent matrix are stored in a memory associated with a device that implements the ANN.
  • Clause 9 The processor-implemented method of any one of Clauses 1-8, in which the layer is a convolutional layer or a fully connected layer.
  • Clause 10 The processor-implemented method of any one of Clauses 1-9, in which the ANN is a deep convolutional neural network.
  • Clause 11 The processor-implemented method of any one of Clauses 1-10, in which the latent matrix is a sparse quantized matrix and the codebook matrix is a dense quantized matrix.
  • An apparatus implementing an ANN comprising a processor, memory coupled with the processor, and instructions stored in the memory and operable, when executed by the processor to cause the apparatus to perform any one of Clauses 1 through 11.
  • Clause 13 An apparatus configured for an ANN, the apparatus comprising at least one means for performing any one of Clauses 1 through 11.
  • Clause 14 A non-transitory computer-readable medium having program code recorded thereon for an artificial neural network, the program code comprising program code to cause an ANN to perform any one of Clauses 1 through 11.
  • the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions.
  • the means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor.
  • ASIC application specific integrated circuit
  • determining encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Additionally, “determining” may include receiving (e g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing, and the like.
  • a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members.
  • “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array signal
  • PLD programmable logic device
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • a software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth.
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • registers a hard disk, a removable disk, a CD-ROM and so forth.
  • a software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media.
  • a storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • the methods disclosed comprise one or more steps or actions for achieving the described method.
  • the method steps and/or actions may be interchanged with one another without departing from the scope of the claims.
  • the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
  • an example hardware configuration may comprise a processing system in a device.
  • the processing system may be implemented with a bus architecture.
  • the bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints.
  • the bus may link together various circuits including a processor, machine-readable media, and a bus interface.
  • the bus interface may be used to connect a network adapter, among other things, to the processing system via the bus.
  • the network adapter may be used to implement signal processing functions.
  • a user interface e.g., keypad, display, mouse, joystick, etc.
  • the bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.
  • the processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media.
  • the processor may be implemented with one or more general-purpose and/or specialpurpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software.
  • Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof.
  • RAM random access memory
  • ROM read only memory
  • PROM programmable read-only memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable Read-only memory
  • registers magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof.
  • the machine-readable media may be embodied in a computer-program product.
  • the computer-program product may comprise packaging materials.
  • the machine-readable media may be part of the processing system separate from the processor.
  • the machine-readable media, or any portion thereof may be external to the processing system.
  • the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface.
  • the machine-readable media, or any portion thereof may be integrated into the processor, such as the case may be with cache and/or general register files.
  • the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.
  • the processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture.
  • the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described.
  • the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure.
  • ASIC application specific integrated circuit
  • FPGAs field programmable gate arrays
  • PLDs programmable logic devices
  • controllers state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure.
  • the machine-readable media may comprise a number of software modules.
  • the software modules include instructions that, when executed by the processor, cause the processing system to perform various functions.
  • the software modules may include a transmission module and a receiving module.
  • Each software module may reside in a single storage device or be distributed across multiple storage devices.
  • a software module may be loaded into RAM from a hard drive when a triggering event occurs.
  • the processor may load some of the instructions into cache to increase access speed.
  • One or more cache lines may then be loaded into a general register file for execution by the processor.
  • Computer- readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage medium may be any available medium that can be accessed by a computer.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium.
  • Disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
  • computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media).
  • computer-readable media may comprise transitory computer- readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.
  • certain aspects may comprise a computer program product for performing the operations presented.
  • a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described.
  • the computer program product may include packaging material.
  • modules and/or other appropriate means for performing the methods and techniques described can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable.
  • a user terminal and/or base station can be coupled to a server to facilitate the transfer of means for performing the methods described.
  • various methods described can be provided via storage means (e g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device.
  • storage means e g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.
  • CD compact disc
  • floppy disk etc.
  • any other suitable technique for providing the methods and techniques to a device can be utilized.

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Abstract

Un procédé mis en œuvre par processeur comprend la récupération, pour une couche d'un ensemble de couches d'un réseau de neurones artificiels (ANN), d'une matrice quantifiée dense représentant un livre de codes et d'une matrice quantifiée creuse représentant des coefficients linéaires. La matrice quantifiée dense et la matrice quantifiée creuse peuvent être associées à un tenseur de poids de la couche. Le procédé mis en œuvre par processeur comprend également la détermination, pour la couche de l'ensemble de couches, du tenseur de poids sur la base d'un produit de la matrice quantifiée dense et de la matrice quantifiée creuse. Le procédé mis en œuvre par processeur comprend en outre le traitement, au niveau de la couche, d'une entrée sur la base du tenseur de poids.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117194051A (zh) * 2023-11-01 2023-12-08 北京灵汐科技有限公司 脑仿真处理方法及装置、电子设备、计算机可读存储介质

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KUZMIN ANDREY ET AL: "QUANTIZED SPARSE PCA FOR NEURAL NETWORK WEIGHT COMPRESSION", OPENREVIEW.NET (UNDER REVIEW AS A CONFERENCE PAPER AT ICLR 2022), 29 September 2021 (2021-09-29), XP093009815, Retrieved from the Internet <URL:https://openreview.net/references/pdf?id=WmRR4Ej6Nt> [retrieved on 20221220] *
MARTINEZ JULIETA ET AL: "Permute, Quantize, and Fine-tune: Efficient Compression of Neural Networks", 2021 IEEE/CVF CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION (CVPR), 10 April 2021 (2021-04-10), pages 15694 - 15703, XP093010226, ISBN: 978-1-6654-4509-2, Retrieved from the Internet <URL:https://arxiv.org/pdf/2010.15703.pdf> [retrieved on 20221220], DOI: 10.1109/CVPR46437.2021.01544 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117194051A (zh) * 2023-11-01 2023-12-08 北京灵汐科技有限公司 脑仿真处理方法及装置、电子设备、计算机可读存储介质
CN117194051B (zh) * 2023-11-01 2024-01-23 北京灵汐科技有限公司 脑仿真处理方法及装置、电子设备、计算机可读存储介质

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