WO2023241334A1 - 一种通信方法及装置 - Google Patents

一种通信方法及装置 Download PDF

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Publication number
WO2023241334A1
WO2023241334A1 PCT/CN2023/096532 CN2023096532W WO2023241334A1 WO 2023241334 A1 WO2023241334 A1 WO 2023241334A1 CN 2023096532 W CN2023096532 W CN 2023096532W WO 2023241334 A1 WO2023241334 A1 WO 2023241334A1
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Prior art keywords
sequence
bits
value
code rate
information bits
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PCT/CN2023/096532
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English (en)
French (fr)
Inventor
王献斌
童佳杰
张华滋
李榕
王俊
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华为技术有限公司
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Publication of WO2023241334A1 publication Critical patent/WO2023241334A1/zh

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/0001Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/0001Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013Rate matching, e.g. puncturing or repetition of code symbols

Definitions

  • Embodiments of the present application provide a communication method and device for reducing the complexity of the Polar code construction process.
  • the first aspect provides a communication method.
  • the execution subject of the method can be the sending end or a chip, chip system or circuit located in the sending end.
  • the method can be implemented through the following steps: Obtain the bit sequence to be encoded, and the bit sequence to be encoded Including K information bits, K is an integer greater than 0; determine the first sequence, and the position of the K information bits in the first sequence is determined based on the second sequence corresponding to the target code rate and the value of K, where the The two sequences are used to represent the selection priority of N 0 bits, where N 0 is an integer greater than K; the first sequence is polarized coded to obtain the third sequence; and the third sequence is sent.
  • the second sequence is designed for a fixed code rate.
  • the same sequence can be used to construct a series of Polar codes with the same code rate and different lengths.
  • the second sequence in the embodiment of this application can reduce the power consumption of system implementation.
  • the method provided by the embodiments of the present application can greatly reduce the power consumption of system implementation.
  • the method before sending the third sequence, also includes: puncturing (N 0 -E) bits in the third sequence, E is the target code length, and E is greater than 0 and less than or equal to N 0 integer.
  • the sequence number of any one of the (N 0 -E) bits in the third sequence is based on N 0 /2 and the remainder satisfies the second criterion.
  • the second criterion is that the remainder is less than (N 0 /2-E/2).
  • the target code rate can correspond to a sequence
  • the transmitter can determine the sequence corresponding to the target code length based on the sequence, that is, the second sequence is determined based on the sequence corresponding to the target code rate.
  • the positions of the K information bits in the first sequence correspond to the first K bits of the N 0 bits sorted from high to low according to the selection priority.
  • the second sequence includes N 0 values, where the n-th value in the second sequence is used to represent the selection priority of the n-th bit among the N 0 bits, and n traverses from 0 to N 0 -1 integer.
  • the corresponding values of the bits used to place the frozen bits in the first sequence in the second sequence satisfy the first criterion; the bits used to place the information bits in the first sequence correspond to the values in the second sequence.
  • the value of does not satisfy the first criterion.
  • the value in the second sequence is inversely proportional to the selection priority, and the first criterion is that the value is greater than or equal to K; or, the value in the second sequence is directly proportional to the selection priority, and the first criterion is the value Less than or equal to (N 0 -K).
  • the target code rate is preset, or the target code rate is selected from a code rate set, and the code rate set includes one or more code rates.
  • the second aspect provides a communication method.
  • the execution subject of the method can be the receiving end or a chip, chip system or circuit located in the receiving end.
  • the method can be implemented through the following steps: obtaining the third sequence; determining K information bits The positions of the K information bits are determined based on the second sequence corresponding to the target code rate and the value of K, where the second sequence is used to characterize the selection priority of N 0 bits , the N 0 is an integer greater than K; the third sequence is decoded according to the positions of K information bits.
  • the second sequence is designed for a fixed code rate.
  • the same sequence can be used to construct a series of Polar codes with the same code rate and different lengths.
  • the second sequence in the embodiment of this application can reduce the power consumption of system implementation.
  • the method provided by the embodiments of the present application can greatly reduce the power consumption of system implementation.
  • the method before decoding the third sequence according to the positions of K information bits, the method further includes: recovering the (N 0 -E) bits that were punctured in the third sequence, and E is the target.
  • Code length, E is an integer greater than 0 and less than or equal to N 0 .
  • the sequence number of any one of the (N 0 -E) bits in the third sequence is based on N 0 /2 and the remainder satisfies the second criterion.
  • the second criterion is that the remainder is less than (N 0 /2-E/2).
  • the target code rate can also correspond to multiple sequences, wherein the multiple sequences correspond to different code lengths, and the second sequence can be one of the multiple sequences corresponding to the target code rate that has a corresponding relationship with the target code length. the sequence of. In this implementation In the way, Indicates rounding up. By designing different sequences for different code lengths, the puncturing step can be omitted or simplified, thereby further reducing complexity.
  • the target code rate can correspond to one sequence
  • the second sequence is the sequence corresponding to the target code rate.
  • N 0 may be a preset value.
  • the target code rate can correspond to one sequence
  • the second sequence is determined based on the sequence corresponding to the target code rate.
  • the above design can reduce system complexity by designing the same sequence for the same code rate and different code lengths, so that the same sequence can be used to construct a series of Polar codes with the same code rate and different lengths.
  • the positions of the K information bits correspond to the first K bits of the N 0 bits sorted from high to low according to the selection priority.
  • the second sequence includes N 0 values, where the n-th value in the second sequence is used to represent the selection priority of the n-th bit among the N 0 bits, and n traverses from 0 to N 0 -1 integer.
  • the corresponding value of the bit used to place the frozen bit in the second sequence satisfies the first criterion; the corresponding value of the bit used to place the information bit in the second sequence does not meet the first criterion.
  • the value in the second sequence is inversely proportional to the selection priority, and the first criterion is that the value is greater than or equal to K; or, the value in the second sequence is directly proportional to the selection priority, and the first criterion is the value Less than or equal to (N 0 -K).
  • the target code rate is preset, or the target code rate is selected from a code rate set, and the code rate set includes one or more code rates.
  • the present application also provides a communication device, where the device is a sending-side device or a chip in the sending-side device.
  • the communication device has the function of implementing any of the methods provided in the first aspect.
  • the communication device can be implemented by hardware, or can also be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more units or modules corresponding to the above functions.
  • the communication device includes: a processor, the processor is configured to support the communication device in performing the corresponding functions of the sending side device in the method shown above.
  • the communications device may also include memory, which storage may be coupled to the processor, which holds program instructions and data necessary for the communications device.
  • the communication device further includes an interface circuit, which is used to support communication between the communication device and a device such as a receiving side device, such as the sending and receiving of data or signals.
  • the communication interface may be a transceiver, a circuit, a bus, a module, or other types of communication interfaces.
  • the communication device includes corresponding functional modules, respectively used to implement the steps in the above method.
  • Functions can be implemented by hardware, or by hardware executing corresponding software.
  • Hardware or software includes one or more modules corresponding to the above functions.
  • the structure of the communication device includes a processing unit (or processing unit) and a communication unit (or communication unit). These units can perform the corresponding functions in the above method examples. For details, see the method in the first aspect. Description, no details will be given here.
  • the present application also provides a communication device, where the device is a receiving-side device or a chip in the receiving-side device.
  • the communication device has the function of implementing any of the methods provided in the second aspect.
  • the communication device can be implemented by hardware, or can also be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more units or modules corresponding to the above functions.
  • the communication device includes: a processor, the processor is configured to support the communication device in performing the corresponding functions of the receiving side device in the method shown above.
  • the communications device may also include memory, which storage may be coupled to the processor, which holds program instructions and data necessary for the communications device.
  • the communication device further includes an interface circuit, which is used to support communication between the communication device and a device such as a sending side device, such as the sending and receiving of data or signals.
  • the communication interface may be a transceiver, a circuit, a bus, a module, or other types of communication interfaces.
  • the communication device includes corresponding functional modules, respectively used to implement the steps in the above method.
  • Functions can be implemented by hardware, or by hardware executing corresponding software.
  • Hardware or software includes one or more modules corresponding to the above functions.
  • the structure of the communication device includes a processing unit (or processing unit) and a communication unit (or communication unit). These units can perform the corresponding functions in the above method examples. For details, see the method in the second aspect. Description, no details will be given here.
  • a communication device including a processor and an interface circuit.
  • the interface circuit is used to receive signals from other communication devices other than the communication device and transmit them to the processor or to send signals from the processor.
  • the processor is used to implement the method in the first aspect and any possible design through logic circuits or executing code instructions.
  • a communication device including a processor and an interface circuit.
  • the interface circuit is used to receive signals from other communication devices other than the communication device and transmit them to the processor or to send signals from the processor.
  • the processor is used to implement the method in the aforementioned second aspect and any possible design through logic circuits or executing code instructions.
  • a computer-readable storage medium In a seventh aspect, a computer-readable storage medium is provided. Computer programs or instructions are stored in the computer-readable storage medium. When the computer program or instructions are executed by a processor, the first aspect or the second aspect and the above are realized. method in any possible design.
  • An eighth aspect provides a computer program product that stores instructions. When the instructions are executed by a processor, the method in the first aspect or the second aspect and any possible design is implemented.
  • a tenth aspect provides a communication system, which system includes the device described in the first aspect (such as a sending-side device) and the device described in the second aspect (such as a receiving-side device).
  • Figure 5 is a schematic structural diagram of a communication device in an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of another communication device in an embodiment of the present application.
  • Polar code coding is a channel coding scheme that can be strictly proven to achieve channel capacity. It has the characteristics of high performance, low complexity, and flexible matching method. It has been determined by the 3rd generation partnership project (3GPP) as the 5G control channel enhanced mobile broadband (eMBB) scenario control channel coding scheme.
  • 3GPP 3rd generation partnership project
  • eMBB enhanced mobile broadband
  • the information bit length in the upper half area satisfies P*K1 ⁇ P*K2, and the information bit length in the lower half area satisfies (1-P) *K1 ⁇ (1-P)*K2. Constructing a polar code based on this principle can make the information bits of Polar codes with the same code rate and different lengths satisfy the nesting property.
  • At least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • the communication system includes a sending end 201 and a receiving end 202 .
  • the sending end 201 may be a network device or a terminal device
  • the receiving end 202 may be a network device or a terminal device.
  • the sending end 201 is a network device
  • the receiving end 202 may be a terminal device; when the sending end 201 is a terminal device, the receiving end 202 may be a network device or a terminal device.
  • FIG. 2 illustrates that the sending end 201 is a terminal device and the receiving end 202 is a network device. It should be noted that the number of devices in the communication system shown in Figure 2 is only an example and does not limit the present application.
  • the sending end obtains the bit sequence to be encoded.
  • the second sequence includes N 0 values, where the position of the value in the second sequence represents the corresponding bit, and the size of the value represents the selection priority of the bit, that is, the second
  • the nth value in the sequence is used to represent the selection priority of the nth bit among the N 0 bits, and n traverses the integers from 0 to N 0 -1.
  • the numerical value and the selection priority may be in an inverse relationship, that is, the larger the numerical value, the lower the selection priority.
  • the value and the selection priority can also be directly proportional, that is, the larger the value, the higher the selection priority. How to determine the positions of the K information bits in the first sequence will be explained in detail below.
  • the target code rate can correspond to one sequence
  • the second sequence is the sequence corresponding to the target code rate.
  • N 0 may be a preset value.
  • the target code rate may also correspond to multiple sequences, wherein the multiple sequences correspond to different code lengths, and the second sequence may be one of the multiple sequences corresponding to the target code rate that is different from the target code length.
  • E is the target code length, Indicates rounding up.
  • the target code rate may correspond to a sequence
  • the transmitting end may determine the sequence corresponding to the target code length based on the sequence, that is, the second sequence is determined based on the sequence corresponding to the target code rate.
  • the second sequence and the sequence corresponding to the target code rate satisfy a nesting relationship, and the sending end determines the second sequence through the sequence corresponding to the target code rate according to the nesting relationship.
  • the lower half is [486, 466, 461, 432, 454, 422, 415, 374, 447, 412, 406, 362, 396, 351, 342, 291, 437, 400, 393, 348, 382, 335, 326 ,274,369,320,311,252,299,248,244,232,424,385,375,328,365,316,305,249,353,302,292,243,280,238,234,216 ,338,286,276,233,264,225,222,208,257,221,220,205,217,204,200,196,407,363,355,304,344,293,282,237,330 ,278,268,224,259,212,209,184,313,262,254,206,246,195,192,176,240,189,188,172,183,170,168,164,295,250 ,242,190,226,187,185,157,219,182,180,156,177,154,153,
  • Sequence 2 with a length of 256 can include the last 128 values of the upper half of sequence 1, namely [495, 479, 475, 450, 471, 444, 439, 402, 464, 435, 429, 390, 420, 379, 371, 322, 456, 425, 417, 376, 409, 366, 357, 306, 398, 354, 345, 294, 332, 281, 270, 171, 445, 410, 403, 358, 394, 349, 340, 288, 381, 334, 324, 272, 312, 247, 227, 138, 367, 318, 307, 229, 297, 213, 201, 115, 283, 198, 194, 102, 160, 97, 95, 77, 431, 392, 384, 337, 373, 325, 315, 251, 361, 310, 301, 203, 290, 193, 179, 113, 347, 296, 285, 175, 273, 159,
  • Sequence 3 with a length of 128 can include the last 64 values of the upper half of sequence 1, which is the last 64 values of the upper half of sequence 2, that is, [431, 392, 384, 337, 373, 325, 315, 251, 361, 310, 301, 203, 290, 193, 179, 113, 347, 296, 285, 175, 273, 159, 150, 90, 261, 143, 135, 73, 130, 65, 59, 42, 327, 275, 266, 146, 258, 137, 131, 71, 230, 123, 103, 57, 96, 52, 51, 25, 202, 98, 87, 49, 82, 41, 35, 20, 74, 34, 31, 19, 29, 17, 16, 6]; and, the last 64 values in the lower half of sequence 1, which is the last 64 values in the lower half of sequence 2, that is, [256, 186, 181 ,119,163,112,107,60,158,101,91,58,83,56
  • the positions of the K information bits in the first sequence are determined according to the second sequence corresponding to the target code rate and the value of K.
  • the positions of the K information bits in the first sequence can be the same as N
  • the 0 bits correspond to the first K bits sorted from high to low in selection priority.
  • the position of the K information bits in the first sequence can be determined in the following way: compare each value in the second sequence with K. If the value satisfies the first criterion, then the value The corresponding bit is used to place the frozen bit. If the value does not meet the first criterion, the bit corresponding to the value is used to place the information bit.
  • the corresponding values of the bits used to place the frozen bits in the first sequence in the second sequence satisfy the first criterion; the values of the bits used to place the information bits in the first sequence do not meet the first criterion.
  • the target code rate may be preset, or may be selected from a code rate set, and the code rate set includes one or more code rates.
  • the second sequence may include selection priorities corresponding to at least ⁇ *N 0 bits, and the selection priority for all or part of the other (N 0 - ⁇ *N 0 ) bits.
  • a level can be a specific identifier such as a specific value, etc.
  • the target code rate is 1/2 code rate
  • N 0 is 512
  • the maximum number of information bits supported by the second sequence is 256.
  • the second sequence includes 256 bits corresponding to the selection priority, and the other 256
  • the bit selection priority can be X.
  • the above method can further reduce the complexity of the second sequence by expressing the selection priorities of all or part of the remaining (N 0 - ⁇ *N 0 ) bits with specific identifiers.
  • the second sequence is designed for a fixed code rate.
  • the same sequence can be used to construct a series of Polar codes with the same code rate and different lengths.
  • the second sequence in the embodiment of this application can reduce the power consumption of system implementation.
  • the method provided by the embodiments of this application can greatly reduce the power consumption of system implementation.
  • S403 The sending end performs polar code encoding on the first sequence to obtain the third sequence.
  • the receiving end decodes the third sequence according to the positions of the K information bits.
  • the method of determining the positions of the K information bits is the same as the method used by the transmitting end to determine the positions of the K information bits. For details, please refer to the description of the transmitting end, and the description will not be repeated here.
  • the sending end before sending the third sequence, can puncture (N 0 -E) bits in the third sequence, where E is the target code length, and E is greater than 0 and less than or equal to N 0 integer.
  • the receiving end can recover the (N 0 -E) punctured bits in the third sequence before decoding the third sequence according to the positions of the K information bits. For example, the position of the punctured (N 0 -E) bits in the third sequence may be determined, and the punctured (N 0 -E) bits may be filled with zeros.
  • the receiving end determines the positions of the (N 0 -E) bits that are punctured in the third sequence in the same manner as the transmitting end determines the positions of the (N 0 -E) bits.
  • the transmitting end determines the (N 0 -E) bits.
  • N 0 -E) bit positions the repetitive parts will not be described again.
  • the (N 0 -E) bits can be determined in the following way: taking the remainder of the sequence number i of each bit in the third sequence based on N 0 /2, and if the remainder meets the second criterion, determine the bit Needs to be punctured, that is, the bit belongs to the above (N 0 -E) bits. If the remainder does not meet the second criterion, it is determined that the bit is not punctured (that is, the bit is retained), that is, the bit does not belong to the above (N 0 -E) bits. N 0 -E) bits, the above i traverses the integers from 0 to N 0 -1.
  • the second criterion may be that the remainder is less than (N 0 /2-E/2).
  • A1 determine the position of the 32 information bits of the bit sequence to be encoded in the first sequence.
  • the positions of the bits where the frozen bits are placed and the bits where the information bits are placed in the first sequence refer to the following sequence, where 1 indicates that it is used to place the information bits, and 0 indicates that it is used to place the frozen bits: [0, 0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
  • the length matching process that is, the process of determining the puncture bits
  • the coding construction process the process of determining the position of the information bits
  • both the length matching process and the coding construction process in the embodiment of the present application can ensure the nesting of the polar code, that is, the information bit lengths of the upper half and lower half of the polar code increase equally, thereby ensuring communication performance.
  • the communication device can be used to implement the method performed by the sending end in the embodiment of Figure 4.
  • the device can be the sending end itself, or it can be a chip or chipset in the sending end or a chip for Execute part of the related method functionality.
  • the processing unit 602 is used to obtain a sequence of bits to be encoded, the sequence of bits to be encoded includes K information bits, and the K is an integer greater than 0; and, determine the first sequence, where the K information bits are The position in the first sequence is determined based on the second sequence corresponding to the target code rate and the value of K, where the second sequence is used to represent the selection priority of N 0 bits, and the N 0 is an integer greater than K; and the first sequence is polarized coded to obtain a third sequence; the communication unit 601 is used to send the third sequence.
  • the processing unit 602 is also configured to puncture (N 0 -E) bits in the third sequence before sending the third sequence, where E is the target code length, so The E is an integer greater than 0 and less than or equal to the N 0 .
  • the second criterion is that the remainder is less than (N 0 /2-E/2).
  • the second sequence includes N 0 values, wherein the n-th value in the second sequence is used to represent the selection priority of the n-th bit among the N 0 bits, and the n traverses the integers from 0 to N 0 -1.
  • the corresponding value of the bits used to place the frozen bits in the first sequence in the second sequence satisfies the first criterion; the bits used to place the information bits in the first sequence are in the second sequence The corresponding value does not satisfy the first criterion.
  • the value in the second sequence is inversely proportional to the selection priority, and the first criterion is that the value is greater than or equal to K; or the value in the second sequence is directly proportional to the selection priority, and the first criterion is One criterion is that the value is less than or equal to (N 0 -K).
  • the target code rate is preset, or the target code rate is selected from a code rate set, and the code rate set includes one or more code rates.
  • the communication device shown in Figure 5 can be used to implement the method performed by the receiving end in the embodiment of Figure 4.
  • the device can be the receiving end itself, or it can be a chip or chipset in the receiving end. Or a part of the chip used to perform the relevant method functions.
  • the communication unit 601 is used to obtain the third sequence;
  • the processing unit 602 is used to determine the positions of K information bits.
  • the positions of the K information bits are based on the second sequence corresponding to the target code rate and the K The value is determined, wherein the second sequence is used to characterize the selection priority of N 0 bits, and the N 0 is an integer greater than K; and, the third sequence is selected according to the positions of the K information bits. to decode.
  • the processing unit 602 is also configured to: before decoding the third sequence according to the positions of the K information bits, restore the punctured (N 0 -E) bits in the third sequence, E is Target code length, E is an integer greater than 0 and less than or equal to N 0 .
  • the remainder after taking the remainder of the sequence number of any one of the (N 0 -E) bits in the third sequence based on N 0 /2 satisfies the second criterion.
  • the second criterion is that the remainder is less than (N 0 /2-E/2).
  • the positions of the K information bits correspond to the first K bits of the N 0 bits sorted from high to low according to the selection priority.
  • the second sequence includes N 0 values, wherein the n-th value in the second sequence is used to characterize the selection priority of the n-th bit among the N 0 bits, and n traverses from 0 to N 0 - an integer of 1.
  • the corresponding value of the bit used to place the frozen bit in the second sequence satisfies the first criterion; the corresponding value of the bit used to place the information bit in the second sequence does not meet the first criterion.
  • the above method makes the length matching process (that is, the process of determining the puncture bits) and the coding construction process (the process of determining the position of the information bits) independent of each other, which can reduce the implementation complexity.
  • the value in the second sequence is inversely proportional to the selection priority, and the first criterion is that the value is greater than or equal to K; or, the value in the second sequence is directly proportional to the selection priority, and the first criterion is that the value is less than or equal to (N 0 -K).
  • the target code rate is preset, or the target code rate is selected from a code rate set, and the code rate set includes one or more code rates.
  • each functional module in each embodiment of the present application may be integrated into one processing unit. In the device, it can exist physically alone, or two or more modules can be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or software function modules. It can be understood that, for the functions or implementation of each module in the embodiments of this application, further reference can be made to the relevant descriptions of the method embodiments.
  • the communication device may be as shown in Figure 6.
  • the device may be a communication device or a chip in the communication device.
  • the communication device may be a terminal device in the above embodiment or may be a terminal device in the above embodiment.
  • the device includes a processor 701 and a communication interface 702, and may also include a memory 703.
  • the processing unit 602 may be the processor 701.
  • the communication unit 601 may be a communication interface 702.
  • the processor 701 and the memory 703 can also be integrated together.
  • the processor 701 may be a CPU, a digital processing unit, or the like.
  • the communication interface 702 may be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, or the like.
  • the device also includes: a memory 703 for storing programs executed by the processor 701.
  • the memory 703 can be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or a volatile memory (volatile memory), such as a random access memory (random access memory). -access memory, RAM).
  • Memory 703 is, but is not limited to, any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • the processor 701 is used to execute the program code stored in the memory 703, and is specifically used to execute the above-mentioned actions of the processing unit 602, which will not be described again in this application.
  • the communication interface 702 is specifically used to perform the above-mentioned actions of the communication unit 601, which will not be described again in this application.
  • the embodiment of the present application does not limit the specific connection medium between the communication interface 702, the processor 701 and the memory 703.
  • the memory 703, the processor 701 and the communication interface 702 are connected through a bus 704 in Figure 6.
  • the bus is represented by a thick line in Figure 6.
  • the connection methods between other components are only schematically explained. , is not limited.
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 6, but it does not mean that there is only one bus or one type of bus.
  • Embodiments of the present application also provide a communication system, including a communication device for realizing the functions of the sender in the embodiment of FIG. 4 and a communication device for realizing the functions of the receiver in the embodiment of FIG. 4 .

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Abstract

本申请实施例提供一种通信方法及装置,用于降低Polar码构造过程的复杂度。该方法包括:获取待编码比特序列,待编码比特序列包括K个信息比特,K为大于0的整数;确定第一序列,K个信息比特在第一序列中的位置是根据目标码率对应的第二序列以及K的取值确定的,其中,第二序列用于表征N0个比特位的选择优先级,N0为大于K的整数;将第一序列进行极化码编码,得到第三序列;发送第三序列。上述第二序列是针对固定码率设计的,同一个序列可以用于构造一系列相同码率、不同长度的Polar码,相比于针对不同码率、不同码长设计的Q序列,本申请实施例中第二序列可以降低系统实现的功耗。

Description

一种通信方法及装置
相关申请的交叉引用
本申请要求在2022年06月17日提交中国专利局、申请号为202210693015.5、申请名称为“一种通信方法及装置”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域,尤其涉及一种通信方法及装置。
背景技术
在基于极化(Polar)码编码进行通信过程中,若实际通信的码长与Polar码编码后的码长不同,则需要对Polar码编码后的比特序列通过打孔、重传等方式实现码长匹配过程,然后根据码长匹配的结果进行编码构造。具体的,以打孔的码长匹配方式为例,首先根据实际通信的码长与Polar码编码后的码长确定采用打孔的方式进行码长匹配,然后确定打孔的位置。在确定打孔的比特位置后确定信息位和冻结位进行编码构造。当前新无线(new radio,NR)标准中这一过程实现比较复杂,不适用于超低功耗需求。
发明内容
本申请实施例提供一种通信方法及装置,用于降低Polar码构造过程的复杂度。
第一方面,提供一种通信方法,该方法的执行主体可以是发送端或者位于发送端中的芯片、芯片系统或者电路,该方法可以通过以下步骤实现:获取待编码比特序列,待编码比特序列包括K个信息比特,K为大于0的整数;确定第一序列,K个信息比特在第一序列中的位置是根据目标码率对应的第二序列以及K的取值确定的,其中,第二序列用于表征N0个比特位的选择优先级,N0为大于K的整数;将第一序列进行极化码编码,得到第三序列;发送第三序列。
本申请实施例中第二序列是针对固定码率设计的,同一个序列可以用于构造一系列相同码率、不同长度的Polar码,相比于针对不同码率、不同码长设计的Q序列,本申请实施例中第二序列可以降低系统实现的功耗。尤其是在只需要支持几个码率,但需要支持较多不同的码长一些场景下,本申请实施例提供的方法可以极大地降低系统实现的功耗。
一种可能的设计中,在发送第三序列之前,方法还包括:打孔第三序列中的(N0-E)个比特,E为目标码长,E为大于0且小于或等于N0的整数。通过上述方式,可以使得发送的码长与目标码长相匹配。
一种可能的设计中,(N0-E)个比特中任一比特在第三序列中的序号基于N0/2进行取余后的余数满足第二准则。上述方式使得长度匹配过程(也就是确定打孔比特的过程)与编码构造过程(确定信息比特位置的过程)互相独立,可以降低实现复杂度。
一种可能的设计中,第二准则为余数小于(N0/2-E/2)。
一种可能的设计中,目标码率也可以对应多个序列,其中,该多个序列对应不同的码长,第二序列可以是目标码率对应的多个序列中与目标码长有对应关系的序列。在该实现 方式中,表示向上取整。上述通过针对不同码长设计不同的序列,从而可以省略或者简化打孔步骤,从而可以进一步降低复杂性。
一种可能的设计中,目标码率可以对应一个序列,第二序列即目标码率对应的该序列。在该实现方式中,N0可以为预设值。上述设计,通过针对相同的码率、不同的码长设计同一个序列,使得同一个序列可以用于构造一系列相同码率、不同长度的Polar码,可以降低系统复杂度。
一种可能的设计中,目标码率可以对应一个序列,发送端可以根据该序列确定目标码长对应的序列,即第二序列是根据目标码率对应的序列确定。上述设计,通过针对相同的码率、不同的码长设计同一个序列,使得同一个序列可以用于构造一系列相同码率、不同长度的Polar码,可以降低系统复杂度。
一种可能的设计中,K个信息比特在第一序列中的位置与N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
一种可能的设计中,第二序列包括N0个数值,其中,第二序列中第n个数值用于表征N0个比特位中第n个比特位的选择优先级,n遍历从0到N0-1的整数。
一种可能的设计中,第一序列中用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;第一序列中用于放置信息比特的比特位在第二序列中对应的数值不满足第一准则。上述方式使得长度匹配过程(也就是确定打孔比特的过程)与编码构造过程(确定信息比特位置的过程)互相独立,可以降低实现复杂度。
一种可能的设计中,第二序列中数值与选择优先级成反比,第一准则为取值大于或等于K;或者,第二序列中数值与选择优先级成正比,第一准则为取值小于或等于(N0-K)。
一种可能的设计中,目标码率为预先设置的,或者,目标码率是在码率集合中选择的,码率集合包括一个或多个码率。
第二方面,提供一种通信方法,该方法的执行主体可以是接收端或者位于接收端中的芯片、芯片系统或者电路,该方法可以通过以下步骤实现:获取第三序列;确定K个信息比特的位置,所述K个信息比特的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;根据K个信息比特的位置对所述第三序列进行解码。
本申请实施例中第二序列是针对固定码率设计的,同一个序列可以用于构造一系列相同码率、不同长度的Polar码,相比于针对不同码率、不同码长设计的Q序列,本申请实施例中第二序列可以降低系统实现的功耗。尤其是在只需要支持几个码率,但需要支持较多不同的码长一些场景下,本申请实施例提供的方法可以极大地降低系统实现的功耗。
一种可能的设计中,在根据K个信息比特的位置对所述第三序列进行解码之前,方法还包括:恢复第三序列中被打孔的(N0-E)个比特,E为目标码长,E为大于0且小于或等于N0的整数。通过上述方式,可以使得发送的码长与目标码长相匹配。
一种可能的设计中,(N0-E)个比特中任一比特在第三序列中的序号基于N0/2进行取余后的余数满足第二准则。上述方式使得长度匹配过程(也就是确定打孔比特的过程)与编码构造过程(确定信息比特位置的过程)互相独立,可以降低实现复杂度。
一种可能的设计中,第二准则为余数小于(N0/2-E/2)。
一种可能的设计中,目标码率也可以对应多个序列,其中,该多个序列对应不同的码长,第二序列可以是目标码率对应的多个序列中与目标码长有对应关系的序列。在该实现 方式中,表示向上取整。上述通过针对不同码长设计不同的序列,从而可以省略或者简化打孔步骤,从而可以进一步降低复杂性。
一种可能的设计中,目标码率可以对应一个序列,第二序列即目标码率对应的该序列。在该实现方式中,N0可以为预设值。上述设计,通过针对相同的码率、不同的码长设计同一个序列,使得同一个序列可以用于构造一系列相同码率、不同长度的Polar码,可以降低系统复杂度。
一种可能的设计中,目标码率可以对应一个序列,第二序列是根据目标码率对应的序列确定的。上述设计,通过针对相同的码率、不同的码长设计同一个序列,使得同一个序列可以用于构造一系列相同码率、不同长度的Polar码,可以降低系统复杂度。
一种可能的设计中,K个信息比特的位置与N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
一种可能的设计中,第二序列包括N0个数值,其中,第二序列中第n个数值用于表征N0个比特位中第n个比特位的选择优先级,n遍历从0到N0-1的整数。
一种可能的设计中,用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;用于放置信息比特的比特位在第二序列中对应的数值不满足第一准则。上述方式使得长度匹配过程(也就是确定打孔比特的过程)与编码构造过程(确定信息比特位置的过程)互相独立,可以降低实现复杂度。
一种可能的设计中,第二序列中数值与选择优先级成反比,第一准则为取值大于或等于K;或者,第二序列中数值与选择优先级成正比,第一准则为取值小于或等于(N0-K)。
一种可能的设计中,目标码率为预先设置的,或者,目标码率是在码率集合中选择的,码率集合包括一个或多个码率。
第三方面,本申请还提供一种通信装置,所述装置为发送侧设备或发送侧设备中的芯片。该通信装置具有实现上述第一方面提供的任一方法的功能。该通信装置可以通过硬件实现,也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元或模块。
一种可能的设计中,该通信装置包括:处理器,该处理器被配置为支持该通信装置执行以上所示方法中发送侧设备的相应功能。该通信装置还可以包括存储器,该存储可以与处理器耦合,其保存该通信装置必要的程序指令和数据。可选地,该通信装置还包括接口电路,该接口电路用于支持该通信装置与接收侧设备等设备之间的通信,例如数据或信号的收发。示例性的,通信接口可以是收发器、电路、总线、模块或其它类型的通信接口。
一种可能的设计中,该通信装置包括相应的功能模块,分别用于实现以上方法中的步骤。功能可以通过硬件实现,也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。
一种可能的设计中,通信装置的结构中包括处理单元(或处理单元)和通信单元(或通信单元),这些单元可以执行上述方法示例中相应功能,具体参见第一方面提供的方法中的描述,此处不做赘述。
第四方面,本申请还提供一种通信装置,所述装置为接收侧设备或接收侧设备中的芯片。该通信装置具有实现上述第二方面提供的任一方法的功能。该通信装置可以通过硬件实现,也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元或模块。
一种可能的设计中,该通信装置包括:处理器,该处理器被配置为支持该通信装置执行以上所示方法中接收侧设备的相应功能。该通信装置还可以包括存储器,该存储可以与处理器耦合,其保存该通信装置必要的程序指令和数据。可选地,该通信装置还包括接口电路,该接口电路用于支持该通信装置与发送侧设备等设备之间的通信,例如数据或信号的收发。示例性的,通信接口可以是收发器、电路、总线、模块或其它类型的通信接口。
一种可能的设计中,该通信装置包括相应的功能模块,分别用于实现以上方法中的步骤。功能可以通过硬件实现,也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。
一种可能的设计中,通信装置的结构中包括处理单元(或处理单元)和通信单元(或通信单元),这些单元可以执行上述方法示例中相应功能,具体参见第二方面提供的方法中的描述,此处不做赘述。
第五方面,提供了一种通信装置,包括处理器和接口电路,接口电路用于接收来自该通信装置之外的其它通信装置的信号并传输至该处理器或将来自该处理器的信号发送给该通信装置之外的其它通信装置,该处理器通过逻辑电路或执行代码指令用于实现前述第一方面以及任意可能的设计中的方法。
第六方面,提供了一种通信装置,包括处理器和接口电路,接口电路用于接收来自该通信装置之外的其它通信装置的信号并传输至该处理器或将来自该处理器的信号发送给该通信装置之外的其它通信装置,该处理器通过逻辑电路或执行代码指令用于实现前述第二方面以及任意可能的设计中的方法。
第七方面,提供了一种计算机可读存储介质,该计算机可读存储介质中存储有计算机程序或指令,当该计算机程序或指令被处理器执行时,实现前述第一方面或第二方面以及任意可能的设计中的方法。
第八方面,提供了一种存储有指令的计算机程序产品,当该指令被处理器运行时,实现前述第一方面或第二方面以及任意可能的设计中的方法。
第九方面,提供一种芯片系统,该芯片系统包括处理器,还可以包括存储器,用于实现前述第一方面或第二方面以及任意可能的设计中的方法。该芯片系统可以由芯片构成,也可以包含芯片和其他分立器件。
第十方面,提供一种通信系统,所述系统包括第一方面所述的装置(如发送侧设备)以及第二方面所述的装置(如接收侧设备)。
上述第三方面至第十方面中任一方面的技术方案可以达到的技术效果,可以参照上述第一方面的技术方案可以达到的技术效果描述,重复之处不予赘述。
附图说明
图1为本申请实施例中的一种polar码编码示意图;
图2为本申请实施例中的一种通信系统架构示意图;
图3为本申请实施例中的一种发送端和接收端之间的交互示意图;
图4为本申请实施例中的一种通信方法的流程示意图;
图5为本申请实施例中的一种通信装置的结构示意图;
图6为本申请实施例中的另一种通信装置的结构示意图。
具体实施方式
为了使本申请实施例的目的、技术方案和优点更加清楚,下面将结合附图对本申请实施例作进一步地详细描述。
以下,对本申请实施例中的部分用语进行解释说明,以便于本领域技术人员理解。
1)极化(polar)码编码:polar码编码是一种能够被严格证明达到信道容量的信道编码方案,具有高性能,较低复杂度,匹配方式灵活等特点。目前已经被第三代合作计划(3rd generation partnership project,3GPP)确定成为5G控制信道增强移动宽带(enhanced mobile broadband,eMBB)场景控制信道编码方案。
参见图1,示意一种典型的长度为8的polar码编码过程。待编码比特序列根据其各自的可靠度分为固定比特(frozen)和信息比特(data)两类。一般地,可靠度较高的比特设置为信息比特(data),可靠度较低的比特设置为固定比特(frozen),固定比特的值通常设置为0,在实际传输中发送端和接收端均已知。图1对应的编码码长为8比特(bits),示意出了{u0,u1,u2,u4}为固定比特的位置,{u3,u5,u6,u7}为信息比特的位置。每一行中的每一个圆圈表示圆圈所在行的比特与圆圈所达行之间的一次异或运算(或称,模二加),圆圈右侧的比特即为求和结果。
2)嵌套性
对于给定码率情况下,一个长度为M的Polar码可以分为上半区与下半区,其中分别对应于前M/2个比特、后M/2个比特。Polar码的构造可以理解为将K个信息位合理地分配在这两个半区,且在给定码率时,无论码长多少,两个半区的信息位分配比率可以保持不变。例如,短码长Polar码的信息位长度是K1,长码长Polar码的信息位长度是K2,两个码长下分配在上半区的信息位比例均是P。随着信息位长度增加,上半区、下半区的信息位长度均等比增加,上半区的信息位长度满足P*K1<P*K2,下半区的信息位满足(1-P)*K1<(1-P)*K2,基于这个原则构造polar码可以使得满足相同码率、不同长度的Polar码的信息位满足嵌套性。
本申请实施例中“至少一个”是指一个或者多个,“多个”是指两个或两个以上。“和/或”,描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B的情况,其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达,是指的这些项中的任意组合,包括单项(个)或复数项(个)的任意组合。例如,a,b,或c中的至少一项(个),可以表示:a,b,c,a-b,a-c,b-c,或a-b-c,其中a,b,c可以是单个,也可以是多个。
以及,除非有相反的说明,本申请实施例提及“第一”、“第二”等序数词是用于对多个对象进行区分,不用于限定多个对象的大小、内容、顺序、时序、优先级或者重要程度等。例如,第一序列和第二序列,只是为了区分不同的序列,而并不是表示这两个序列的长度、优先级或者重要程度等的不同。
前文介绍了本申请实施例所涉及到的一些名词概念,下面介绍本申请实施例涉及的技术特征。
从前文术语介绍可以看出,Polar码编码后的母码长度通常是2的整数次幂。当实际通信的码长N不等于Polar码编码后的长度时,需要进一步通过打孔、重传等方式实现码长匹配过程。打孔、重传就是指将编码得到的比特序列去掉或者重传若干个比特,使其适用码长的需求。
Polar码构造是指基于给定码长N与信息比特长度K,得到Polar码构造的过程。目前构造Polar码时,首先需要先确定长度匹配方式如打孔(puncture)、重传、截断(shorten)等,再根据长度匹配方式去除预冻结位置,再基于Q序列获取Polar码的信息位。Q序列用于表征子信道的可靠度。Q序列中的值表示子信道的序号,其在序列中的位置表示对应子信道的可靠度。例如,对于长度为8的Q序列,[0 1 2 4 3 5 6 7],即表示序列为7的信道是最可靠的一个子信道,序列6的信道是第二可靠的信道。结合该举例对Polar码构造过程进行说明。假设构造N=6、K=4长的Polar码,首先基于码率确定长度匹配方式为shorten,再进一步确定出shorten位置是6与7,因此将6与7子信道预冻结,即6与7不能选择信息位。因此在构造Polar码之前,先将Q序列中的6与7去掉,即得到[0 1 2 4 3 5],再从后往前选出4个位置,即2、4、3、5作为信息位,剩余位置作为冻结位。
可以看出,现在的Polar码构造方式中必须先执行长度匹配,再进行信息位选择,这个实现过程比较复杂,不适配超低功耗场景的需求。
基于此,本申请实施例提供一种通信方法及装置,用于降低Polar码构造过程的复杂度。其中,方法和装置是基于同一构思的,由于方法及装置解决问题的原理相似,因此装置与方法的实施可以相互参见,重复之处不再赘述。
本申请实施例可以应用于多种需要信道编码的无线通信领域,例如前述无线通信领域可以包括但不限于5G通信系统、未来的通信系统(如6G通信系统)、卫星通信系统、设备到设备(device-to-device,D2D)通信系统、机器到机器(machine to machine,M2M)通信系统、物联网(internet of things,IoT)、无人机通信系统、窄带物联网系统(narrow band-internet of things,NB-IoT)、长期演进系统(long term evolution,LTE)以及5G移动通信系统的三大应用场景eMBB,超高可靠与低延迟的通信(ultra reliable low latency communication,URLLC)以及大规模机器通信(massive machine-type communications,mMTC)。
下面结合图2,介绍本申请实施例提供的编码和译码方法所适用的通信系统。参见图2示意的一种通信系统架构,该通信系统包括发送端201和接收端202。其中,发送端201可以是网络设备或者可以是终端设备,接收端202可以是网络设备也可以是终端设备。可选的,当发送端201是网络设备时,接收端202可以是终端设备;当发送端201是终端设备,接收端202可以是网络设备也可以是终端设备。示例性的,图2示意出了发送端201为终端设备、接收端202为网络设备。需要说明的是,图2所示的通信系统中的设备的数量仅仅为示例,不作为对本申请的限定。
其中,网络设备可以为具有无线收发功能的设备或可设置于该网络设备的芯片,该网络设备包括但不限于:基站(generation node B,gNB)、无线网络控制器(radio network controller,RNC)、节点B(Node B,NB)、基站控制器(base station controller,BSC)、基站收发台(base transceiver station,BTS)、家庭基站(例如,home evolved NodeB,或home Node B,HNB)、基带单元(baseband unit,BBU),无线保真(wireless fidelity,Wi-Fi)系统中的接入点(access point,AP)、无线中继节点、无线回传节点、卫星、无人机、传输点(transmission and reception point,TRP或者transmission point,TP)等,还可以为构成gNB或传输点的网络节点,如基带单元(BBU),或,分布式单元(distributed unit,DU)等。
终端设备也可以称为用户设备(user equipment,UE)、接入终端、用户单元、用户站、 移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。本申请的实施例中的终端设备可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、虚拟现实(virtual reality,VR)终端设备、增强现实(augmented reality,AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、无人机、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智能穿戴设备(智能眼镜、智能手表、智能耳机等)、智慧家庭(smart home)中的无线终端等等,也可以是能够设置于以上设备的芯片或芯片模组(或芯片系统)等。本申请中将具有无线收发功能的终端设备及可设置于前述终端设备的芯片统称为终端设备。
参见图3示意性的示出一种发送端和接收端之间的交互示意图,发送端的信源依次经过信源编码、信道编码、速率匹配和调制后在信道上发出。接收端收到信号后依次经过解调及解速率匹配、信道解码和信源解码后获得信宿。本申请实施例提供的方法可以用于在信道编码过程。
参见图4,为本申请提供的一种通信方法的流程示意图。该方法包括:
S401,发送端获取待编码比特序列。
待编码比特序列包括K个信息比特,K为大于0的整数。
S402,发送端确定第一序列。
其中,K个信息比特在第一序列中的位置是根据目标码率对应的第二序列以及K的取值确定的,其中,第二序列用于表征N0个比特位的选择优先级,N0为大于K的整数。本申请实施例中N0的取值与polar码母码长度没有严格的对应关系。
第二序列的一种举例说明,第二序列包括N0个数值,其中,第二序列中数值的位置表示对应的比特位,数值的大小表示该比特位的选择优先级,也就是,第二序列中第n个数值用于表征N0个比特位中第n个比特位的选择优先级,n遍历从0到N0-1的整数。其中,第二序列中,数值和选择优先级可以是反比关系,也就是,数值越大表示选择优先级越低。或者,数值和选择优先级也可以是正比关系,即数值越大表示选择优先级越高。如何确定K个信息比特在第一序列中的位置,将在下文详细说明。
一种可能的实现方式中,目标码率可以对应一个序列,第二序列即目标码率对应的该序列。在该实现方式中,N0可以为预设值。
另一种可能的实现方式中,目标码率也可以对应多个序列,其中,该多个序列对应不同的码长,第二序列可以是目标码率对应的多个序列中与目标码长有对应关系的序列。在该实现方式中,E为目标码长,表示向上取整。
在上述实现方式中,目标码率对应的序列中长度为N0的序列和长度为的序列满足嵌套关系,R为大于0的整数。一种可能的实现方式中,R最大可以为3。
再一种可能的实现方式中,目标码率可以对应一个序列,发送端可以根据该序列确定目标码长对应的序列,即第二序列是根据目标码率对应的序列确定。具体的,第二序列与目标码率对应的序列满足嵌套关系,发送端根据嵌套关系通过目标码率对应的序列确定第二序列。
下面以长度为512的序列1和长度为256的序列2、长度为128的序列3、长度为64的序列4之间的嵌套关系为例进行说明。
假设长度为512的序列1为[511,510,509,505,508,503,502,491,507,501,499,487,497,483,480,457,506,498,496,482,493,477,473,448,490,472,468,441,462,433,426,387,504,494,492,474,489,470,467,438,484,463,458,427,452,419,413,370,478,455,449,416,443,408,401,356,434,397,388,343,378,331,321,269,500,488,485,465,481,459,453,421,476,451,446,411,440,404,395,350,469,442,436,399,428,389,380,333,418,377,368,319,359,308,298,235,460,430,423,383,414,372,364,314,405,360,352,300,341,289,279,207,391,346,336,284,323,271,263,191,309,260,231,178,223,165,162,144,495,479,475,450,471,444,439,402,464,435,429,390,420,379,371,322,456,425,417,376,409,366,357,306,398,354,345,294,332,281,270,171,445,410,403,358,394,349,340,288,381,334,324,272,312,247,227,138,367,318,307,229,297,213,201,115,283,198,194,102,160,97,95,77,431,392,384,337,373,325,315,251,361,310,301,203,290,193,179,113,347,296,285,175,273,159,150,90,261,143,135,73,130,65,59,42,327,275,266,146,258,137,131,71,230,123,103,57,96,52,51,25,202,98,87,49,82,41,35,20,74,34,31,19,29,17,16,6,486,466,461,432,454,422,415,374,447,412,406,362,396,351,342,291,437,400,393,348,382,335,326,274,369,320,311,252,299,248,244,232,424,385,375,328,365,316,305,249,353,302,292,243,280,238,234,216,338,286,276,233,264,225,222,208,257,221,220,205,217,204,200,196,407,363,355,304,344,293,282,237,330,278,268,224,259,212,209,184,313,262,254,206,246,195,192,176,240,189,188,172,183,170,168,164,295,250,242,190,226,187,185,157,219,182,180,156,177,154,153,148,211,174,173,155,169,152,149,140,161,147,145,136,142,133,132,128,386,339,329,277,317,265,255,199,303,253,245,167,241,151,139,117,287,239,236,141,228,129,126,110,215,124,122,108,118,105,104,100,267,218,214,125,210,121,120,93,197,116,114,92,111,89,88,81,166,109,106,86,99,84,80,72,94,79,78,70,76,69,68,64,256,186,181,119,163,112,107,60,158,101,91,58,83,56,54,48,134,85,75,53,66,50,47,40,62,45,44,38,43,37,36,32,127,67,63,39,61,33,30,18,55,28,27,15,24,14,13,5,46,26,23,12,22,11,10,4,21,9,8,3,7,2,1,0]。
该序列1分为长度为256的上半区和长度为256的下半区,其中,上半区为[511,510,509,505,508,503,502,491,507,501,499,487,497,483,480,457,506,498,496,482,493,477,473,448,490,472,468,441,462,433,426,387,504,494,492,474,489,470,467,438,484,463,458,427,452,419,413,370,478,455,449,416,443,408,401,356,434,397,388,343,378,331,321,269,500,488,485,465,481,459,453,421,476,451,446,411,440,404,395,350,469,442,436,399,428,389,380,333,418,377,368,319,359,308,298,235,460,430,423,383,414,372,364,314,405,360,352,300,341,289,279,207,391,346, 336,284,323,271,263,191,309,260,231,178,223,165,162,144,495,479,475,450,471,444,439,402,464,435,429,390,420,379,371,322,456,425,417,376,409,366,357,306,398,354,345,294,332,281,270,171,445,410,403,358,394,349,340,288,381,334,324,272,312,247,227,138,367,318,307,229,297,213,201,115,283,198,194,102,160,97,95,77,431,392,384,337,373,325,315,251,361,310,301,203,290,193,179,113,347,296,285,175,273,159,150,90,261,143,135,73,130,65,59,42,327,275,266,146,258,137,131,71,230,123,103,57,96,52,51,25,202,98,87,49,82,41,35,20,74,34,31,19,29,17,16,6]。下半区为[486,466,461,432,454,422,415,374,447,412,406,362,396,351,342,291,437,400,393,348,382,335,326,274,369,320,311,252,299,248,244,232,424,385,375,328,365,316,305,249,353,302,292,243,280,238,234,216,338,286,276,233,264,225,222,208,257,221,220,205,217,204,200,196,407,363,355,304,344,293,282,237,330,278,268,224,259,212,209,184,313,262,254,206,246,195,192,176,240,189,188,172,183,170,168,164,295,250,242,190,226,187,185,157,219,182,180,156,177,154,153,148,211,174,173,155,169,152,149,140,161,147,145,136,142,133,132,128,386,339,329,277,317,265,255,199,303,253,245,167,241,151,139,117,287,239,236,141,228,129,126,110,215,124,122,108,118,105,104,100,267,218,214,125,210,121,120,93,197,116,114,92,111,89,88,81,166,109,106,86,99,84,80,72,94,79,78,70,76,69,68,64,256,186,181,119,163,112,107,60,158,101,91,58,83,56,54,48,134,85,75,53,66,50,47,40,62,45,44,38,43,37,36,32,127,67,63,39,61,33,30,18,55,28,27,15,24,14,13,5,46,26,23,12,22,11,10,4,21,9,8,3,7,2,1,0]。
长度为256的序列2可以包括序列1的上半区的后128个数值,即[495,479,475,450,471,444,439,402,464,435,429,390,420,379,371,322,456,425,417,376,409,366,357,306,398,354,345,294,332,281,270,171,445,410,403,358,394,349,340,288,381,334,324,272,312,247,227,138,367,318,307,229,297,213,201,115,283,198,194,102,160,97,95,77,431,392,384,337,373,325,315,251,361,310,301,203,290,193,179,113,347,296,285,175,273,159,150,90,261,143,135,73,130,65,59,42,327,275,266,146,258,137,131,71,230,123,103,57,96,52,51,25,202,98,87,49,82,41,35,20,74,34,31,19,29,17,16,6];以及,序列1的下半区的后128个数值即[386,339,329,277,317,265,255,199,303,253,245,167,241,151,139,117,287,239,236,141,228,129,126,110,215,124,122,108,118,105,104,100,267,218,214,125,210,121,120,93,197,116,114,92,111,89,88,81,166,109,106,86,99,84,80,72,94,79,78,70,76,69,68,64,256,186,181,119,163,112,107,60,158,101,91,58,83,56,54,48,134,85,75,53,66,50,47,40,62,45,44,38,43,37,36,32,127,67,63,39,61,33,30,18,55,28,27,15,24,14,13,5,46,26,23,12,22,11,10,4,21,9,8,3,7,2,1,0]。
长度为128的序列3可以包括序列1的上半区的后64个数值,也就是序列2的上半区的后64个数值,即[431,392,384,337,373,325,315,251,361,310,301,203,290,193,179,113,347,296,285,175,273,159,150,90,261,143,135,73,130,65,59,42,327,275,266,146,258,137,131,71,230,123,103,57,96,52,51,25,202,98,87,49,82,41,35,20,74,34,31,19,29,17,16,6];以及,序列1的下半区的后64个数值,也就是序列2的下半区的后64个数值,即[256,186,181,119,163,112,107,60,158,101,91,58,83,56,54,48,134,85,75,53,66,50,47,40,62,45,44,38,43,37,36,32,127,67,63,39,61,33,30,18,55,28,27,15,24,14,13,5,46,26,23,12,22,11,10,4,21,9,8,3,7,2,1,0]。
长度为64的序列4可以包括序列1的上半区的后32个数值,也就是序列2的上半区的后32个数值,也就是序列3的上半区的后32个数值,即[327,275,266,146,258,137,131,71,230,123,103,57,96,52,51,25,202,98,87,49,82,41,35,20,74,34,31,19,29,17,16,6];以及,序列1的下半区的后32个数值,也就是序列2的下半区的后32个数值,也就是序列3的下半区的后32个数值,即[127,67,63,39,61,33,30,18,55,28,27,15,24,14,13,5,46,26,23,12,22,11,10,4,21,9,8,3,7,2,1,0]。
可以理解的,基于相同的目标码长、目标码率以及待编码比特序列,基于序列1~4发送的第一序列是一致的。
可选的,K个信息比特在第一序列中的位置根据目标码率对应的第二序列以及K的取值确定,具体可以是,该K个信息比特在第一序列中的位置可以与N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
作为一种可能的实现方式,K个信息比特在第一序列中的位置可以通过如下方式确定:将第二序列中的每个数值与K进行对比,若该数值满足第一准则,则该数值对应的比特位用于放置冻结比特,若该数值不满足第一准则,则该数值对应的比特位用于放置信息比特。
也就是,第一序列中用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;第一序列中用于放置信息比特的比特位的取值不满足第一准则。
例如,若第二序列中数值越大表示选择优先级越小,则第一准则可以为数值大于或等于K。又例如,若第二序列中数值越小表示选择优先级越小,则第一准则可以为数值小于或等于(N0-K)。
本申请实施例中,目标码率可以是为预先设置的,或者,也可以是在码率集合中选择的,码率集合包括一个或多个码率。
可以理解的,根据目标码率α和N0的取值,可以确定第二序列支持的信息比特的最大数量也即是α*N0。一种可能的实现方式中,第二序列中可以包括至少α*N0个比特位对应的选择优先级,其他(N0-α*N0)个比特位中全部或部分比特位的选择优先级可以是特定标识例如特定值等。
例如,目标码率为1/2码率,N0为512,可以确定第二序列支持的信息比特的最大数量为256,第二序列中包括256个比特位对应的选择优先级,其他256个比特位的选择优先级可以是X。
由于第二序列最多支持α*N0个比特位,因此其余(N0-α*N0)个比特位不会被用于放 置信息比特,上述方式通过将其余(N0-α*N0)个比特位中全部或部分比特位的选择优先级用特定标识表示,可以进一步降低第二序列的复杂度。
本申请实施例中第二序列是针对固定码率设计的,同一个序列可以用于构造一系列相同码率、不同长度的Polar码,相比于针对不同码率、不同码长设计的Q序列,本申请实施例中第二序列可以降低系统实现的功耗。尤其是在只需要支持几个码率,但需要支持较多不同的码长一些极简场景下,本申请实施例提供的方法可以极大地降低系统实现的功耗。
S403,发送端将第一序列进行极化码编码,得到第三序列。
S404,发送端发送第三序列。相应的,接收端接收第三序列。
应理解,S404只是为了简化描述,在具体实施中还可以包括速率匹配、调制、变频等操作。相应的,接收端接收第三序列,实际是第三序列经过了速率匹配、调制、变频等操作后经过空间信道收到的信号,在不影响理解的情况下,本申请不再区分。
一种可能的实施方式中,接收端在接收到第三序列后,根据K个信息比特的位置对第三序列进行译码。其中,K个信息比特的位置的确定方式与发送端确定K个信息比特的位置的方式相同,具体可以参阅发送端的描述,这里不再重复说明。
一种可能的实施方式中,发送端在发送第三序列之前,可以打孔第三序列中的(N0-E)个比特,E为目标码长,E为大于0且小于或等于N0的整数。相应的,接收端在根据K个信息比特的位置对第三序列进行译码之前,可以恢复第三序列中被打孔的(N0-E)个比特。例如,可以确定第三序列中被打孔的(N0-E)个比特的位置,并将该被打孔的(N0-E)个比特填充为0。
接收端确定第三序列中被打孔的(N0-E)个比特的位置的方式与发送端确定该(N0-E)个比特的位置的方式相同,具体可以参阅发送端确定该(N0-E)个比特的位置的方式,重复之处不再赘述。
可选的,该(N0-E)个比特可以通过如下方式确定:将第三序列中每个比特的序号i基于N0/2进行取余,若余数满足第二准则,则确定该比特需要被打孔,即该比特属于上述(N0-E)个比特,若余数不满足第二准则,则确定该比特不被打孔(也就是保留该比特),即该比特不属于上述(N0-E)个比特,上述i遍历从0到N0-1的整数。
也就是,(N0-E)个比特中任一比特在第三序列中的序号基于N0/2进行取余后的余数满足第二准则。
示例性的,第二准则可以为余数小于(N0/2-E/2)。
为了便于对本申请实施例的理解,下面以K=32,E为64为例,分别结合上述序列1对polar码构造过程进行举例说明。假设序列1中数值越大表示选择优先级越小,polar码构造以及发送过程可以包括如下A1~A4实现:
A1,确定待编码比特序列的32个信息比特在第一序列中的位置。
具体的,可以将序列1中的每个数值与K也就是32进行对比,若该数值大于或等于32,则该数值对应的比特位用于放置冻结比特,若该数值小于32,则该数值对应的比特位用于放置信息比特。
根据步骤A1,第一序列中放置冻结比特的比特位和放置信息比特的比特位的位置参阅如下序列,其中,1表示用于放置信息比特,0表示用于放置冻结比特:[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,0,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]。
应理解,这里仅是一种示例性说明,在具体实施中也可以用0表示用于放置信息比特,1表示用于放置冻结比特。
需要注意的是,上述序列仅是用于示意第一序列中放置冻结比特的比特位和放置信息比特的比特位的位置,并不表示第一序列中各比特的取值。上述序列中,480个0对应的比特位可以放置冻结比特,32个1对应的比特位可以放置待编码比特序列的32个信息比特。
A2,将第一序列进行极化码编码,得到第三序列。
A3,打孔第三序列中的448个比特。
具体的,可以遍历i从0到N0-1的整数,如果rem(i,N0/2)小于(N0/2-E/2),则第一序列中第i个比特被打孔,如果rem(i,N0/2)不小于(N0/2-E/2),则第一序列中第i个比特不被打孔。则第一序列中第1~224个比特和第257~480个比特被打孔。
A4,发送打孔后的第三序列。
本申请实施例中第二序列是针对固定码率设计的,同一个序列可以用于构造一系列相同码率、不同长度的Polar码,相比于针对不同码率、不同码长设计的Q序列,本申请实施例中第二序列可以降低系统实现的功耗。尤其是在只需要支持几个码率,但需要支持较多不同的码长一些极简场景下,本申请实施例提供的方法可以极大地降低系统实现的功耗。
此外,本申请实施例中长度匹配过程(也就是确定打孔比特的过程)与编码构造过程(确定信息比特位置的过程)互相独立,可以降低实现复杂度。并且,本申请实施例中长度匹配过程、编码构造过程均可以保证polar码的嵌套性,也就是polar码的上半区、下半区的信息位长度均等比增加,从而可以保证通信性能。
基于与方法实施例的同一发明构思,本申请实施例提供一种通信装置,该通信装置的结构可以如图5所示,包括通信单元601和处理单元602。
在一种实施方式中,通信装置具体可以用于实现图4的实施例中发送端执行的方法,该装置可以是发送端本身,也可以是发送端中的芯片或芯片组或芯片中用于执行相关方法功能的一部分。其中,处理单元602,用于获取待编码比特序列,所述待编码比特序列包括K个信息比特,所述K为大于0的整数;以及,确定第一序列,所述K个信息比特在所述第一序列中的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;以及,将所述第一序列进行极化码编码,得到第三序列;通信单元601,用于发送所述第三序列。
可选的,所述处理单元602,还用于:在发送所述第三序列之前,打孔所述第三序列中的(N0-E)个比特,所述E为目标码长,所述E为大于0且小于或等于所述N0的整数。
示例性的,所述(N0-E)个比特中任一比特在所述第三序列中的序号基于N0/2进行取余后的余数满足第二准则。
示例性的,所述第二准则为余数小于(N0/2-E/2)。
示例性的,或者,所述N0为预设值。
示例性的,所述K个信息比特在所述第一序列中的位置与所述N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
示例性的,所述第二序列包括N0个数值,其中,所述第二序列中第n个数值用于表征所述N0个比特位中第n个比特位的选择优先级,所述n遍历从0到N0-1的整数。
示例性的,所述第一序列中用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;所述第一序列中用于放置信息比特的比特位在第二序列中对应的数值不满足所述第一准则。
示例性的,所述第二序列中数值与选择优先级成反比,所述第一准则为取值大于或等于K;或者,所述第二序列中数值与选择优先级成正比,所述第一准则为取值小于或等于(N0-K)。
示例性的,所述目标码率为预先设置的,或者,所述目标码率是在码率集合中选择的,所述码率集合包括一个或多个码率。
在一种实施方式中,图5所示的通信装置具体可以用于实现图4的实施例中接收端执行的方法,该装置可以是接收端本身,也可以是接收端中的芯片或芯片组或芯片中用于执行相关方法功能的一部分。其中,通信单元601,用于获取第三序列;处理单元602,用于确定K个信息比特的位置,所述K个信息比特的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;以及,根据K个信息比特的位置对所述第三序列进行解码。
可选的,处理单元602,还用于:在根据K个信息比特的位置对所述第三序列进行解码之前,恢复第三序列中被打孔的(N0-E)个比特,E为目标码长,E为大于0且小于或等于N0的整数。
示例性的,(N0-E)个比特中任一比特在第三序列中的序号基于N0/2进行取余后的余数满足第二准则。
示例性的,第二准则为余数小于(N0/2-E/2)。
示例性的,表示向上取整。
示例性的,K个信息比特的位置与N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
示例性的,第二序列包括N0个数值,其中,第二序列中第n个数值用于表征N0个比特位中第n个比特位的选择优先级,n遍历从0到N0-1的整数。
示例性的,用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;用于放置信息比特的比特位在第二序列中对应的数值不满足第一准则。上述方式使得长度匹配过程(也就是确定打孔比特的过程)与编码构造过程(确定信息比特位置的过程)互相独立,可以降低实现复杂度。
示例性的,第二序列中数值与选择优先级成反比,第一准则为取值大于或等于K;或者,第二序列中数值与选择优先级成正比,第一准则为取值小于或等于(N0-K)。
示例性的,目标码率为预先设置的,或者,目标码率是在码率集合中选择的,码率集合包括一个或多个码率。
本申请实施例中对模块的划分是示意性的,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,另外,在本申请各个实施例中的各功能模块可以集成在一个处理器中,也可以是单独物理存在,也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现,也可以采用软件功能模块的形式实现。可以理解的是,本申请实施例中各个模块的功能或者实现可以进一步参考方法实施例的相关描述。
一种可能的方式中,通信装置可以如图6所示,该装置可以是通信设备或者通信设备中的芯片,其中该通信设备可以为上述实施例中的终端设备也可以是上述实施例中的网络设备。该装置包括处理器701和通信接口702,还可以包括存储器703。其中,处理单元602可以为处理器701。通信单元601可以为通信接口702。可选的,处理器701和存储器703也可以集成在一起。
处理器701,可以是一个CPU,或者为数字处理单元等等。通信接口702可以是收发器、也可以为接口电路如收发电路等、也可以为收发芯片等等。该装置还包括:存储器703,用于存储处理器701执行的程序。存储器703可以是非易失性存储器,比如硬盘(hard disk drive,HDD)或固态硬盘(solid-state drive,SSD)等,还可以是易失性存储器(volatile memory),例如随机存取存储器(random-access memory,RAM)。存储器703是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质,但不限于此。
处理器701用于执行存储器703存储的程序代码,具体用于执行上述处理单元602的动作,本申请在此不再赘述。通信接口702具体用于执行上述通信单元601的动作,本申请在此不再赘述。
本申请实施例中不限定上述通信接口702、处理器701以及存储器703之间的具体连接介质。本申请实施例在图6中以存储器703、处理器701以及通信接口702之间通过总线704连接,总线在图6中以粗线表示,其它部件之间的连接方式,仅是进行示意性说明,并不引以为限。总线可以分为地址总线、数据总线、控制总线等。为便于表示,图6中仅用一条粗线表示,但并不表示仅有一根总线或一种类型的总线。
本发明实施例还提供了一种计算机可读存储介质,用于存储为执行上述处理器所需执行的计算机软件指令,其包含用于执行上述处理器所需执行的程序。
本申请实施例还提供一种通信系统,包括用于实现图4的实施例中发送端功能的通信装置和用于实现图4的实施例中接收端功能的通信装置。
本领域内的技术人员应明白,本申请的实施例可提供为方法、系统、或计算机程序产 品。因此,本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且,本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器,使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中,使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品,该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上,使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理,从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。

Claims (28)

  1. 一种通信方法,其特征在于,所述方法包括:
    获取待编码比特序列,所述待编码比特序列包括K个信息比特,所述K为大于0的整数;
    确定第一序列,所述K个信息比特在所述第一序列中的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;
    将所述第一序列进行极化码编码,得到第三序列;
    发送所述第三序列。
  2. 如权利要求1所述的方法,其特征在于,在发送所述第三序列之前,所述方法还包括:
    打孔所述第三序列中的(N0-E)个比特,所述E为目标码长,所述E为大于0且小于所述N0的整数。
  3. 如权利要求2所述的方法,其特征在于,所述(N0-E)个比特中任一比特在所述第三序列中的序号基于N0/2进行取余后的余数满足第二准则。
  4. 如权利要求3所述的方法,其特征在于,所述第二准则为余数小于(N0/2-E/2)。
  5. 如权利要求1-4任一项所述的方法,其特征在于,或者,所述N0为预设值,表示向上取整。
  6. 如权利要求1-5任一项所述的方法,其特征在于,所述K个信息比特在所述第一序列中的位置与所述N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
  7. 如权利要求1-6任一项所述的方法,其特征在于,所述第二序列包括N0个数值,其中,所述第二序列中第n个数值用于表征所述N0个比特位中第n个比特位的选择优先级,所述n遍历从0到N0-1的整数。
  8. 如权利要求7所述的方法,其特征在于,所述第一序列中用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;
    所述第一序列中用于放置信息比特的比特位在第二序列中对应的数值不满足所述第一准则。
  9. 如权利要求8所述的方法,其特征在于,所述第二序列中数值与选择优先级成反比,所述第一准则为取值大于或等于K;
    或者,所述第二序列中数值与选择优先级成正比,所述第一准则为取值小于或等于(N0-K)。
  10. 如权利要求1-9任一项所述的方法,其特征在于,所述目标码率为预先设置的,或者,所述目标码率是在码率集合中选择的,所述码率集合包括一个或多个码率。
  11. 一种通信方法,其特征在于,所述方法包括:
    获取第三序列;
    确定K个信息比特的位置,所述K个信息比特的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;
    根据K个信息比特的位置对所述第三序列进行解码。
  12. 一种通信装置,其特征在于,所述装置包括:
    处理单元,用于获取待编码比特序列,所述待编码比特序列包括K个信息比特,所述K为大于0的整数;
    以及,确定第一序列,所述K个信息比特在所述第一序列中的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;
    以及,将所述第一序列进行极化码编码,得到第三序列;
    通信单元,用于发送所述第三序列。
  13. 如权利要求12所述的装置,其特征在于,所述处理单元,还用于:
    在发送所述第三序列之前,打孔所述第三序列中的(N0-E)个比特,所述E为目标码长,所述E为大于0且小于所述N0的整数。
  14. 如权利要求13所述的装置,其特征在于,所述(N0-E)个比特中任一比特在所述第三序列中的序号基于N0/2进行取余后的余数满足第二准则。
  15. 如权利要求14所述的装置,其特征在于,所述第二准则为余数小于(N0/2-E/2)。
  16. 如权利要求12-15任一项所述的装置,其特征在于,或者,所述N0为预设值。
  17. 如权利要求12-16任一项所述的装置,其特征在于,所述K个信息比特在所述第一序列中的位置与所述N0个比特位按照选择优先级从高到低排序的前K个比特位一一对应。
  18. 如权利要求12-17任一项所述的装置,其特征在于,所述第二序列包括N0个数值,其中,所述第二序列中第n个数值用于表征所述N0个比特位中第n个比特位的选择优先级,所述n遍历从0到N0-1的整数。
  19. 如权利要求18所述的装置,其特征在于,所述第一序列中用于放置冻结比特的比特位在第二序列中对应的数值满足第一准则;
    所述第一序列中用于放置信息比特的比特位在第二序列中对应的数值不满足所述第一准则。
  20. 如权利要求19所述的装置,其特征在于,所述第二序列中数值与选择优先级成反比,所述第一准则为取值大于或等于K;
    或者,所述第二序列中数值与选择优先级成正比,所述第一准则为取值小于或等于(N0-K)。
  21. 如权利要求12-20任一项所述的装置,其特征在于,所述目标码率为预先设置的,或者,所述目标码率是在码率集合中选择的,所述码率集合包括一个或多个码率。
  22. 一种通信装置,其特征在于,所述装置包括:
    通信单元,用于获取第三序列;
    处理单元,用于确定K个信息比特的位置,所述K个信息比特的位置是根据目标码率对应的第二序列以及所述K的取值确定的,其中,所述第二序列用于表征N0个比特位的选择优先级,所述N0为大于K的整数;
    以及,根据K个信息比特的位置对所述第三序列进行解码。
  23. 一种通信装置,其特征在于,包括处理器,所述处理器用于运行一组程序,以使得如权利要求1~10任一项所述的方法被执行,或如权利要求11所述的方法被执行。
  24. 如权利要求23所述的装置,其特征在于,还包括存储器,所述存储器存储有所述 处理器运行的程序。
  25. 如权利要求23或24所述的装置,其特征在于,所述装置为芯片或集成电路。
  26. 一种计算机可读存储介质,其特征在于,所述计算机存储介质中存储有计算机可读指令,当所述计算机可读指令在通信装置上运行时,使得如权利要求1~10任一项所述的方法被执行,或,如权利要求11所述的方法被执行。
  27. 一种计算机程序产品,其特征在于,当所述计算机程序产品在设备上运行时,使得所述设备执行权利要求1至10任一项所述的方法或者权利要求11所述的方法。
  28. 一种通信系统,其特征在于,所述系统包括如权利要求12-21任一项所述的装置以及权利要求22所述的装置。
PCT/CN2023/096532 2022-06-17 2023-05-26 一种通信方法及装置 WO2023241334A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018127155A1 (zh) * 2017-01-06 2018-07-12 株式会社Ntt都科摩 编码方法和编码器
CN109150378A (zh) * 2017-06-16 2019-01-04 华为技术有限公司 一种数据处理方法及数据处理装置
CN110048726A (zh) * 2017-04-25 2019-07-23 华为技术有限公司 编码方法、译码方法、装置和设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018127155A1 (zh) * 2017-01-06 2018-07-12 株式会社Ntt都科摩 编码方法和编码器
CN110048726A (zh) * 2017-04-25 2019-07-23 华为技术有限公司 编码方法、译码方法、装置和设备
CN109150378A (zh) * 2017-06-16 2019-01-04 华为技术有限公司 一种数据处理方法及数据处理装置

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