WO2023240586A1 - 显示面板的驱动方法、驱动电路、驱动芯片和显示设备 - Google Patents

显示面板的驱动方法、驱动电路、驱动芯片和显示设备 Download PDF

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Publication number
WO2023240586A1
WO2023240586A1 PCT/CN2022/099392 CN2022099392W WO2023240586A1 WO 2023240586 A1 WO2023240586 A1 WO 2023240586A1 CN 2022099392 W CN2022099392 W CN 2022099392W WO 2023240586 A1 WO2023240586 A1 WO 2023240586A1
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Prior art keywords
negative
driving
voltage
signal
positive
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PCT/CN2022/099392
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English (en)
French (fr)
Inventor
魏重光
杨炜帆
丁璐
王琳琳
冯博
尹晓峰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/099392 priority Critical patent/WO2023240586A1/zh
Priority to CN202280001815.4A priority patent/CN117795591A/zh
Publication of WO2023240586A1 publication Critical patent/WO2023240586A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving method, a driving circuit, a driving chip and a display device for a display panel.
  • LCD Liquid Crystal Display
  • e-sports displays increasing the refresh rate is an important measure to improve the performance of the LCD display.
  • increasing the refresh rate will shorten the charging time of the pixels, causing the voltage that drives the display to become unstable, causing an afterimage to appear on the LCD display and affecting the display effect.
  • the present disclosure provides a driving method, a driving circuit, a driving chip and a display device for a display panel.
  • the present disclosure provides a driving method for a display panel.
  • the display panel includes a driving pixel array, and the pixel array includes multiple rows of sub-pixels.
  • the driving method includes: within the same display frame, different sub-pixels in a row of sub-pixels are driven by positive driving signals and negative driving signals respectively, and the voltage conversion rate of the positive driving signals is greater than that of the negative driving signals under the same display gray scale. The voltage slew rate of a signal.
  • the rise time of the positive drive signal is shorter than the rise time of the negative drive signal; where the rise time of the forward drive signal represents the rise time required for the forward drive signal to rise from the first voltage to the second voltage, and the negative drive signal
  • the rise time of the signal represents the rise time required for the negative driving signal to rise from the third voltage to the fourth voltage.
  • the ratio between the rise time of the positive drive signal and the rise time of the negative drive signal ranges from 0.25 to 0.4.
  • the falling time of the forward driving signal is greater than the falling time of the negative driving signal; where the falling time of the forward driving signal represents the falling time required for the forward driving signal to drop from the second voltage to the first voltage, and the negative driving signal
  • the fall time of the signal represents the fall time required for the negative driving signal to fall from the fourth voltage to the third voltage.
  • the ratio between the falling time of the positive driving signal and the falling time of the negative driving signal ranges from 1.16 to 1.34.
  • the ratio range between the voltage difference from the first voltage to the forward driving signal valley voltage and the voltage difference from the forward driving signal peak voltage to the forward driving signal valley voltage is 5% to 10%
  • the second voltage to the forward driving signal valley voltage ranges from 5% to 10%
  • the ratio range between the voltage difference of the driving signal valley voltage and the voltage difference from the forward driving signal peak voltage to the forward driving signal valley voltage is 90% to 95%
  • the ratio range to the voltage difference from the negative driving signal peak voltage to the negative driving signal trough voltage is 5% to 10%.
  • the voltage difference from the fourth voltage to the negative driving signal trough voltage is equal to the voltage difference from the negative driving signal peak voltage to
  • the ratio between the voltage differences of the negative drive signal valley voltage ranges from 90% to 95%.
  • the sum of the rise time and fall time of the positive drive signal is smaller than the sum of the rise time and fall time of the negative drive signal.
  • driving different sub-pixels in a row of sub-pixels through positive driving signals and negative driving signals respectively includes: during the process of driving a row of sub-pixels, adjacent sub-pixels along the row direction receive positive driving signals and negative driving signals respectively. Signal.
  • the display panel also includes a data line through which positive driving signals and/or negative driving signals provide driving signals for sub-pixels.
  • the same data line only receives positive driving signals or negative driving signals.
  • the forward drive gear of the positive drive signal is greater than the negative drive gear of the negative drive signal; the forward drive gear represents the rate at which the forward drive signal rises from the first voltage to the second voltage, and the negative drive gear represents the rate at which the forward drive signal rises from the first voltage to the second voltage.
  • the bit represents the rate at which the negative driving signal rises from the third voltage to the fourth voltage.
  • the present disclosure provides a driving circuit for a display panel according to a driving method according to an embodiment of the present disclosure, for driving a pixel array, the pixel array including a plurality of rows of sub-pixels.
  • the drive circuit includes: a drive signal generation sub-circuit for generating a positive drive signal and a negative drive signal; and a drive signal gating sub-circuit for strobing the positive drive signal and the negative drive signal so that they can operate at the same time.
  • the forward drive signal and the negative drive signal drive different sub-pixels in a row of sub-pixels respectively, and the voltage conversion rate of the forward drive signal is greater than the voltage conversion rate of the negative drive signal.
  • the display panel includes 2N data lines; the driving signal gating sub-circuit includes N driving signal gating sub-circuits; wherein, the driving signal gating sub-circuit includes 2 output terminals, respectively electrically connected to 2 data lines, 2 Each output terminal outputs a positive driving signal and a negative driving signal respectively to drive sub-pixels connected to two data lines.
  • the drive signal generation sub-circuit includes: a positive frame amplification unit, electrically connected to the data signal terminal, for receiving the data signal from the data signal terminal and outputting a positive drive signal; and a negative frame amplification unit, electrically connected to the data signal terminal. , used to receive the data signal from the data signal terminal and output the negative driving signal.
  • the positive frame amplification unit includes: a positive frame operational amplifier, electrically connected to the data signal terminal; and a first transistor array, electrically connected between the output terminal of the positive frame amplification operator and the drive signal gating subcircuit.
  • the negative frame amplification unit includes: a negative frame operational amplifier whose input terminal is electrically connected to the data signal terminal; and a second transistor array electrically connected between the output terminal of the positive frame amplification operator and the drive signal gating subcircuit.
  • the driving circuit further includes a first power supply electrically connected to the first transistor array for outputting a first power supply voltage; and a second power supply electrically connected to the second transistor array for outputting a second power supply voltage; wherein, the The first power supply voltage is twice the second power supply voltage.
  • the present disclosure provides a driving chip for a display panel.
  • the driving chip is used to provide a positive driving signal and a negative driving signal to the display panel.
  • the voltage conversion rate of the positive driving signal is greater than that of the negative driving signal. voltage slew rate.
  • the present disclosure provides a display device including a pixel array and a driving circuit according to an embodiment of the present disclosure.
  • the display device further includes: a plurality of data lines, the driving circuit includes a plurality of output terminals, and the plurality of data lines and the plurality of output terminals are respectively connected.
  • Figure 1A is a schematic diagram of an example transistor cell
  • FIG. 1B is a schematic diagram of an I-V characteristic curve according to an example transistor cell
  • FIG. 1C is a schematic diagram of a display screen of a black (L0) white (L255) checkerboard according to an example
  • Figure 1D is a schematic diagram of abnormal display of L127 grayscale image according to an example
  • Figure 1E is a schematic diagram of the normal display of the L127 grayscale image according to an example
  • FIG. 2 shows a flow chart of a driving method of a display panel according to an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of sub-pixel polarity in an example pixel array
  • Figure 4B is a test waveform diagram according to another embodiment of the present disclosure.
  • Figure 4C is a test waveform diagram according to another embodiment of the present disclosure.
  • Figure 4D is a test waveform diagram according to another embodiment of the present disclosure.
  • Figure 4E is a test waveform diagram according to another embodiment of the present disclosure.
  • Figure 4F is a test waveform diagram according to another embodiment of the present disclosure.
  • Figure 4G is a test waveform diagram of a forward driving signal according to another embodiment of the present disclosure.
  • Figure 5 is a block diagram of a driving circuit of a display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a driving circuit of a display panel according to an embodiment of the present disclosure.
  • the electric field generated between the edges of the pixel electrodes and the electric field generated between the pixel electrodes and the common electrode constitute a multi-dimensional electric field, which causes the electric field between the pixel electrodes and above the pixel electrodes in the liquid crystal cell to All aligned liquid crystal molecules can rotate, thereby greatly improving the viewing angle of the display screen.
  • the flipping of liquid crystal molecules can control the amount of light transmitted through the liquid crystal molecules by the backlight, so that the sub-pixels corresponding to the liquid crystal molecules produce corresponding brightness and achieve different grayscale displays.
  • the voltage difference between the data signal voltage applied to the pixel electrode and the common voltage is a negative value.
  • the absolute values of the differences between the positive and negative directions relative to the common voltage are approximately equal, so that the brightness of the positive and negative directions of the same gray scale can be displayed to be the same.
  • Figure 1A is a schematic diagram of an example transistor unit
  • Figure 1B is a schematic diagram of the I-V characteristic curve of an example transistor unit
  • Figure 1C is a schematic diagram of an example black (L0) white (L255) checkerboard display
  • Figure 1D is a schematic diagram showing abnormal display of the L127 gray-scale image according to an example
  • FIG. 1E is a schematic diagram showing normal display of the L127 gray-scale image based on an example.
  • the display displays a black and white checkerboard image
  • the liquid crystal molecules 110 display a black image (B)
  • the liquid crystal molecules 120 display a white image (W).
  • the sub-pixel corresponding to the liquid crystal molecules 110 is driven by the positive driving signal
  • the sub-pixel corresponding to the liquid crystal molecule 120 is driven by the negative driving signal.
  • the sub-pixel corresponding to the liquid crystal molecules 110 is driven by the negative driving signal
  • the sub-pixel corresponding to the liquid crystal molecule 120 is driven by the positive driving signal.
  • a special display test screen which generally refers to the display test of the LCD display under certain extreme circumstances, such as a special test screen under certain specific pixel voltage flip modes, For example, after a checkerboard screen), when displaying a grayscale image, it will cause charge accumulation at the boundary of some liquid crystal molecules under the overloaded screen. The superposition of accumulated charges will cause the voltage difference at both ends of the boundary to increase, and the actual brightness at the boundary will If the value is greater than the target brightness value corresponding to the grayscale image at this time, an afterimage will appear on the display screen.
  • FIG. 2 shows a flowchart of a driving method of a display panel according to an embodiment of the present disclosure.
  • the display panel includes a driving pixel array including multiple rows of sub-pixels.
  • the ratio range between the voltage difference from the third voltage to the negative drive signal trough voltage and the voltage difference from the negative drive signal peak voltage to the negative drive signal trough voltage is 5% to 10%, and the fourth voltage to the negative drive signal
  • the ratio range between the voltage difference of the valley voltage and the voltage difference from the peak voltage of the negative driving signal to the valley voltage of the negative driving signal ranges from 90% to 95%.
  • the voltage at the valley of the negative driving signal may be 0V
  • the voltage at the peak may be 10V
  • the voltage difference between the peak voltage of the negative driving signal and the valley voltage of the negative driving signal is 10V.
  • the rise time of the negative drive signal can characterize the time required for the negative drive signal to rise from 05V to 9.5V
  • the corresponding fall time can characterize the time required to drop from 9.5V to 0.5V.
  • the rise time of the negative drive signal can characterize the time required for the negative drive signal to rise from 1V to 9V
  • the corresponding fall time can characterize the time required to fall from 9V to 1V.
  • the ratio between the rise time of the positive drive signal and the rise time of the negative drive signal ranges from 0.25 to 0.4.
  • the ratio between the falling time of the positive driving signal and the falling time of the negative driving signal ranges from 1.16 to 1.34.
  • a shorter rise time of the forward drive signal indicates a faster voltage slew rate of the forward drive signal.
  • the charging efficiency of the pixel capacitor is higher when driven by the forward driving signal.
  • the difference in charging efficiency of the pixel capacitor in the two driving modes can be improved.
  • the ratio between the rise time of the forward driving signal and the rise time of the negative driving signal is less than 0.4, the difference in charging efficiency of the pixel capacitor in the two driving modes can be improved.
  • the positive driving gear of the positive driving signal is greater than the negative driving gear of the negative driving signal.
  • the forward driving gear can represent the rate at which the forward driving signal rises from the first voltage to the second voltage
  • the negative driving gear can represent the rate at which the negative driving signal rises from the third voltage to the fourth voltage.
  • the forward driving gear may also represent the fall time required for the forward driving signal to fall from the second voltage to the first voltage.
  • the negative drive gear can also represent the fall time required for the negative drive signal to drop from the fourth voltage to the third voltage.
  • the driving gear can represent the driving capability of the driving signal, or can also represent the charging efficiency of the pixel capacitor when driven by the driving signal. For example, the larger the driving gear, the greater the voltage conversion rate, and the corresponding charging efficiency of the pixel capacitor is higher.
  • the forward driving gear and the negative driving gear may be set by a display device including a display panel according to an embodiment of the present disclosure, or may be set before shipment of the display device.
  • both the positive driving signal and the initial driving gear of negative driving can be considered to be 100%.
  • the initial drive gears of both the forward drive signal and the negative drive are 100%, which is not intended to limit the charging efficiency of the pixel capacitor under the drive of the forward drive signal and the charge efficiency of the pixel capacitor under the drive of the negative drive signal in the initial situation.
  • the charging efficiency of the pixel capacitor is equal.
  • the initial drive gear of the forward drive signal is 100%, which means that the forward drive signal provides 100% forward drive thrust for the pixel array
  • the initial drive gear of the negative drive signal is 100%, which means that the negative drive signal provides 100% of the forward drive thrust for the pixel array. 100% negative drive thrust.
  • the 100% positive driving thrust and the 100% negative driving thrust may or may not be equal. Different driving gears can provide different thrusts for liquid crystal molecules to provide pixel capacitance CS with different charging levels.
  • 100% negative driving thrust is greater than 100% forward driving thrust, so the positive driving gear of the positive driving signal can be increased, and the negative driving gear of the negative driving signal can be reduced, so that the positive
  • the voltage conversion rate of the forward driving signal is greater than the voltage conversion rate of the negative driving signal, thereby ensuring that the charging rate of the pixel capacitor under the positive driving signal is the same or similar to the charging rate of the pixel capacitor under the negative driving signal, thereby improving the problem of display afterimages.
  • the positive drive signal and the negative drive signal may be set to the same drive gear, or may be set to different drive gears.
  • the positive driving signal and the negative driving signal may respectively have 8 identically settable driving gears.
  • the eight settable drive gears of the positive drive signal and the negative drive signal are shown in Table 1.
  • the forward drive gear and the negative drive gear are individually adjustable.
  • a larger forward driving gear can be set independently and the negative driving gear can be kept unchanged; it can also be Set a larger forward driving gear and a smaller negative driving gear to adjust the charging level of the pixel capacitor CS.
  • the pixel capacitance CS can have the same charge level under forward drive and negative drive to avoid liquid crystal molecules changing after displaying a overloaded picture. Charge accumulation is formed at the boundary to improve the line afterimage problem in the display screen.
  • the present disclosure also provides a driving method of another embodiment.
  • step S210 respectively drives different sub-pixels in a row of sub-pixels through positive driving signals and negative driving signals, including: during the process of driving a row of sub-pixels, adjacent sub-pixels along the row direction receive positive driving signals respectively. drive signal and negative drive signal.
  • Sexuality can also be thought of as negative, positive, negative, positive, negative, positive....
  • the polarity of the sub-pixels in the first column of two adjacent columns of sub-pixels can be considered to be negative, positive, negative, positive, negative, positive...
  • the polarity of the sub-pixels in the second column can be considered as negative, positive, negative, positive, negative, positive...
  • Sexuality can also be considered as positive, negative, positive, negative, positive, negative... in order.
  • each data line can alternately output a positive driving signal and a negative driving signal to a single column of sub-pixels in the pixel array, so that adjacent sub-pixels in the same column have different polarities.
  • the polarity of the same subpixel in adjacent display frames is reversed once.
  • the polarities of the sub-pixels in the first and second columns can be considered to be positive, negative, positive, negative, positive, negative...
  • the polarities of the sub-pixels in the third and fourth columns can be considered to be positive, negative, positive, negative, positive, negative...
  • the polarity of can be considered as negative, positive, negative, positive, negative, positive...
  • the same data line may only receive a positive driving signal or a negative driving signal.
  • the data lines connecting two adjacent columns of sub-pixels may have different polarities.
  • the two adjacent data lines can respectively output a positive driving signal and a negative driving signal to the connected single column of sub-pixels.
  • one data line only receives a positive drive signal or a negative drive signal.
  • the polarity of the same subpixel in adjacent display frames is reversed once.
  • the polarities of two adjacent columns of sub-pixels can be considered to be positive, positive, positive, positive, positive, positive... and negative, negative, negative, negative, negative... respectively.
  • the polarities of the sub-pixels in two adjacent columns can be considered to be negative, negative, negative, negative, negative... and positive, positive, positive, positive, positive... in order.
  • the data lines connecting two adjacent columns of sub-pixels may have the same polarity.
  • the polarity of the driving signals input by the two data lines connecting the sub-pixels in the first column and the second column are the same.
  • the polarities of the driving signals input by the two data lines connecting the third and fourth columns of sub-pixels are the same.
  • the driving signals input by the two data lines connecting the second column and the third column of sub-pixels have opposite polarities.
  • one data line only receives a positive drive signal or a negative drive signal.
  • the forward drive gear is 100% and the negative drive gear is 70%.
  • the average rise time of the forward drive signal is 269.6ns, and the average fall time is 656.8ns.
  • the average rise time of the forward drive signal is 762.3ns, and the average fall time is 510.7ns.
  • the ratio between the rise time of the positive drive signal and the rise time of the negative drive signal is 0.35, and the ratio between the fall time of the positive drive signal and the fall time of the negative drive signal is 1.29.
  • the sum of the rise time and fall time of the positive drive signal is 926.4ns, and the sum of the rise time and fall time of the negative drive signal is 1273.0ns.
  • the difference between the time sum of the positive drive signal and the negative drive signal is -346.6ns.
  • the forward drive gear is 100% and the negative drive gear is 80%.
  • the average rise time of the forward drive signal is 301.9ns, and the average fall time is 693.3ns.
  • the average rise time of the forward drive signal is 757.5ns, and the average fall time is 526.9ns.
  • the ratio between the rise time of the forward drive signal and the rise time of the negative drive signal is 0.40, and the ratio between the fall time of the forward drive signal and the fall time of the negative drive signal is 1.34.
  • the sum of the rise time and fall time of the positive drive signal is 995.2ns, and the sum of the rise time and fall time of the negative drive signal is 1274.4ns.
  • the difference between the time sum of the positive driving signal and the negative driving signal is -279.2ns.
  • the charging speed of the pixel capacitor when driven in the negative direction is greater than the charging speed of the pixel capacitor when driven in the forward direction.
  • the forward drive gear can be increased and the negative drive gear can be lowered to balance the difference in charging efficiency under positive and negative drives and avoid the generation of afterimages.
  • the present disclosure also provides a driving circuit for a display panel, used to drive a pixel array, where the pixel array includes a plurality of sub-pixels.
  • Figure 5 is a block diagram of a driving circuit according to one embodiment of the present disclosure. As shown in FIG. 5 , the driving circuit 500 includes a driving sub-circuit 510 .
  • the driving sub-circuit 510 is used to drive different sub-pixels in a row of sub-pixels through positive driving signals and negative driving signals in the same display frame, and the voltage conversion rate of the positive driving signal is greater than the voltage conversion rate of the negative driving signal. .
  • the driving subcircuit 510 is used to perform operation S210 in the above embodiment, which will not be described again.
  • FIG. 6 is a schematic structural diagram of a driving circuit of a display panel according to an embodiment of the present disclosure.
  • the driving circuit is used to drive a pixel array, and the pixel array includes multiple rows of sub-pixels.
  • the driving circuit 600 of the display panel includes a driving signal generating sub-circuit 610 and a driving signal gating sub-circuit 620 .
  • the driving signal generating sub-circuit 610 and the driving signal gating sub-circuit 620 may be disposed on the array substrate, for example, directly fabricated through a patterning process.
  • the driving signal generation sub-circuit 610 and the driving signal gating sub-circuit 620 can also be provided inside the IC.
  • the IC is bound to the array substrate and provides signals through a transmission path from terminals ⁇ leads ⁇ data lines ⁇ sub-pixel electrodes.
  • the driving signal generating sub-circuit 610 is used to generate a positive driving signal and a negative driving signal.
  • the driving signal gating sub-circuit 620 is used to gate the positive driving signal and the negative driving signal, so that in the same display frame, the positive driving signal and the negative driving signal drive different sub-pixels in a row of sub-pixels, The voltage slew rate of the positive drive signal is greater than the voltage slew rate of the negative drive signal.
  • the rise time of the positive drive signal is shorter than the rise time of the negative drive signal.
  • the rise time of the forward drive signal can represent the rise time required for the forward drive signal to rise from the first voltage to the second voltage
  • the rise time of the negative drive signal can represent the rise time of the negative drive signal from the third voltage to the fourth voltage. required rise time.
  • the ratio between the rise time of the positive drive signal and the rise time of the negative drive signal ranges from 0.25 to 0.4.
  • the falling time of the positive driving signal is greater than the falling time of the negative driving signal.
  • the falling time of the forward driving signal can represent the falling time required for the forward driving signal to fall from the second voltage to the first voltage
  • the falling time of the negative driving signal can represent the falling time of the negative driving signal from the fourth voltage to the third voltage. Required drop time.
  • the ratio between the falling time of the positive driving signal and the falling time of the negative driving signal ranges from 1.16 to 1.34.
  • the ratio range between the voltage difference from the first voltage to the forward driving signal valley voltage and the voltage difference from the forward driving signal peak voltage to the forward driving signal valley voltage is 5% to 10%
  • the second voltage to the forward driving signal valley voltage ranges from 5% to 10%
  • the ratio range between the voltage difference of the driving signal valley voltage and the voltage difference from the forward driving signal peak voltage to the forward driving signal valley voltage ranges from 90% to 95%.
  • the ratio range between the voltage difference from the third voltage to the negative drive signal trough voltage and the voltage difference from the negative drive signal peak voltage to the negative drive signal trough voltage is 5% to 10%, and the fourth voltage to the negative drive signal
  • the ratio range between the voltage difference of the valley voltage and the voltage difference from the peak voltage of the negative driving signal to the valley voltage of the negative driving signal ranges from 90% to 95%.
  • the sum of the rise time and fall time of the positive drive signal is smaller than the sum of the rise time and fall time of the negative drive signal.
  • the positive driving gear of the positive driving signal is greater than the negative driving gear of the negative driving signal.
  • the forward driving gear can also represent the rate at which the forward driving signal rises from the first voltage to the second voltage
  • the negative driving gear can also represent the rate at which the negative driving signal rises from the third voltage to the fourth voltage.
  • the driving signal generation sub-circuit 610 includes a positive frame amplification unit 611 and a negative frame amplification unit 612.
  • the positive frame amplifying unit 611 is electrically connected to the data signal terminal, receives the data signal from the data signal terminal, and outputs a forward driving signal.
  • the negative frame amplification unit 612 is electrically connected to the data signal terminal, receives the data signal from the data signal terminal, and outputs a negative driving signal.
  • setting the forward driving gear of the positive frame amplification subcircuit and the negative driving gear of the negative frame amplification subcircuit can be performed during the driving process of the driving circuit, or the setting of the positive frame amplification can be performed before the display device leaves the factory.
  • the forward drive gear of the sub-circuit and the negative drive gear of the negative frame amplification sub-circuit can be performed during the driving process of the driving circuit, or the setting of the positive frame amplification can be performed before the display device leaves the factory.
  • the input end of the drive signal gating sub-circuit 620 is electrically connected to the positive frame amplification unit 611 and the negative frame amplification unit 612, and the output end of the drive signal gating sub-circuit 620 is electrically connected to the data line of the display panel.
  • the driving signal gating sub-circuit 620 can gate the positive driving signal and the negative driving signal, so that the positive driving signal and the negative driving signal drive the sub-pixels of the pixel array through the data lines.
  • the drive signal gating subcircuit 620 includes an output multiplexer OUT MUX and two output ports CH1 and CH2. The output multiplexer OUT MUX selects the positive drive signal and the negative drive signal.
  • the positive frame amplification unit 611 includes a positive frame operational amplifier POP and a transistor array TFT Array 1.
  • the positive frame operational amplifier POP is electrically connected to the data signal terminal.
  • the transistor array TFT Array 1 is electrically connected between the output end of the positive frame amplification operator POP and the drive signal gating subcircuit.
  • the positive frame operational amplifier POP receives the data signal from the data signal terminal and controls the transistor array TFT Array 1 to generate a forward drive signal.
  • the negative frame amplification unit 612 includes a negative frame operational amplifier NOP and a transistor array TFT Array 2.
  • the input terminal of the negative frame operational amplifier NOP is electrically connected to the data signal terminal.
  • the transistor array TFT Array 2 is electrically connected between the output end of the negative frame amplification operator NOP and the drive signal gating subcircuit.
  • the negative frame operational amplifier NOP receives the data signal from the data signal terminal and controls the transistor array TFT Array 2 to generate a negative driving signal.
  • the positive frame amplification unit 611 and the negative frame amplification unit 612 are respectively configured as amplification sub-circuits with individually adjustable drive gears. When the positive frame amplification unit 611 and the negative frame amplification unit 612 are set to different driving gears, they can provide different thrusts to the pixel array to adjust the charging level of the pixel capacitor CS.
  • the present disclosure also provides another embodiment of a driving circuit.
  • the driving circuit 600 further includes a first power supply VDDA, a second power supply VDDAH and a third power supply VSSA.
  • the first power supply VDDA is electrically connected to the transistor array TFT Array 1, and the first power supply VDDA outputs the first power supply voltage.
  • the second power supply VDDAH transistor array TFT Array 2 is electrically connected, and the second power supply VDDAH outputs the second power supply voltage.
  • the first power supply voltage is twice the second power supply voltage. For example, when the first power supply voltage is 10V, the second power supply voltage is 5V.
  • the voltage of the third power supply VSSA outputs the ground terminal.
  • the two output terminals of the positive frame amplifier POP are electrically connected to the first power supply VDDA and the second power supply signal terminal VDDAH respectively.
  • the two output terminals of the negative frame amplifier NOP are connected to the second power supply VDDAH and the third power supply VSSA respectively.
  • the display panel includes 2N data lines
  • the pixel array includes 2N columns of sub-pixels
  • the positive frame amplification unit includes N positive frame amplification units 611
  • the negative frame amplification unit includes N negative frame amplification units 612
  • the driver The signal gating sub-circuit includes N driving signal gating sub-circuits 620 .
  • Each drive signal gating sub-circuit 620 includes two input terminals, which are electrically connected to a positive frame amplification unit 611 and a negative frame amplification unit 612 respectively.
  • Each drive signal gating sub-circuit 620 includes two output terminals, which are electrically connected to two adjacent data lines respectively. The two output terminals output a positive drive signal and a negative drive signal to drive the connected data lines.
  • adjacent sub-pixels along the row direction receive positive driving signals and negative driving signals respectively.
  • the display panel includes 100 data lines
  • the pixel array includes 100 columns of sub-pixels
  • the positive frame amplification unit includes 50 positive frame amplification units 611
  • the negative frame amplification unit includes 50 negative frame amplification units 612
  • the driving signal gating subcircuit It includes 50 drive signal gating sub-circuits 620.
  • One positive frame amplification unit and one negative frame amplification unit constitute a group of amplification sub-circuits.
  • Each group of amplifier sub-circuits is gated by a driving signal gating sub-circuit 620, and the gated driving signals are input to the sub-pixels connected to the data lines through two output terminals.
  • the driving signal gating subcircuit 620 when outputting the Nth frame, the driving signal gating subcircuit 620 outputs a positive driving signal from the port CH1 to the connected data line, and outputs a negative driving signal from the port CH2 to the connected data line.
  • the driving signal gating subcircuit 620 When outputting the N+1th frame, the driving signal gating subcircuit 620 outputs a negative driving signal from the port CH1 to the connected data line, and outputs a positive driving signal from the port CH2 to the connected data line.
  • the driving signal gating subcircuit 620 is used to output the positive driving signal and the negative driving signal respectively to the data lines connecting two adjacent columns of sub-pixels in the pixel array.
  • the present disclosure also provides an embodiment of a driving chip of a display panel.
  • the driving chip of the display panel is used to provide a positive driving signal and a negative driving signal to the display panel.
  • the voltage conversion rate of the positive driving signal is greater than the voltage conversion rate of the negative driving signal.
  • the driving chip of the display panel is connected to multiple gate lines Gate, and is used to provide scanning signals to multiple gate lines Gate in sequence during the driving stage.
  • the gate line Gate receives the scanning signal to turn on the TFT corresponding to the gate line Gate, so that the TFT Source and drain are connected.
  • the driver chip 800 is also connected to multiple data lines Data, and is used to write data voltages to the multiple data lines Data respectively during the driving phase, and the data voltages are input to corresponding pixel electrodes through the turned-on TFTs.
  • the driving chip of the display panel is also used to generate a reference voltage.
  • the reference voltage includes a first power supply voltage, a second power supply voltage and a third power supply voltage.
  • the rise time of the positive drive signal is shorter than the rise time of the negative drive signal.
  • the rise time of the forward drive signal represents the rise time required for the forward drive signal to rise from the first voltage to the second voltage
  • the rise time of the negative drive signal represents the rise time required for the negative drive signal to rise from the third voltage to the fourth voltage. rise time.
  • the ratio between the rise time of the positive drive signal and the rise time of the negative drive signal ranges from 0.25 to 0.4.
  • the ratio between the falling time of the positive driving signal and the falling time of the negative driving signal ranges from 1.16 to 1.34.
  • the ratio range between the voltage difference from the first voltage to the forward driving signal valley voltage and the voltage difference from the forward driving signal peak voltage to the forward driving signal valley voltage is 5% to 10%
  • the second voltage to the forward driving signal valley voltage ranges from 5% to 10%
  • the ratio range between the voltage difference of the driving signal valley voltage and the voltage difference from the forward driving signal peak voltage to the forward driving signal valley voltage is 90% to 95%
  • the ratio range to the voltage difference from the negative driving signal peak voltage to the negative driving signal trough voltage is 5% to 10%.
  • the voltage difference from the fourth voltage to the negative driving signal trough voltage is equal to the voltage difference from the negative driving signal peak voltage to
  • the ratio between the voltage differences of the negative drive signal valley voltage ranges from 90% to 95%.
  • the forward drive gear of the forward drive signal is greater than the negative drive gear of the negative drive signal; where the forward drive gear represents the rate at which the forward drive signal rises from the first voltage to the second voltage, and the negative drive gear represents the rate at which the forward drive signal rises from the first voltage to the second voltage.
  • the driving gear represents the rate at which the negative driving signal rises from the third voltage to the fourth voltage.
  • each block in the flowchart or block diagrams may represent a module subcircuit, segment, or portion of code that contains one or more components used to implement the specified Executable instructions for logical functions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.

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Abstract

一种显示面板的驱动方法。显示面板包括像素阵列，像素阵列包括多行亚像素，该驱动方法包括在同一显示帧内，通过正向驱动信号和负向驱动信号分别一行亚像素中的不同亚像素，且在相同显示灰阶下正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率（S210）。还提供了一种驱动电路(500,600)、驱动芯片和显示设备(700)。

Description

显示面板的驱动方法、驱动电路、驱动芯片和显示设备 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板的驱动方法、驱动电路、驱动芯片和显示设备。
背景技术
液晶显示器(Liquid Crystal Display，LCD)是一种利用稳定电压驱动的显示器。对于液晶显示器而言，尤其是电竞显示器，提升刷新率是改善液晶显示器性能的重要措施。然而，提升刷新率，会导致像素的充电时间变短，造成驱动显示器的电压不稳定，从而使液晶显示器在显示画面出现残像画面，影响显示效果。
发明内容
本公开提供了一种显示面板的驱动方法、驱动电路、驱动芯片和显示设备。
根据第一方面，本公开提供了一种显示面板的驱动方法，显示面板包括驱动像素阵列，像素阵列包括多行亚像素。驱动方法包括：在同一显示帧内，通过正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素，且在相同显示灰阶下正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
例如，正向驱动信号的上升时间小于负向驱动信号的上升时间；其中，正向驱动信号的上升时间表征正向驱动信号从第一电压上升到第二电压所需的上升时间，负向驱动信号的上升时间表征负向驱动信号从第三电压上升到第四电压所需的上升时间。
例如，正向驱动信号的上升时间和负向驱动信号的上升时间之间的比值范围为0.25-0.4。
例如，正向驱动信号的下降时间大于负向驱动信号的下降时间；其中，正向驱动信号的下降时间表征正向驱动信号从第二电压下降到第一电压所需的下降时间，负向驱动信号的下降时间表征负向驱动信号从第四电压下降到第三电压所需的下降时间。
例如，正向驱动信号的下降时间和负向驱动信号的下降时间之间的比值范围为1.16～1.34。
例如，第一电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第二电压到正向驱动信号 波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为90％～95％；以及第三电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第四电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为90％～95％。
例如，正向驱动信号的上升时间与下降时间之和小于负向驱动信号的上升时间与下降时间之和。
例如，通过正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素，包括：在驱动一行亚像素过程中，沿行方向相邻亚像素分别接收正向驱动信号和负向驱动信号。
例如，显示面板还包括数据线，正向驱动信号和/或负向驱动信号通过数据线为亚像素提供驱动信号，在同一显示帧内，同一数据线仅接收正向驱动信号或负向驱动信号。
例如，正向驱动信号的正向驱动档位大于负向驱动信号的负向驱动档位；正向驱动档位表征正向驱动信号从第一电压上升到第二电压的速率，负向驱动档位表征负向驱动信号从第三电压上升到第四电压的速率。
根据第二方面，本公开提供了一种用于根据本公开实施例的驱动方法的显示面板的驱动电路，用于驱动像素阵列，像素阵列包括多行亚像素。驱动电路包括：驱动信号产生子电路，用于产生正向驱动信号和负向驱动信号；以及驱动信号选通子电路，用于对正向驱动信号和负向驱动信号进行选通，使在同一显示帧内，正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素，正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
例如，显示面板包括2N个数据线；驱动信号选通子电路包括N个驱动信号选通子电路；其中，驱动信号选通子电路包括2个输出端，分别与2个数据线电连接，2个输出端分别输出将正向驱动信号和负向驱动信号以驱动2个数据线连接的亚像素。
例如，驱动信号产生子电路包括：正帧放大单元，与数据信号端电连接，用于接收来自数据信号端的数据信号，并输出正向驱动信号；以及负帧放大单元，与数据信号端电连接，用于接收来自数据信号端的数据信号，并输出负向驱动信号。
例如，正帧放大单元包括：正帧运算放大器，与数据信号端电连接；以及第一晶体管阵列，电连接在正帧放大运算器的输出端与驱动信号选通子电路之间。
例如，负帧放大单元包括：负帧运算放大器，输入端与数据信号端电连接；以及第 二晶体管阵列，电连接在正帧放大运算器的输出端和驱动信号选通子电路之间。
例如，驱动电路还包括第一电源，与第一晶体管阵列电连接，用于输出第一电源电压；以及第二电源，与第二晶体管阵列电连接，用于输出第二电源电压；其中，第一电源电压为第二电源电压的2倍。
根据第三方面，本公开提供了一种用于显示面板的驱动芯片，驱动芯片用于向显示面板提供正向驱动信号和负向驱动信号，正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
根据第四方面，本公开提供了一种显示设备，包括像素阵列和根据本公开实施例的驱动电路。
例如，显示设备还包括：多根数据线，驱动电路包括多个输出端，多根数据线和多个输出端分别连接。
附图说明
图1A是根据一个示例晶体管单元的示意图；
图1B是根据一个示例晶体管单元的I-V特性曲线的示意图；
图1C是根据一个示例黑(L0)白(L255)棋盘格的显示画面的示意图；
图1D是根据一个示例L127灰阶画面异常显示的示意图；
图1E是根据一个示例L127灰阶画面正常显示的示意图；
图2示出了根据本公开实施例的显示面板的驱动方法的流程图；
图3是一个示例的像素阵列中亚像素极性的示意图；
图4A是根据本公开一个实施例的测试波形图；
图4B是根据本公开另一个实施例的测试波形图；
图4C是根据本公开另一个实施例的测试波形图；
图4D是根据本公开另一个实施例的测试波形图；
图4E是根据本公开另一个实施例的测试波形图；
图4F是根据本公开另一个实施例的测试波形图；
图4G是根据本公开另一个实施例的正向驱动信号的测试波形图；
图4H是根据本公开另一个实施例的负向驱动信号的测试波形图；
图5是根据本公开一个实施例的显示面板的驱动电路的框图；
图6是根据本公开一个实施例的显示面板的驱动电路的结构示意图；以及
图7是根据本公开一个实施例的显示设备的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
对于高级超维电场转换(Advanced Super Dimension Switch，ADS)产品，由像素电极边缘间产生的电场及像素电极与公共电极间产生的电场构成多维电场，使液晶盒内像素电极之间以及像素电极上方所有取向液晶分子均可以发生旋转，从而大幅提高显示画面的可视角度。液晶分子翻转可以控制背光通过液晶分子的透光量，使液晶分子对应的亚像素产生相应的亮度，实现不同灰阶的显示。
在液晶显示器显示画面的过程中，对像素电极施加极性变化的数据信号，可以避免液晶分子产生极化现象，改善显示画面中残影的出现。例如，以公共电极施加的公共电压Vcom为基准电压，对像素电极施加极性在正向和负向之间呈周期性变化的数据信号。对像素电极施加正向数据信号可认为是正向驱动模式，此时施加至像素电极的数据信号电压与公共电压的电压差为正值。对像素电极施加负向数据信号可认为是负向驱动模式，此时施加至像素电极的数据信号电压与公共电压的电压差为负值。在理想状态下，对于同一个灰阶，正向和负向相对于公共电压的差值的绝对值是大致相等，这样可以对同一个灰阶的正向和负向显示的亮度是相同的。
图1A是根据一个示例晶体管单元的示意图，图1B是根据一个示例晶体管单元的I-V特性曲线的示意图，图1C是根据一个示例黑(L0)白(L255)棋盘格的显示画面的示意图，图1D是根据一个示例L127灰阶画面异常显示的示意图，以及图1E是根据一个示例L127灰阶画面正常显示的示意图。
如图1A所示，晶体管单元的栅极接收栅极驱动信号，源极接收数据信号。晶体管的单元栅极与源极之间的栅源电压Vgs对像素电容CS进行充电。在一些实施例中，如图1B所示，根据TFT单元的驱动电流Ids与栅源电压Vgs之间的I-V传输特性曲线可知，负向驱动NOUT下的栅源电压Vgs通常会大于正向驱动POUT下的栅源电压Vgs。负向驱动NOUT下的栅源电压Vgs与正向驱动POUT下的栅源电压Vgs之间的差值越大，两种驱动模式下的驱动电流差值ΔIds越大。负向驱动下像素电容CS的充电电荷相较于正向驱动下像素电容CS的充电电荷更多，长时间将造成液晶分子的分界处形成电荷累积，出现残像。
如图1C所示，显示器显示黑白棋盘格画面，液晶分子110显示黑色图像(B)，液晶分子120显示白色图像(W)。在显示第n帧画面时，通过正向驱动信号驱动液晶分子110对应的亚像素，通过负向驱动信号驱动液晶分子120对应的亚像素。在显示第n+1帧画面时，通过负向驱动信号驱动液晶分子110对应的亚像素，通过正向驱动信号驱动液晶分子120对应的亚像素。
在显示画面中棋盘格由黑变为白时，根据TFT单元的I-V传输特性，晶体管的栅极电压Vg不变，负极性下源极电压Vs比正极性下的源极电压Vs要小，又由于Vgs＝Vg-Vs，从而造成液晶分子对应的亚像素在负向驱动时的栅源电压Vgs要明显高于在正向驱动时的栅源电压Vgs。例如，栅极电压Vg约为30V，源极电源Vs的范围约10～20V。源极电源Vs始终比栅极电压Vg小，栅源电压Vgs始终为正值。
对于具有高刷新频率的监视器显示器(MoNiTor)、电视显示(TeleVision)，笔记本电脑显示器(NoteBook)等产品而言，像素阵列中相同行或相同列的亚像素在驱动时间内负向驱动(-B到-W)时的对像素电容CS的充电速率比正向驱动(+B到+W)时的充电速率更高，负向驱动下像素电容CS的充电电荷相较于正向驱动下像素电容CS的充电电荷更多。经过长时间的显示重载画面(属于特殊的显示测试画面，一般指的是LCD显示屏在某些极端情况下的显示测试，比如，在某些特定的像素电压翻转模式下的特殊测试画面，例如棋盘格画面)之后，在显示灰阶图像时，会造成重载画面下部分液晶分子分界处的电荷累积，累积电荷的叠加作用造成分界处两端的压差增大，在分界处的实 际亮度值比此时灰阶图像对应的目标亮度值大，显示画面会出现残像。
残像通常是指影像残留(Image Sticking)。例如，当TFT-LCD长时间显示同一幅画面时，液晶分子由于受到长时间的驱动，造成液晶分子不能在信号电压的控制下正常偏转。即使改变显示画面的内容，屏幕上仍然可以看到前一时间的静止图像的痕迹。如图1D所示，残像130是显示面板在长时间棋盘格画面驱动后产生的残像效果，可以清晰看到在L127灰阶画面下有明显的棋盘格画面残留。
发明人研究发现，在液晶分子中TFT单元在负向驱动时的栅源电压Vgs电压与正向驱动时的栅源电压Vgs电压相近，以及负向驱动时的对像素电容CS的充电速率与正向驱动时的充电速率相近时，液晶显示器的正常显示画面如图1E所示。
下面，将参照附图详细描述根据本公开的各个实施例。需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
图2示出了根据本公开实施例的显示面板的驱动方法的流程图。该显示面板包括驱动像素阵列，像素阵列包括多行亚像素。
如图2所示，根据本公开实施例的驱动方法可以包括以下步骤。应注意，以下方法中各个步骤的序号仅作为该步骤的表示以便描述，而不应被看作表示该各个步骤的执行顺序。除非明确指出，否则该方法不需要完全按照所示顺序来执行。
在步骤S210，在同一显示帧内，通过正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素，且在相同显示灰阶下正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
例如，电压转换速率可以表征完成上升沿的速率，或者在上升沿内相同时间里电压升高的幅度。
电压转换速率还可以表征正向驱动信号从第一电压上升到第二电压的速率，或者负向驱动信号从第三电压上升到第四电压的速率。其中，第一电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第二电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为90％～95％。第三电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第四电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为90％～95％。
在本公开实施例，在相同显示灰阶下，正向驱动信号的上升时间小于负向驱动信号的上升时间。正向驱动信号的上升时间也可以表征正向驱动信号从第一电压上升到第二电压所需的上升时间，负向驱动信号的上升时间也可以表征负向驱动信号从第三电压上升到第四电压所需的上升时间。
在本公开实施例，在相同显示灰阶下，正向驱动信号的下降时间大于负向驱动信号的下降时间。正向驱动信号的下降时间表征正向驱动信号从第二电压下降到第一电压所需的下降时间，负向驱动信号的下降时间表征负向驱动信号从第四电压下降到第三电压所需的下降时间。
例如，正向驱动信号波谷处的电压可以为10V，波峰处的电压可以为20V，正向驱动信号波峰电压与正向驱动信号波谷电压的电压差为10V。正向驱动信号的上升时间可以表征正向驱动信号从10.5V上升到19.5V所需的时间，相应的下降时间可以表征从19.5V下降到10.5V所需的时间。或者，正向驱动信号的上升时间可以表征正向驱动信号从11V上升到19V所需的时间，相应的下降时间可以表征从19V下降到11V所需的时间。例如，负向驱动信号波谷处的电压可以为0V，波峰处的电压可以为10V，负向驱动信号波峰电压与负向驱动信号波谷电压的电压差为10V。负向驱动信号的上升时间可以表征负向驱动信号从05V上升到9.5V所需的时间，相应的下降时间可以表征从9.5V下降到0.5V所需的时间。或者，负向驱动信号的上升时间可以表征负向驱动信号从1V上升到9V所需的时间，相应的下降时间可以表征从9V下降到1V所需的时间。
在本公开实施例，在相同显示灰阶下，正向驱动信号的上升时间和负向驱动信号的上升时间之间的比值范围为0.25～0.4。正向驱动信号的下降时间和负向驱动信号的下降时间之间的比值范围为1.16～1.34。
例如，正向驱动信号的上升时间越短表示正向驱动信号的电压转换速率越快。相应地，在正向驱动信号驱动下像素电容的充电效率越高。
通过具有较大电压转换速率的正向驱动信号和较小电压转换速率的负向驱动信号，可以改善两种驱动模式下像素电容的充电效率差异。例如，在正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值小于0.4的情况下，可以改善两种驱动模式下像素电容的充电效率差异。
在本公开实施例，在相同显示灰阶下，正向驱动信号的上升时间与下降时间之和小于负向驱动信号的上升时间与下降时间之和。正向驱动信号的上升时间与下降时间之和与负向驱动信号的上升时间与下降时间之和的比值范围为0.61～0.78。在该比值越小的情 况下，改善两种驱动模式下像素电容的充电效率差异的效果越好。
在本公开实施例，在相同显示灰阶下，正向驱动信号的正向驱动档位大于负向驱动信号的负向驱动档位。正向驱动档位可以表征正向驱动信号从第一电压上升到第二电压的速率，负向驱动档位可以表征负向驱动信号从第三电压上升到第四电压的速率。
例如，正向驱动档位还可以表征正向驱动信号的从第二电压下降到第一电压所需的下降时间。负向驱动档位还可以表征负向驱动信号从第四电压下降到第三电压所需的下降时间。
驱动档位可以表示驱动信号的驱动能力，也可以表示在驱动信号的驱动下像素电容的充电效率。例如，驱动档位越大，电压转换速率越大，相应的像素电容的充电效率更高。
例如，正向驱动档位和负向驱动档位可以由包括本公开实施例显示面板的显示设备设置，也可以在该显示设备的出厂前设置。
在常规的驱动方法中，可认为正向驱动信号和负向驱动的初始驱动档位均为100％。需要说明的是，正向驱动信号和负向驱动的初始驱动档位均为100％并不是为了限定在初始情况下正向驱动信号的驱动下像素电容的充电效率与负向驱动信号的驱动下像素电容的充电效率相等。正向驱动信号的初始驱动档位为100％表示正向驱动信号为像素阵列提供了100％正向驱动推力，负向驱动信号的初始驱动档位为100％表示负向驱动信号为像素阵列提供了100％负向驱动推力。100％正向驱动推力与100％负向驱动推力可以相等，也可以不相等。不同驱动档位可以为液晶分子提供不同的推力，以提供不同充电水平的像素电容CS。
在一些实施例中，100％负向驱动推力比100％正向驱动推力大，因此可以增大正向驱动信号的正向驱动档位，减小负向驱动信号的负向驱动档位，使得正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率，进而确保正向驱动信号下像素电容的充电速率与负向驱动信号下像素电容的充电速率相同或相近，改善显示残像的问题。
在本公开实施例中，正向驱动信号和负向驱动信号可以设置有相同的驱动档位，也可以设置有不同的驱动档位。例如，正向驱动信号和负向驱动信号可以分别具有8个相同可设置的驱动档位。例如，正向驱动信号和负向驱动信号的8个可设置驱动档位如表1所示。
表1
驱动档位 1 2 3 4 4 5 6 7
POP 120％ 110％ 100％ 90％ 80％ 70％ 60％ 50％
NOP 120％ 110％ 100％ 90％ 80％ 70％ 60％ 50％
在本公开实施例中，正向驱动信号的8个正向驱动档位可以分别为120％、110％、100％、90％、80％、70％、60％和50％。负向驱动信号的8个负向驱动档位可以分别为120％、110％、100％、90％、80％、70％、60％和50％。正向驱动信号设置的正向驱动档位和负向驱动信号设置的负向驱动档位可以相同，也可以不同。
例如，正向驱动档位和负向驱动档位是单独可调的。在确定正向驱动下驱动晶体管的栅源电压小于负向驱动下驱动晶体管的栅源电压的情况下，可以单独设置较大的正向驱动档位，保持负向驱动档位不变；还可以设置较大的正向驱动档位和较小的负向驱动档位，以对像素电容CS的充电水平进行调整。
在相同显示灰阶下，在不同驱动档位的驱动下，驱动信号的上升时间和下降时间均会发生变化。随着正向驱动档位和负向驱动档位比值的变化，正向驱动信号的上升时间和负向驱动信号的上升时间之间的比值以及正向驱动信号的下降时间和负向驱动信号的下降时间之间的比值也会发生改变。例如，在上述实施例列举的正向驱动档位和负向驱动档位的驱动下，正向驱动信号的上升时间和负向驱动信号的上升时间之间的比值范围为0.25～0.4，正向驱动信号的下降时间和负向驱动信号的下降时间之间的比值范围为1.16～1.34。
在正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率的情况下，正向驱动和负向驱动下像素电容CS可以具有相同的充电水平，以避免显示重载画面后在液晶分子分界处形成电荷累积，改善显示画面中的线残像问题。
本公开还提供另一实施例的驱动方法。
在本公开实施例中，步骤S210通过正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素包括：在驱动一行亚像素过程中，沿行方向相邻亚像素分别接收正向驱动信号和负向驱动信号。
例如，正向驱动信号和负向驱动信号分别通过第一数据线和第二数据线输出至像素阵列的一列亚像素。在确定像素阵列包括2N列亚像素单元的情况下，显示面板包括2N个数据线，第一数据线包括N条第一数据线，第二数据包括N条第二数据线，N为正 整数。每一条数据线与像素阵列的单列亚像素相连，正向驱动信号和/或负向驱动信号通过数据线为亚像素提供驱动信号。
例如，相邻的两列亚像素连接的数据线的极性可以不相同。在同一显示帧内，对于单列亚像素而言，每一条数据线可以将正向驱动信号和负向驱动信号交替输出至像素阵列的单列亚像素，使得同一列的相邻亚像素的极性不同。相邻显示帧的同一亚像素极性反转一次。例如，在显示第n帧画面时，相邻两列亚像素中第一列亚像素的极性可认为依次为正、负、正、负、正、负……，第二列亚像素的极性也可认为依次为负、正、负、正、负、正……。在显示第n+1帧画面时，相邻两列亚像素中第一列亚像素的极性可认为依次为负、正、负、正、负、正……，第二列亚像素的极性也可认为依次为正、负、正、负、正、负……。
例如，相邻的两列亚像素连接的数据线的极性可以相同。在同一显示帧内，对于像素阵列中相邻的第一列和第二列亚像素而言，连接第一列和第二列亚像素的两条数据线输入的驱动信号的极性相同。对于像素阵列中相邻第三列和第四列亚像素而言，连接第三列和第四列亚像素的两条数据线输入的驱动信号的极性相同。连接相邻的第二列和第三列亚像素的两条数据线输入的驱动信号的极性相反。对于单列亚像素而言，每一条数据线可以将正向驱动信号和负向驱动信号交替输出至像素阵列的单列亚像素，使得同一列的相邻亚像素的极性不同。相邻显示帧的同一亚像素极性反转一次。例如，在显示第n帧画面时，第一列和第二列亚像素的极性可认为均依次为正、负、正、负、正、负……，第三列和第四列亚像素的极性可认为均依次为负、正、负、正、负、正……。在显示第n+1帧画面时，第一列和第二列亚像素的极性可认为均依次为负、正、负、正、负、正……，第三列和第四列亚像素的极性可认为均依次为正、负、正、负、正、负……。
本公开还提供另一实施例的驱动方法。
在本公开实施例中，在同一显示帧内，同一数据线可以仅接收正向驱动信号或负向驱动信号。
例如，相邻的两列亚像素连接的数据线的极性可以不相同。在同一显示帧内，对于相邻两列亚像素而言，相邻两条数据线可以将正向驱动信号和负向驱动信号分别输出至连接的单列亚像素。对于单列亚像素而言，一条数据线仅接收正向驱动信号或负向驱动信号。相邻显示帧的同一亚像素极性反转一次。例如，在显示第n帧画面时，相邻两列亚像素的极性可认为分别依次为正、正、正、正、正、正……和负、负、负、负、负、负……。在显示第n+1帧画面时，相邻两列亚像素的极性可认为依次为负、负、负、负、 负、负……和正、正、正、正、正、正……。
例如，相邻的两列亚像素连接的数据线的极性可以相同。在同一显示帧内，对于像素阵列中相邻第一列和第二列亚像素而言，连接第一列和第二列亚像素的两条数据线输入的驱动信号的极性相同。对于像素阵列中相邻第三列和第四列亚像素而言，连接第三列和第四列亚像素的两条数据线输入的驱动信号的极性相同。连接第二列和第三列亚像素的两条数据线输入的驱动信号的极性相反。对于单列亚像素而言，一条数据线仅接收正向驱动信号或负向驱动信号。相邻显示帧的同一亚像素极性反转一次。例如，在显示第n帧画面时，第一列和第二列亚像素的极性可认为均依次为正、正、正、正、正、正……和正、正、正、正、正、正……，第三列和第四列亚像素的极性可认为均依次为负、负、负、负、负、负……和负、负、负、负、负、负……。在显示第n+1帧画面时，第一列和第二列亚像素的极性可认为均依次为负、负、负、负、负、负……和负、负、负、负、负、负……，第三列和第四列亚像素的极性可认为均依次为正、正、正、正、正、正……和正、正、正、正、正、正……。
本公开还提供一种测试不同驱动档位下驱动信号驱动能力的实施例。
图3是一个示例的像素阵列中亚像素极性的示意图。如图3所示，在输出第N帧画面被施加正向驱动信号的亚像素，在输出第N+1帧画面时被施加负向驱动信号。在输出第N帧画面被施加负向驱动信号的亚像素，在输出第N+1帧画面时被施加正向驱动信号。在输出第N帧画面时，任意两个相邻的亚像素被施加不同极性的驱动电压。
通过本公开上述任一实施例的驱动方法对图3所示的像素阵列进行驱动，并对不同驱动档位下输出的驱动信号进行测试。在一个示例中，测试的正向驱动档位包括50％～120％，负向驱动档位包括50％～120％，测试结果如表2以及图4A～图4H所示。表2示出了不同驱动档位下的驱动信号的参数，包括：正向驱动信号的上升时间、正向驱动信号的下降时间、负向驱动信号的上升时间、负向驱动信号的下降时间、正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值、正向驱动信号的下降时间与负向驱动信号的下降时间之间的比值、正向驱动信号的上升时间与下降时间之和、负向驱动信号的上升时间与下降时间之和以及正向驱动信号与负向驱动信号的时间和之差。图4A～图4H示出了正向驱动信号和负向驱动信号的幅值随时间的变化曲线，纵坐标所示幅值的单位为伏特，横坐标所示时间的单元为纳秒。
表2
Figure PCTCN2022099392-appb-000001
如表2和图4A所示，正向驱动档位为100％，负向驱动档位为50％。正向驱动信号的上升时间平均值为298.0ns，下降时间平均值为705.7ns。负向驱动信号的上升时间平均值为773.5ns，下降时间平均值为575.3ns。正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值为0.39，正向驱动信号的下降时间与负向驱动信号的下降时间之间的比值为1.23。正向驱动信号的上升时间与下降时间之和为1003.7ns，负向驱动信号的上升时间与下降时间之和为1348.8ns。正向驱动信号与负向驱动信号的时间和之差为-345.1ns。
如表2和图4B所示，正向驱动档位为100％，负向驱动档位为60％。正向驱动信号的上升时间平均值为263.7ns，下降时间平均值为667.4ns。负向驱动信号的上升时间平均值为787.8ns，下降时间平均值为512.6ns。正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值为0.33，正向驱动信号的下降时间与负向驱动信号的下降时间之间的比值为1.32。正向驱动信号的上升时间与下降时间之和为941.1ns，负向驱动信号的上升时间与下降时间之和为1300.4ns。正向驱动信号与负向驱动信号的时间和之差为-359.3ns。
如表2和图4C所示，正向驱动档位为100％，负向驱动档位为70％。正向驱动信号的上升时间平均值为269.6ns，下降时间平均值为656.8ns。正向驱动信号的上升时间平均值为762.3ns，下降时间平均值为510.7ns。正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值为0.35，正向驱动信号的下降时间与负向驱动信号的下降时间 之间的比值为1.29。正向驱动信号的上升时间与下降时间之和为926.4ns，负向驱动信号的上升时间与下降时间之和为1273.0ns。正向驱动信号与负向驱动信号的时间和之差为-346.6ns。
如表2和图4D所示，正向驱动档位为100％，负向驱动档位为80％。正向驱动信号的上升时间平均值为301.9ns，下降时间平均值为693.3ns。正向驱动信号的上升时间平均值为757.5ns，下降时间平均值为526.9ns。正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值为0.40，正向驱动信号的下降时间与负正向驱动信号的下降时间之间的比值为1.34。正向驱动信号的上升时间与下降时间之和为995.2ns，负向驱动信号的上升时间与下降时间之和为1274.4ns。正向驱动信号与负向驱动信号的时间和之差为-279.2ns。
如表2和图4E所示，正向驱动档位为120％，负向驱动档位为80％。正向驱动信号的上升时间平均值为228.0ns，下降时间平均值为611.1ns。正向驱动信号的上升时间平均值为763.1ns，下降时间平均值为514.4ns。正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值为0.30，正向驱动信号的下降时间与负向驱动信号的下降时间之间的比值为1.19。正向驱动信号的上升时间与下降时间之和为839.1ns，负向驱动信号的上升时间与下降时间之和为1277.5ns。正向驱动信号与负向驱动信号的时间和之差为-438.4ns。
如表2和图4F所示，正向驱动档位为120％，负向驱动档位为50％。正向驱动信号的上升时间平均值为213.9ns，下降时间平均值为620.3ns。正向驱动信号的上升时间平均值为839.9ns，下降时间平均值为532.5ns。正向驱动信号的上升时间与负向驱动信号的上升时间之间的比值为0.25，正向驱动信号的下降时间与负向驱动信号的下降时间之间的比值为1.16。正向驱动信号的上升时间与下降时间之和为834.2ns，负向驱动信号的上升时间与下降时间之和为1372.4ns。正向驱动信号与负向驱动信号的时间和之差为-538.2ns。
如图4G所示，正向驱动档位由80％增加到120％的过程中，正向驱动信号由第一电压上升到第二电压的上升时间平均值和由第二电压下降到第一电压的下降时间平均值均逐渐减小。
如图4H所示，负向驱动档位由50％增加到120％的过程中，负向驱动信号由第三电压上升到第四电压的上升时间平均值逐渐减小。
由上述测试结果可知，在不同驱动档位的驱动下，驱动信号对像素电容的充电水平 的影响也不同。在正向驱动档位逐渐增大的情况下，正向驱动信号的上升时间和下降时间呈逐渐减少的趋势。在负向驱动档位逐渐增大的情况下，负向驱动信号的上升时间和下降时间也呈逐渐减少的趋势。当正向驱动档位为120％，负向驱动档位为50％时，正向驱动信号的上升时间和负向驱动信号的上升时间的比值最小，正向驱动信号的下降时间和负向驱动信号的上升时间的比值最小。可认为，当正向驱动档位为120％，负向驱动档位为50％时，正向驱动信号与负向驱动信号的驱动能力相差最大。
例如，在大于或等于240Hz的高频条件下，由于刷新频率过快，充电时间较短，容易在正向驱动和负向驱动之间产生充电差异。在一些实施例中，负向驱动时像素电容的充电速度要大于正向驱动时像素电容的充电速度。在此种情况下可以提高正向驱动档位，降低负向驱动档位，以平衡正负向驱动下的充电效率差异，避免残像的产生。
本公开还提供了一种显示面板的驱动电路，用于驱动像素阵列，像素阵列包括多个亚像素。图5是根据本公开一个实施例的驱动电路的框图。如图5所示，驱动电路500包括驱动子电路510。驱动子电路510用于在同一显示帧内通过正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素，且正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
例如，驱动子电路510用于执行上述实施例中的操作S210，不再赘述。
图6是根据本公开一个实施例的显示面板的驱动电路的结构示意图。该驱动电路用于驱动像素阵列，像素阵列包括多行亚像素。如图6所示，显示面板的驱动电路600包括驱动信号产生子电路610和驱动信号选通子电路620。
驱动信号产生子电路610和驱动信号选通子电路620可以设置在阵列基板上，例如通过构图工艺直接制作。驱动信号产生子电路610和驱动信号选通子电路620也可以设置在IC内部，例如，IC绑定在阵列基板上，通过由端子→引线→数据线→亚像素电极的传输路径提供信号。
驱动信号产生子电路610用于产生正向驱动信号和负向驱动信号。驱动信号选通子电路620用于对正向驱动信号和负向驱动信号进行选通，使在同一显示帧内，正向驱动信号和负向驱动信号分别驱动一行亚像素中的不同亚像素，正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
在本公开实施例中，正向驱动信号的上升时间小于负向驱动信号的上升时间。正向驱动信号的上升时间可以表征正向驱动信号从第一电压上升到第二电压所需的上升时间，负向驱动信号的上升时间可以表征负向驱动信号从第三电压上升到第四电压所需的 上升时间。正向驱动信号的上升时间和负向驱动信号的上升时间之间的比值范围为0.25～0.4。
在本公开实施例中，正向驱动信号的下降时间大于负向驱动信号的下降时间。正向驱动信号的下降时间可以表征正向驱动信号从第二电压下降到第一电压所需的下降时间，负向驱动信号的下降时间可以表征负向驱动信号从第四电压下降到第三电压所需的下降时间。正向驱动信号的下降时间和负向驱动信号的下降时间之间的比值范围为1.16～1.34。
例如，第一电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第二电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为90％～95％。第三电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第四电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为90％～95％。
例如，正向驱动信号的上升时间与下降时间之和小于负向驱动信号的上升时间与下降时间之和。
在本公开实施例中，正向驱动信号的正向驱动档位大于负向驱动信号的负向驱动档位。正向驱动档位还可以表征正向驱动信号从第一电压上升到第二电压的速率，负向驱动档位还可以表征负向驱动信号从第三电压上升到第四电压的速率。
在本公开实施例中，驱动信号产生子电路610包括正帧放大单元611、负帧放大单元612。
正帧放大单元611与数据信号端电连接，接收来自数据信号端的数据信号，并输出正向驱动信号。负帧放大单元612与数据信号端电连接，接收来自数据信号端的数据信号，并输出负向驱动信号。
例如，可以在驱动电路驱动过程中执行设置正帧放大子电路的正向驱动档位和负帧放大子电路的负向驱动档位，也可以是对在显示设备的出厂前执行设置正帧放大子电路的正向驱动档位和负帧放大子电路的负向驱动档位。
例如，驱动信号选通子电路620的输入端电连接正帧放大单元611和负帧放大单元612，驱动信号选通子电路620的输出端电连接显示面板的数据线。驱动信号选通子电路620可以对正向驱动信号和负向驱动信号进行选通，使正向驱动信号和负向驱动信号 通过数据线驱动像素阵列的亚像素。驱动信号选通子电路620包括输出多路选择器OUT MUX和两个输出端口CH1、CH2。输出多路选择器OUT MUX对正向驱动信号和负向驱动信号进行选通，两个输出端口CH1、CH2可以与像素阵列中相邻两列亚像素的数据线电连接，两个输出端口CH1、CH2还可以与像素阵列中不相邻两列亚像素的数据线电连接，以向像素单元输入选通驱动信号。
正帧放大单元611包括正帧运算放大器POP和晶体管阵列TFT Array 1。正帧运算放大器POP与数据信号端电连接。晶体管阵列TFT Array 1电连接在正帧放大运算器POP的输出端与驱动信号选通子电路之间。正帧运算放大器POP接收来自数据信号端的数据信号，并控制晶体管阵列TFT Array 1生成正向驱动信号。
负帧放大单元612包括负帧运算放大器NOP和晶体管阵列TFT Array 2。负帧运算放大器NOP的输入端与数据信号端电连接。晶体管阵列TFT Array 2电连接在负帧放大运算器NOP的输出端和驱动信号选通子电路之间。负帧运算放大器NOP接收来自数据信号端的数据信号，并控制晶体管阵列TFT Array 2生成负向驱动信号。
正帧放大单元611和负帧放大单元612分别被配置为驱动档位单独可调的放大子电路。正帧放大单元611和负帧放大单元612在被设置为不同的驱动档位时，可以为像素阵列提供不同的推力，以对像素电容CS的充电水平进行调整。
本公开还提供另一种驱动电路的实施例。在上述实施例的驱动电路600的基础上，驱动电路600还包括第一电源VDDA，第二电源VDDAH和第三电源VSSA。
第一电源VDDA与晶体管阵列TFT Array 1电连接，第一电源VDDA输出第一电源电压。第二电源VDDAH晶体管阵列TFT Array 2电连接，第二电源VDDAH输出第二电源电压。第一电源电压为第二电源电压的2倍。例如，在第一电源电压为10V时，第二电源电压为5V。第三电源VSSA输出接地端的电压。
正帧放大器POP的两个输出端分别与第一电源VDDA和第二电源信号端VDDAH电连接。负帧放大器NOP的两个输出端分别与第二电源VDDAH和第三电源VSSA相连。
在本公开实施例中，显示面板包括2N个数据线，像素阵列包括2N列亚像素，正帧放大单元包括N个正帧放大单元611，负帧放大单元包括N个负帧放大单元612，驱动信号选通子电路包括N个驱动信号选通子电路620。每个驱动信号选通子电路620包括2个输入端，分别与一个正帧放大单元611和一个负帧放大单元612电连接。每个驱动信号选通子电路620包括2个输出端，分别与相邻两个数据线电连接，2个输出端输 出正向驱动信号和负向驱动信号以驱动连接的数据线。在驱动一行亚像素过程中，沿行方向相邻亚像素分别接收正向驱动信号和负向驱动信号。
例如，显示面板包括100个数据线，像素阵列包括100列亚像素，正帧放大单元包括50个正帧放大单元611，负帧放大单元包括50个负帧放大单元612，驱动信号选通子电路包括50个驱动信号选通子电路620。1个正帧放大单元和1个负帧放大单元构成1组放大子电路。每组放大子电路由1个驱动信号选通子电路620进行驱动信号选通，并通过2个输出端分别选通后的驱动信号输入至数据线连接的亚像素。
例如，在输出第N帧画面时，驱动信号选通子电路620从端口CH1输出正向驱动信号至相连的数据线，从端口CH2输出负向驱动信号至相连的数据线。在输出第N+1帧画面时，驱动信号选通子电路620从端口CH1输出负向驱动信号至相连的数据线，从端口CH2输出正向驱动信号至相连的数据线。
例如，驱动信号选通子电路620用于将正向驱动信号和负向驱动信号分别输出至连接像素阵列的中相邻两列亚像素的数据线。
本公开还提供一种显示面板的驱动芯片的实施例。
显示面板的驱动芯片用于向显示面板提供正向驱动信号和负向驱动信号，正向驱动信号的电压转换速率大于负向驱动信号的电压转换速率。
显示面板的驱动芯片与多条栅线Gate均相连，用于在驱动阶段向多条栅线Gate依次提供扫描信号，栅线Gate接收到扫描信号以将栅线Gate对应的TFT开启，使TFT的源极和漏极导通。驱动芯片800还与多条数据线Data均相连，用于在驱动阶段向多条数据线Data分别写入数据电压，数据电压通过开启的TFT输入至相应的像素电极。
显示面板的驱动芯片还用于产生基准电压，基准电压包括第一电源电压、第二电源电压和第三电源电压。
图7是根据本公开一个实施例的显示设备的结构示意图。
如图7所示，显示设备700包括像素阵列710和驱动电路720，像素阵列710与驱动电路720电连接。驱动电路720包括上述图6对应实施例中提供的驱动电路600。在同一显示帧中，驱动电路720将正向驱动信号和负向驱动信号交替输出至连接亚像素的数据线。驱动一行亚像素过程中，沿行方向相邻亚像素分别接收正向驱动信号和负向驱动信号。显示设备700还包括多根数据线。驱动电路包括多个输出端，多根数据线和多个输出端分别连接。
图7所示的驱动电路720可认为是包括一组放大子电路的驱动电路。一组放大子电 路连接的驱动信号选通子电路的两个输出端分别连接像素阵列710中相邻两列亚像素的数据信号端上。在像素阵列包括2N列亚像素时，2N个数据线分别连接2N列亚像素，N个驱动电路连接2N个数据线，每个驱动电路包括1个正帧放大单元和1个负帧放大单元。驱动信号选通子电路的2个输出端分别电连接相邻两列亚像素的数据线。在调整正向驱动信号和/或负向驱动信号的驱动档位时，对应连接的像素列的充电水平均发生相应的变化。
例如，正向驱动信号的上升时间小于负向驱动信号的上升时间。正向驱动信号的上升时间表征正向驱动信号从第一电压上升到第二电压所需的上升时间，负向驱动信号的上升时间表征负向驱动信号从第三电压上升到第四电压所需的上升时间。
例如，正向驱动信号的上升时间和负向驱动信号的上升时间之间的比值范围为0.25～0.4。
例如，正向驱动信号的下降时间大于负向驱动信号的下降时间。正向驱动信号的下降时间表征正向驱动信号从第二电压下降到第一电压所需的下降时间；负向驱动信号的下降时间表征负向驱动信号从第四电压下降到第三电压所需的下降时间。
例如，正向驱动信号的下降时间和负向驱动信号的下降时间之间的比值范围为1.16～1.34。
例如，第一电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第二电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为90％～95％，以及第三电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为5％～10％，第四电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为90％～95％。
例如，正向驱动信号的上升时间与下降时间之和小于负向驱动信号的上升时间与下降时间之和。
例如，正向驱动信号的正向驱动档位大于负向驱动信号的负向驱动档位；其中，正向驱动档位表征正向驱动信号从第一电压上升到第二电压的速率，负向驱动档位表征负向驱动信号从第三电压上升到第四电压的速率。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以 代表一个模块子电路、程序段、或代码的一部分，上述子电路、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (19)

  1. 一种显示面板的驱动方法，所述显示面板包括像素阵列，所述像素阵列包括多行亚像素，所述驱动方法包括：
    在同一显示帧内，通过正向驱动信号和负向驱动信号分别驱动一行所述亚像素中的不同所述亚像素，且在相同显示灰阶下，所述正向驱动信号的电压转换速率大于所述负向驱动信号的电压转换速率。
  2. 根据权利要求1所述的驱动方法，其中，所述正向驱动信号的上升时间小于所述负向驱动信号的上升时间；其中，所述正向驱动信号的上升时间表征正向驱动信号从第一电压上升到第二电压所需的上升时间，所述负向驱动信号的上升时间表征负向驱动信号从第三电压上升到第四电压所需的上升时间。
  3. 根据权利要求2所述的驱动方法，其中，所述正向驱动信号的上升时间和所述负向驱动信号的上升时间之间的比值范围为0.25～04。
  4. 根据权利要求1所述的驱动方法，其中，所述正向驱动信号的下降时间大于所述负向驱动信号的下降时间；其中，所述正向驱动信号的下降时间表征正向驱动信号从第二电压下降到第一电压所需的下降时间，所述负向驱动信号的下降时间表征负向驱动信号从第四电压下降到第三电压所需的下降时间。
  5. 根据权利要求4所述的驱动方法，其中，所述正向驱动信号的下降时间和所述负向驱动信号的下降时间之间的比值范围为116～1.34。
  6. 根据权利要求2或4所述的驱动方法，其中，所述第一电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为5％～10％，所述第二电压到正向驱动信号波谷电压的电压差与正向驱动信号波峰电压到正向驱动信号波谷电压的电压差之间的比值范围为90％～95％；以及
    所述第三电压到负向驱动信号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为5％～10％，所述第四电压到负向驱动信 号波谷电压的电压差与负向驱动信号波峰电压到负向驱动信号波谷电压的电压差之间的比值范围为90％～95％。
  7. 根据权利要求6所述的驱动方法，其中，所述正向驱动信号的上升时间与下降时间之和小于所述负向驱动信号的上升时间与下降时间之和。
  8. 根据权利要求1所述的驱动方法，其中，所述通过正向驱动信号和负向驱动信号分别驱动一行所述亚像素中的不同所述亚像素，包括：
    在驱动一行所述亚像素过程中，沿行方向相邻所述亚像素分别接收所述正向驱动信号和所述负向驱动信号。
  9. 根据权利要求1所述的驱动方法，其中，所述显示面板还包括数据线，所述正向驱动信号和/或所述负向驱动信号通过所述数据线为所述亚像素提供驱动信号，
    在同一显示帧内，同一数据线仅接收所述正向驱动信号或所述负向驱动信号。
  10. 根据权利要求1或6所述的驱动方法，其中，所述正向驱动信号的正向驱动档位大于负向驱动信号的负向驱动档位；其中，所述正向驱动档位表征正向驱动信号从第一电压上升到第二电压的速率，所述负向驱动档位表征负向驱动信号从第三电压上升到第四电压的速率。
  11. 一种用于权利要求1-10任一项所述驱动方法的显示面板的驱动电路，用于驱动像素阵列，所述像素阵列包括多行亚像素，所述驱动电路包括：
    驱动信号产生子电路，用于产生正向驱动信号和负向驱动信号；以及
    驱动信号选通子电路，用于对所述正向驱动信号和所述负向驱动信号进行选通，使在同一显示帧内，所述正向驱动信号和所述负向驱动信号分别驱动一行所述亚像素中的不同所述亚像素，所述正向驱动信号的电压转换速率大于所述负向驱动信号的电压转换速率。
  12. 根据权利要求11所述的驱动电路，其中，所述显示面板还包括2N个数据线；所述驱动信号选通子电路包括N个驱动信号选通子电路，N为正整数；其中，所述驱 动信号选通子电路包括2个输出端，分别与2个数据线电连接，所述2个输出端分别输出所述正向驱动信号和所述负向驱动信号以驱动所述数据线连接的亚像素单元。
  13. 根据权利要求11所述的驱动电路，其中，所述驱动信号产生子电路包括：
    正帧放大单元，与数据信号端电连接，用于接收来自数据信号端的数据信号，并输出正向驱动信号；以及
    负帧放大单元，与数据信号端电连接，用于接收来自所述数据信号端的数据信号，并输出负向驱动信号。
  14. 根据权利要求13所述的驱动电路，其中，所述正帧放大单元包括：
    正帧运算放大器，与所述数据信号端电连接；以及
    第一晶体管阵列，电连接在所述正帧放大运算器的输出端与所述驱动信号选通子电路之间。
  15. 根据权利要求14所述的驱动电路，其中，所述负帧放大单元包括：
    负帧运算放大器，输入端与所述数据信号端电连接；以及
    第二晶体管阵列，电连接在所述正帧放大运算器的输出端和所述驱动信号选通子电路之间。
  16. 根据权利要求15所述的驱动电路，还包括：
    第一电源，与所述第一晶体管阵列电连接，用于输出第一电源电压；以及
    第二电源，与所述第二晶体管阵列电连接，用于输出第二电源电压；
    其中，所述第一电源电压为所述第二电源电压的2倍。
  17. 一种用于权利要求1-10任一项所述驱动方法的显示面板的驱动芯片，
    所述驱动芯片用于向显示面板提供正向驱动信号和负向驱动信号，所述正向驱动信号的电压转换速率大于所述负向驱动信号的电压转换速率。
  18. 一种显示设备，包括：
    像素阵列；
    根据权利要求11-16中任一项所述的驱动电路。
  19. 根据权利要求18所述的显示设备，还包括：
    多根数据线，
    所述驱动电路包括多个输出端，所述多根数据线和所述多个输出端分别连接。
PCT/CN2022/099392 2022-06-17 2022-06-17 显示面板的驱动方法、驱动电路、驱动芯片和显示设备 WO2023240586A1 (zh)

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