WO2023235312A1 - Structures d'interconnexion pour performances de puce de diode électroluminescente améliorées - Google Patents

Structures d'interconnexion pour performances de puce de diode électroluminescente améliorées Download PDF

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Publication number
WO2023235312A1
WO2023235312A1 PCT/US2023/023861 US2023023861W WO2023235312A1 WO 2023235312 A1 WO2023235312 A1 WO 2023235312A1 US 2023023861 W US2023023861 W US 2023023861W WO 2023235312 A1 WO2023235312 A1 WO 2023235312A1
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Prior art keywords
layer
interconnect
opening
type layer
reflective
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PCT/US2023/023861
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English (en)
Inventor
Michael CHECK
Justin White
Steven WUESTER
Kevin Haberern
Colin BLAKELY
Jesse Reiherzer
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Creeled, Inc.
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Priority claimed from US18/302,106 external-priority patent/US20230395756A1/en
Application filed by Creeled, Inc. filed Critical Creeled, Inc.
Publication of WO2023235312A1 publication Critical patent/WO2023235312A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Definitions

  • the present disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs) and more particularly to interconnect structures for improved LED chip performance.
  • LEDs light-emitting diodes
  • Solid-state lighting devices such as light-emitting diodes (LEDs) are increasingly used in both consumer and commercial applications.
  • LEDs light-emitting diodes
  • LEDs have enabled a variety of new display applications and are being increasingly utilized for general illumination applications, often replacing incandescent and fluorescent light sources.
  • LEDs are solid-state devices that convert electrical energy to light and generally include one or more active layers of semiconductor material (or an active region) arranged between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into the one or more active layers where they recombine to generate emissions such as visible light or ultraviolet emissions.
  • An active region may be fabricated, for example, from silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, and/or gallium arsenide-based materials and/or from organic semiconductor materials. Photons generated by the active region are initiated in all directions.
  • LEDs typically operate LEDs at the highest light emission efficiency, which can be measured by the emission intensity in relation to the output power (e.g., in lumens per watt).
  • a practical goal to enhance emission efficiency is to maximize extraction of light emitted by the active region in the direction of the desired transmission of light.
  • Light extraction and external quantum efficiency of an LED can be limited by a number of factors, including internal reflection. If photons are internally reflected in a repeated manner, then such photons will eventually be absorbed and never provide visible light that exits an LED.
  • LEDs To increase the opportunity for photons to exit an LED, it has been found useful to pattern, roughen, or otherwise texture the interface between an LED surface and the surrounding environment to provide a varying surface that increases the probability of refraction over internal reflection and thus enhances light extraction. Reflective surfaces may also be provided to reflect generated light so that such light may contribute to useful emission from an LED chip. LEDs have been developed with internal reflective surfaces or layers to reflect generated light.
  • the quantum efficiency of an LED can also be limited by other factors, such as how well current is able to spread within an LED.
  • electrodes for the LEDs can have larger surface area and may include various electrode extensions or fingers that are configured to route and more evenly distribute current across an LED.
  • the present disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs) and more particularly to interconnect structures for improved LED chip performance.
  • Interconnect structures are disclosed within LED chips that are structured to increase perimeter contact areas within localized LED chip areas without substantial increases to overall areas occupied by the interconnect structures. By increasing contact perimeters of interconnects within a certain area, increased current injection efficiency may be provided.
  • Interconnect structures for increased current injection are disclosed for both n-type layers and p-type layers.
  • Interconnect structures may include patterned dielectric materials within interconnect openings and corresponding interconnects that are formed around the patterned dielectric materials. Additional interconnect structures include nested patterns and extensions that provide enhanced adhesion along LED chip perimeters.
  • an LED chip comprises: an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer, the active LED structure forming a first opening that extends through the p-type layer, the active layer, and a portion of the n-type layer; a dielectric material on a portion of the n-type layer within the first opening; and an n-contact interconnect that is electrically connected to the n- type layer within the first opening, the n-contact interconnect forming edges that extend from the n-contact interconnect to electrically contact the n-type layer around a perimeter of the dielectric material.
  • the LED chip may further comprise: a reflective structure on the p-type layer, wherein the reflective structure comprises a dielectric layer and a metal layer; and a reflective layer interconnect that extends through a second opening of the dielectric layer; wherein the dielectric material on the portion of the n-type layer within the first opening comprises a same material as the dielectric layer of the reflective structure.
  • a portion of the dielectric layer is arranged within the second opening and the reflective layer interconnect forms edges that extend from the reflective layer interconnect to electrically connect with the p-type layer.
  • an LED chip comprises: an active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; a reflective structure on the p-type layer, the reflective structure comprising a dielectric layer, a metal layer, and a dielectric layer opening that is formed through the dielectric layer, a portion of the dielectric layer being arranged within the dielectric layer opening; and a reflective layer interconnect that extends through the dielectric layer opening, the reflective layer interconnect forming edges that extend from the reflective layer interconnect to electrically connect with the p-type layer.
  • any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.
  • FIG. 1 is a general cross-section of a portion of a light-emitting diode (LED) chip that includes an interconnect that provides an electrically conductive path through a dielectric layer.
  • LED light-emitting diode
  • FIG. 2 is a general cross-section of a portion of an LED chip that is similar to the LED chip of FIG. 1 except an interconnect structure is provided that increases current injection into a semiconductor layer for a same chip area.
  • FIG. 3A is a generalized cross-section of an LED chip that includes an interconnect structure as described above for FIG. 2.
  • FIG. 3B is a top view of a portion of the LED chip of FIG. 3A at a fabrication step before the LED chip is flipped and bonded to a carrier submount.
  • FIG. 4A is a generalized cross-section of an LED chip that is similar to the LED chip of FIG. 3A for embodiments where various reflective layer interconnects are formed with structures that promote enhanced current injection at the p-type layer.
  • FIG. 4B is a top view of a portion of the LED chip of FIG. 4A at a fabrication step before the LED chip is flipped and bonded to the carrier submount of FIG. 4A.
  • FIG. 5A is a generalized cross-section of another LED chip that is similar to the LED chip of FIG. 3A for embodiments where various reflective layer interconnects are formed with structures that promote enhanced current injection at the p-type layer.
  • FIG. 5B is a top view of a portion of the LED chip of FIG. 5A at a fabrication step before the LED chip is flipped and bonded to the carrier submount of FIG. 5A.
  • FIG. 6A is a view of a portion of an LED chip that is similar to FIG. 3B with an alternative arrangement of the portion of the first reflective layer within the opening.
  • FIG. 6B is a view of a portion of an LED chip that is similar to the LED chip of FIG. 6A for embodiments where the first reflective layer may be provided as a larger circular shape with a larger hollow center.
  • FIG. 6C is a view of a portion of an LED chip that is similar to the LED chip of FIG. 6B for embodiments where the first reflective layer may be provided as a larger circular shape with a larger hollow center and another portion of the first reflective layer is provided within the hollow center.
  • FIG. 6D is a view of a portion of an LED chip that is similar to the LED chip of FIG. 6C for embodiments where the first reflective layer may be provided as a larger circular shape with a larger hollow center and another portion of the first reflective layer is provided with a smaller diameter within the hollow center.
  • FIG. 7 A is an illustration of a circular interconnect that may be subdivided into four pie-shaped interconnect regions within a same chip area.
  • FIG. 7B is an illustration of a circular interconnect that may be subdivided into four circular interconnect regions within a same chip area.
  • FIG. 7C is an illustration of a circular interconnect that may be subdivided into five circular interconnect regions within a same chip area.
  • FIG. 8 illustrates interconnect structures formed as any number of fractal shapes for increasing perimeter edges thereof.
  • Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
  • Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure.
  • the present disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs) and more particularly to interconnect structures for improved LED chip performance.
  • Interconnect structures are disclosed within LED chips that are structured to increase perimeter contact areas within localized LED chip areas without substantial increases to overall areas occupied by the interconnect structures. By increasing contact perimeters of interconnects within a certain area, increased current injection efficiency may be provided.
  • Interconnect structures for increased current injection are disclosed for both n-type layers and p-type layers.
  • Interconnect structures may include patterned dielectric materials within interconnect openings and corresponding interconnects that are formed around the patterned dielectric materials.
  • Additional interconnect structures include nested patterns and extensions that provide enhanced adhesion along LED chip perimeters.
  • An LED chip typically comprises an active LED structure or region that can have many different semiconductor layers arranged in different ways.
  • the fabrication and operation of LEDs and their active structures are generally known in the art and are only briefly discussed herein.
  • the layers of the active LED structure can be fabricated using known processes with a suitable process being fabrication using metal organic chemical vapor deposition.
  • the layers of the active LED structure can comprise many different layers and generally comprise an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all of which are formed successively on a growth substrate.
  • additional layers and elements can also be included in the active LED structure, including, but not limited to, buffer layers, nucleation layers, super lattice structures, un-doped layers, cladding layers, contact layers, and currentspreading layers and light extraction layers and elements.
  • the active layer can comprise a single quantum well, a multiple quantum well, a double heterostructure, or super lattice structures.
  • the active LED structure can be fabricated from different material systems, with some material systems being Group III nitride-based material systems.
  • Group III nitrides refer to those semiconductor compounds formed between nitrogen (N) and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In).
  • Gallium nitride (GaN) is a common binary compound.
  • Group III nitrides also refer to ternary and quaternary compounds such as aluminum gallium nitride (AIGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AllnGaN).
  • the active layer, n-type layer, and p-type layer may include one or more layers of GaN, AIGaN, InGaN, and AllnGaN that are either undoped or doped with Si or Mg for a material system based on Group III nitrides.
  • Other material systems include silicon carbide (SiC), organic semiconductor materials, and other Group lll-V systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.
  • the active LED structure may be grown on a growth substrate that can include many materials, such as sapphire, SiC, aluminum nitride (AIN), GaN, with a suitable substrate being a 4H polytype of SiC, although other SiC polytypes can also be used including 3C, 6H, and 15R polytypes.
  • SiC has certain advantages, such as a closer crystal lattice match to Group III nitrides than other substrates and results in Group III nitride films of high quality.
  • SiC also has a very high thermal conductivity so that the total output power of Group III nitride devices on SiC is not limited by the thermal dissipation of the substrate.
  • Sapphire is another common substrate for Group III nitrides and also has certain advantages, including being lower cost, having established manufacturing processes, and having good light transmissive optical properties.
  • the active LED structure can emit different wavelengths of light depending on the composition of the active layer and n-type and p-type layers.
  • the active LED structure may emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm.
  • the active LED structure may emit green light with a peak wavelength range of 500 nm to 570 nm.
  • the active LED structure may emit red light with a peak wavelength range of 600 nm to 650 nm.
  • the active LED structure may emit light with a peak wavelength in any area of the visible spectrum, for example peak wavelengths primarily in a range from 400 nm to 700 nm.
  • the active LED structure may be configured to emit light that is outside the visible spectrum, including one or more portions of the ultraviolet (UV) spectrum, the infrared (IR) or near-IR spectrum.
  • the UV spectrum is typically divided into three wavelength range categories denotated with letters A, B, and C.
  • UV-A light is typically defined as a peak wavelength range from 315 nm to 400 nm
  • UV-B is typically defined as a peak wavelength range from 280 nm to 315 nm
  • UV-C is typically defined as a peak wavelength range from 100 nm to 280 nm.
  • UV LEDs are of particular interest for use in applications related to the disinfection of microorganisms in air, water, and surfaces, among others.
  • UV LEDs may also be provided with one or more lumiphoric materials to provide LED packages with aggregated emissions having a broad spectrum and improved color quality for visible light applications.
  • Near-IR and/or IR wavelengths for LED structures of the present disclosure may have wavelengths above 700 nm, such as in a range from 750 nm to 1100 nm, or more.
  • the LED chip can also be covered with one or more lumiphoric or other conversion materials, such as phosphors, such that at least some of the light from the LED chip is absorbed by the one or more phosphors and is converted to one or more different wavelength spectra according to the characteristic emission from the one or more phosphors.
  • the combination of the LED chip and the one or more phosphors emits a generally white combination of light.
  • the one or more phosphors may include yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Cai-x-ySrxEuyAISiNs) emitting phosphors, and combinations thereof.
  • Lumiphoric materials as described herein may be or include one or more of a phosphor, a scintillator, a lumiphoric ink, a quantum dot material, a day glow tape, and the like.
  • Lumiphoric materials may be provided by any suitable means, for example, direct coating on one or more surfaces of an LED, dispersal in an encapsulant material configured to cover one or more LEDs, and/or coating on one or more optical or support elements (e.g., by powder coating, inkjet printing, or the like).
  • lumiphoric materials may be downconverting or upconverting, and combinations of both downconverting and upconverting materials may be provided.
  • multiple different (e.g., compositionally different) lumiphoric materials arranged to produce different peak wavelengths may be arranged to receive emissions from one or more LED chips.
  • one or more phosphors may include yellow phosphor (e.g., YAG:Ce), green phosphor (e.g., LuAg:Ce), and red phosphor (e.g., Cai-x- ySrxEuyAISiNs) and combinations thereof.
  • One or more lumiphoric materials may be provided on one or more portions of an LED chip and/or a submount in various configurations.
  • one or more surfaces of LED chips may be conformally coated with one or more lumiphoric materials, while other surfaces of such LED chips and/or associated submounts may be devoid of lumiphoric material.
  • a top surface of an LED chip may include lumiphoric material, while one or more side surfaces of an LED chip may be devoid of lumiphoric material.
  • all or substantially all outer surfaces of an LED chip e.g., other than contact-defining or mounting surfaces
  • one or more lumiphoric materials may be arranged on or over one or more surfaces of an LED chip in a substantially uniform manner.
  • one or more lumiphoric materials may be arranged on or over one or more surfaces of an LED chip in a manner that is non-uniform with respect to one or more of material composition, concentration, and thickness.
  • the loading percentage of one or more lumiphoric materials may be varied on or among one or more outer surfaces of an LED chip.
  • one or more lumiphoric materials may be patterned on portions of one or more surfaces of an LED chip to include one or more stripes, dots, curves, or polygonal shapes.
  • multiple lumiphoric materials may be arranged in different discrete regions or discrete layers on or over an LED chip.
  • Light emitted by the active layer or region of an LED chip is typically initiated in multiple directions.
  • internal mirrors or external reflective surfaces may be employed to redirect as much light as possible toward a desired emission direction.
  • Internal mirrors may include single or multiple layers.
  • Some multi-layer mirrors include a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is arranged between the metal reflector layer and a plurality of semiconductor layers.
  • a passivation layer is arranged between the metal reflector layer and first and second electrical contacts, wherein the first electrical contact is arranged in conductive electrical communication with a first semiconductor layer, and the second electrical contact is arranged in conductive electrical communication with a second semiconductor layer.
  • some light may be absorbed by the mirror. Additionally, light that is redirected through the active LED structure may be absorbed by other layers or elements within the LED chip.
  • a layer or region of a light-emitting device may be considered to be “transparent” when at least 80% of emitted radiation that impinges on the layer or region emerges through the layer or region.
  • a layer or region of an LED is considered to be “reflective” or embody a “mirror” or a “reflector” when at least 80% of the emitted radiation that impinges on the layer or region is reflected.
  • the emitted radiation comprises visible light such as blue and/or green LEDs with or without lumiphoric materials. In other embodiments, the emitted radiation may comprise nonvisible light.
  • silver (Ag) may be considered a reflective material (e.g., at least 80% reflective).
  • appropriate materials may be selected to provide a desired, and in some embodiments high, reflectivity and/or a desired, and in some embodiments low, absorption.
  • a “light- transmissive” material may be configured to transmit at least 50% of emitted radiation of a desired wavelength.
  • a vertical geometry LED chip typically includes anode and cathode connections on opposing sides or faces of the LED chip.
  • a vertical geometry LED chip may also include a growth substrate that is arranged between the anode and cathode connections.
  • LED chip structures may include a carrier submount and where the growth substrate is removed.
  • any of the principles described may also be applicable to flip-chip structures where anode and cathode connections are made from a same side of the LED chip for flip-chip mounting to another surface.
  • Embodiments of the present disclosure provide interconnect structures, or vias, within LED chips that are structured to increase the perimeter contact areas of the interconnects within a same contact area for increasing efficiency of current injection. Since the majority of the current is typically ejected at the edge of the interconnects, the effective amount of useful current injection area can be increased by increasing a length of interconnect edges. For solid surfaces, it is well known that the shape with the largest perimeter to area is a circle. In certain embodiments, a circular interconnect structure is subdivided into concentric rings where the perimeter is increased without substantially increasing an area of the chip occupied by the interconnect. Such arrangements are applicable to both n-contact interconnects and p-type interconnects.
  • p-type interconnects may also be referred to as reflective layer interconnects or p-vias.
  • reflective layer interconnect structures are provided that increase current injection efficiency while also forming a seal along perimeter chip edges of the LED chip for decreased delamination of chip elements, such as reflective structures or mirrors. Such perimeter structures may also serve to push increased current to the outside of the LED chip.
  • FIG. 1 is a general cross-section of a portion of an LED chip 10 that includes an interconnect 12, or via, that provides an electrically conductive path through a dielectric layer 14.
  • the interconnect 12 may be electrically coupled to a semiconductor layer 16 and/or an intervening current spreading layer 18.
  • the semiconductor layer 16 may embody an n-type layer or a p-type layer of an active LED structure
  • the current spreading layer 18 may embody a layer of conductive material, for example a transparent conductive oxide such indium tin oxide (ITO) or a metal such as platinum (Pt), although other materials may be used.
  • ITO indium tin oxide
  • Pt platinum
  • a majority of current 20 is ejected along one or more edges 12’ of the interconnect 12, with less amounts of the current 20 being ejected centrally with respect to the interconnect 12.
  • current injection into the semiconductor layer 16 and the current spreading layer 18 is non-uniform across a contact area at the interface between the interconnect 12 and the current spreading layer 18.
  • FIG. 2 is a general cross-section of a portion of an LED chip 22 that is similar to the LED chip 10 of FIG. 1 except an interconnect structure is provided that increases current injection into the semiconductor layer 16 for a same chip area.
  • an interconnect structure is provided that increases current injection into the semiconductor layer 16 for a same chip area.
  • two smaller interconnects 12 are formed to contact the current spreading layer 18 with a spacing that corresponds to a width of the interconnect 12 of FIG. 1 .
  • the interconnects 12 of FIG. 2 may reside within a same area of the LED chip 22 as the area occupied by the single interconnect 12 of the LED chip 10 of FIG. 1 .
  • such an arrangement forms an increased area of one or more edges 12’ of the interconnects 12 within the same chip area such that increased current 20 is ejected from the interconnects 12 and into the current spreading layer 18 and the semiconductor layer 16.
  • an effective amount of useful current injection area can be increased.
  • the interconnects 12 may be separate structures while in other embodiments, the interconnects 12 may be extensions from a same interconnect structure.
  • FIG. 3A is a generalized cross-section of an LED chip 24 that includes an interconnect structure as described above for FIG. 2.
  • the LED chip 24 includes an active structure 26 formed on a carrier submount 28.
  • the active structure 26 may also be referred to as an active LED structure.
  • the active structure 26 generally refers to portions of the LED chip 24 that include semiconductor layers, such as epitaxial semiconductor layers, that form a structure that generates light when electrically activated.
  • the carrier submount 28 can be made of many different materials, with a suitable material being silicon, or doped silicon.
  • the carrier submount 28 comprises an electrically conductive material such that the carrier submount 28 is part of electrically conductive connections to the active structure 26.
  • the active structure 26 may generally comprise a p-type layer 30, an n-type layer 32, and an active layer 34 arranged between the p-type layer 30 and the n-type layer 32.
  • the active LED structure 26 may include many additional layers such as, but not limited to, buffer layers, nucleation layers, super lattice structures, un-doped layers, cladding layers, contact layers, current-spreading layers, and light extraction layers and elements.
  • the active layer 34 may comprise a single quantum well, a multiple quantum well, a double heterostructure, or super lattice structures. In FIG.
  • the p-type layer 30 is arranged between the active layer 34 and the carrier submount 28 such that the p-type layer 30 is closer to the carrier submount 28 than the n-type layer 32.
  • the active LED structure 26 may initially be formed by epitaxially growing or depositing the n-type layer 32, the active layer 34, and the p-type layer 30 sequentially on a growth substrate. The active LED structure 26 may then be flipped and bonded to the carrier submount 28 by way of one or more bond metals 38 and the growth substrate is removed. In this manner, a top surface 32' of the n-type layer 32 forms a primary light extracting face of the LED chip 24. In certain embodiments, the top surface 32' may comprise a textured or patterned surface for improving light extraction. In other embodiments, the doping order may be reversed such that n-type layer 32 is arranged between the active layer 34 and the carrier submount 28.
  • the LED chip 24 may include a first reflective layer 40 that is provided on the p-type layer 14.
  • the current spreading layer 18 may be provided between the p-type layer 30 and the first reflective layer 40.
  • the current spreading layer 18 may include a thin layer of a transparent conductive oxide such as ITO or a thin metal layer such as Pt, although other materials may be used.
  • the first reflective layer 40 may comprise many different materials and preferably comprises a material that presents an index of refraction step with the material of the active LED structure 26 to promote total internal reflection (TIR) of light generated from the active LED structure 26. Light that experiences TIR is redirected without experiencing absorption or loss and can thereby contribute to useful or desired LED chip emission.
  • the first reflective layer 40 comprises a material with an index of refraction lower than the index of refraction of the active LED structure 26 material.
  • the first reflective layer 40 may comprise many different materials, with some having an index of refraction less than 2.3, while others can have an index of refraction less than 2.15, less than 2.0, and less than 1 .5.
  • the first reflective layer 40 comprises a dielectric material, such as silicon dioxide (SiOz) and/or silicon nitride (SiN).
  • the first reflective layer 40 may include multiple alternating layers of different dielectric materials, e.g., alternating layers of SiO2 and SiN that symmetrically repeat or are asymmetrically arranged.
  • Some Group III nitride materials such as GaN can have an index of refraction of approximately 2.4, and SiO2 can have an index of refraction of approximately 1 .48, and SiN can have an index of refraction of approximately 1 .9.
  • Embodiments with an active LED structure 26 comprising GaN and the first reflective layer 40 that comprises SiOs may form a sufficient index of refraction step between the two to allow for efficient TIR of light.
  • the first reflective layer 40 may have different thicknesses depending on the type of materials used, with some embodiments having a thickness of at least 0.2 microns (pm). In some of these embodiments, the first reflective layer 40 can have a thickness in the range of 0.2 pm to 0.7 pm, while in some embodiments the thickness can be approximately 0.5 pm.
  • the LED chip 24 may further include a second reflective layer 42 that is on the first reflective layer 40 such that the first reflective layer 40 is arranged between the active LED structure 26 and the second reflective layer 42.
  • the second reflective layer 42 may include a metal layer that is configured to reflect light from the active LED structure 26 that may pass through the first reflective layer 40.
  • the second reflective layer 42 may comprise many different materials such as Ag, gold (Au), Al, nickel (Ni), titanium (Ti), or combinations thereof.
  • the second reflective layer 42 may have different thicknesses depending on the type of materials used, with some embodiments having a thickness of at least 0.1 pm, or in a range including 0.1 pm to 0.7 pm, or in a range including 0.1 urn to 0.5 urn, or in a range including 0.1 pm to 0.3 pm.
  • the second reflective layer 42 may include or form one or more reflective layer interconnects 44 that provide an electrically conductive path through the first reflective layer 40. In this manner, the one or more reflective layer interconnects 44 may extend through an entire thickness of the first reflective layer 40.
  • the second reflective layer 42 is a metal reflective layer and the reflective layer interconnects 44 comprise reflective layer metal vias.
  • the first reflective layer 40, the second reflective layer 42, and the reflective layer interconnects 44 form a reflective structure of the LED chip 24 that is on the p- type layer 30.
  • the reflective structure may comprise a dielectric reflective layer and a metal reflective layer as disclosed herein.
  • the reflective layer interconnects 44 comprise the same material as the second reflective layer 42 and are formed at the same time as the second reflective layer 42.
  • the reflective layer interconnects 44 may comprise a different material than the second reflective layer 42.
  • Certain embodiments may also comprise an adhesion layer 46 that is positioned at one or more interfaces between the first reflective layer 40 and the second reflective layer 42 and/or interfaces between the first reflective layer 40 and the current spreading layer 18 to promote improved adhesion therebetween.
  • the adhesion layer 46 can be used for the adhesion layer 46, such as titanium oxide (TiO, TiO2), titanium oxynitride (TiON, TixOyN), tantalum oxide (TaO, Ta2Os), tantalum oxynitride (TaON), aluminum oxide (AIO, AlxOy) or combinations thereof, with a preferred material being TiON, AIO, or AlxOy.
  • the adhesion layer comprises AlxOy, where 1 ⁇ x ⁇ 4 and 1 ⁇ y ⁇ 6.
  • the adhesion layer 46 may be deposited by electron beam deposition that may provide a smooth, dense, and continuous layer without notable variations in surface morphology.
  • the adhesion layer 46 may also be deposited by sputtering, chemical vapor deposition, plasma enhanced chemical vapor deposition, or atomic layer deposition (ALD).
  • the LED chip 24 may also comprise a barrier layer 48 on the second reflective layer 42 to prevent migration of material of the second reflective layer 42, such as Ag, to other layers. Preventing this migration helps the LED chip 24 maintain efficient operation throughout its lifetime.
  • the barrier layer 48 may comprise an electrically conductive material, with suitable materials including but not limited Ti, Pt, Ni, Au, tungsten (W), and combinations or alloys thereof.
  • the barrier layer 48 is arranged to laterally extend beyond portions of the active LED structure 26, or a peripheral border of the active LED structure 26 in order to provide an electrical connection with a p-contact 50.
  • an electrical path between the p-contact 50 and the p-type layer 30 may include the barrier layer 48, the second reflective layer 42, and the reflective layer interconnects 44.
  • the polarity may be reversed such that the p-contact 50 is replaced with an n-contact that is electrically coupled to the n-type layer 32, and electrical connections to the p-type layer 30 are made through the carrier submount 28.
  • a passivation layer 52 is included on the barrier layer 48 as well as any portions of the second reflective layer 42 that may be uncovered by the barrier layer 48. The passivation layer 52 protects and provides electrical insulation for the LED chip 24 and can comprise many different materials, such as a dielectric material including but not limited to silicon nitride.
  • the passivation layer 52 is a single layer, and in other embodiments, the passivation layer 52 comprises a plurality of layers.
  • the passivation layer 52 may include one or more metal-containing interlayers arranged or embedded therein that may function as a crack stop layer for any cracks that may propagate through the passivation layer 52 as well as an additional light reflective layer.
  • the active LED structure 26 forms a first opening 54 or recess that extends through the p-type layer 30, the active layer 34, and a portion of the n-type layer 32.
  • the first opening 54 may be formed by a subtractive material process, such as etching, that is applied to the active LED structure 26 before bonding with the carrier submount 28.
  • the first opening 54 may also be referred to as an active LED structure opening.
  • a portion of the first reflective layer 40, and adhesion layer 46 is arranged to cover sidewall surfaces of the p-type layer 30, the active layer 34, and the n-type layer 32 within the first opening 54.
  • the passivation layer 52 extends along the first reflective layer 40 in the first opening 54 and is arranged on a surface of the n- type layer 32.
  • the LED chip 24 further includes an n-contact metal layer 56 that is arranged on the passivation layer 52 and across the LED chip 24.
  • the n-contact metal layer 56 extends into the first opening 54 to form an n-contact interconnect 58, which may be referred to as an n-contact via.
  • the first opening 54 may be defined where portions of the n-contact metal layer 56, the n-contact interconnect 58, the passivation layer 52, and the first reflective layer 40 extend into the active LED structure 26.
  • the n- contact metal layer 56 and the n-contact interconnect 58 may be integrally formed to provide an electrical connection to the n-type layer 32 through the first opening 54.
  • the n-contact metal layer 56 and the n- contact interconnect 58 may be separately formed and may comprise the same or different materials.
  • the n-contact metal layer 56 and the n-contact interconnect 58 comprise a single layer or a plurality of layers that include conductive metals, such as one or more of Al, Ti, and alloys thereof.
  • the p-contact 50 may be formed on the barrier layer 48, and one or more top passivation layers 60-1 , 60-2 may be provided on one or more top or side surfaces of the n-type layer 32 for additional electrical insulation.
  • the top passivation layers 60-1 , 60-2 may comprise separate layers of a continuous layer of dielectric material, such as silicon nitride.
  • the n-contact interconnect 58 may be formed with an interconnect structure similar to the embodiments of FIG. 2. As illustrated in FIG. 3A, a portion of the first reflective layer 40 forms a dielectric material that resides within the opening 54 and on a portion of the n-type layer 32. When the n-contact interconnect 58 is formed through the passivation layer 52, the n-contact interconnect 58 may contact the n-type layer 32 around a perimeter, or an entire perimeter, of the portion of the first reflective layer 40 within the opening 54. In this manner, the n-contact interconnect 58 may be formed with increased amounts of one or more edges 58’ to provide enhanced current injection as described for FIG. 2. As illustrated, the interconnect structure of FIG.
  • the 3A includes an arrangement where the n-contact interconnect 58 is a continuous solid material through portions of the passivation layer 52 before effectively splitting around the portion of the first reflective layer 40 to provide the multiple edges 58’ at the n-type layer 32.
  • the edges 58’ are portions that extend from the n-contact interconnect 58 to electrically connect with portions of the n-type layer 32 within the opening 54 and adjacent to the portion of the first reflective layer 40.
  • FIG. 3B is a top view of a portion of the LED chip 24 of FIG. 3A at a fabrication step before the LED chip 24 is flipped and bonded to the carrier submount 28.
  • the fabrication step of FIG. 3B illustrates an etch pattern for removing portions of the first reflective layer 40.
  • the top view of FIG. 3B is from the perspective of the first reflective layer 40 before it is inverted as illustrated in FIG. 3A.
  • the first reflective layer 40 may be blanket deposited across the p-type layer 30 and current spreading layer 18 of FIG. 3A and within the opening 54.
  • the first reflective layer 40 is subjected to a patterned etching process within the opening 54.
  • a portion of the first reflective layer 40 remains within a center of the opening 54, and the n-type layer 32 is accessible in a radial manner around the first reflective layer 40 within the opening 54 as illustrated by the radial opening 36 of the first reflective layer 40.
  • a location 52’ of the passivation layer 52 and a location of the edges 58’ of the n-contact interconnect 58 within the opening 54 and within the radial opening 36 around the central portion of the first reflective layer 40 are indicated, as will be later formed at subsequent processing steps.
  • the n-contact interconnect 58 may accordingly be formed with increased edges for enhanced current injection. While FIG. 3B is provided in the context of a portion of the first reflective layer 40 within the opening 54, the principles disclosed are applicable to any dielectric material formed in the opening 54 to provide the increased contact for edges of the n-contact interconnect 58 and the n-type layer 32.
  • FIG. 4A is a generalized cross-section of an LED chip 62 that is similar to the LED chip 24 of FIG. 3A for embodiments where various reflective layer interconnects 44-1 to 44-2 are formed with structures that promote enhanced current injection at the p-type layer 30.
  • one or more of the reflective layer interconnects 44-1 , 44-2 are formed around the n-contact interconnect 58.
  • the first reflective layer interconnect 44-1 is visible on both sides of the n-contact interconnect 58. Accordingly, a first reflective layer interconnect 44-1 may form a ring around the n-contact interconnect 58.
  • a second reflective layer interconnect 44-2 may be formed in a similar manner around a perimeter of the first reflective layer interconnect 44-1 to form concentric rings around the n-contact interconnect 58. In this manner, the reflective layer interconnects 44-1 , 44-2 may be formed with increased edges along portions of the p-type layer 30 for enhanced current injection. Such an arrangement for the reflective layer interconnects 44-1 , 44-2 may be provided alone or in combination with the interconnect structure of the n-contact interconnect 58 as illustrated in FIG. 4A and described above for FIGS. 3A to 3B. [0060] FIG. 4B is a top view of a portion of the LED chip 62 of FIG.
  • the reflective layer interconnects 44-1 to 44-2 may be formed as concentric rings around multiple n-contact interconnects 58. In this manner, current injection for the p-type layer 30 may be enhanced at locations closest to the n-contact interconnects 58.
  • third and fourth reflective layer interconnects 44-3, 44-4 may laterally surround at least one of the n-contact interconnects 58 in proximity to a perimeter of the LED chip 62. The third reflective layer interconnect 44-3 may extend away from the n- contact interconnect 58 and extend along the perimeter of the LED chip 62.
  • the fourth reflective layer interconnect 44-4 may also extend away from the n-contact interconnect 58 and along the perimeter of the LED chip 62 in a similar manner. In such areas, the reflective layer interconnects 44-3, 44-4 correspond with areas of the LED chip 62 where material of the second reflective layer 42 contacts the current spreading layer 18 to provide improved adhesion along the perimeter of the LED chip 62. The improved perimeter adhesion may advantageously provide an enhanced seal along the perimeter of the LED chip 62 that may reduce instances of delamination. In certain embodiments, at least one of the reflective layer interconnects 44-3, 44-4, and in some instances both, may traverse along the entire perimeter of the LED chip 62.
  • a number of other reflective layer interconnects 44-5 may form an array pattern of vias throughout a remainder of the LED chip 62 and between reflective layer interconnects 44-1 , 44-2 at adjacent n-contact interconnects 58.
  • diameters of the reflective layer interconnects 44-5 may decrease with increasing distance from the reflective layer interconnects 44-1 , 44-2 and the n-contact interconnects 58 to control current spreading.
  • reflective layer interconnects 44-5 that are farthest away from the n-contact interconnects 58 may have the smallest diameters.
  • FIG. 5A is a generalized cross-section of another LED chip 64 that is similar to the LED chip 24 of FIG.
  • FIG. 5A for embodiments where various reflective layer interconnects 44 are formed with structures that promote enhanced current injection at the p-type layer 30.
  • one or more of the reflective layer interconnects 44 are formed in a similar manner to the n-contact interconnect 58 of FIG. 3A.
  • an opening 66 in the first reflective layer 40 is defined where the reflective layer interconnect 44 extends to contact the current spreading layer 18.
  • the opening 66 may also be referred to as a first reflective layer opening or a dielectric layer opening.
  • a portion of the reflective layer 40 is intentionally left within the opening 66 and spaced from the remainder of the first reflective layer 40.
  • the reflective layer interconnect 44 may fill the remainder of the opening 66 and form increased edges 44’ along the current spreading layer 18 in positions that surround the portion of the first reflective layer 40 within the opening 66.
  • the edges 44’ may embody portions of the reflective layer interconnect 44 that extend to electrically connect with portions of the current spreading layer 18 within the opening 66 and adjacent to the portion of the first reflective layer 40.
  • FIG. 5B is a top view of a portion of the LED chip 64 of FIG. 5A at a fabrication step before the LED chip 64 is flipped and bonded to the carrier submount 28 of FIG. 5A.
  • the fabrication step of FIG. 5B illustrates an etch pattern for removing portions of the first reflective layer 40.
  • the top view of FIG. 5B is from the perspective of the first reflective layer 40 before it is inverted as illustrated in FIG. 3A.
  • the first reflective layer 40 may be blanket deposited across the p-type layer 30 and current spreading layer 18 of FIG. 5A and within the opening 66.
  • the first reflective layer 40 is subjected to a patterned etching process within the opening 66. In this manner, a portion of the first reflective layer 40 remains within a center of the opening 66, and the current spreading layer 18 and/or the p-type layer 30 is accessible in a radial manner around the first reflective layer 40 within the opening 66.
  • a location of the edges 44’ of the reflective layer interconnect 44 within the opening 66 is indicated, as will be later formed at subsequent processing steps.
  • the reflective layer interconnect 44 may accordingly be formed with increased edges for enhanced current injection. While FIG. 5B is provided in the context of a portion of the first reflective layer 40 within the opening 66, the principles disclosed are applicable to any dielectric material formed in the opening 66 to provide the increased contact for edges of the reflective layer interconnect 44.
  • FIGS. 6A to 6D illustrated views of other arrangements of interconnect structures that provide increased current injection according to principles of the present disclosure.
  • FIGS. 6A to 6D are described in the context of n-contact interconnects. However, the principles described are also applicable to reflective layer interconnects.
  • various nested structures are shown that increase the perimeter surface injected area relative to the contact area, creating a more efficient contact for one or more of the n-type or p- type semiconductor layers of active LED structures.
  • openings 36 of the first reflective layer 40 provide access for electrically coupling to underlying layers.
  • FIG. 6A is a view of a portion of an LED chip 68 that is similar to FIG. 3B with an alternative arrangement of the portion of the first reflective layer 40 within the opening 54.
  • the first reflective layer 40 may be provided as a circular shape with a hollow center, such as a ring shape.
  • the location of the edges 58’ of the n-contact interconnect 58 may be formed around the perimeter of the first reflective layer 40 within the opening 54 and also within the hollow portion, thereby providing even further increased edges 58’ for current injection.
  • FIG. 6B is a view of a portion of an LED chip 70 that is similar to the LED chip 68 of FIG.
  • FIG. 6A is a view of a portion of an LED chip 72 that is similar to the LED chip 70 of FIG. 6B for embodiments where the first reflective layer 40 may be provided as a larger circular shape with a larger hollow center and another portion of the first reflective layer 40 is provided within the hollow center.
  • FIG. 6D is a view of a portion of an LED chip 74 that is similar to the LED chip 72 of FIG. 6C for embodiments where the first reflective layer 40 may be provided as a larger circular shape with a larger hollow center and another portion of the first reflective layer 40 is provided with a smaller diameter within the hollow center.
  • FIGS. 6A to 6D illustrates exemplary patterns of the first reflective layer 40 and edges 58’ of the n-contact interconnect 58 that may be provided. Other patterns are contemplated where one or more discontinuous regions of the first reflective layer 40 are formed within the opening 54 for providing increased surface area of the edges 58’ for increased current injection. Additionally, each of the discontinuous regions of the first reflective layer 40 as illustrated in FIGS. 6A to 6D may also be provided within the openings 66 for the reflective layer interconnects 44 as illustrated in FIGS. 5A and 5B.
  • FIGS. 7A to 7B illustrate even further patterns of interconnect structures for providing increased edges for current injection.
  • the interconnect structures of FIGS. 7A to 7B may embody either n-contact interconnects or reflective layer interconnects as described above.
  • illustrations are provided for an interconnect in an undivided arrangement (left illustration) and a divided arrangement (right illustration) into multiple regions within a same surface area.
  • the undivided arrangements may embody portions of the interconnects that are spaced away from the intended contact surface (e.g., the n-type layer or the current spreading layer) and the divided arrangements may embody the edge portions of the interconnect formed at the contact surface.
  • the divided arrangements may embody entire discontinuous segments that may replace a location of the undivided arrangement.
  • FIG. 7A is an illustration of a circular interconnect 76 that may be subdivided into four pie-shaped interconnect regions 76-1 to 76-4 within a same chip area.
  • FIG. 7B is an illustration of a circular interconnect 78 that may be subdivided into four circular interconnect regions 78-1 to 78-4 within a same chip area.
  • FIG. 7C is an illustration of a circular interconnect 80 that may be subdivided into five circular interconnect regions 80-1 to 80-4 within a same chip area.
  • the principles of the present disclosure may provide many different patterns and/or shapes of interconnects that provide enhanced current injection. Current spreading characteristics of different types of LED chips may vary. As such, the particular patterns and/or shapes may be selected based on current spreading characteristics particular to LED chip type.
  • FIG. 8 illustrates how the principles of the present disclosure are applicable to any fractal shapes of an interconnect for increasing perimeter edges thereof.
  • a column of undivided shapes is provided on the left and a series of corresponding fractal shapes are provided as rows from each of the undivided shapes.
  • each fractal shape from left to right is formed within increasing surface area of perimeter edges, thereby providing even further enhanced current injection.
  • the shape and geometry of various structures are modified into repeated fractural structures, such as repeated squares or triangles of smaller sizes.
  • the principles of the present disclosure are applicable to many different types of shapes, each of which may be provided by patterned masking of dielectric materials, such as the first reflective layer as previously described, within openings for the interconnects.

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Abstract

Sont divulgués des dispositifs d'éclairage à semi-conducteurs comprenant des puces de diode électroluminescente (DEL) et plus particulièrement des structures d'interconnexion pour des performances de puce de DEL améliorées. Sont divulguées des structures d'interconnexion à l'intérieur de puces de DEL qui sont structurées de sorte à augmenter des zones de contact de périmètre à l'intérieur de zones de puce de DEL localisées sans augmentation sensible de zones globales occupées par les structures d'interconnexion. En augmentant les périmètres de contact d'interconnexions dans une certaine zone, une efficacité d'injection de courant accrue peut être obtenue. Des structures d'interconnexion pour une injection de courant accrue sont divulguées à la fois pour des couches de type n et des couches de type p. Des structures d'interconnexion peuvent comprendre des matériaux diélectriques à motifs à l'intérieur d'ouvertures d'interconnexion et des interconnexions correspondantes qui sont formées autour des matériaux diélectriques à motifs. Des structures d'interconnexion supplémentaires comprennent des motifs imbriqués et des extensions qui fournissent une adhérence améliorée le long de périmètres de puce de DEL.
PCT/US2023/023861 2022-06-01 2023-05-30 Structures d'interconnexion pour performances de puce de diode électroluminescente améliorées WO2023235312A1 (fr)

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US18/302,106 US20230395756A1 (en) 2022-06-01 2023-04-18 Interconnect structures for improved light-emitting diode chip performance

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009010762A1 (fr) * 2007-07-19 2009-01-22 Photonstar Led Limited Del verticale à trous d'interconnexion conducteurs
US20150263236A1 (en) * 2014-03-11 2015-09-17 Kabushiki Kaisha Toshiba Semiconductor light emitting element
US20190115511A1 (en) * 2017-10-16 2019-04-18 Xiamen Sanan Optoelectronics Technology Co., Ltd. Light Emitting Diode and Fabrication Method Thereof
JP2019195050A (ja) * 2018-04-26 2019-11-07 日亜化学工業株式会社 発光素子
US20200303591A1 (en) * 2019-03-19 2020-09-24 Cree, Inc. Contact structures for light emitting diode chips

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009010762A1 (fr) * 2007-07-19 2009-01-22 Photonstar Led Limited Del verticale à trous d'interconnexion conducteurs
US20150263236A1 (en) * 2014-03-11 2015-09-17 Kabushiki Kaisha Toshiba Semiconductor light emitting element
US20190115511A1 (en) * 2017-10-16 2019-04-18 Xiamen Sanan Optoelectronics Technology Co., Ltd. Light Emitting Diode and Fabrication Method Thereof
JP2019195050A (ja) * 2018-04-26 2019-11-07 日亜化学工業株式会社 発光素子
US20200303591A1 (en) * 2019-03-19 2020-09-24 Cree, Inc. Contact structures for light emitting diode chips

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