WO2023231956A1 - 一种图像传感器的像素和图像传感器 - Google Patents

一种图像传感器的像素和图像传感器 Download PDF

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Publication number
WO2023231956A1
WO2023231956A1 PCT/CN2023/096805 CN2023096805W WO2023231956A1 WO 2023231956 A1 WO2023231956 A1 WO 2023231956A1 CN 2023096805 W CN2023096805 W CN 2023096805W WO 2023231956 A1 WO2023231956 A1 WO 2023231956A1
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Prior art keywords
signal
switch
coupled
level
terminal
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PCT/CN2023/096805
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English (en)
French (fr)
Inventor
王耀园
张子阳
刘力源
章宦慧
廖健行
王瀛
黄鹤鸣
Original Assignee
华为技术有限公司
中国科学院半导体研究所
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Publication of WO2023231956A1 publication Critical patent/WO2023231956A1/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • G01S17/89—Lidar systems specially adapted for specific applications for mapping or imaging
    • G01S17/894—3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present application relates to image sensor technology, and in particular to a pixel of an image sensor and an image sensor.
  • each pixel in the image sensor can convert the incident light into a corresponding electrical signal.
  • the processor can generate an image of the object or determine changes in the object through electrical signals provided by each pixel in the image sensor.
  • a grayscale image sensor converts incident light into an electrical signal that represents the intensity information of the incident light.
  • the processor can use the light intensity information to generate an image of the object.
  • the dynamic visual image sensor converts the incident light into an electrical signal that represents the change in the intensity of the incident light.
  • the processor can update the image using changes in light intensity.
  • Grayscale image sensors and dynamic vision image sensors are often called two-dimensional image sensors. The intensity information of the incident light and the change in the intensity of the incident light generated respectively are called two-dimensional information.
  • the time-of-flight image sensor converts the incident light into an electrical signal that represents the time-of-flight information of the incident light, and the incident light is the light reflected by the object from the active light source.
  • the processor can use the time-of-flight information to determine the distance between the object and the active light source, that is, the depth between the object and the active light source. Therefore, time-of-flight image sensors are often called three-dimensional image sensors, and the generated time-of-flight information of incident light is called three-dimensional information.
  • multiple types of image sensors are usually required.
  • vehicles need to accurately detect surrounding objects.
  • an active light source is emitted by the vehicle.
  • the active light source is reflected after encountering the detected object.
  • the vehicle needs to process the light reflected into the image sensor to generate two-dimensional information or three-dimensional information to facilitate the generation of a two-dimensional or three-dimensional image of the object. Therefore, multiple types of image sensors need to be installed in the vehicle, which is costly, and the process of matching information generated by pixels of different types of image sensors is complicated.
  • the present application provides a pixel of an image sensor and an image sensor that can provide intensity information and flight time information of incident light.
  • the pixels of the image sensor provided by the embodiments of the present application may include photoelectric conversion circuits and composite measurement circuits.
  • the photoelectric conversion circuit may be used to generate a first current based on incident light incident on the pixel.
  • the composite measurement circuit is coupled with the photoelectric conversion circuit.
  • the pixel may have multiple working modes, such as a first working mode and a second working mode. When the pixel is in the first working mode, it can provide intensity information of incident light. The pixel can be improved in the second working mode Provides time-of-flight information for incident light.
  • the composite measurement circuit may generate a first pulse signal based on the first current when the pixel operates in the first operating mode, and the first pulse signal represents intensity information of the incident light.
  • a plurality of sampling signals are received, and a plurality of second pulse signals are generated based on the first current and the plurality of sampling signals; wherein the plurality of sampling signals and the plurality of sampling signals are The plurality of second pulse signals are in one-to-one correspondence.
  • the plurality of second pulse signals are used to represent the phase offset between the phase of the incident light and the set phase.
  • the incident light is the set phase.
  • the light incident on the target object is reflected.
  • the set phase can be the phase of the active light.
  • the phase shift between the phase of the incident light and the set phase is the flight time information of the incident light, which can be used to determine the distance between the pixel and the target object.
  • the composite measurement circuit uses pulse-form data output when the pixels are in different working modes. Save the processing of analog physical quantities in peripheral circuits.
  • the back-end circuit such as an image signal processor, may directly use digital signal processing to process the first pulse signal or the second pulse signal.
  • the composite measurement circuit has multiple functions and can provide intensity information of incident light and time-of-flight information, reducing the chip area.
  • the composite measurement circuit includes a configuration signal receiving unit, an integrating unit, a comparing unit, and a delayed sampling unit.
  • the first end of the configuration signal receiving unit is coupled to the photoelectric conversion circuit; the second end of the configuration signal receiving unit is coupled to the first end of the integrating unit and coupled to the input end of the comparison unit.
  • the configuration signal receiving unit may output the first current to the integrating unit in the first working mode; receive the multiple sampling signals in the second working mode, and based on the multiple sampling signals The first current is periodically output to the integrating unit during a signal period of a sampling signal.
  • the second end of the integrating unit is coupled to the first level, the integrating unit may be used to integrate the first current to obtain a measured voltage, and provide the measured voltage to the comparison unit.
  • the coupling between the input end of the comparison unit and the first end of the integration unit can be used to compare the measured voltage with a preset reference voltage, and send the comparison result signal to the delayed sampling unit, where , when the measured voltage is less than the reference level, the level of the comparison result signal is the second level, and when the measured voltage is greater than or equal to the reference level, the level of the comparison result signal is a third level, the second level is greater than the third level;
  • the delay sampling unit is coupled to the output end of the comparison unit; the delay sampling unit is used to: compare the comparison result signal Perform sampling processing to generate the first pulse signal or the plurality of second pulse signals.
  • the configuration signal receiving unit includes a first switch and a second switch.
  • the first end of the first switch is coupled to the third power level
  • the second end of the first switch is coupled to the photoelectric conversion circuit
  • the second end of the first switch is coupled to the second end of the second switch.
  • the first terminal is coupled
  • the second terminal of the second switch is coupled with the first terminal of the integrating unit
  • the third power supply level is smaller than the second power supply level; wherein, when the first switch is in When the first switch is in the on state and the second switch is in the off state, the first current is transmitted to the integrating unit; when the first switch is in the on state and the second switch is in the off state, the first current is transmitted to the integrating unit.
  • the first current is transferred to the third power level.
  • the integrating unit includes a first capacitor; a first pole of the first capacitor is coupled to the photoelectric conversion circuit through the second switch, and a second pole of the first capacitor is coupled to the photoelectric conversion circuit.
  • the first level coupling is a possible design.
  • the comparison unit includes a comparator.
  • the first input terminal of the comparator is coupled to the first terminal of the integrating unit for receiving the measured voltage.
  • the second input terminal of the comparator is coupled to the reference voltage.
  • the output end of the comparator is coupled to the delayed sampling unit and used to output the comparison result signal.
  • the initial voltage of the first pole of the first capacitor may be the same as the level of the ground. At this time, the level of the comparison result signal output by the comparator is the second level.
  • the control end of the first switch receives a first drive signal, and the first drive signal is a fixed level signal for driving the first switch to be in an off-circuit state.
  • the control terminal of the second switch receives a second drive signal, and the second drive signal is a fixed level signal for driving the second switch to be in a conductive state. Therefore, the first current generated by the photodiode can be transmitted to the first pole of the first capacitor via the second switch.
  • the first pole of the first capacitor is connected to the cathode of the photodiode, the first capacitor integrates the first current, and the voltage at the first pole of the first capacitor increases.
  • the level of the comparison result signal output by the comparator is the third level.
  • the voltage at the first pole of the first capacitor is reset to the initial level, so that the first capacitor can start a new integration process.
  • the level of the comparison result signal output by the comparator becomes the second level.
  • the low level output by the comparator can be regarded as the reset effective level generated by the comparator.
  • the voltage at the first pole of the first capacitor increases from the initial voltage to the reference level, the comparator outputs a low level, and the voltage at the first pole of the first capacitor is reset to the initial level.
  • the comparator outputs a high level, so the comparator generates a pulse.
  • the number of pulses in the first pulse signal output by the comparator within a fixed time that is, the frequency of the first pulse signal output by the comparator, can represent the intensity information of the incident light.
  • the image signal processor may encode the intensity information of the incident light using the frequency of the first pulse signal output by the comparator.
  • the control end of the first switch receives a third driving signal; the third driving signal is a periodic signal, and the first switch is used to control the third driving signal.
  • a switch alternates between an on state and an off state according to the period of the third driving signal.
  • the control terminal of the second switch receives the plurality of sampling signals; wherein any sampling signal is a periodic signal, and the second switch is used to control the second switch to conduct the signal according to the period of each sampling signal. Alternate between on state and off state. Wherein, when the second switch is in the on state, the first switch is in the off state, and if the photoelectric conversion circuit outputs the first current, the first current can be transmitted to the first pole of the first capacitor.
  • the first switch When the first switch is in the on state and the second switch is in the off state, if the photoelectric conversion circuit outputs the first current, the first current can be transmitted to the third power level.
  • the third driving signal and the sampling signal may be a pair of inverted clock signals.
  • the frequency of the sampled signal is the same as the frequency of the phase-set optical fiber.
  • the control terminal of the second switch receives the plurality of sampling signals in a time-sharing manner, and the comparator can output a second pulse signal corresponding to each sampling signal in a time-sharing manner.
  • the plurality of sampling signals respectively have different phases.
  • the comparator outputs the second pulse signal corresponding to the first phase.
  • the total number of pulses in the second pulse signal corresponding to the first phase represents the integral value corresponding to the first phase.
  • the integrated value corresponding to the phase of each sampling signal can be used to determine the phase offset between the phase of the incident light and the set phase.
  • the delayed sampling unit includes a D latch and a NOR gate circuit; the data input end of the D latch is coupled to the output end of the comparator for receiving the comparison Result signal; the timing control input terminal of the D latch is used to receive the first clock signal; the Q output terminal of the D latch is coupled to the first input terminal of the NOR circuit and is used to provide the signal to the OR circuit.
  • the composite measurement circuit further includes a reset switch.
  • the first terminal of the reset switch is grounded, and the second terminal is coupled to the first terminal of the integrating unit.
  • the control terminal of the reset switch is coupled to the delay sampling unit and is used for receiving the first pulse signal.
  • the reset The switch is in the off-circuit state; during the period when the level of the first pulse signal is the fifth level, the reset switch is in the on-state, so that the voltage at the first end of the integrating unit is the reset voltage, such as ground level.
  • the fourth level is greater than the fifth level.
  • the composite measurement circuit further includes a readout unit.
  • the readout unit is coupled to the delayed sampling unit and coupled to the image signal processor.
  • the readout unit is configured to receive a storage signal provided by the image signal processor, and cache the first pulse signal or the second pulse signal according to the storage signal.
  • the readout unit may receive a scanning signal provided by the image signal processor, and output a buffered signal to the image signal processor according to the scanning signal.
  • the readout unit includes a third switch, a fourth switch and an RS latch.
  • the first end of the third switch is coupled to the image signal processor; the second end of the third switch is coupled to the first pole of the fourth switch; the control end of the third switch is used to receive The scan signal provided by the image signal processor, wherein the scan signal is used to drive the third switch to be in a conductive state.
  • the second pole of the fourth switch is grounded, the control terminal of the fourth switch is coupled to the Q output terminal of the RS latch; the reset terminal of the RS latch is coupled to the image signal processor , used to receive the storage signal or the reset signal provided by the image signal processor, the set end of the RS latch is coupled with the output end of the delay sampling unit, and used to receive the first A pulse signal, the level at the Q output terminal of the RS latch is the same as the level of the first pulse signal, or receiving the second pulse signal, the Q output terminal of the RS latch is at The level is the same as the level of the second pulse signal.
  • the pixel further includes a dynamic visual measurement circuit; the dynamic visual measurement circuit is coupled to the photoelectric conversion circuit and coupled to the image signal processor.
  • the dynamic visual measurement circuit may generate an indication level signal based on the first current, and send the indication level signal to the image signal processor, where the indication level signal represents the light intensity of the incident light. Intensity change information.
  • the pixels provided in the embodiments of the present application can also provide intensity information of incident light, light intensity change information of incident light, and flight time information of incident light. Pixels have multiple functions, which help image sensors serve more application scenarios.
  • the pixel further includes a current mirror circuit.
  • the composite measurement circuit is coupled to the photoelectric conversion circuit through the current mirror circuit.
  • the current mirror circuit may be used to provide the first current generated by the photoelectric conversion circuit to the composite measurement circuit.
  • the first current is reused to provide the dynamic visual measurement circuit and the composite measurement circuit, so that the two circuits can work synchronously. Furthermore, the isolation between the dynamic vision circuit and the composite measurement circuit is increased, and the mutual influence between the composite measurement circuit and the dynamic vision measurement circuit is reduced.
  • the photoelectric conversion circuit includes a photodiode. Wherein the anode of the photodiode is coupled to the first power supply level; the cathode of the photodiode is coupled to the composite measurement circuit and coupled to the second power supply level. The second power level is greater than the first power level.
  • the voltage of the first power level is less than zero. Such a design can increase the current gain of the photodiode so that the pixel can operate normally in a darker environment. In some application scenarios, by selecting materials with different absorption wavelengths as photodiodes, the pixels can process incident light in various bands.
  • embodiments of the present application further provide an image sensor, which may include an array of multiple pixels, at least one of which is a pixel of any possible design in the first aspect.
  • the image sensor may also include an image signal processor.
  • the image signal processor is coupled to the composite measurement circuit.
  • the image signal processor may control the target pixel to be in the first working mode, and the target pixel
  • the target pixel is any pixel in the at least one pixel; the first pulse signal is received, and the intensity information of the incident light incident on the target pixel is determined according to the frequency of the first pulse signal.
  • the image signal processor is further configured to: control the target pixel to be in a second working mode, and sequentially send multiple signals corresponding to the multiple phases to the target pixel according to a plurality of preset phases.
  • a sampling signal wherein the plurality of phases corresponds to the plurality of sampling signals on a one-to-one basis; receiving a plurality of second pulse signals, where the plurality of sampling signals correspond to the plurality of second pulse signals on a one-to-one basis; according to Each second pulse signal in the plurality of second pulse signals determines the phase offset between the phase of the incident light incident on the target pixel and the set phase, wherein the incident light is the Sets the phase of light rays incident on the target object that are reflected.
  • the image signal processor may determine the number corresponding to each second pulse signal, wherein the number corresponding to each second pulse signal is within a preset time period, and the number corresponding to each second pulse signal is The number of rising edges in the pulse signal; determining the phase offset based on the number corresponding to the plurality of second pulse signals; determining the phase offset between the target pixel and the target object based on the phase offset. distance.
  • Figure 1 shows a schematic structural diagram of a pixel
  • Figure 2 shows a schematic diagram of a specific structure of a pixel
  • Figure 3 shows a specific structural schematic diagram of a composite measurement circuit in a pixel
  • Figure 4 shows a specific structural schematic diagram of a comparator
  • Figure 5 shows a specific structural diagram of a D latch
  • Figure 6 shows a schematic diagram of a sampling signal according to an exemplary embodiment
  • Figure 7 shows a specific structural diagram of an RS latch
  • Figure 8 shows a schematic structural diagram of another pixel
  • Figure 9 shows a schematic structural diagram of a dynamic vision measurement circuit
  • Figure 10 shows a specific structural schematic diagram of a dynamic vision measurement circuit
  • Figure 11 shows a specific structural schematic diagram of a response circuit in a dynamic visual measurement circuit
  • Figure 12 shows a specific structural schematic diagram of a pixel circuit
  • Figure 13 shows a schematic structural diagram of an image sensor.
  • connection in the embodiments of this application can be understood as electrical connection, and coupling between two electrical components can be direct or indirect coupling between two electrical components.
  • connection between A and B can be either direct coupling between A and B, or indirect coupling between A and B through one or more other electrical components, such as coupling between A and B, or direct coupling between A and C.
  • C and B are directly coupled, and the coupling between A and B is realized through C.
  • “coupling” can also be understood as connection.
  • the coupling between A and B enables the transmission of electrical energy between A and B.
  • Each switch tube may include a first electrode (or first terminal), a second electrode (or second terminal), and a control electrode (or control terminal), where the control electrode is used to control the conduction or conduction of the switch tube. disconnect.
  • the switch tube When the switch tube is turned on, current can be transmitted between the first electrode and the second electrode of the switch tube.
  • the switch tube is turned off, current cannot be transmitted between the first electrode and the second electrode of the switch tube.
  • the control electrode of the switch tube is the gate
  • the first electrode of the switch tube can be the source of the switch tube
  • the second electrode can be the drain of the switch tube, or the first electrode can be the drain of the switch tube.
  • the second electrode may be the source of the switch tube.
  • the switch tube is turned on when driven by a high level, and the switch tube is turned off when driven by a low level. In other cases, the switch tube is turned on when driven by a low level, and is turned off when driven by a low level.
  • the embodiments of this application do not limit this too much.
  • the following is an example where the switch tube is turned on under high-level driving and turned off under low-level driving. It should be understood that high level and low level are relative concepts.
  • the level level (voltage value) of high level is greater than the level level of low level.
  • 1 is usually used to represent high level and 0 to represent low level. level.
  • the high level levels can be the same or different.
  • the high level may be 1.8V and the low level may be 0V.
  • An embodiment of this application provides a pixel of an image sensor that can be coupled with an image signal processor.
  • the pixel may include a photoelectric conversion circuit and a composite measurement circuit.
  • the pixels may be used to convert light incident on the pixels into corresponding electrical signals.
  • the composite measurement circuit can be coupled with the photoelectric conversion circuit.
  • the photoelectric conversion circuit may generate a first current based on incident light incident on the pixel.
  • the first current may also be called photocurrent, that is, the photoelectric conversion circuit converts the incident light into the corresponding current.
  • the pixels provided in the embodiments of the present application have multiple working modes, respectively corresponding to the multiple working modes of the composite measurement circuit.
  • the composite measurement circuit in the pixel provided by the embodiment of the present application has multiple working modes to realize multiple functions of the pixel.
  • the composite measurement circuit can switch working modes driven by the image signal processor.
  • the composite measurement circuit can receive the photocurrent from the photoelectric conversion circuit, and then detect the two-dimensional information of the incident light (such as the intensity information of the incident light) or the three-dimensional information (such as the flight time information of the incident light) based on the photocurrent.
  • the composite measurement current is used to detect intensity information of incident light.
  • the composite measurement circuit can be used to detect the time-of-flight information of the incident light.
  • the working process of the composite measurement circuit in different pixel working modes is introduced below.
  • the composite measurement circuit can generate a first pulse signal based on the first current when the pixel is working in the first working mode.
  • the first pulse signal represents the intensity information of the incident light, which can realize the detection of the incident light by the pixel. two-dimensional information.
  • the image signal processor may control the composite measurement circuit to operate in the first operating mode.
  • image letter The number processor may send the first working mode control signal to the composite measurement circuit.
  • the composite measurement circuit may generate a first pulse signal based on the first current in response to the first operating mode control signal.
  • the composite measurement circuit may receive a plurality of sampling signals when the pixel operates in the second operating mode, and generate a plurality of second pulse signals based on the first current and the plurality of sampling signals.
  • the plurality of sampling signals correspond to the plurality of second pulse signals one-to-one.
  • the plurality of second pulse signals are used to represent the phase offset between the phase of the incident light and the set phase.
  • the incident light is the light with the set phase incident on the target object and reflected. This enables the pixels to detect three-dimensional information of incident light.
  • the three-dimensional information of the incident light detected by the composite measurement current (that is, the time-of-flight information) may be the phase offset between the phase of the incident light and the phase of the active light source.
  • the image signal processor may send a second working mode control signal to the composite measurement circuit.
  • the second working mode control signal may include multiple sampling signals, wherein the multiple sampling signals are all periodic signals, and the phases of the multiple sampling signals different.
  • the image signal processor may sequentially send sampling signals to the composite measurement circuit, and the composite measurement circuit may respond to each received sampling signal and generate a second pulse signal corresponding to the sampling signal based on the first current and the received sampling signal.
  • the second pulse signal corresponding to each sampling signal generated by the composite measurement circuit can represent the phase offset between the phase of the incident light and the set phase (such as the phase of the active light source).
  • the image sensor is used to detect three-dimensional information scenes. The light emitted by the active light source is reflected by the object to be measured and then enters the pixels of the image sensor.
  • the frequency of the active light source is preconfigured, and the image signal processor can obtain the frequency of the active light source in advance.
  • the following is a brief introduction to the process by which the image signal processor can use the phase offset to determine the distance between the pixel and the object to be measured.
  • the incident light is delayed after being reflected from the active light source and reflected by the target object.
  • the incident light can be recorded as in, is the phase shift between the incident light and the active light source.
  • the image signal processor may determine the distance corresponding to the detected phase offset based on a preset relationship between phase offset and distance.
  • the relationship can be expressed as: where c is the speed of light and fmod is the frequency of the active light source.
  • the image signal processor may determine the distance corresponding to the detected phase offset based on a preset relationship between phase offset and distance.
  • the relationship is expressed as: Among them, c is the speed of light, fmod is the frequency of the active light source, and k is the refractive index.
  • the photoelectric conversion circuit may include a photodiode (PD).
  • the photodiode (PD) may be disposed between a first power supply level and a second power supply level, the second power supply level being greater than the first power supply level.
  • the cathode of the photodiode (PD) is coupled to the second power level (VDD1).
  • the anode of the photodiode (PD) is coupled to the first supply level (VSS) and the cathode of the photodiode (PD) is coupled to the composite measurement circuit.
  • the second power supply level (VDD1) can be 3.3V.
  • the first supply level (VSS) may be less than zero, that is, less than the ground level. Such a design can improve the current gain of the photoelectric conversion circuit.
  • the composite measurement circuit may include a configuration signal receiving unit, an integrating unit, a comparing unit and a delayed sampling unit.
  • a first end of the configuration signal receiving unit is coupled to a photoelectric conversion circuit, such as a cathode coupling of the photodiode (PD).
  • the second end of the configuration signal receiving unit and the integrating unit The first terminal is coupled to and coupled to the input terminal of the comparison unit.
  • the configuration signal receiving unit may receive the first working mode control signal and conduct connection between the photoelectric conversion circuit and the integrating unit to realize the configuration.
  • the signal receiving unit receives the first current and outputs the first current to the integrating unit.
  • the configuration signal unit may receive each sampling signal, and based on the signal period of the sampling signal, periodically conduct the connection between the photoelectric conversion circuit and the integrating unit. Through, the configuration signal receiving unit periodically outputs the first current to the integrating unit.
  • the first end of the integrating unit is coupled to the second end of the configuration signal receiving unit, the first end of the integrating unit is coupled to the comparison unit, and the second end of the integrating unit is coupled to the third end.
  • One level (VQ) coupling may be a fixed voltage.
  • the first level (VQ) may be a ground level, or the second terminal of the integrating unit may be grounded.
  • the integrating unit may receive the first current output by the configuration signal receiving unit.
  • the integrating unit may be used to integrate the received first current to obtain a measured voltage, and provide the measured voltage to the comparison unit.
  • Node VD is shown in Figure 2 .
  • the node VD can be any point between the second end of the configuration signal receiving unit and the comparison unit.
  • the integrating unit integrates the first current to change the voltage at the node VD, and the voltage at the node VD is the aforementioned measured voltage.
  • the input terminal of the comparison unit may be coupled with the first terminal of the integration unit, and the output terminal of the comparison unit may be coupled with the delayed sampling unit.
  • the comparison unit may receive the measured voltage, compare the measured voltage with a preset reference voltage, and output (send) the comparison result signal to the delayed sampling unit.
  • the comparison unit can output the comparison result signal to the second level when the measured voltage is less than the reference level.
  • the level of the signal that outputs the comparison result is a third level, wherein the second level is greater than the third level.
  • the comparison result signal output by the comparison unit is an analog signal. It is convenient to distinguish and record the signal output by the comparison unit as the first analog signal. It can be seen from the above introduction that the level of the first analog signal in the period when the measured voltage is less than the reference voltage is the second level, and the level in the period when the measured voltage is greater than or equal to the reference voltage is the second level. Level is the third level.
  • the delayed sampling unit is coupled to the output end of the comparison unit, and the delayed sampling unit is coupled to the image signal processor.
  • the delayed sampling unit may perform delayed sampling processing on the signal output by the comparison unit to generate the first pulse signal or the second pulse signal.
  • the delayed sampling unit may receive a first clock signal (clk) provided by the image signal processor, and sample the signal output by the comparison unit based on the first clock signal (clk).
  • the delayed sampling unit can convert analog signals into digital signals. Within a given period, the delayed sampling unit outputs a pulse. Such a design can meet the time requirements of the image signal processor.
  • the delayed sampling unit samples the signal output by the comparison unit based on the first clock signal (clk), and the pulse signal obtained is the first pulse signal.
  • the pulse signal obtained is the aforementioned second pulse signal.
  • the configuration signal receiving unit may include a first switch (Q1) and a second switch (Q2).
  • the first terminal of the first switch (Q1) is coupled to the third power level (DR)
  • the second terminal of the first switch (Q1) is coupled to the anode of the photodiode (PD)
  • the first terminal of the first switch (Q1) is coupled to the anode of the photodiode (PD).
  • the second terminal of switch (Q1) is coupled to the first terminal of said second switch (Q2).
  • the control end of the first switch (Q1) is coupled to the image signal processor.
  • the second terminal of the second switch (Q2) is coupled to the first terminal of the integrating unit.
  • the control terminal and image of the second switch (Q2) Signal processor coupling.
  • the integrating unit may include an integrating device.
  • the integrating unit may include a first capacitor (CD).
  • the first pole of the first capacitor (CD) is coupled to the photoelectric conversion circuit, and the second pole of the first circuit (CD) is grounded.
  • the first pole of the first capacitor (CD) is coupled to the anode of the photodiode (PD) through the second switch (Q2).
  • the second switch (Q2) When the second switch (Q2) is in the on state, it can connect the anode of the photodiode (PD) and the first pole of the first capacitor (CD).
  • the anode of the photodiode (PD) can be disconnected from the first pole of the first capacitor (CD).
  • the first pole of the first capacitor (CD) can be embodied as a first terminal of the integrating unit, and the second pole of the first capacitor (CD) can be embodied as a second terminal of the integrating unit.
  • the comparison unit includes a first comparator.
  • the first input terminal of the first comparator is coupled to the first terminal of the integrating unit, the second input terminal of the first comparator receives a reference level (VREF), and the output terminal of the first comparator For outputting the first analog signal.
  • the first comparator can be any comparator that can implement the function of the above comparison unit.
  • FIG. 4 shows a circuit structure diagram of a first comparator according to an exemplary embodiment, wherein the voltage of the power supply level VDD of the first comparator may be 1.8V.
  • the Vin terminal shown in FIG. 4 may be an input terminal of the first comparator and may be coupled to the first pole of the first capacitor (CD).
  • the Vref terminal is coupled to the reference level.
  • the Vb terminal is coupled to a fixed voltage.
  • the Vcomp terminal is the output terminal of the first comparator.
  • the delayed sampling unit may include a D latch and a NOR gate circuit.
  • the D latch can be any type of D latch.
  • the D latch usually has a data input terminal (D), a timing control input terminal (EN), and a Q output terminal. Among them, when EN is high level, the level of the Q output terminal changes with the level of the data input terminal (D); when the timing control input terminal (EN) is low level, the level of the Q output terminal does not change the output state.
  • Figure 5 exemplarily shows a circuit structure diagram of a D latch.
  • the data input terminal (D) of the D latch is coupled to the output terminal of the first comparator for receiving the first analog signal.
  • the timing control input terminal (EN) of the D latch is coupled to the image signal processor for receiving the first clock signal (clk).
  • the NOR gate circuit is used to perform NOR processing on two input signals and output the processed signal. The NOR processing of the NOR gate circuit is introduced below. If both input signals are low level, the NOR gate circuit outputs a high level. If both input signals are high level (or the two input signals are high level and low level respectively), the NOR gate circuit outputs low level.
  • the first input terminal of the NOR circuit is coupled to the Q output terminal of the D latch for outputting a signal to the NOR circuit.
  • the second input terminal of the NOR gate circuit is coupled to the image signal processor for receiving the first clock signal (clk).
  • the NOR gate circuit can perform NOR processing on the signal output by the Q output terminal of the D latch and the first clock signal (clk), and can generate a pulse signal.
  • the output end of the NOR gate circuit can be coupled with the image signal processor to output a pulse signal.
  • the pixel is in a first working mode, and the NOR gate circuit outputs the first pulse signal.
  • the pixel is in the second working mode, and the NOR gate circuit outputs the second pulse signal.
  • the image signal processor may send a first working mode control signal to the composite measurement circuit, and the first working mode control signal may include a first driving signal and a second driving signal.
  • the control end of the first switch (Q1) is used to receive the first driving signal
  • the control end of the second switch (Q2) is used to receive the second driving signal.
  • the first driving signal and the second driving signal are both fixed level signals.
  • the first driving signal can drive the first switch (Q1) to be in the off state
  • the second driving signal can drive the second switch (Q2) to be in the on state.
  • the first current (I) generated by the photodiode (PD) can be transferred to the first capacitor (CD) via the second switch (Q2) The first extreme point.
  • the configuration signal receiving unit can maintain the connection between the photoelectric conversion circuit and the integrating unit under the control of the first driving signal and the second driving signal, so that the first current can be continuously input into the integrating unit.
  • the first capacitor (CD) may be an integrating capacitor. When the first electrode of the first capacitor (CD) is connected to the cathode of the photodiode (PD), the first capacitor (CD) integrates the first current (I), and the voltage (VFD) at the node VD changes, which facilitates Introduce node VD to be recorded as an integral node. The first capacitor (CD) integrates the first current (I), which actually charges the first capacitor (CD) with the first current (I).
  • the initial voltage of the integrating node may be the same as the level of the ground.
  • the level of the comparison result signal output by the first comparator is the second level.
  • the first capacitor (CD) integrates the first current.
  • the voltage (VFD) at the integration node increases.
  • the level at the integration node increases to the reference voltage
  • the level of the comparison result signal output by the first comparator is the third level.
  • the voltage at the integration node (VFD) is reset to the initial level, allowing the first capacitor (CD) to start a new integration process.
  • the level of the comparison result signal output by the first comparator becomes the second level.
  • the low level output by the first comparator can be regarded as the reset effective level generated by the first comparator. It can be seen that during an integration process of the first capacitor (CD), the voltage at the integration node (VFD) increases from the initial voltage to the reference level, the first comparator outputs a low level, and the voltage at the integration node (VFD) After resetting to the initial voltage, the first comparator outputs a high level, so the first comparator generates a pulse.
  • the number of pulses output by the first comparator within a fixed period of time that is, the frequency of pulses output by the first comparator.
  • the frequency of the output pulse of the first comparator can represent the intensity information of the incident light.
  • the image signal processor may encode the intensity information of the incident light using the pulse frequency output by the first comparator. Since the composite measurement circuit outputs a first pulse signal in the first working mode, the grayscale data has only 1 bit.
  • the image signal processor can count the number of valid reset levels output by the first comparator within a fixed period of time. This number can represent the intensity information of the incident light, that is, the intensity information of the incident light.
  • This method of detecting light intensity in the frequency domain can also be called grayscale pulse imaging technology.
  • the image signal processor may send a second working mode control signal to the composite measurement circuit, and the second working mode control signal may include a third driving signal and a fourth driving signal.
  • the control end of the first switch (Q1) is used to receive the third driving signal
  • the control end of the second switch (Q2) is used to receive the fourth driving signal.
  • the third driving signal is used to drive the first switch (Q1)
  • the fourth driving signal is used to drive the second switch (Q2).
  • the third driving signal and the fourth driving signal are both periodic signals.
  • the third driving signal and the fourth driving signal may be a pair of inverted clock signals.
  • the third driving signal and the fourth driving signal provided by the image signal processor to the composite measurement circuit are both periodic square wave signals, and the frequency is the same as the frequency of the active light source.
  • the first switch (Q1) may be in a conductive state periodically.
  • the second switch (Q2) may be in a conductive state periodically.
  • the second switch (Q2) is turned on, the first switch (Q1) is turned off, and the first current (I) is transmitted to the integration node.
  • the second switch (Q2) is turned off, the first switch (Q1) is turned on, and all the first current is transmitted to DR.
  • the second switch (Q2) alternates between the on state and the off state, and has a gating function.
  • the fourth driving signal may be the aforementioned sampling signal, denoted as g(t).
  • the sampling signal g(t) can drive the second switch (Q2) to be in a conductive state alternately status and open circuit status.
  • (a) in Figure 6 exemplarily shows the waveform of the sampling signal in the duration corresponding to a period T, Among them, k0 and T are preconfigured constants. For example, in one cycle, when -k0/2 ⁇ t ⁇ k0/2, if the photoelectric conversion circuit generates a first current, the second switch (Q2) can transfer the first current to the first capacitor (CD). At other times within a period T, if the photoelectric conversion circuit generates the first current, the second switch (Q2) will not transfer the first current to the first capacitor (CD).
  • sampling signal g(t) shown in (a) of Figure 6 is used to illustrate the gating function of the second switch (Q2) under the control of the fourth driving signal, and does not As a specific limitation on the sampled signal.
  • the sampling signal is a periodic signal, and in each cycle, the moment when the level in the sampling signal converts from low level to high level (referred to as the phase of the sampling signal in this application) can be Regulated.
  • the fourth driving signal is a control signal for driving the second switch (Q2), and the period of high level in the fourth driving signal is the period when the second switch (Q2) is in a conductive state.
  • the period of low level in the fourth driving signal is the period when the second switch (Q2) is in the off-circuit state.
  • the second switch (Q2) has a gating function under the control of the fourth driving signal.
  • the first current (I) can only be transmitted to the first capacitor (CD) when the second switch (Q2) is in the on state to charge the first capacitor (CD) so that the first capacitor (CD) stores Optoelectronics realizes the integration of the first capacitance (CD) with the first current.
  • the shaded part in (b) in FIG. 6 is the period corresponding to the first current being transmitted to the first capacitor (CD).
  • the first capacitor (CD) integrates the first current in each period, and the total number of pulses output by the first comparator represents the preset number.
  • the integrated value of the first current within the corresponding period of time (such as hundreds of cycles).
  • the image signal processor can adjust the phase of the fourth driving signal, that is, the image signal processor can provide the fourth driving signal with multiple phase combinations, for example, four phase combinations, and any two of the four phase combinations are orthogonal to each other. .
  • the fourth driving signal may be the aforementioned sampling signal.
  • the image signal processor provides the sampling signal to the second switch (Q2) to drive the second switch (Q2) to alternate between the on state and the off state.
  • the second switch (Q2) is in the on state, the first current is transmitted to the integrating capacitor (CD).
  • the second switch (Q2) is in the off state, the first current cannot be transmitted to the integrating capacitor (CD).
  • the second switch (Q2) is in a conductive state, causing the integrating capacitor to integrate the first current.
  • This process can realize the cross-correlation processing between the sampling signal g(t) and the incident light signal s(t).
  • the processed signal can be represented by C( ⁇ ), and its mathematical expression is: k0 is a preconfigured constant.
  • the phase of each of the multiple sampled signals provided by the image signal processor is different. Please refer to (c) in Figure 6.
  • the following uses multiple sampling signals g 0 (t), g 1 (t), g 2 (t), and g 3 (t) as an example for introduction.
  • the phases of g 0 (t), g 1 (t), g 2 (t), and g 3 (t) can be 0, ⁇ ,
  • the image signal processor provides each sampled signal to the second switch (Q2) in a time-sharing manner. As shown in (c) in Figure 6, assuming that the incident light signal has a phase of Sampling signals of different phases play different gating functions.
  • the second switch (Q2) transmits the first current to the first capacitor (CD), and the second switch (Q2) transmits the first current to the first capacitor (CD).
  • the duration of the current is During the period of the shaded part of the waveform of the sampling signal g 1 (t), the second switch (Q2) switches the first voltage The current is transmitted to the first capacitor (CD), and the second switch (Q2) transmits the first current for During the period of the shaded part of the waveform of the sampling signal g 2 (t), the second switch (Q2) transmits the first current to the first capacitor (CD), and the duration of the second switch (Q2) transmitting the first current is Under the control of the second switch (Q2) by the sampling signal g 3 (t), the duration of the second switch (Q2) transmitting the first current is 0.
  • the sampling signal is g 0 (t)
  • the sampling signal is the cross-correlation function value of g 0 (t) and the incident light signal s(t)
  • the sampling signal is g 1 (t)
  • the sampling signal is the cross-correlation function value of g 1 (t) and the incident light signal s(t)
  • the sampling signal is g 2 (t)
  • the sampling signal is the cross-correlation function value of g 2 (t) and the incident light signal s(t)
  • the sampling signal is g 3 (t)
  • the sampling signal is the cross-correlation function value of g 3 (t) and the incident light signal s(t)
  • the second switch (Q2) When the sampling signal g 0 (t) is input, the second switch (Q2) is periodically in a conductive state under the control of the sampling signal g 0 (t), and the first comparator outputs the sampling signal g 0 (t) corresponding to The second pulse signal, wherein within the duration of a preset number of cycles (the period of the sampling signal), the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g 0 (t) represents the sampling
  • the cross-correlation function value C 0 corresponding to the signal g 0 (t) is also the cross-correlation function value C 0 corresponding to the phase of the sampled signal g 0 (t).
  • the second switch (Q2) is periodically in a conductive state under the control of the sampling signal g 1 (t), and the first comparator outputs the sampling signal g 1 (t ) corresponding to the second pulse signal, wherein within the duration of the preset number of cycles (the period of the sampling signal), the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g 1 (t) ) represents the cross-correlation function value C 1 corresponding to the sampling signal g 1 (t), and is also the cross-correlation function value C 1 corresponding to the phase of the sampling signal g 1 (t).
  • the second switch (Q2) is periodically in a conductive state under the control of the sampling signal g 2 (t), and the first comparator outputs the sampling signal g 2 (t ), wherein the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g 2 (t) within a preset number of cycles (the period of the sampling signal) ) represents the cross-correlation function value C 2 corresponding to the sampling signal g 2 (t), and is also the cross-correlation function value C 2 corresponding to the phase of the sampling signal g 2 (t).
  • the second switch (Q2) is periodically in a conductive state under the control of the sampling signal g 3 (t), and the first comparator outputs the sampling signal g 3 (t ), wherein, within the duration of a preset number of periods (the period of the sampling signal), the pulse in the second pulse signal corresponding to the sampling signal g 3 (t)
  • the total number of represents the cross-correlation function value C 3 corresponding to the sampling signal g 3 (t), and is also the cross-correlation function value C 3 corresponding to the phase of the sampling signal g 3 (t).
  • the image signal processor may determine the cross-correlation function value corresponding to each sampling signal according to the received second pulse signal corresponding to each sampling signal. And determine the phase offset according to the cross-correlation function value corresponding to the sampled signal, where,
  • the composite measurement circuit may also include a reset switch (MRST).
  • the first end of the reset switch (MRST) is grounded, and the second end is connected to the integrating unit. The first end of the coupling.
  • the second terminal of the reset switch (MRST) can be coupled with the first pole of the first capacitor (CD), and the control terminal of the reset switch (MRST) can be coupled with the output terminal of the NOR gate circuit.
  • the reset switch (MRST) can alternate between the on state and the off state under the control of the pulse signal output by the delayed sampling unit.
  • the reset switch (MRST) is in a conductive state, which can reset the voltage at the first end of the integrating unit to the initial voltage, that is, 0V.
  • the reset switch (MRST) is turned on and the voltage at the integrating node (VFD) can be reset to the initial voltage.
  • the D latch can sample the falling edge (or negative pulse, that is, the high level) of the first analog signal generated by the first comparator at the high level edge (rising edge) of the first clock signal (clk).
  • the output level of the Q output terminal is low level.
  • the level of the first pulse signal output by the NOR gate circuit is high level, which can drive the reset switch (MRST ) is on, which resets the level at the integration node to its initial level, such as 0V.
  • the composite measurement circuit may also include a readout unit.
  • the readout unit is coupled to the delayed sampling unit and to the image signal processor.
  • the readout unit may include a third switch (Q3), a fourth switch (Q4), and an RS latch.
  • the first end of the third switch (Q3) can be coupled to the output end (out) of the readout unit and the image signal processor.
  • the first terminal of the third switch (Q3) can be used as the output terminal (out) of the readout unit.
  • the second terminal of the third switch (Q3) is coupled to the first pole of the fourth switch (Q4), and the control terminal of the third switch (Q3) is used to receive the selection signal (sel), so The selection signal is used to drive the third switch (Q3) to be in a conductive state.
  • the second pole of the fourth switch (Q4) is grounded, and the control terminal of the fourth switch (Q4) is coupled with the Q output terminal of the RS-th latch.
  • the set terminal of the RS latch (S) is coupled to the output end of the NOR gate circuit for receiving the first pulse signal or the second pulse signal.
  • the RS latch has the function of recording levels.
  • the image signal processor can provide a storage signal to the reset terminal (R) of the RS latch to drive the record level function of the RS latch.
  • the RS latch latches the level of the set terminal (S), and the level state of the Q output terminal of the RS latch is high level. , and keep Output high level.
  • the image signal processor can provide a reset signal to the reset terminal (R) of the RS latch, driving the RS latch to reset, so that the initial output of the RS latch is 0.
  • FIG. 7 shows a circuit diagram of an RS latch according to an exemplary embodiment.
  • the control terminal of the fourth switch (Q4) is coupled to the Q output terminal of the RS latch.
  • the Q output terminal of the RS latch outputs a high level, which can drive the fourth switch (Q4) to turn on.
  • the Q output terminal of the RS latch outputs a low level, which can drive the fourth switch (Q4) to open circuit. Therefore, after the RS latch records the high level of the first pulse signal, the fourth switch (Q4) is turned on.
  • the image signal processor provides the selection signal (sel) to the third switch (Q3), so that the third switch (Q3) is in a conductive state driven by the selection signal (sel), so that the fourth switch (Q4) can communicate with the image signal processors.
  • the fourth switch (Q4) can couple the bus pull-up resistor.
  • the third switch (Q3) is in the on state driven by the selection signal (sel), and when the fourth switch (Q4) is on, the first end of the third switch (Q3) (can also be regarded as the pixel Output terminal) has level output.
  • the fourth switch (Q4) is open, the first terminal of the third switch (Q3) has no level output. If the image signal processor does not provide the selection signal (sel) to the third switch (Q3), the third switch (Q3) is in an off-circuit state, and the first terminal of the third switch (Q3) has no level output.
  • the pixels provided in the embodiments of the present application can provide information on changes in light intensity.
  • the pixel provided by the embodiment of the present application may also include a dynamic visual measurement circuit.
  • the dynamic vision measurement circuit may be coupled to the photoelectric conversion circuit, and the dynamic vision measurement circuit may provide the image signal processor with a signal of the incident light based on the first current generated by the photoelectric conversion circuit. Information about changes in light intensity.
  • the dynamic vision measurement circuit can compress the intensity of incident light in the logarithmic domain and sense changes in the measured object, that is, it refers to sensing image points that change drastically.
  • the embodiment of the present application may also include a current mirror circuit.
  • the composite measurement circuit is coupled to the photoelectric conversion circuit through the current mirror circuit.
  • the current mirror circuit may provide the current generated by the photoelectric conversion circuit to the composite measurement circuit.
  • the current mirror circuit can increase the isolation between the composite measurement circuit and the dynamic vision measurement circuit, and reduce the influence between the composite measurement circuit and the dynamic vision measurement circuit.
  • the dynamic vision measurement circuit may include a light receiving stage, a driving stage, an amplification stage, a comparison stage and a response circuit.
  • the light receiving stage can convert the first current into a logarithmic domain.
  • the light receiving stage includes a fifth switch (M1), a sixth switch (M2), and a seventh switch (M3). Wherein, the first terminal of the fifth switch (M1) is coupled with the cathode of the photodiode, and the second terminal of the fifth switch (M1) is coupled with the current mirror circuit.
  • the control terminal of the fifth switch (M1) is coupled to the first terminal of the sixth switch (M2), and the second terminal of the sixth switch (M2) is coupled to the fourth power supply level (VDD2).
  • VDD2 the voltage of the fourth power level
  • the control end of the sixth switch (M2) is coupled to a preset fixed level (Vb1).
  • the first terminal of the seventh switch (M3) is coupled to the control terminal of the fifth switch (M1) and to the first terminal of the sixth switch (M2).
  • the second terminal of the seventh switch (M3) is grounded, and the control terminal of the seventh switch (M3) is coupled with the cathode of the photodiode (PD). light receiving grade
  • the output terminal is the first terminal of the sixth switch (M2).
  • the output terminal of the light receiving stage is virtual ground.
  • the sub-threshold region characteristics of the fifth switch (M1) make the output terminal of the light receiving stage at There is a logarithmic relationship between the voltage (VQ) and the first current I, such as lnI.
  • the driving stage can increase the isolation between the amplifying stage and the light receiving stage, and the driving stage is used to provide the first current in the logarithmic domain to the amplifying stage.
  • the driver stage (which may also be called a source follower stage) may include an eighth switch (M4) and a ninth switch (M5).
  • the first terminal of the eighth switch (M4) is coupled to the fourth power supply level (VDD2)
  • the second terminal of the eighth switch (M4) is coupled to the first terminal of the ninth switch (M5).
  • the control end of the eighth switch (M4) is coupled to a preset fixed level (Vb3).
  • the second terminal of the ninth switch (M5) is grounded, and the control terminal of the ninth switch (M5) is coupled with the control terminal of the fifth switch (M1).
  • the amplification stage may include a capacitive feedback circuit to amplify the changing small signal.
  • the amplification stage may include a second capacitor (C1), a third capacitor (C2), a tenth switch (M6), an eleventh switch (M7), and a twelfth switch (M8).
  • the first pole of the second capacitor (C1) is coupled with the second terminal of the eighth switch (M4)
  • the second pole of the second capacitor (C1) is coupled with the first pole of the third capacitor (C2)
  • the second pole of the second capacitor (C1) is coupled with the second terminal of the eighth switch (M4).
  • the second pole of the capacitor (C1) is coupled with the first terminal of the tenth switch (M6)
  • the second pole of the second capacitor (C1) is coupled with the control terminal of the eleventh switch (M7).
  • the second terminal of the tenth switch (M6) is coupled with the second pole of the third capacitor (C2), the second terminal of the tenth switch (M6) is coupled with the first terminal of the eleventh switch (M7), and the tenth switch
  • the second terminal of (M6) is coupled with the first terminal of the twelfth switch (M8).
  • the control end of the tenth switch (M6) is coupled to the image signal processor and receives the amplification control signal (RST_N). Among them, the amplification control signal (RST_N) can be provided by the response circuit in the dynamic visual measurement circuit.
  • the second terminal of the eleventh switch (M7) is coupled to said fourth power supply level (VDD2).
  • the second terminal of the twelfth switch (M8) is grounded, and the control terminal of the twelfth switch (M8) receives the fixed level VO.
  • the capacitive feedback circuit formed by the second capacitor (C1), the third capacitor (C2), the tenth switch (M6), the eleventh switch (M7) and the twelfth switch (M8) amplifies the changing small signal C1/C2 times, and superimposed on the reset DC bias voltage, changing the voltage of the second pole of the third capacitor (C2).
  • the second pole of the third capacitor (C2) can also be used as the output terminal (VC) of the amplifier stage.
  • the comparison stage may include a thirteenth switch (M9), a fourteenth switch (M10), a fifteenth switch (M11), and a sixteenth switch (M12).
  • the first terminal of the thirteenth switch (M9) is coupled to the second power level
  • the second terminal of the thirteenth switch (M9) is coupled to the first terminal of the fourteenth switch (M10)
  • the thirteenth switch (M9) ) is coupled to the second pole of the third capacitor (C2).
  • the second terminal of the fourteenth switch (M10) is connected to ground, and the control terminal of the fourteenth switch (M10) receives a fixed level VN.
  • the second terminal of the thirteenth switch (M9) is the first output terminal ON of the comparison stage.
  • the first terminal of the fifteenth switch (M11) is coupled to the second power level
  • the second terminal of the fifteenth switch (M11) is coupled to the first terminal of the sixteenth switch (M12)
  • the fifteenth switch (M11) ) is coupled to the second pole of the third capacitor (C2).
  • the second terminal of the sixteenth switch (M12) is grounded, and the control terminal of the sixteenth switch (M12) receives the fixed level VP.
  • the second terminal of the fifteenth switch (M11) is the second output terminal OFF of the comparison stage.
  • the eleventh switch (M7), the thirteenth switch (M9), and the fifteenth switch (M11) are PMOS tubes of the same size.
  • the twelfth switch (M8), the fourteenth switch (M10), and the sixteenth switch (M12) are NMOS tubes of the same size.
  • the fixed level VN received by the control terminal of the fourteenth switch (M10) is greater than the fixed level VO received by the control terminal of the twelfth switch (M8), and the fixed level VP received by the control terminal of the sixteenth switch (M12) It is less than the fixed level VO received by the control terminal of the twelfth switch (M8).
  • the tenth switch (M6) When the amplification control signal (RST_N) is low level (0), the tenth switch (M6) is in the on state. The level of the output terminal (VC) of the amplifier stage returns to the preset reset level. At this time, the first output terminal ON of the comparison stage outputs low level (0), and the second output terminal OFF outputs high level (1). .
  • the second output terminal OFF When the level of the amplifier stage output terminal (VC) shifts from the reset level to the positive level to cancel the current source mismatch caused by the difference between the fixed level VP and the comparison threshold BIAS, the second output terminal OFF outputs a low level ( 0).
  • the first output terminal ON When the level of the amplifier stage output terminal (VC) shifts from the reset level to negative to cancel the current source mismatch caused by the difference between the fixed level VN and the comparison threshold BIAS, the first output terminal ON outputs a high level ( 1). Based on this preset comparison threshold BIAS, fixed level VP, fixed level VN, fixed level VO, the above process can be realized.
  • the dynamic visual measurement circuit may also include a response circuit.
  • the response circuit may receive the level of the first output terminal ON and the second output terminal OFF of the comparison stage, and latch the level of the first output terminal ON and the level of the second output terminal OFF. flat.
  • the response circuit can generate a request signal (REQ) based on the level of the first output terminal ON and the level of the second output terminal OFF of the comparison stage. Generating the request signal (REQ) can represent the occurrence of a change in light intensity.
  • the response circuit can generate a request signal (REQ), and/or compare
  • REQ request signal
  • the first output terminal ON of the comparison stage When the dynamic visual measurement circuit is in the initial state, the first output terminal ON of the comparison stage outputs low level (0), and the second output terminal OFF outputs high level (1). If the first current of the incident light increases, the level of the output terminal (VC) of the amplifier stage becomes smaller, the first output terminal ON of the comparison stage outputs a high level (1), and the second output terminal OFF outputs a high level ( 1). If the first current of the incident light decreases, the first output terminal ON of the comparison stage outputs a low level (0), and the second output terminal OFF outputs a low level (0).
  • the response circuit is coupled to the image signal processor and sends the request signal (REQ) to the image signal processor.
  • the response circuit sends a request signal (REQ) to the image signal processor.
  • the response circuit sends a request signal (REQ) to the image signal processor so that the image signal processor knows that the light intensity change event occurs.
  • a dynamic event occurs (such as a change in light intensity)
  • the rise or fall of the output level is accelerated.
  • the response circuit may include logic circuits such as NAND gates, NOR gates, and NOT gates, and adopt a standard CMOS digital push-pull structure to implement the above functions.
  • the response circuit can receive the level provided by the first output terminal ON of the comparison stage and the level provided by the second output terminal OFF of the comparison stage.
  • the response circuit can receive the response signal (ACK) and the reset dynamic measurement signal (RST) provided by the image signal processor.
  • the reset dynamic measurement signal (RST) can drive the dynamic visual measurement circuit to restore the initial state and wait for the next change event.
  • the comparison stage is connected to the tenth switch to receive the amplified control signal (RST_N), which is the inverse signal of the reset dynamic measurement signal (RST).
  • the response circuit has multiple output terminals, the output terminal CON and the output terminal COFF.
  • the level of the output terminal CON is low level (0)
  • the level of the output terminal COFF is low level (0).
  • the level of the output terminal CON is high level (1) and the level of the output terminal COFF is low level (0)
  • the light intensity changes positively that is, the light intensity increases
  • the level of the output terminal CON is low level (0) and the level of the output terminal COFF is high level (1), it means that the light intensity changes negatively (that is, the light intensity decreases).
  • the image signal processor can determine the change in light intensity through the level conditions of the output terminal CON and the output terminal COFF.
  • the input terminal that receives the reset dynamic measurement signal (RST) in the response circuit is recorded as the input terminal RST.
  • the input terminal in the response circuit that receives the response signal (ACK) is denoted as the input terminal ACK.
  • the response circuit may include multiple switches and multiple inverters.
  • the plurality of switches are respectively denoted as switch S1, switch S2, ..., and switch S14.
  • the plurality of inverters are respectively denoted as inverter NG1, inverter NG2 and inverter NG3.
  • the first terminal of the switch S1 is coupled to the power level
  • the second terminal of the switch S1 is coupled to the first terminal of the switch S2, and the control terminal of the switch S1 is coupled to the input terminal RST.
  • the second terminal of the switch S2 is coupled to the input terminal ON and coupled to the first terminal of the switch S3.
  • the control terminal of the switch S2 is coupled to the output terminal of the inverter NG2.
  • the input terminal of the inverter NG2 is coupled to the input terminal ON.
  • the second terminal of the switch S3 is connected to ground, and the control terminal of the switch S3 is coupled to the input terminal RST.
  • the level at the output terminal of inverter NG2 is recorded as N
  • the first terminal of the switch S4 is coupled to the power level, and the second terminal of the switch S4 is coupled to the first terminal of the switch S5 and coupled to the input terminal OFF.
  • the input terminal of the inverter NG1 is coupled to the input terminal RST, and the output terminal of the inverter NG1 is coupled to the control terminal of the switch S4.
  • the level at the output end of the inverter NG1 is marked as RST_N.
  • the second terminal of switch S5 is coupled to the first terminal of switch S6.
  • the input terminal of the inverter NG3 is coupled to the input terminal OFF, and the output terminal of the inverter NG3 is coupled to the control terminal of the switch S5.
  • the level at the input terminal of inverter NG3 is recorded as NOFF.
  • the second terminal of the switch S6 is connected to ground, and the control terminal of the switch S6 is coupled to the output terminal of the inverter NG1.
  • the first terminal of the switch S7 is coupled to the input terminal ON, the second terminal of the switch S7 is grounded, and the control terminal of the switch S7 is coupled to the output terminal of the inverter NG3.
  • the first terminal of the switch S8 is coupled to the power level, the second terminal of the switch S8 is coupled to the input terminal OFF, and the control terminal of the switch S8 is coupled to the output terminal of the inverter NG2.
  • the first terminal of the switch S9 is coupled to the output terminal REQ, the second terminal of the switch S9 is grounded, and the control terminal of the switch S9 is coupled to the input terminal ON.
  • the first terminal of the switch S10 is coupled to the output terminal REQ, the second terminal of the switch S10 is grounded, and the control terminal of the switch S10 is coupled to the output terminal of the inverter NG3.
  • the first terminal of the switch S11 is connected to the ground, the second terminal of the switch S11 is coupled to the first terminal of the switch S12, and the control terminal of the switch S11 is coupled to the input terminal ON.
  • the second terminal of the switch S12 is coupled to the output terminal CON, and the control terminal of the switch S12 is coupled to the input terminal ACK.
  • the first terminal of the switch S13 is connected to ground, the second terminal of the switch S13 is coupled to the first terminal of the switch S14, and the control terminal of the switch S13 is coupled to the output terminal of the inverter NG3.
  • the second terminal of the switch S14 is coupled to the output terminal COFF, and the control terminal of the switch S14 is coupled to the input terminal ACK.
  • the switch S13 and the switch S14 can be in a conductive state driven by the response control signal received by the input terminal ACK, so that the second terminal of the switch S11 is connected to the output terminal CON, and the second terminal of the switch S13 is connected to the output terminal COFF. If the level at the input terminal ON can drive the switch S11 to turn on, the output terminal CON outputs a high level (1). If the level at the input terminal ON cannot drive the switch S11 to turn on, the output terminal CON outputs a low level (0).
  • the current mirror circuit may include a seventeenth switch (M13), an eighteenth switch (M14), a nineteenth switch (M15), and a twentieth switch (M16). and switch MBIAS.
  • the first terminal of the seventeenth switch (M13) is coupled with the second power level (VDD1)
  • the second terminal of the seventeenth switch (M13) is coupled with the first terminal of the eighteenth switch (M14)
  • the first terminal of the seventeenth switch (M13) is coupled with the second power level (VDD1).
  • the control terminal of the seventeenth switch (M13) is also coupled with the first terminal of the eighteenth switch (M14).
  • the second terminal of the eighteenth switch (M14) is coupled to the first terminal of the switch MBIAS, and the control terminal of the eighteenth switch (M14) is also coupled to the first terminal of the switch MBIAS.
  • the second terminal of the switch MBIAS is coupled to the second terminal of the fifth switch (M1) in the dynamic vision measurement circuit, and the control terminal of the switch MBIAS is coupled to the bias level BIAS.
  • the first terminal of the nineteenth switch (M15) is coupled to the second power supply level (VDD1)
  • the second terminal of the nineteenth switch (M15) is coupled to the first terminal of the twentieth switch (M16)
  • the nineteenth The control end of switch (M15) and the seventeenth switch (M13) control terminal coupling is
  • the second terminal of the twentieth switch (M16) is coupled to the second terminal of the first switch in the composite measurement circuit.
  • the control terminal of the twentieth switch (M16) is coupled with the control terminal of the eighteenth switch (M14).
  • a current mirror circuit is used to copy the first current into the composite measurement circuit.
  • the switch MBIAS can shield the coupling interference of the service current of the composite measurement circuit on the dynamic visual measurement circuit.
  • an image sensor which may include multiple pixels arranged in an array and an image signal processor.
  • the squares in the figure represent pixels provided by the embodiments of the present application.
  • the image processor may include a column selection unit.
  • an image sensor may include n rows and m columns of pixels.
  • the control terminal of the first switch (Q1) in the configuration signal receiving unit of the pixels in the nth row is coupled to the nth first configuration signal terminal (TXD) of the column selection unit, and the configuration signal receiving unit of the pixels in the nth row
  • the control terminal of the second switch (Q2) is coupled to the n-th second configuration signal terminal (TX) of the column selection unit.
  • the first configuration signal terminal of the column selection unit is used to provide the aforementioned first driving signal or third driving signal.
  • the second configuration signal terminal of the column selection unit is used to provide the aforementioned second driving signal or fourth driving signal.
  • the timing control input terminal of the D latch in the delay sampling unit of the pixel in the nth row is coupled to the nth clock signal output terminal of the column selection unit.
  • the second input terminal of the NOR gate circuit in the delayed sampling unit of the pixel in the nth row is coupled to the nth clock signal output terminal of the column selection unit.
  • the clock signal output terminal of the column selection unit is used to output the aforementioned first clock signal (clk).
  • the reset terminal of the RS latch of the readout unit of the pixel in the nth row is coupled to the nth reset signal terminal of the column selection unit.
  • the reset signal terminal of the column selection unit is used to output the aforementioned reset signal (clr).
  • the first end of the third switch (Q3) of the readout unit of the m-th column pixel is coupled to the m-th column data bus, and the image signal processor can receive the pixel output in the m-th column via the m-th column grayscale data bus.
  • the readout signal terminal of the column selection unit is used to output the aforementioned selection signal (sel).
  • the control terminal of the third switch (Q3) of the readout unit of the pixels in the nth row is coupled to the nth readout signal terminal of the column selection unit.
  • the pixels in the nth row output data to the grayscale data bus coupled to the column where each pixel is located, driven by the readout signal of the column selection unit.
  • all pixels in the nth row can share the five control signals provided by the column selection unit, which are the selection signal (sel), the reset signal (clr), the first clock signal (clk), and the first configuration signal terminal.
  • the signal (TXD) provided by the first configuration signal terminal and the signal (TX) provided by the second configuration signal terminal can be used to configure the working mode of the composite measurement circuit.
  • the composite measurement circuit After completing an integration process and resetting from the threshold voltage to the initial voltage, the composite measurement circuit will output a pulse, which is sampled multiple times by the first clock signal (clk) and the selection signal (sel) within a fixed period of time. After each sampling, reset signal (clr) is used to clear it. Counting the frequency of generated pulses encodes the intensity of the light. Therefore, the grayscale data of the pixel only has one bit, and the column selection unit scans and outputs the pulse data OUT row by row.
  • each pixel in the image sensor includes a dynamic visual measurement circuit.
  • the image signal processor may also include a row selection unit (also known as a dynamic visual measurement synchronization arbiter).
  • the input terminal RST of the pixel in the nth row is coupled with the nth reset dynamic measurement signal terminal of the row selection unit.
  • the reset dynamic measurement signal terminal of the row selection unit is used to output the aforementioned reset dynamic measurement signal (RET).
  • the input terminal ACK of the pixel in the nth row is coupled to the nth response control signal terminal of the row selection unit.
  • the response control signal terminal of the row selection unit is used to output the aforementioned response control signal (ACK).
  • the output terminal REQ of the pixel in the nth row is coupled to the nth time request signal terminal of the row selection unit, and the request signal terminal of the row selection unit is coupled for receiving the aforementioned request signal (REQ).
  • the output terminal CON of the pixel in the m-th column is coupled to the image processor through the first dynamic event data bus, and the output terminal COFF of the pixel in the m-th column is coupled to the image processor through the second dynamic event data bus.
  • a request signal (REQ) is sent to the row selection unit (arbiter), and the row selection unit (arbiter) sends a response signal (ACK) signal to the pixel in the i-th row.
  • REQ request signal
  • ACK response signal
  • the row selection unit (arbiter) sends a reset signal (RST) to the pixels in the i-th row, causing the dynamic visual measurement circuit in the pixels in the i-th row to return to the initial state and wait for the next change time.
  • RST reset signal

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Abstract

本申请提供一种图像传感器的像素和图像传感器，可以提供入射光的强度信息和飞行时间信息。像素可以包括光电转换电路和复合测量电路。光电转换电路可以用于基于入射在像素上的入射光，生成第一电流。复合测量电路与光电转换电路耦合。像素可以具有第一工作模式和第二工作模式。复合测量电路可以当像素工作在第一工作模式时，基于第一电流，生成第一脉冲信号，第一脉冲信号表征入射光的强度信息。当像素工作在第二工作模式时，接收多个采样信号，基于第一电流和多个采样信号，生成多个第二脉冲信号；多个第二脉冲信号用于表征入射光的相位与设定相位之间的相位偏移量，相位偏移量可以用于确定像素与目标对象之间的距离。

Description

一种图像传感器的像素和图像传感器
相关申请的交叉引用
本申请要求在2022年05月30日提交中华人民共和国专利局、申请号为202210597585.4、申请名称为“一种图像传感器的像素和图像传感器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及图像传感器技术，尤其涉及一种图像传感器的像素和图像传感器。
背景技术
随着图像传感器应用场景增多，图像传感器的类型也不断增多。当照射在对象上的光入射到图像传感器中，图像传感器中的各像素可以将入射到像素中的入射光转换为相应的电信号。处理器可以通过图像传感器中各像素提供的电信号，产生对象的图像或者确定对象的变化情况。
不同类型的图像传感器将入射光转换的电信号的过程也不相同。例如灰度图像传感器将入射光转换的电信号表征入射光的光强信息。处理器可以利用光强信息生成对象的图像。动态视觉图像传感器将入射光转换的电信号表征入射光的光强的变化量。处理器可以利用光强的变化量更新图像。灰度图像传感器和动态视觉图像传感器通常被称为二维图像传感器，分别产生的入射光的强度信息和入射光的光强的变化量称为二维信息。
飞行时间图像传感器将入射光转换的电信号表征入射光的飞行时间信息，并且该入射光是主动光源经对象反射后的光。处理器可以利用飞行时间信息确定对象与主动光源之间的距离，也即确定对象与主动光源之间的深度。因而飞行时间图像传感器通常被称为三维图像传感器，所产生的入射光的飞行时间信息称为三维信息。
在一些图像传感器的新应用场景中，通常需要多个类型的图像传感器。例如，自动驾驶场景中，车辆需要准确探测周围对象的情况。一般由车辆发射出主动光源，主动光源遇到被探测对象后被反射，车辆需要对反射到图像传感器中的光进行处理产生二维信息或者三维信息，便于生成对象的二维图像或者三维图像。因而车辆中需要设置多个类型的图像传感器，具有较高成本，并且将不同类型的图像传感器的像素产生的信息进行匹配的过程较为复杂。
发明内容
有鉴于此，本申请提供一种图像传感器的像素和图像传感器，可以提供入射光的强度信息和飞行时间信息。
第一方面，本申请实施例提供中图像传感器的像素，可以包括光电转换电路和复合测量电路。光电转换电路可以用于基于入射在所述像素上的入射光，生成第一电流。复合测量电路与光电转换电路耦合。像素可以具有多种工作模式，如第一工作模式和第二工作模式。像素在第一工作模式时，可以提供入射光的强度信息。像素在第二工作模式时可以提 供入射光的飞行时间信息。复合测量电路可以当所述像素工作在第一工作模式时，基于所述第一电流，生成第一脉冲信号，所述第一脉冲信号表征所述入射光的强度信息。当所述像素工作在第二工作模式时，接收多个采样信号，基于所述第一电流和所述多个采样信号，生成多个第二脉冲信号；其中，所述多个采样信号与所述多个第二脉冲信号一一对应，所述多个第二脉冲信号用于表征所述入射光的相位与设定相位之间的相位偏移量，所述入射光是所述设定相位的光线入射到目标对象反射的。设定相位可以为主动光的相位。入射光的相位与设定相位之间的相位偏移为入射光的飞行时间信息，可以用于确定像素与目标对象之间的距离。
本申请实施例中，复合测量电路在像素处于不同工作模式下，均采用脉冲形式的数据输出。节省外围电路中对模拟物理量处理。后端电路如图像信号处理器，可以直接采用数字信号处理的方式对所述第一脉冲信号或者所述第二脉冲信号进行处理。并且，复合测量电路具有多种功能，可以提供入射光的强度信息，以及飞行时间信息，减少占片面积。
一种可能的设计中，所述复合测量电路包括配置信号接收单元、积分单元、比较单元、以及延时采样单元。所述配置信号接收单元的第一端与所述光电转换电路耦合；所述配置信号接收单元的第二端与所述积分单元的第一端耦合，以及与所述比较单元的输入端耦合。
所述配置信号接收单元可以在所述第一工作模式下，将所述第一电流输出至所述积分单元；在所述第二工作模式下，接收所述多个采样信号，基于所述多个采样信号的信号周期，周期性地将所述第一电流输出至所述积分单元。所述积分单元的第二端与第一电平耦合，所述积分单元可以用于对所述第一电流积分得到测量电压，并向所述比较单元提供所述测量电压。
所述比较单元的输入端与所述积分单元的第一端耦合可以用于：将所述测量电压与预设的参考电压进行比较，并将比较结果信号发送至所述延时采样单元，其中，在所述测量电压小于所述参考电平时，所述比较结果信号的电平为第二电平，在所述测量电压大于或等于所述参考电平时，所述比较结果信号的电平为第三电平，所述第二电平大于所述第三电平；所述延时采样单元与所述比较单元的输出端耦合；所述延时采样单元用于：对所述比较结果信号进行采样处理，生成所述第一脉冲信号或者所述多个第二脉冲信号。
一种可能的设计中，所述配置信号接收单元包括第一开关和第二开关。所述第一开关的第一端与第三电源电平耦合，所述第一开关的第二端与所述光电转换电路耦合，所述第一开关的第二端与所述第二开关的第一端耦合，所述第二开关的第二端与所述积分单元的第一端耦合，所述第三电源电平小于所述第二电源电平；其中，当所述第一开关处于断路状态，且所述第二开关处于导通状态时，所述第一电流传输至所述积分单元；当所述第一开关处于导通状态，且所述第二开关处于断路状态时，所述第一电流传输至所述第三电源电平。
一种可能的设计中，所述积分单元包括第一电容；所述第一电容的第一极通过所述第二开关与所述光电转换电路耦合，所述第一电容的第二极与所述第一电平耦合。
一种可能的设计中，所述比较单元包括比较器。所述比较器的第一输入端与所述积分单元的第一端耦合，用于接收所述测量电压。所述比较器的第二输入端与所述参考电压耦合。所述比较器的输出端与所述延迟采样单元耦合，用于输出所述比较结果信号。第一电容的第一极的初始电压可以与接地的电平相同，此时比较器输出比较结果信号的电平为第二电平。
一个示例中，在所述第一工作模式下，所述第一开关的控制端接收第一驱动信号，所述第一驱动信号为固定电平信号，用于驱动所述第一开关处于断路状态。所述第二开关的控制端接收第二驱动信号，所述第二驱动信号为固定电平信号，用于驱动所述第二开关处于导通状态。从而光电二极管产生的第一电流可以经由第二开关传输至第一电容的第一极处。第一电容的第一极与光电二极管的阴极之间连通时，第一电容对第一电流积分，第一电容的第一极处的电压增大。第一电容的第一极处的电压增大至参考电压时，比较器输出比较结果信号的电平为第三电平。经过一段延迟时间后，第一电容的第一极处的电压被复位为初始电平，便于第一电容开始新的积分过程。此时比较器输出比较结果信号的电平变为第二电平。
本申请实施例中，比较器输出低电平可视为比较器产生复位有效电平。在第一电容的一次积分过程中，第一电容的第一极处的电压从初始电压增大到参考电平，比较器输出低电平，第一电容的第一极处的电压复位到初始电压后，比较器输出高电平，因而比较器会产生一次脉冲。在第一工作模式下，在固定时间内比较器输出的第一脉冲信号中脉冲的数量，也即比较器输出的第一脉冲信号的频率，可以表征入射光的强度信息。图像信号处理器可以利用比较器输出的第一脉冲信号的频率编码入射光的强度信息。
另一个示例中，在所述第二工作模式下，所述第一开关的控制端接收第三驱动信号；所述第三驱动信号为周期性信号，所述第一开关用于控制所述第一开关按照所述第三驱动信号的周期，在导通状态和断路状态之间交替。所述第二开关的控制端接收所述多个采样信号；其中，任一个采样信号为周期性信号，所述第二开关用于控制所述第二开关按照每个采样信号的周期，在导通状态和断路状态之间交替。其中，在所述第二开关处于导通状态时，所述第一开关处于断路状态，若光电转换电路输出第一电流则所述第一电流可以传输至所述第一电容的第一极。在所述第一开关处于导通状态时，所述第二开关处于断路状态，若光电转换电路输出第一电流，则所述第一电流可以传输至第三电源电平。一些场景中，第三驱动信号和所述采样信号可以是一对反相的时钟信号。采样信号的频率与所述设定相位的光纤的频率相同。
第二开关的控制端分时地接收所述多个采样信号，比较器可以分时地输出各采样信号对应的第二脉冲信号。其中所述多个采样信号分别具有不同的相位。第二开关的控制端接收到相位为第一相位的采样信号时，比较器输出第一相位对应的第二脉冲信号。在预设数量个周期的时长内，第一相位对应的第二脉冲信号中脉冲的总数量表征第一相位对应的积分值。各采样信号的相位对应的积分值可以用于确定入射光的相位与设定相位之间的相位偏移量。
一种可能的设计中，所述延时采样单元包括D锁存器和或非门电路；所述D锁存器的数据输入端与所述比较器的输出端耦合，用于接收所述比较结果信号；所述D锁存器的时序控制输入端，用于接收第一时钟信号；所述D锁存器的Q输出端与或非电路的第一输入端耦合，用于向所述或非电路输出信号；所述或非门电路的第二输入端，用于接收所述第一时钟信号；所述或非门电路的输出端与图像信号处理器耦合，用于输出所述第一脉冲信号或者所述第二脉冲信号。
一种可能的设计中，所述复合测量电路还包括复位开关。所述复位开关的第一端接地，第二端与所述积分单元的第一端耦合。所述复位开关的控制端与所述延时采样单元耦合，用于接收所述第一脉冲信号。在所述第一脉冲信号的电平为第四电平的时段内，所述复位 开关处于断路状态；在所述第一脉冲信号的电平为第五电平的时段内，所述复位开关处于导通状态，使所述积分单元的第一端处的电压为复位电压，如接地电平。其中，所述第四电平大于所述第五电平。
一种可能的设计中，所述复合测量电路还包括读出单元。所述读出单元与所述延时采样单元耦合，与图像信号处理器耦合。所述读出单元用于接收所述图像信号处理器提供的存储信号，并根据所述存储信号缓存所述第一脉冲信号或者所述第二脉冲信号。所述读出单元可以接收所述图像信号处理器提供的扫描信号，根据所述扫描信号向所述图像信号处理器输出缓存的信号。
一种可能的设计中，所述读出单元包括第三开关、第四开关以及RS锁存器。所述第三开关的第一端与所述图像信号处理器耦合；所述第三开关的第二端与所述第四开关的第一极耦合；所述第三开关的控制端用于接收所述图像信号处理器提供的所述扫描信号，其中，所述扫描信号用于驱动所述第三开关处于导通状态。所述第四开关的第二极接地，所述第四开关的控制端与所述第RS锁存器的Q输出端耦合；所述RS锁存器的复位端与所述图像信号处理器耦合，用于接收所述图像信号处理器提供的所述存储信号或者所述复位信号，所述RS锁存器的置位端与所述延时采样单元的输出端耦合，用于接收所述第一脉冲信号，所述RS锁存器的Q输出端处的电平与所述第一脉冲信号的电平相同，或者接收所述第二脉冲信号，所述RS锁存器的Q输出端处的电平与所述的第二脉冲信号的电平相同。
一种可能的设计中，所述像素还包括动态视觉测量电路；所述动态视觉测量电路与所述光电转换电路耦合，以及与图像信号处理器耦合。所述动态视觉测量电路可以基于所述第一电流，生成指示电平信号，并将所述指示电平信号发送给所述图像信号处理器，所述指示电平信号表征所述入射光的光强度变化信息。
本申请实施例提供的像素可以提供还可以提供入射光的强度信息、入射光的光强度变化信息以及入射光的飞行时间信息。像素具有多种功能，有利于图像传感器可以服务于更多的应用场景中。
一种可能的设计中，所述像素还包括电流镜电路。所述复合测量电路通过所述电流镜电路与所述光电转换电路耦合。所述电流镜电路可以用于向所述复合测量电路提供所述光电转换电路生成的所述第一电流。这样的设计中，复用第一电流提供给动态视觉测量电路和复合测量电路，使两个电路可以同步工作。并且增加动态视觉电路与复合测量电路之间的隔离度，减少复合测量电路与动态视觉测量电路之间的相互影响。
一种可能的设计中，所述光电转换电路包括光电二极管。其中所述光电二极管的阳极与第一电源电平耦合；所述光电二极管的阴极与所述复合测量电路耦合，以及与第二电源电平耦合。所述第二电源电平大于所述第一电源电平。
一种可能的设计中，第一电源电平的电压小于零，这样的设计可以增加光电二极管的电流增益，使像素在较暗的环境中能够正常工作。一些应用场景中，通过选择不同吸收波长的材料作为光电二极管，使得像素可以对各波段的入射光进行处理。
第二方面，本申请实施例还提供一种图像传感器，可以包括多个像素的阵列，其中至少一个像素为如第一方面中任一可能的设计中国的像素。
一种可能的设计中，图像传感器还可以包括图像信号处理器。述图像信号处理器与所述复合测量电路耦合。所述图像信号处理器可以控制目标像素处于第一工作模式，所述目 标像素为所述至少一个像素中的任意一个像素；接收第一脉冲信号，根据所述第一脉冲信号的频率确定入射在所述目标像素上的入射光的强度信息。
一种可能的设计中，所述图像信号处理器，还用于：控制所述目标像素处于第二工作模式，按照预设的多个相位，依次向目标像素发送所述多个相位对应的多个采样信号，其中，所述多个相位与所述多个采样信号一一对应；接收多个第二脉冲信号，所述多个采样信号与所述多个第二脉冲信号一一对应；根据所述多个第二脉冲信号中每个第二脉冲信号，确定入射在所述目标像素上的入射光的相位与设定相位之间的相位偏移量，其中，所述入射光是所述设定相位的光线入射到目标对象反射的。
一种可能的设计中，图像信号处理器可以确定所述每个第二脉冲信号对应的数量，其中，所述每个第二脉冲信号对应的数量为预设时长内，所述每个第二脉冲信号中上升沿的数量；基于所述多个第二脉冲信号对应的数量，确定所述相位偏移量；根据所述相位偏移量，确定所述目标像素与所述目标对象之间的距离。
上述第二方面可以达到的技术效果可以参照上述第一方面及第一方面中任一可能的设计可以达到的技术效果说明，重复之处不予论述。
附图说明
图1示出一种像素的结构示意图；
图2示出一种像素的具体结构示意图；
图3示出一种像素中复合测量电路的具体结构示意图；
图4示出一种比较器的具体结构示意图；
图5示出一种D锁存器的具体结构示意图；
图6示根据一示例性实施例示出的采样信号的示意图；
图7示出一种RS锁存器的具体结构示意图；
图8示出另一种像素的结构示意图；
图9示出一种动态视觉测量电路的结构示意图；
图10示出一种动态视觉测量电路的具体结构示意图；
图11示出一种动态视觉测量电路中应答电路的具体结构示意图；
图12示出一种像素电路的具体结构示意图；
图13示出一种图像传感器的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或 暗示顺序。
需要指出的是，本申请实施例中“耦合”可以理解为电连接，两个电学元件耦合可以是两个电学元件之间的直接或间接耦合。例如，A与B连接，既可以是A与B直接耦合，也可以是A与B之间通过一个或多个其它电学元件间接耦合，例如A与B耦合，也可以是A与C直接耦合，C与B直接耦合，A与B之间通过C实现了耦合。在一些场景下，“耦合”也可以理解为连接。总之，A与B之间耦合，可以使A与B之间能够传输电能。
需要指出的是，本申请实施例中的开关管和开关可以是继电器、金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)，双极结型管(bipolar junction transistor，BJT)，绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)等多种类型的开关管中的一种或多种，本申请实施例对此不再一一列举。每个开关管皆可以包括第一电极(或者第一端)、第二电极(或者第二端)和控制电极(或者称为控制端)，其中，控制电极用于控制开关管的导通或断开。当开关管导通时，开关管的第一电极和第二电极之间可以传输电流，当开关管断开时，开关管的第一电极和第二电极之间无法传输电流。以MOSFET为例，开关管的控制电极为栅极，开关管的第一电极可以是开关管的源极，第二电极可以是开关管的漏极，或者，第一电极可以是开关管的漏极，第二电极可以是开关管的源极。
一些情形中，开关管在高电平的驱动下导通，开关管在低电平驱动下断路。另一些情形中，开关管在低电平的驱动下导通，在低电平驱动下断路。本申请实施例对此不作过多限定。下面以开关管在高电平驱动下导通，在低电平驱动下断路作为举例进行介绍。应理解的是，高电平和低电平为相对概念，高电平的电平水平(电压值)大于低电平的电平水平，在数字电路中通常用1表征高电平，0表征低电平。对于电路中不同元器件来说，高电平的电平水平可以相同，也可以不同。便于介绍，在本申请实施例中，高电平可为1.8V，低电平为0V。
下面结合附图对本申请提供的图像传感器的像素(或称像素电路)进行介绍，请参见图1，本申请实施例提供一种图像传感器的像素，可以与图像信号处理器耦合。所述像素可以包括光电转换电路和复合测量电路。像素可以用于对入射到像素的光转换成对应的电信号。复合测量电路可以与光电转换电路耦合。光电转换电路可以基于入射在像素上的入射光，生成第一电流。可选的，该第一电流还可以称为光电流，也即光电转换电路将入射光转换成的对应的电流。
本申请实施例提供的像素具有多个工作模式，分别对应复合测量电路的多种工作模式。或者说，本申请实施例提供的像素中的复合测量电路具有多个工作模式，以实现像素的多种功能。可选的，复合测量电路可以在图像信号处理器的驱动下切换工作模式。复合测量电路可以接收到来自光电转换电路的光电流，然后可以基于光电流，检测入射光的二维信息(如入射光的强度信息)或者三维信息(如入射光的飞行时间信息)。
例如，像素在第一工作模式下，复合测量电流用于检测入射光的强度信息。像素在第二工作模式下，复合测量电路可以用于检测入射光的飞行时间信息。下面对在像素不同工作模式下复合测量电路的工作过程分别进行介绍。
复合测量电路可以在所述像素工作在第一工作模式时，基于所述第一电流，生成第一脉冲信号，所述第一脉冲信号表征所述入射光的强度信息，可以实现像素检测入射光的二维信息。例如，图像信号处理器可以控制所述复合测量电路工作在第一工作模式。图像信 号处理器可以向复合测量电路发送第一工作模式控制信号。复合测量电路可以响应于第一工作模式控制信号，基于所述第一电流，生成第一脉冲信号。
复合测量电路可以在所述像素工作在第二工作模式时，接收多个采样信号，基于所述第一电流和所述多个采样信号后，生成多个第二脉冲信号。所述多个采样信号与所述多个第二脉冲信号一一对应，所述多个第二脉冲信号用于表征所述入射光的相位与设定相位之间的相位偏移量，所述入射光是所述设定相位的光线入射到目标对象反射的。从而实现像素检测入射光的三维信息。本申请实施例中，复合测量电流检测入射光的三维信息(也即飞行时间信息)可以为入射光的相位与主动光源的相位之间的相位偏移。例如，图像信号处理器可以向复合测量电路发送第二工作模式控制信号，第二工作模式控制信号可以包括多个采样信号，其中，多个采样信号均为周期信号，且多个采样信号的相位不同。图像信号处理器可以依次向复合测量电路发送采样信号，复合测量电路可以响应于接收的每个采样信号，基于第一电流和接收的该采样信号，生成该采样信号对应的第二脉冲信号。复合测量电路生成的各采样信号对应的第二脉冲信号，可以表征入射光的相位与设定相位(如主动光源的相位)之间的相位偏移量。图像传感器应用在检测三维信息场景中，由主动光源发射的光经待测对象反射后，入射到图像传感器的像素中。主动光源的频率是预先配置的，图像信号处理器可以预先获取到主动光源的频率。
下面简单对图像信号处理器可以利用相位偏移量确定像素与待测对象之间距离的过程进行简单介绍。以正弦波调制主动光源作为举例。主动光源可记为r(t)＝coswt。其中w为前述设定的相位。所述入射光为主动光源入射到目标对象反射后的光线是延迟的，入射光可以记为其中，为入射光的相位与主动光源的相位偏移。
在一种实施方式中，图像信号处理器可以基于预设的相位偏移与距离的关系确定检测到的相位偏移量对应的距离。其中，该关系可以表示为：其中c为光速，fmod为主动光源的频率。
在另一种实施方式中，图像信号处理器可以基于预设的相位偏移与距离的关系确定检测到的相位偏移量对应的距离。其中，该关系表示为：其中，c为光速，fmod为主动光源的频率，k为折射率。
下面结合像素结构，对像素的多个工作模式进行详细介绍。在一种实施方式中，光电转换电路可以包括光电二极管(PD)。光电二极管(PD)可以设置在第一电源电平和第二电源电平之间，第二电源电平大于所述第一电源电平。一种可能的实施方式中，请参见图2，光电二极管(PD)的阴极与第二电源电平(VDD1)耦合。光电二极管(PD)的阳极耦合至第一电源电平(VSS)，光电二极管(PD)的阴极与复合测量电路耦合。可选的，第二电源电平(VDD1)可以为3.3V。第一电源电平(VSS)可以小于零，也即小于接地电平。这样的设计可以提升光电转换电路的电流增益。
在一种实施方式中，请再参见图2，复合测量电路可以包括配置信号接收单元、积分单元、比较单元以及延时采样单元。所述配置信号接收单元的第一端与光电转换电路耦合，如所述光电二极管(PD)的阴极耦合。所述配置信号接收单元的第二端与所述积分单元的 第一端耦合，以及与所述比较单元的输入端耦合。
所述像素在所述第一工作模式下时，所述配置信号接收单元可以接收所述第一工作模式控制信号，将所述光电转换电路与所述积分单元之间导通，实现所述配置信号接收单元接收第一电流，并将第一电流输出至积分单元。
所述像素在所述第二工作模式下时，所述配置信号单元可以接收各采样信号，并基于该采样信号的信号周期，周期性地将所述光电转换电路与所述积分单元之间导通，实现所述配置信号接收单元周期性地将所述第一电流输出至所述积分单元。
如图2所示，所述积分单元的第一端与所述配置信号接收单元的第二端耦合，所述积分单元的第一端与比较单元耦合，所述积分单元的第二端与第一电平(VQ)耦合。其中，第一电平(VQ)可以为固定电压。可选的，第一电平(VQ)可以为接地电平，或者说所述积分单元的第二端可以接地。所述积分单元可以接收所述配置信号接收单元输出的第一电流。所述积分单元可以用于对接收到第一电流积分，得到测量电压，并向比较单元提供测量电压。如图2中示出节点VD。该节点VD可以为配置信号接收单元的第二端与比较单元之间的任意一个点。所述积分单元对第一电流进行积分，可以改变节点VD处的电压，节点VD处的电压为前述测量电压。
如图2所示，所述比较单元的输入端可以与所述积分单元的第一端耦合，所述比较单元的输出端可以与延时采样单元耦合。所述比较单元可以接收所述测量电压，并将测量电压与预设的参考电压进行比较，将比较结果信号输出至(发送至)延时采样单元。比较单元可以在测量电压小于参考电平时，输出比较结果信号的电平为第二电平。在所述测量电压大于或等于参考电平时，输出比较结果的信号的电平为第三电平，其中，第二电平大于所述第三电平。
比较单元输出的比较结果信号为模拟信号，便于区分将比较单元输出的信号记为第一模拟信号。通过上述介绍可见所述第一模拟信号中在所述测量电压小于所述参考电压的时段内的电平为第二电平，在所述测量电压大于或等于所述参考电压的时段内的电平为第三电平。
所述延时采样单元与所述比较单元的输出端耦合，所述延时采样单元与所述图像信号处理器耦合。延时采样单元可以对比较单元输出的信号进行延时采样处理，生成所述第一脉冲信号，或者所述第二脉冲信号。所述延时采样单元可以接收图像信号处理器提供的第一时钟信号(clk)，基于第一时钟信号(clk)对比较单元输出的信号进行采样。延时采样单元可以将模拟信号转换为数字信号，在给定周期内，延时采样单元输出一个脉冲。这样的设计可以满足图像信号处理器对时间的要求。
所述像素工作在第一工作模式时，延时采样单元基于第一时钟信号(clk)对比较单元输出的信号进行采样后，得到的脉冲信号为前述第一脉冲信号。所述像素工作在第二工作模式时，延时采样单元基于第一时钟信号(clk)对比较单元输出的信号进行采样后，得到的脉冲信号为前述第二脉冲信号。
一种可能的实施方式中，请参见图3，配置信号接收单元可以包括第一开关(Q1)和第二开关(Q2)。所述第一开关(Q1)的第一端与第三电源电平(DR)，所述第一开关(Q1)的第二端与所述光电二极管(PD)的阳极耦合，所述第一开关(Q1)的第二端与所述第二开关(Q2)的第一端耦合。第一开关(Q1)的控制端与图像信号处理器耦合。所述第二开关(Q2)的第二端与所述积分单元的第一端耦合。所述第二开关(Q2)的控制端与图像 信号处理器耦合。
在一种实施方式中，继续参见图3所示，所述积分单元可以包括积分器件。一些示例中，积分单元可以包括第一电容(CD)。所述第一电容(CD)的第一极与所述光电转换电路耦合，所述第一电路(CD)的第二极接地。如第一电容(CD)的第一极通过第二开关(Q2)与所述光电二极管(PD)的阳极耦合。第二开关(Q2)处于导通状态时，可以将所述光电二极管(PD)的阳极与第一电容(CD)的第一极之间连通。第二开关(Q2)处于断路状态时，可以将所述光电二极管(PD)的阳极与第一电容(CD)的第一极之间断开。第一电容(CD)的第一极可以实施为积分单元的第一端，第一电容(CD)的第二极可以实施为积分单元的第二端。
在一种实施方式中，继续参见图3所示，所述比较单元包括第一比较器。所述第一比较器的第一输入端与所述积分单元的第一端耦合，所述第一比较器的第二输入端接收参考电平(VREF)，所述第一比较器的输出端用于输出所述第一模拟信号。第一比较器可以为任意一种可以实现上述比较单元功能的比较器。图4根据一示例性实施例示出一种第一比较器的电路结构图，其中第一比较器的电源电平VDD的电压可以为1.8V。图4中示出的Vin端子可为第一比较器的输入端，可以与第一电容(CD)的第一极耦合。Vref端子与参考电平耦合。Vb端子耦合固定电压。Vcomp端子为第一比较器的输出端。
一种可能的实施方式中，继续参见图3所示，所述延时采样单元可以包括D锁存器和或非门电路。本申请实施例中，D锁存器可以为任意一种D锁存器。D锁存器通常具有数据输入端(D)、时序控制输入端(EN)，Q输出端。其中，EN为高电平时，则Q输出端的电平随着数据输入端(D)的电平改变；时序控制输入端(EN)为低电平时，Q输出端电平不改变输出状态。图5示例性的示出一种D锁存器的电路结构图。
所述D锁存器的数据输入端(D)与所述第一比较器的输出端耦合，用于接收所述第一模拟信号。所述D锁存器的时序控制输入端(EN)与所述图像信号处理器耦合，用于接收所述第一时钟信号(clk)。所述或非门电路用于对两路输入信号进行或非处理并，输出处理后的信号。下面对所述或非门电路进行或非处理进行介绍，若两路输入信号均为低电平，则或非门电路输出高电平。若两路输入信号均为高电平(或者两路输入信号分别为高电平和低电平)，则或非门电路输出低电平。
所述或非电路的第一输入端与所述D锁存器的Q输出端耦合，用于向所述或非电路输出信号。所述或非门电路的第二输入端与所述图像信号处理器耦合，用于接收所述第一时钟信号(clk)。或非门电路可以对D锁存器的Q输出端输出的信号以及第一时钟信号(clk)进行或非处理后，可以产生脉冲信号。所述或非门电路的输出端可以与图像信号处理器耦合，输出脉冲信号。其中，所述像素处于第一工作模式下，或非门电路输出所述第一脉冲信号。所述像素处于第二工作模式下，或非门电路输出所述第二脉冲信号。
下面结合图3中示出的像素的具体电路结构，对像素在第一工作模式下复合测量电路的工作过程进行介绍。图像信号处理器可以向复合测量电路发送的第一工作模式控制信号，第一工作模式控制信号可以包括第一驱动信号和第二驱动信号。配置信号接收单元中，第一开关(Q1)的控制端用于接收第一驱动信号，第二开关(Q2)的控制端用于接收第二驱动信号。其中，第一驱动信号和第二驱动信号均为固定电平信号。第一驱动信号可以驱动第一开关(Q1)处于断路状态，第二驱动信号可以驱动第二开关(Q2)处于导通状态。从而光电二极管(PD)产生的第一电流(I)可以经由第二开关(Q2)传输至第一电容(CD) 的第一极处。
配置信号接收单元可以在第一驱动信号和第二驱动信号的控制下，保持将光电转换电路与积分单元连通，可使第一电流持续输入积分单元。第一电容(CD)可以为积分电容器。第一电容(CD)的第一极与光电二极管(PD)的阴极之间连通时，第一电容(CD)对第一电流(I)积分，节点VD处的电压(VFD)发生变化，便于介绍将节点VD记为积分节点。第一电容(CD)对第一电流(I)积分，实际也是第一电流(I)对第一电容(CD)充电。
积分节点的初始电压可以与接地的电平相同，此时第一比较器输出比较结果信号的电平为第二电平。配置信号接收单元将第一电流输出至积分单元时，第一电容(CD)对第一电流进行积分。第一电容(CD)对第一电流积分时，积分节点处的电压(VFD)增大。积分节点处的电平增大至参考电压时，第一比较器输出比较结果信号的电平为第三电平。经过一段延迟时间后，积分节点处的电压(VFD)被复位为初始电平，便于第一电容(CD)开始新的积分过程。此时第一比较器输出比较结果信号的电平变为第二电平。本申请实施例中，第一比较器输出低电平可视为第一比较器产生复位有效电平。可见，在第一电容(CD)的一次积分过程中，积分节点处的电压(VFD)从初始电压增大到参考电平，第一比较器输出低电平，积分节点处的电压(VFD)复位到初始电压后，第一比较器输出高电平，因而第一比较器会产生一次脉冲。在固定时间内第一比较器输出的脉冲的数量，也即第一比较器输出的脉冲的频率。第一比较器输出脉冲的频率可以表征入射光的强度信息。图像信号处理器可以利用第一比较器输出的脉冲频率编码入射光的强度信息。由于复合测量电路在第一工作模式下输出一个第一脉冲信号，因此灰度数据只有1比特。
本申请实施例提供的像素中，入射光的光强越大，产生的第一电流越大，第一电容(CD)在初始电平与参考电平之间的积分时间越短。那么一定时间内第一比较器产生复位有效电平(也即产生脉冲)的频率越高。图像信号处理器可以统计在固定时间内，第一比较器输出的有效复位电平的次数。该次数可以表征入射光的光强信息，也即入射光的强度信息。这样在频率域检测光的强度的方式也可以称为灰度脉冲成像技术。
下面结合图3中示出的像素的具体电路结构，对像素在第二工作模式下复合测量电路的工作过程进行介绍。图像信号处理器可以向复合测量电路发送的第二工作模式控制信号，第二工作模式控制信号可以包括第三驱动信号和第四驱动信号。配置信号接收单元中，第一开关(Q1)的控制端用于接收第三驱动信号，第二开关(Q2)的控制端用于接收第四驱动信号。所述第三驱动信号用于驱动所述第一开关(Q1)，所述第四驱动信号用于驱动所述第二开关(Q2)。其中，所述第三驱动信号和所述第四驱动信号均为周期性信号。所述第二开关(Q2)处于导通状态时，所述第一开关(Q1)处于断路状态，所述第一开关(Q1)处于导通状态时，所述第二开关(Q2)处于断路状态。一些示例中，第三驱动信号和第四驱动信号可以是一对反相的时钟信号。
图像信号处理器向复合测量电路提供的第三驱动信号和第四驱动信号均为周期性的方波信号，且频率与主动光源的频率相同。在第三驱动信号的驱动下，第一开关(Q1)可以周期性地处于导通状态。在第四驱动信号的驱动下，第二开关(Q2)可以周期性地处于导通状态。第二开关(Q2)导通，第一开关(Q1)断路，第一电流(I)传输至积分节点。第二开关(Q2)断路，第一开关(Q1)导通，第一电流全部传输至DR。在第四驱动信号的驱动下第二开关(Q2)在导通状态和断路状态之间交替，具有门控作用。第四驱动信号可以为前述采样信号，记为g(t)。采样信号g(t)可以驱动第二开关(Q2)交替处于导通状 态和断路状态。图6中的(a)示例性的示出一个周期T对应的时长中采样信号的波形，其中k0和T均为预先配置的常数。例如，一个周期中，在-k0/2<t<k0/2时，若光电转换电路产生第一电流，则第二开关(Q2)可以将第一电流传输到第一电容(CD)处。而在一个周期T内的其它时刻，若光电转换电路产生第一电流，则第二开关(Q2)不会将第一电流传输到第一电容(CD)处。需要说明的是，图6中的(a)所述示出的采样信号g(t)用于举例说明第二开关(Q2)在第四驱动信号的控制下起到的门控作用，并不作为对采样信号的具体限定。在实际应用场景中，采样信号为周期性的信号，并且在各周期中，采样信号中的电平由低电平转换为高电平的时刻(本申请中称为采样信号的相位)是可调节的。
如图6中的(b)所示，主动光信号被目标对象反射后的光，入射到像素中。入射到像素中的光信号记为入射光信号。入射光信号相对于主动光信号来说，入射光信号的频率未发生改变，与主动光信号的频率相同。入射光信号的相位和幅值可能发生改变，可能与主动光信号的相位和幅值不同。第四驱动信号为驱动第二开关(Q2)的控制信号，第四驱动信号中高电平的时段为在第二开关(Q2)处于导通状态的时段。第四驱动信号中低电平的时段为第二开关(Q2)处于断路状态的时段。第二开关(Q2)在第四驱动信号的控制下，具有门控作用。第一电流(I)仅可以在第二开关(Q2)处于导通状态时，传输至第一电容(CD)处，对第一电容(CD)充电，使第一电容(CD)处存有光电子，实现第一电容(CD)对第一电流积分。图6中的(b)的阴影部分为第一电流传输至第一电容(CD)对应的时段。
在预设数量的周期(如第四驱动信号的周期T)内，第一电容(CD)在每个周期内对第一电流进行积分，第一比较器输出的脉冲的总数量表征预设数量个周期(如数百个周期)内对应的时间内第一电流的积分值。
图像信号处理器可以调整第四驱动信号的相位，也即图像信号处理器可以提供多种相位组合的第四驱动信号，例如提供四种相位组合，且四种相位组合中任意两个相位正交。
其中，第四驱动信号可以为前述采样信号。图像信号处理器向第二开关(Q2)提供采样信号，驱动第二开关(Q2)在导通状态和断路状态之间交替。第二开关(Q2)处于导通状态时，第一电流传输至积分电容(CD)，第二开关(Q2)处于断路状态时，第一电流不能传输至积分电容(CD)。在采样信号的控制下，第二开关(Q2)处于导通状态，使积分电容对第一电流积分。此过程，可实现采样信号g(t)与入射光信号s(t)的互相关处理，处理后的信号可用C(τ)表示，其数学表达式为： k0为预先配置的常数。
图像信号处理器提供的多个采样信号中各采样信号的相位不同。请参见图6中的(c)，下面以多个采样信号分别为g0(t)、g1(t)、g2(t)、g3(t)作为举例进行介绍。g0(t)、g1(t)、g2(t)、g3(t)的相位可以分别为0、π、图像信号处理器分时地向第二开关(Q2)提供各采样信号。如图6中的(c)所示，假设入射光信号为相位为不同相位的采样信号起到的门控作用不同。如在一个周期T中，采样信号g0(t)波形的阴影部分的时段内第二开关(Q2)将第一电流传输到第一电容(CD)处，第二开关(Q2)传输第一电流的时长为采样信号g1(t)波形的阴影部分的时段内第二开关(Q2)将第一电 流传输到第一电容(CD)处，第二开关(Q2)传输第一电流的时长为采样信号g2(t)波形的阴影部分的时段内第二开关(Q2)将第一电流传输到第一电容(CD)处，第二开关(Q2)传输第一电流的时长为采样信号g3(t)对第二开关(Q2)控制下，第二开关(Q2)传输第一电流的时长为0。
在中，当采样信号为g0(t)时，采样信号为g0(t)与入射光信号s(t)的互相关函数值采样信号为g1(t)时，采样信号为g1(t)与入射光信号s(t)的互相关函数值采样信号为g2(t)时，采样信号为g2(t)与入射光信号s(t)的互相关函数值 采样信号为g3(t)时，采样信号为g3(t)与入射光信号s(t)的互相关函数值
当输入采样信号g0(t)时，第二开关(Q2)在采样信号g0(t)的控制下周期性的处于导通状态，第一比较器输出采样信号g0(t)对应的第二脉冲信号，其中，在预设数量个周期(采样信号的周期)的时长内，采样信号g0(t)对应的第二脉冲信号中脉冲的总数量(上升沿的总数量)表征采样信号g0(t)对应的互相关函数值C0，也是采样信号g0(t)的相位对应的互相关函数值C0。
类似地，当输入采样信号g1(t)时，第二开关(Q2)在采样信号g1(t)的控制下周期性的处于导通状态，第一比较器输出采样信号g1(t)对应的第二脉冲信号，其中，在预设数量个周期(采样信号的周期)的时长内，采样信号g1(t)对应的第二脉冲信号中脉冲的总数量(上升沿的总数量)表征采样信号g1(t)对应的互相关函数值C1，也是采样信号g1(t)的相位对应的互相关函数值C1。
类似地，当输入采样信号g2(t)时，第二开关(Q2)在采样信号g2(t)的控制下周期性的处于导通状态，第一比较器输出采样信号g2(t)对应的第二脉冲信号，其中，在预设数量个周期(采样信号的周期)的时长内，采样信号g2(t)对应的第二脉冲信号中脉冲的总数量(上升沿的总数量)表征采样信号g2(t)对应的互相关函数值C2，也是采样信号g2(t)的相位对应的互相关函数值C2。
类似地，当输入采样信号g3(t)时，第二开关(Q2)在采样信号g3(t)的控制下周期性的处于导通状态，第一比较器输出采样信号g3(t)对应的第二脉冲信号，其中，在预设数量个周期(采样信号的周期)的时长内，采样信号g3(t)对应的第二脉冲信号中脉冲 的总数量(上升沿的总数量)表征采样信号g3(t)对应的互相关函数值C3，也是采样信号g3(t)的相位对应的互相关函数值C3。
图像信号处理器可以根据接收到的各采样信号对应的第二脉冲信号，确定出各采样信号对应的互相关函数值。并根据采样信号对应的互相关函数值确定相位偏移，其中，
请再参见图2，为了便于对积分节点处的电压进行复位，复合测量电路还可以包括复位开关(MRST)，所述复位开关(MRST)的第一端接地，第二端与所述积分单元的第一端耦合。复位开关(MRST)的控制端与所述延时采样单元的输出端。请结合图3，复位开关(MRST)的第二端可以与第一电容(CD)的第一极耦合，复位开关(MRST)的控制端可以与所述或非门电路的输出端耦合。复位开关(MRST)可以在延时采样单元输出的脉冲信号控制下，在导通状态和断路状态之间交替。其中复位开关(MRST)处于导通状态，可使所述积分单元的第一端的电压复位为初始电压，也即0V。或者说复位开关(MRST)处于导通装填可以使积分节点处的电压(VFD)复位为初始电压。
例如，D锁存器可以在第一时钟信号(clk)中的高电平沿(上升沿)采样第一比较器产生的第一模拟信号中的下降沿(或称负脉冲，也即高电平跳变为低电平的沿)时，Q输出端输出电平为低电平。在第一时钟信号(clk)的低电平时段内，且Q输出端输出信号为低电平时，或非门电路输出的第一脉冲信号的电平为高电平，可以驱动复位开关(MRST)处于导通，使积分节点处的电平复位，恢复为初始电平，如0V。
一种可能的设计中，请再参见图2，复合测量电路还可以包括读出单元。所述读出单元与所述延时采样单元耦合，以及与所述图像信号处理器耦合。所述读出单元可以在所述图像信号处理器提供存储信号(clr＝0)的驱动下，缓存延时采样单元输出的信号，如所述第一脉冲信号或者所述第二脉冲信号。在所述图像信号处理器提供的选择信号(sel)的驱动下，通过读出单元的输出端(out)向所述图像信号处理器输出缓存的信号；或者在所述图像信号处理器提供复位信号(clr＝1)的驱动下，对向所述图像信号处理器输出信号复位。
一些示例中，请参见图3，读出单元可以包括第三开关(Q3)、第四开关(Q4)以及RS锁存器。其中，所述第三开关(Q3)的第一端可以读出单元的输出端(out)与所述图像信号处理器耦合。或者所述第三开关(Q3)的第一端可以作为读出单元的输出端(out)。所述第三开关(Q3)的第二端与所述第四开关(Q4)的第一极耦合，所述第三开关(Q3)的控制端用于接收所述选择信号(sel)，所述选择信号用于驱动所述第三开关(Q3)处于导通状态。所述第四开关(Q4)的第二极接地，所述第四开关(Q4)的控制端与所述第RS锁存器的Q输出端耦合。所述RS锁存器的复位端(R)与所述图像信号处理器耦合，可以用于接收所述存储信号或者所述复位信号(clr＝1)，所述RS锁存器的置位端(S)与所述或非门电路的输出端耦合，用于接收所述第一脉冲信号或者所述第二脉冲信号。
RS锁存器具有记录电平的功能。图像信号处理器可以向RS锁存器的复位端(R)提供存储信号，驱动RS锁存器的记录电平功能。存储信号可以为固定电平信号，存储信号(clr＝0)的电平水平可以为低电平(0)，使RS锁存器可以锁存置位端(S)处信号(也即第一脉冲信号)正脉冲(上升沿)的电平。置位端(S)处电平为由低电平变为高电平时，RS锁存器锁存置位端(S)的电平，RS锁存器的Q输出端的电平状态为高电平，并保持 输出高电平。
图像信号处理器可以向RS锁存器的复位端(R)提供复位信号，驱动RS锁存器复位，使RS锁存器初始输出为0。复位信号可以为固定电平信号，复位信号(clr＝1)的电平水平可以为高电平(1)，使RS锁存器的输出电平状态为低电平，便于图像信号处理器向RS锁存器发送存储信号时，RS锁存器可以记录电平。图7根据一示例性实施例示出一种RS锁存器的电路图。
第四开关(Q4)的控制端与RS锁存器的Q输出端耦合。RS锁存器的Q输出端输出高电平，可驱动第四开关(Q4)导通。RS锁存器的Q输出端输出低电平，可驱动第四开关(Q4)断路。从而，RS锁存器记录所述第一脉冲信号的高电平后，第四开关(Q4)导通。
图像信号处理器向第三开关(Q3)提供选择信号(sel)，使得第三开关(Q3)在选择信号(sel)的驱动下，处于导通状态，可使第四开关(Q4)与图像信号处理器之间连通。第四开关(Q4)可以耦合总线上拉电阻。
若第三开关(Q3)在选择信号(sel)的驱动下处于导通状态，在第四开关(Q4)导通时，则第三开关(Q3)的第一端(也可以视为像素的输出端)有电平输出。在第四开关(Q4)断路时，则第三开关(Q3)的第一端无电平输出。若图像信号处理器未向第三开关(Q3)提供选择信号(sel)，则第三开关(Q3)处于断路状态，第三开关(Q3)的第一端无电平输出。
在第一工作模式下，本申请实施例提供的像素可以提供光强变化的信息。然而，当被测对象的位置或者对象的状态发生变化后，入射到像素的光的强度也相应发生变化。基于此，一种可能的实施方式中，本申请实施例提供的像素还可以包括动态视觉测量电路。请参见图8，所述动态视觉测量电路可以与所述光电转换电路耦合，动态视觉测量电路可以基于所述光电转换电路生成的第一电流，向所述图像信号处理器提供所述入射光的光强度变化的信息。动态视觉测量电路可以对入射光的光强进行对数域的压缩，感知被测对象的变化，即指感知变化剧烈的像点。
请再参见图8，本申请实施例还可以包括电流镜电路。所述复合测量电路通过所述电流镜电路与所述光电转换电路耦合。所述电流镜电路可以向所述复合测量电路提供所述光电转换电路生成的电流。这样的设计可以实现光电转换电路生成的第一电流分别被两种电路同时使用，也即复合测量电路和动态视觉测量电路。并且电流镜电路可以增加所述复合测量电路与所述动态视觉测量电路之间的隔离度，减少复合测量电路与动态视觉测量电路之间的影响。
一种可能的实施方式中，请参见图9，所述动态视觉测量电路可以包括光接收级、驱动级、放大级、比较级以及应答电路。光接收级可以将第一电流转化到对数域。一些示例中，请参见图10，光接收级包括第五开关(M1)、第六开关(M2)和第七开关(M3)。其中，第五开关(M1)的第一端与光电二极管的阴极耦合，第五开关(M1)的第二端与电流镜电路耦合。第五开关(M1)的控制端与第六开关(M2)的第一端耦合，第六开关(M2)的第二端与第四电源电平(VDD2)耦合。示例性的，第四电源电平(VDD2)的电压可以为1.8V。第六开关(M2)的控制端耦合预设的固定电平(Vb1)。第七开关(M3)的第一端与第五开关(M1)的控制端耦合，以及与第六开关(M2)的第一端耦合。第七开关(M3)的第二端接地，第七开关(M3)的控制端与光电二极管(PD)的阴极耦合。光接收级的 输出端也即第六开关(M2)的第一端，在负反馈的作用下，光接收级的输出端虚地，第五开关(M1)的亚阈值区特性使得光接收级的输出端处电压(VQ)与第一电流I之间具有对数关系，如lnI。
驱动级可以增加放大级与光接收级之间的隔离度，驱动级用于将对数域的第一电流提供给放大级。一些示例中，请参见图10，驱动级(也可称为源跟随级)可以包括第八开关(M4)和第九开关(M5)。其中，第八开关(M4)的第一端与第四电源电平(VDD2)耦合，第八开关(M4)的第二端与第九开关(M5)的第一端耦合。第八开关(M4)的控制端与预设的固定电平(Vb3)耦合。第九开关(M5)的第二端接地，第九开关(M5)的控制端与第五开关(M1)的控制端耦合。
放大级可以包括电容反馈电路，用于将变化的小信号放大。一些示例中，请参见图10，放大级可以包括第二电容(C1)、第三电容(C2)、第十开关(M6)、第十一开关(M7)和第十二开关(M8)。其中，第二电容(C1)的第一极与第八开关(M4)的第二端耦合，第二电容(C1)的第二极与第三电容(C2)的第一极耦合，第二电容(C1)的第二极与第十开关(M6)的第一端耦合，第二电容(C1)的第二极与第十一开关(M7)的控制端耦合。
第十开关(M6)的第二端与第三电容(C2)的第二极耦合，第十开关(M6)的第二端与第十一开关(M7)的第一端耦合，第十开关(M6)的第二端与第十二开关(M8)的第一端耦合。第十开关(M6)的控制端与图像信号处理器耦合，接收放大控制信号(RST_N)。其中，放大控制信号(RST_N)可由应动态视觉测量电路中的应答电路提供。第十一开关(M7)的第二端与所述第四电源电平(VDD2)耦合。第十二开关(M8)的第二端接地，第十二开关(M8)的控制端接收固定电平VO。
第二电容(C1)、第三电容(C2)、第十开关(M6)、第十一开关(M7)和第十二开关(M8)形成的电容反馈电路将变化的小信号放大C1/C2倍，并叠加在复位的直流偏置电压上，改变第三电容(C2)的第二极的电压。第三电容(C2)的第二极也可以作为放大级的输出端(VC)。
一些示例中，请参见图10，比较级可以包括第十三开关(M9)、第十四开关(M10)、第十五开关(M11)以及第十六开关(M12)。第十三开关(M9)的第一端与第二电源电平耦合，第十三开关(M9)的第二端与第十四开关(M10)的第一端耦合，第十三开关(M9)的控制端与第三电容(C2)的第二极耦合。第十四开关(M10)的第二端接地，第十四开关(M10)的控制端接收固定电平VN。其中，第十三开关(M9)的第二端为比较级的第一输出端ON。
第十五开关(M11)的第一端与第二电源电平耦合，第十五开关(M11)的第二端与第十六开关(M12)的第一端耦合，第十五开关(M11)的控制端与第三电容(C2)的第二极耦合。第十六开关(M12)的第二端接地，第十六开关(M12)的控制端接收固定电平VP。其中，第十五开关(M11)的第二端为比较级的第二输出端OFF。
可选的，第十一开关(M7)、第十三开关(M9)、第十五开关(M11)为相同尺寸的PMOS管。第十二开关(M8)、第十四开关(M10)、第十六开关(M12)为相同尺寸的NMOS管。第十四开关(M10)的控制端接收的固定电平VN大于第十二开关(M8)的控制端接收的固定电平VO，第十六开关(M12)的控制端接收的固定电平VP小于第十二开关(M8)的控制端接收的固定电平VO。
放大控制信号(RST_N)为低电平(0)时，第十开关(M6)处于导通状态。放大级的输出端(VC)的电平恢复为预设的复位电平，此时比较级的第一输出端ON输出低电平(0)，第二输出端OFF输出高电平(1)。
当放大级输出端(VC)的电平从复位电平向正的偏移取消固定电平VP和比较阈值BIAS之差所引起的电流源失配时，第二输出端OFF输出低电平(0)。当放大级输出端(VC)的电平从复位电平向负的偏移取消固定电平VN和比较阈值BIAS之差所引起的电流源失配时，第一输出端ON输出高电平(1)。基于此预先设置的比较阈值BIAS、固定电平VP、固定电平VN、固定电平VO，可以实现上述过程。
动态视觉测量电路还可以包括应答电路，应答电路可以接收比较级的第一输出端ON和第二输出端OFF的电平，以及锁存第一输出端ON的电平和第二输出端OFF的电平。应答电路可以基于比较级的第一输出端ON的电平和第二输出端OFF的电平，产生请求信号(REQ)，产生请求信号(REQ)可以表征发生光强变化。例如，比较级的第一输出端ON为高电平(1)，比较级的第二输出端OFF为低电平(0)时，应答电路可以产生请求信号(REQ)，和/或，比较级的第一输出端ON为低电平(0)，比较级的第二输出端OFF为高电平(1)时，比较级的第二输出端OFF为低电平(0)时，应答电路可以产生请求信号(REQ)。
动态视觉测量电路处于初始状态时，比较级的第一输出端ON输出低电平(0)，第二输出端OFF输出高电平(1)。若入射光的第一电流增大，放大级的输出端(VC)的电平变小，比较级的第一输出端ON输出高电平(1)，第二输出端OFF输出高电平(1)。若入射光的第一电流减小，比较级的第一输出端ON输出低电平(0)，第二输出端OFF输出低电平(0)。
应答电路与图像信号处理器耦合，将请求信号(REQ)发送给图像信号处理器。其中在比较级的第一输出端ON的电平由低电平变为高电平时，应答电路向图像信号处理器发送请求信号(REQ)。以及在比较器的第二输出端OFF的电平由高电平变为低电平时，应答电路向图像信号处理器发送请求信号(REQ)，以便图像信号处理器获知发生光强变化事件。当产生动态事件(如光强变化)，加速输出电平的上升或下降。
在一些示例中，应答电路可以包括与非门、或非门、非门等逻辑电路，并采用标准CMOS数字推挽结构，实现上述功能。如图11所示，应答电路可接收比较级的第一输出端ON提供的电平以及接收比较级第二输出端OFF提供的电平。应答电路可以接收图像信号处理器提供的应答信号(ACK)和复位动态测量信号(RST)。复位动态测量信号(RST)可以驱动动态视觉测量电路恢复初始状态，等待下一次变化事件。前述动态视觉测量电路中比较级接中第十开关接收放大控制信号(RST_N)，为复位动态测量信号(RST)的反相信号。
如图11所示，应答电路具有多个输出端，输出端CON和输出端COFF。应答电路初始状态下，输出端CON的电平为低电平(0)，输出端COFF的电平为低电平(0)。当产生动态事件时，若输出端CON的电平为高电平(1)，输出端COFF的电平为低电平(0)时，表征光强发生正变化(也即光强增大)。若输出端CON的电平为低电平(0)，输出端COFF的电平为高电平(1)时，表征光强发生负变化(也即光强减小)。图像信号处理器可以通过输出端CON和输出端COFF的电平情况，确定光强变化情况。
便于介绍，如图11所示，将应答电路中接收复位动态测量信号(RST)的输入端，记为输入端RST。将应答电路中接收应答信号(ACK)的输入端记为输入端ACK。将应答 电路中连接比较级的第一输出端ON的输入端记为输入端ON，将应答电路中连接比较级的第二输出端OFF的输入端记为输入端OFF。
应答电路可以包括多个开关和多个反相器。多个开关分别记为开关S1、开关S2、…、开关S14。多个反相器分别记为反相器NG1、反相器NG2以及反相器NG3。其中，开关S1的第一端与电源电平耦合，开关S1的第二端与开关S2的第一端耦合，开关S1的控制端与输入端RST耦合。开关S2的第二端与输入端ON耦合，以及与开关S3的第一端耦合，开关S2的控制端与反相器NG2的输出端耦合，反相器NG2的输入端与输入端ON耦合。开关S3的第二端接地，开关S3的控制端与输入端RST耦合。反相器NG2的输出端处电平记为NON。
开关S4的第一端与电源电平耦合，开关S4的第二端与开关S5的第一端耦合，且与输入端OFF耦合。反相器NG1的输入端与输入端RST耦合，反相器NG1的输出端与开关S4的控制端耦合。反相器NG1的输出端处电平记为RST_N。开关S5的第二端与开关S6的第一端耦合。反相器NG3的输入端与输入端OFF耦合，反相器NG3的输出端与开关S5的控制端耦合。反相器NG3的输入端处电平记为NOFF。开关S6的第二端接地，开关S6的控制端与反相器NG1的输出端耦合。
开关S7的第一端与输入端ON耦合，开关S7的第二端接地，开关S7的控制端与反相器NG3的输出端耦合。开关S8的第一端与电源电平耦合，开关S8的第二端与输入端OFF耦合，开关S8的控制端与反相器NG2的输出端耦合。
开关S9的第一端与输出端REQ耦合，开关S9的第二端接地，开关S9的控制端与输入端ON耦合。开关S10的第一端与输出端REQ耦合，开关S10的第二端接地，开关S10的控制端与反相器NG3的输出端耦合。
开关S11的第一端接地，开关S11的第二端与开关S12的第一端耦合，开关S11的控制端与输入端ON耦合。开关S12的第二端与输出端CON耦合，开关S12的控制端与输入端ACK耦合。
开关S13的第一端接地，开关S13的第二端与开关S14的第一端耦合，开关S13的控制端与反相器NG3的输出端耦合。开关S14的第二端与输出端COFF耦合，开关S14的控制端与输入端ACK耦合。
开关S13和开关S14可以在输入端ACK接收的应答控制信号的驱动下处于导通状态，使开关S11的第二端与输出端CON连通，以及使开关S13的第二端与输出端COFF连通。若输入端ON处电平可以驱动开关S11导通，则输出端CON输出高电平(1)。若输入端ON处电平不能驱动开关S11导通，则输出端CON输出低电平(0)。
一种可能的实施方式中，如图12所示，电流镜电路可以包括第十七开关(M13)、第十八开关(M14)、第十九开关(M15)、第二十开关(M16)以及开关MBIAS。其中，第十七开关(M13)的第一端与第二电源电平(VDD1)耦合，第十七开关(M13)的第二端与第十八开关(M14)的第一端耦合，第十七开关(M13)的控制端也与第十八开关(M14)的第一端耦合。第十八开关(M14)的第二端与开关MBIAS的第一端耦合，第十八开关(M14)的控制端也与开关MBIAS的第一端耦合。开关MBIAS的第二端与动态视觉测量电路中的第五开关(M1)的第二端耦合，开关MBIAS的控制端与偏置电平BIAS耦合。第十九开关(M15)的第一端与第二电源电平(VDD1)耦合，第十九开关(M15)的第二端与第二十开关(M16)的第一端耦合，第十九开关(M15)的控制端与第十七开关(M13) 的控制端耦合。第二十开关(M16)的第二端与复合测量电路中的第一开关的第二端耦合。第二十开关(M16)的控制端与第十八开关(M14)的控制端耦合。这样的设计中，利用电流镜电路，将第一电流复制到复合测量电路中。并且开关MBIAS可以屏蔽复合测量电路的服务电流对动态视觉测量电路的耦合干扰。
基于上述任意一个实施例提供的像素，本申请实施例还提供一种图像传感器，可以包括多个阵列排列的像素和图像信号处理器。图中正方形表征本申请实施例提供的像素。请参见图13，图像处理器可以包括列选择单元。作为示例，图像传感器可以包括n排m列像素。第n排中的像素的配置信号接收单元中第一开关(Q1)的控制端与列选择单元的第n个第一配置信号端子(TXD)耦合，第n排中的像素的配置信号接收单元中第二开关(Q2)的控制端与列选择单元的第n个第二配置信号端子(TX)耦合。列选择单元的第一配置信号端子用于提供前述第一驱动信号或者第三驱动信号。列选择单元的第二配置信号端子用于提供前述第二驱动信号或者第四驱动信号。第n排中的像素的延时采样单元中D锁存器的时序控制输入端，与列选择单元的第n个时钟信号输出端子耦合。第n排中的像素的延时采样单元中或非门电路的第二输入端，与列选择单元的第n个时钟信号输出端子耦合。列选择单元的时钟信号输出端子用于输出前述第一时钟信号(clk)。第n排中的像素的读出单元的RS锁存器的复位端与列选择单元的第n个复位信号端子耦合。列选择单元的复位信号端子用于输出前述复位信号(clr)。
第m列的像素的读出单元的第三开关(Q3)的第一端，与第m列数据总线耦合，图像信号处理器可以经由第m列灰度数据总线接收第m列中的像素输出的数据。列选择单元的读出信号端子用于输出前述选择信号(sel)。第n排中的像素的读出单元的第三开关(Q3)的控制端与列选择单元的第n个读出信号端子耦合。第n排中的像素在列选择单元的读出信号的驱动下，向各像素所在列耦合的灰度数据总线输出数据。
通过上述介绍可见，第n行中所有像素可以共享列选择单元提供的五种控制信号，分别为选择信号(sel)、复位信号(clr)、第一时钟信号(clk)、第一配置信号端子提供的信号(TXD)、第二配置信号端子提供的信号(TX)。其中，第一配置信号端子提供的信号(TXD)和第二配置信号端子提供的信号(TX)，可以用于配置复合测量电路的工作模式。复合测量电路在完成一次积分过程从阈值电压复位到初始电压后，会输出一次脉冲，在一段固定时间内由第一时钟信号(clk)和选择信号(sel)信号采样多次。每次采样后再用复位信号(clr)清零。计数产生脉冲的频率就可以编码光强的大小。因此像素的灰度数据只有一比特，由列选择单元逐行扫描向上输出脉冲数据OUT。
请再参见图13，一种可能的实施方式中，图像传感器中的每个像素包括动态视觉测量电路。图像信号处理器还可以包括排选择单元(也可称为动态视觉测量同步仲裁器)。其中，第n排中的像素的输入端RST与排选择单元的第n个复位动态测量信号端耦合。排选择单元的复位动态测量信号端用于输出前述复位动态测量信号(RET)。第n排中的像素的输入端ACK与排选择单元的第n个应答控制信号端耦合。排选择单元的应答控制信号端用于输出前述应答控制信号(ACK)。
第n排中的像素的输出端REQ与排选择单元的第n个时间请求信号端耦合，排选择单元的请求信号端耦合用于接收前述请求信号(REQ)。
第m列中的像素的输出端CON通过第一动态事件数据总线与图像处理器耦合，第m列中的像素的输出端COFF通过第二动态事件数据总线与图像处理器耦合。第n排中的像 素在应答控制信号(ACK)的驱动下，向各像素所在列耦合的第一动态事件总线以及第二动态事件总线分别输出光强变化数据。
假设第i行中的像素产生光强变化事件时，向行选择单元(仲裁器)发送请求信号(REQ)，行选择单元(仲裁器)向第i行中的像素发送应答信号(ACK)信号，使得第i行中的像素向第一动态事件总线和第二动态事件总线传输时间的两位数据(像素的输出端CON的电平和输出端COFF的电平)。经过一段延迟时间后，行选择单元(仲裁器)向第i行中的像素发送复位信号(RST)，使得第i行像素中的动态视觉测量电路恢复初始状态等待下次变化时间。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (18)

  1. 一种图像传感器的像素，其特征在于，包括：
    光电转换电路，用于基于入射在所述像素上的入射光，生成第一电流；
    复合测量电路与光电转换电路耦合；
    所述复合测量电路包括配置信号接收单元、积分单元、比较单元、以及延时采样单元；
    所述配置信号接收单元的第一端与所述光电转换电路耦合；所述配置信号接收单元的第二端与所述积分单元的第一端耦合，以及与所述比较单元的输入端耦合；所述配置信号接收单元用于：将所述第一电流输出至所述积分单元；或者接收多个采样信号，基于所述多个采样信号的信号周期，周期性地将所述第一电流输出至所述积分单元；
    所述积分单元的第二端与第一电平耦合，所述积分单元用于对所述第一电流积分得到测量电压，并向所述比较单元提供所述测量电压；
    所述比较单元的输入端与所述积分单元的第一端耦合，用于：将所述测量电压与预设的参考电压进行比较，并将比较结果信号发送至所述延时采样单元，其中，在所述测量电压小于所述参考电平时，所述比较结果信号的电平为第二电平，在所述测量电压大于或等于所述参考电平时，所述比较结果信号的电平为第三电平，所述第二电平大于所述第三电平；
    所述延时采样单元与所述比较单元的输出端耦合；所述延时采样单元用于：对所述比较结果信号进行采样处理，生成第一脉冲信号或者多个第二脉冲信号，所述第一脉冲信号表征所述入射光的强度信息，其中所述多个采样信号与所述多个第二脉冲信号一一对应，所述多个第二脉冲信号用于表征所述入射光的相位与设定相位之间的相位偏移量，所述入射光是所述设定相位的光线入射到目标对象反射的。
  2. 如权利要求1所述的像素，其特征在于，
    当所述像素工作在第一工作模式时，基于所述第一电流，生成所述第一脉冲信号；
    当所述像素工作在第二工作模式时，接收所述多个采样信号，基于所述第一电流和所述多个采样信号，生成所述多个第二脉冲信号。
  3. 如权利要求1或2所述的像素，其特征在于，所述光电转换电路包括光电二极管；
    其中，所述光电二极管的阳极与第一电源电平耦合；所述光电二极管的阴极与所述复合测量电路耦合，以及与第二电源电平耦合；所述第二电源电平大于所述第一电源电平。
  4. 如权利要求1所述的像素，其特征在于，所述配置信号接收单元包括第一开关和第二开关；
    所述第一开关的第一端与第三电源电平耦合，所述第一开关的第二端与所述光电转换电路耦合，所述第一开关的第二端与所述第二开关的第一端耦合，所述第二开关的第二端与所述积分单元的第一端耦合，所述第三电源电平小于所述第二电源电平；
    其中，当所述第一开关处于断路状态，且所述第二开关处于导通状态时，所述第一电流传输至所述积分单元；当所述第一开关处于导通状态，且所述第二开关处于断路状态时，所述第一电流传输至所述第三电源电平。
  5. 如权利要求4所述的像素，其特征在于，在所述第一工作模式下，所述第一开关的控制端接收第一驱动信号，所述第一驱动信号为固定电平信号，用于驱动所述第一开关处于断路状态；
    所述第二开关的控制端接收第二驱动信号，所述第二驱动信号为固定电平信号，用于驱动所述第二开关处于导通状态。
  6. 如权利要求4或5所述的像素，其特征在于，在所述第二工作模式下，所述第一开关的控制端接收第三驱动信号；所述第三驱动信号为周期性信号，所述第一开关用于控制所述第一开关按照所述第三驱动信号的周期，在导通状态和断路状态之间交替；
    所述第二开关的控制端接收所述多个采样信号；其中，任一个采样信号为周期性信号，所述第二开关用于控制所述第二开关按照每个采样信号的周期，在导通状态和断路状态之间交替；
    其中，在所述第二开关处于导通状态时，所述第一开关处于断路状态，在所述第一开关处于导通状态时，所述第二开关处于断路状态。
  7. 如权利要求1-6中任一项所述的像素，其特征在于，所述积分单元包括第一电容；所述第一电容的第一极通过所述第二开关与所述光电转换电路耦合，所述第一电容的第二极与所述第一电平耦合。
  8. 如权利要求1-6中任一项所述的像素，其特征在于，所述比较单元包括比较器；
    所述比较器的第一输入端与所述积分单元的第一端耦合，用于接收所述测量电压；
    所述比较器的第二输入端与所述参考电压耦合；
    所述比较器的输出端与所述延迟采样单元耦合，用于输出所述比较结果信号。
  9. 如权利要求1-8中任一项所述的像素，其特征在于，所述延时采样单元包括D锁存器和或非门电路；
    所述D锁存器的数据输入端与所述比较器的输出端耦合，用于接收所述比较结果信号；
    所述D锁存器的时序控制输入端，用于接收第一时钟信号；
    所述D锁存器的Q输出端与或非电路的第一输入端耦合，用于向所述或非电路输出信号；
    所述或非门电路的第二输入端，用于接收所述第一时钟信号；
    所述或非门电路的输出端与图像信号处理器耦合，用于输出所述第一脉冲信号或者所述第二脉冲信号。
  10. 如权利要求1-9任一项所述的像素，其特征在于，所述复合测量电路还包括复位开关；所述复位开关的第一端接地，第二端与所述积分单元的第一端耦合；所述复位开关的控制端与所述延时采样单元耦合，用于接收所述第一脉冲信号；
    在所述第一脉冲信号的电平为第四电平的时段内，所述复位开关处于断路状态；在所述第一脉冲信号的电平为第五电平的时段内，所述复位开关处于导通状态，使所述积分单元的第一端处的电压为复位电压；其中，所述第四电平大于所述第五电平。
  11. 如权利要求1-10中任一项所述的像素，其特征在于，所述复合测量电路还包括读出单元；所述读出单元与所述延时采样单元耦合，与图像信号处理器耦合；
    所述读出单元用于：
    接收所述图像信号处理器提供的存储信号，并根据所述存储信号缓存所述第一脉冲信号或者所述第二脉冲信号；
    接收所述图像信号处理器提供的扫描信号，根据所述扫描信号向所述图像信号处理器输出缓存的信号。
  12. 如权利要求11所述的像素，其特征在于，所述读出单元包括第三开关、第四开关以及RS锁存器；
    所述第三开关的第一端与所述图像信号处理器耦合；所述第三开关的第二端与所述第四开关的第一极耦合；所述第三开关的控制端用于接收所述图像信号处理器提供的所述扫描信号，其中，所述扫描信号用于驱动所述第三开关处于导通状态；
    所述第四开关的第二极接地，所述第四开关的控制端与所述第RS锁存器的Q输出端耦合；
    所述RS锁存器的复位端与所述图像信号处理器耦合，用于接收所述图像信号处理器提供的所述存储信号或者所述复位信号，所述RS锁存器的置位端与所述延时采样单元的输出端耦合，用于接收所述第一脉冲信号，所述RS锁存器的Q输出端处的电平与所述第一脉冲信号的电平相同，或者接收所述第二脉冲信号，所述RS锁存器的Q输出端处的电平与所述的第二脉冲信号的电平相同。
  13. 如权利要求1-12任一项所述的像素，其特征在于，所述像素还包括动态视觉测量电路；所述动态视觉测量电路与所述光电转换电路耦合，以及与图像信号处理器耦合，用于：
    基于所述第一电流，生成指示电平信号，并将所述指示电平信号发送给所述图像信号处理器，所述指示电平信号表征所述入射光的光强度变化信息。
  14. 如权利要求13所述的像素，其特征在于，所述像素还包括电流镜电路；所述复合测量电路通过所述电流镜电路与所述光电转换电路耦合；
    所述电流镜电路用于：向所述复合测量电路提供所述光电转换电路生成的所述第一电流。
  15. 一种图像传感器，其特征在于，包括：多个像素的阵列，至少一个像素为如权利要求1-14任一项所述的像素。
  16. 如权利要求15所述的传感器，其特征在于，还包括图像信号处理器；所述图像信号处理器与所述复合测量电路耦合；
    所述图像信号处理器，用于：
    控制目标像素处于第一工作模式，所述目标像素为所述至少一个像素中的任意一个像素；
    接收第一脉冲信号，根据所述第一脉冲信号的频率确定入射在所述目标像素上的入射光的强度信息。
  17. 如权利要求16所述的传感器，其特征在于，所述图像信号处理器，还用于：
    控制所述目标像素处于第二工作模式，按照预设的多个相位，依次向目标像素发送所述多个相位对应的多个采样信号，其中，所述多个相位与所述多个采样信号一一对应；
    接收多个第二脉冲信号，所述多个采样信号与所述多个第二脉冲信号一一对应；
    根据所述多个第二脉冲信号中每个第二脉冲信号，确定入射在所述目标像素上的入射光的相位与设定相位之间的相位偏移量，其中，所述入射光是所述设定相位的光线入射到目标对象反射的。
  18. 如权利要求17所述的传感器，其特征在于，所述图像信号处理器，具体用于：
    确定所述每个第二脉冲信号对应的数量，其中，所述每个第二脉冲信号对应的数量为预设时长内，所述每个第二脉冲信号中上升沿的数量；
    基于所述多个第二脉冲信号对应的数量，确定所述相位偏移量；
    根据所述相位偏移量，确定所述目标像素与所述目标对象之间的距离。
PCT/CN2023/096805 2022-05-30 2023-05-29 一种图像传感器的像素和图像传感器 WO2023231956A1 (zh)

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