WO2023231925A1

WO2023231925A1 - Epitaxial structure of semiconductor, semiconductor device and preparation method therefor

Info

Publication number: WO2023231925A1
Application number: PCT/CN2023/096580
Authority: WO
Inventors: 房育涛; 夏德洋; 叶念慈; 张洁
Original assignee: 湖南三安半导体有限责任公司
Priority date: 2022-05-30
Filing date: 2023-05-26
Publication date: 2023-12-07
Also published as: CN114883405A

Abstract

The present application relates to the technical field of semiconductor epitaxy. Provided in the embodiments of the present application are an epitaxial structure of a semiconductor, a semiconductor device and a preparation method therefor. The epitaxial structure of a semiconductor comprises a silicon substrate, an aluminum-rich silicon layer and an AlN nucleating layer. The aluminum-rich silicon layer is formed on the silicon substrate, and then the nucleating layer is formed on the aluminum-rich silicon layer, wherein the aluminum-rich silicon layer can inhibit the formation of amorphous SiN on the surface of the silicon substrate. In the embodiments of the present application, compared with the prior art, by providing the aluminum-rich silicon layer, it is possible to avoid the formation of amorphous SiN on the surface of the silicon substrate caused by directly reacting the silicon substrate with NH3 during the formation of the AlN nucleating layer, such that the influence of amorphous SiN on epitaxial growth is avoided, and the quality of epitaxial growth is ensured.

Description

Semiconductor epitaxial structure, semiconductor device and preparation method thereof

Cross-references to related applications

This application claims priority to the Chinese patent application with application number 202210604325.5 and titled "Semiconductor Epitaxial Structure, Semiconductor Devices and Preparation Methods" submitted to the State Intellectual Property Office of China on May 30, 2022, the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of semiconductor epitaxial technology, specifically, to a semiconductor epitaxial structure, a semiconductor device and a preparation method thereof.

Background technique

Gallium nitride-based compound semiconductor materials are widely used in high-voltage and high-frequency electronic devices and luminescence due to their advantages such as large bandgap, good thermal stability, radiation resistance, acid and alkali resistance, direct band gap, and easy formation of heterojunction device structures. Fabrication of devices. Due to the high melting point of gallium nitride and the high dissociation pressure of nitrogen, the gallium nitride substrate needs to be prepared under high temperature and high pressure conditions and the single crystal size grown is small and cannot meet the demand for lower cost production. Currently commercial gallium nitride-based devices are generally grown on sapphire, silicon carbide or silicon substrates through heteroepitaxial methods.

As an important gallium nitride heteroepitaxial substrate material for GaN heteroepitaxial growth, Si substrate has the advantages of high crystal quality, low substrate unit price, large size, high thermal conductivity, and electrical conductivity can be controlled by doping; The Si substrate used for gallium nitride epitaxy is generally a (111) plane silicon substrate. This is because the three-dimensional symmetry of the Si (111) plane is conducive to the epitaxy of (0001) plane GaN. Due to the severe metal miscibility between the silicon substrate and metal Ga, the gallium nitride film cannot be directly grown on the silicon substrate, so an AlN nucleation layer needs to be grown first. However, due to the particularity of the material, when growing the AlN nucleation layer, silicon atoms on the surface of the silicon substrate easily react with ammonia gas to form a large amount of amorphous SiN, which affects the epitaxial continuity and thus the quality of epitaxial growth.

Contents of the invention

The purposes of this application include, for example, providing a semiconductor epitaxial structure and a method for preparing a semiconductor epitaxial structure, which can suppress the formation of amorphous SiN on the surface of a silicon substrate, improve the window period for growing high-quality AlN on the silicon substrate, and ensure The epitaxial continuity is improved and the quality of epitaxial growth is improved.

The embodiment of this application can be implemented as follows:

In a first aspect, the present disclosure relates to a method for preparing a semiconductor epitaxial structure of a HEMT device, which includes: providing a silicon substrate; using an ion implantation process to form an aluminum-rich silicon layer heavily doped with aluminum on the surface of the silicon substrate; A nucleation layer is formed on the aluminum-rich silicon layer.

In a second aspect, the present disclosure relates to a method for preparing a semiconductor epitaxial structure of a HEMT device, which includes: providing a silicon substrate; evaporating to form an aluminum layer on the silicon substrate; evaporating to form dioxide on the aluminum layer. silicon layer; for the aluminum layer and The silicon dioxide layer is tempered to form the aluminum-rich silicon layer.

In a third aspect, the present disclosure relates to a HEMT device semiconductor epitaxial structure, which is characterized in that it includes: a silicon substrate; an aluminum-rich silicon layer provided on the silicon substrate; and an aluminum-rich silicon layer provided on the aluminum-rich silicon layer. nuclear layer.

Embodiments of the present application provide a semiconductor epitaxial structure and a preparation method thereof, by forming an aluminum-rich silicon layer on one side of the silicon substrate, and then forming an AlN nucleation layer on the side of the aluminum-rich silicon layer away from the silicon substrate, wherein , the aluminum-rich silicon layer can inhibit the formation of amorphous SiN on the surface of the silicon substrate. Compared with the prior art, the embodiments of the present application can avoid the direct reaction of the silicon substrate with NH ₃ to form amorphous SiN on the surface of the silicon substrate during the formation of the AlN nucleation layer by providing an aluminum-rich silicon layer, thus avoiding Amorphous SiN affects epitaxial growth and ensures the quality of epitaxial growth.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a semiconductor epitaxial structure provided by the first embodiment of the present application;

Figure 2 is a schematic structural diagram of a semiconductor device provided by the first embodiment of the present application;

3 and 4 are schematic process flow diagrams of a method for preparing a semiconductor epitaxial structure provided by the second embodiment of the present application;

FIG. 5 is a schematic structural diagram of a semiconductor epitaxial structure provided by the third embodiment of the present application.

Icon: 100-semiconductor epitaxial structure; 110-silicon substrate; 130-aluminum-rich silicon layer; 131-aluminum layer; 133-silicon dioxide layer; 135-patterned grooves; 150-AlN nucleation layer; 170-No. A buffer layer; 180-second buffer layer; 190-device layer; 200-semiconductor device.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments These are part of the embodiments of this application, but not all of them. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the application provided in the appended drawings is not intended to limit the scope of the claimed application, but rather to represent selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures.

In the description of this application, it should be noted that if the terms "upper", "lower", "inner", "outer", etc. appear to indicate an orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings, or It is the place where the invented product is usually placed when using it. The orientation or positional relationship is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application.

In addition, if the terms "first", "second", etc. appear, they are only used to differentiate the description and shall not be understood as indicating or implying relative importance.

As described in the background art, when epitaxially growing an AlN nucleation layer on a silicon substrate in the prior art, NH ₃ needs to be introduced into the reaction chamber, making NH ₃ easily react with silicon atoms on the surface of the silicon substrate. , thereby forming amorphous SiN on the surface of the silicon substrate, affecting the subsequent epitaxial growth process.

Furthermore, the existing technology also provides a solution of pre-passing an Al atomic layer on the silicon substrate to achieve blocking. However, passing the Al atomic layer is usually affected by the design of the epitaxial growth equipment and the temperature distribution of the substrate. As a result, the growth parameters such as the pre-passing time of Al and the Al atomic precursor flow rate are relatively different, and the window period is small, making the preparation of the Al atomic layer difficult, and the preparation of the Al atomic layer usually requires high temperature conditions (above 400°C) ), and the diffusion of Al atoms to the substrate is affected by temperature, causing the Al atomic layer to be easily distributed unevenly, affecting the quality of epitaxial growth. At the same time, due to the direct preparation of the Al atomic layer, epitaxial growth is required on the Al atomic layer, resulting in poor growth quality. It is difficult to prepare high-quality gallium nitride-based epitaxial films, and it is difficult to manufacture a large number of silicon-based gallium nitride power electronic devices. be applied in production.

In order to solve the above problems, the present application provides a new type of semiconductor epitaxial structure and a preparation method thereof. It should be noted that the features in the embodiments of the present application can be combined with each other as long as there is no conflict.

Some embodiments provide a semiconductor epitaxial structure 100 that can suppress the formation of amorphous SiN on the surface of the silicon substrate 110, improve the window period for growing high-quality AlN on the silicon substrate 110, ensure epitaxial continuity, and improve epitaxial growth. quality.

Please refer to Figure 1. Some embodiments provide a semiconductor epitaxial structure 100, including a silicon substrate 110, an aluminum-rich silicon layer 130 and a nucleation layer 150. The aluminum-rich silicon layer 130 is disposed on the silicon substrate 110. The nucleation layer 150 is disposed on the aluminum-rich silicon layer 130, wherein the nucleation layer 150 may be an AlN nucleation layer. The aluminum-rich silicon layer 130 is located on one side of the silicon substrate 110, and the AlN nucleation layer 150 is located away from the aluminum-rich silicon layer 130. On one side of the bottom 110 , the aluminum-rich silicon layer 130 at least contains aluminum atoms and silicon atoms, and the aluminum-rich silicon layer 130 covers the surface of the silicon substrate 110 to inhibit the formation of amorphous SiN on the surface of the silicon substrate 110 .

It is worth noting that the preparation process of the AlN nucleation layer 150 here is consistent with that of conventional epitaxial structures, both of which require access to NH ₃ . However, some embodiments can avoid the formation of the AlN nucleation layer 150 by providing an aluminum-rich silicon layer 130 During the process, the silicon substrate 110 directly reacts with NH ₃ to form amorphous SiN on the surface of the silicon substrate 110, which avoids amorphous SiN from affecting epitaxial growth and ensures the quality of epitaxial growth.

It should be noted that in some embodiments, the aluminum-rich silicon layer 130 includes aluminum atoms and silicon atoms, which can be formed by doping epitaxial growth, and the aluminum-rich silicon layer 130 evenly covers the top surface of the silicon substrate 110, so that This can prevent silicon atoms at the top surface of the silicon substrate 110 from reacting with NH ₃ to generate amorphous SiN and affect subsequent epitaxial growth.

In some embodiments, the silicon substrate 110 may be a low-resistance (111) surface with a thickness ranging from 500 μm to 1500 μm. Silicon substrate 110. The doping concentration range of silicon substrate 110 is 1E16/cm ³ -1E20/cm ³ . The structure of silicon substrate 110 is consistent with a conventional epitaxial structure and will not be detailed here. Preferably, the silicon substrate 110 here is a P-type (111) crystal silicon substrate 110 with a thickness of 1000um and a resistivity of 0.005ohm.cm, and the deposition method of the silicon substrate 110 may include CVD (Chemical Vapor Deposition, chemical vapor phase). Deposition), VPE (Vapour Phase Epitaxy, vapor phase epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), Atomic Layer Epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, etc.

In some embodiments, the aluminum-rich silicon layer 130 includes a heavily aluminum-doped silicon layer located on the surface of the silicon substrate 110 . Specifically, the silicon layer here may be a silicon layer grown separately after the silicon substrate 110 is formed, and heavy doping with aluminum is achieved during the growth process. At the same time, the silicon layer here can also be a silicon layer near the top surface of the silicon substrate 110, and the top surface of the silicon substrate 110 is directly doped to form a silicon layer heavily doped with aluminum. Specifically, the doping of the aluminum-rich silicon layer 130 here can be achieved through an ion implantation process, that is, the Al-rich silicon layer is formed by heavily doping Al through ion implantation and tempering, that is, a silicon layer heavily doped with aluminum is formed.

In some embodiments, the aluminum doping concentration of the silicon layer is greater than 1E19/cm ³ and less than 1E22/cm ³ . Preferably, a heavily doped Al-rich layer with an Al doping concentration of 5E19/cm ³ can be prepared on the surface of the silicon substrate 110 by ion implantation and then tempered. Of course, the doping concentration of aluminum in the silicon layer is not specifically limited here, and the doping concentration that can suppress the formation of SiN is the limit.

In some embodiments, the thickness of the silicon layer is less than 500 nm. Preferably, the thickness of the silicon layer here may be 200 nm and is located on the top side surface of the silicon substrate 110, and its thickness may be determined by the ion implantation depth.

It should be noted that the silicon layer can be doped here through multiple ion implantations to ensure that the doping concentration meets the requirements. Moreover, in some embodiments, the temperature during ion implantation can be controlled below 400°C to achieve low-temperature preparation to form the aluminum-rich silicon layer 130, avoiding uneven diffusion of aluminum atoms and ensuring uniform doping of the silicon layer. Among them, the basic principles and processes of the ion implantation process will not be introduced in detail here. For details, reference can be made to the ion implantation process in the prior art.

In some embodiments, the nucleation layer 150 can be grown on the surface of the aluminum-rich silicon layer 130 under high temperature conditions. In some embodiments, the nucleation layer 150 is an AlN layer. Of course, the nucleation layer 150 can also be used for epitaxy. The grown III-V semiconductor material, for example, the nucleation layer can be made of a III-nitride material, and the III-nitride material can be composed of _InxAlyGa1 _-xyN , _where x+y≤1, some embodiments The nucleation layer 150 in is described using AlN as an example and does not play any limiting role. In some embodiments, the growth of the AlN nucleation layer 150 may be performed at a growth temperature of 1100°C. Moreover, the thickness of the AlN nucleation layer 150 may be 20-500 nm. Preferably, the thickness of the AlN nucleation layer 150 here is 200nm. It should be noted that the AlN nucleation layer 150 here can also adopt chemical vapor deposition (CVD), VPE (Vapor Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemistry). Vapor phase deposition), LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), PLD (Pulsed Laser Deposition, pulse laser deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy, molecular beam epitaxy), sputtering, evaporation and other methods are prepared and formed. Preferably, in some embodiments, the AlN nucleation layer 150 can be prepared using a MOCVD (Metal-organic Chemical Vapor Deposition) process.

Referring to Figure 2, some embodiments also provide a semiconductor device 200. The semiconductor device 200 includes the aforementioned semiconductor epitaxial structure 100 and may also include a first buffer layer 170, a second buffer layer 180 and a device layer 190, wherein the device The layer 190 may be a GaN-based device layer, the first buffer layer 170 may be an AlGaN layer, and the second buffer layer 180 may be a GaN layer. Of course, the first buffer layer 170 and the second buffer layer 180 may also be other layers. The III-V semiconductor material grown epitaxially, for example, the first buffer layer 170 or _the second buffer layer 180 can be made of a III-nitride material, and the III-nitride material can be composed of _InxAlyGa1 _-xyN , where x+y≤1. The first buffer layer 170 is located on the side of the AlN nucleation layer 150 away from the silicon substrate 110 , the second buffer layer 180 is located on the side of the first buffer layer 170 away from the silicon substrate 110 , and the GaN-based device layer 190 is located on the second buffer layer 180 On the side away from the silicon substrate 110, the GaN-based device layer 190 is a HEMT device layer.

In some embodiments, the thickness of the first buffer layer 170 is 100-5000 nm, the Al composition is between 0% and 100%, and the thickness of the second buffer layer 180 is 1000-5000 nm.

Some embodiments also provide a method for preparing the semiconductor epitaxial structure 100, which is used to prepare the aforementioned semiconductor epitaxial structure 100, which includes the following steps:

S1: Form an aluminum-rich silicon layer 130 on the silicon substrate 110.

Specifically, a silicon substrate 110 needs to be provided first, and then an ion implantation process can be used to form an aluminum-rich silicon layer 130 heavily doped with aluminum on the surface of the silicon substrate 110 . The aluminum-rich silicon layer 130 at least contains aluminum atoms and silicon atoms, and the aluminum-rich silicon layer 130 covers the surface of the silicon substrate 110 to inhibit the formation of amorphous SiN on the surface of the silicon substrate 110 .

It should be noted that here, the surface of the silicon substrate 110 can be heavily doped with aluminum through a low-temperature (below 400° C.) ion implantation process, thereby forming an aluminum-rich silicon layer heavily doped with aluminum. 130.

In other preferred embodiments of the present application, the aluminum-rich silicon layer 130 can also be patterned and distributed on the surface of the silicon substrate 110 , wherein the patterning of the aluminum-rich silicon layer 130 can be formed by local ion implantation, for example, it can be formed on the silicon substrate. A patterned mask is set on the bottom 110, and then an ion implantation process is performed to achieve local implantation and patterning of the aluminum-rich silicon layer 130, thereby forming a patterned substrate-like effect during the subsequent growth of the nucleation layer 150. Reduce dislocation density and improve crystal quality.

S2: Form the nucleation layer 150 on the aluminum-rich silicon layer 130.

Specifically, the AlN nucleation layer 150 can be prepared using a MOCVD (Metal-organic Chemical Vapor Deposition) process. For example, when the growth temperature is 1100° C., a 200 nm thick AlN nucleation layer 150 is formed on the surface of the silicon layer.

When actually growing the AlN nucleation layer 150 , the silicon dioxide on the surface of the aluminum-rich silicon layer 130 can be decomposed at high temperature first, and then the AlN nucleation layer 150 can be grown on the surface of the aluminum-rich silicon layer 130 . Specifically, the MOCVD process can be used to desorb and decompose the silicon dioxide layer 133 on the surface at high temperature, so that the epitaxial growth quality is better.

Some embodiments also provide a method for preparing a semiconductor device. The method for preparing a semiconductor device also needs to perform the aforementioned step S1 and step S2. After step S2, the method for preparing a semiconductor device may also include the following steps:

S3: Form the first buffer layer 170 on the nucleation layer 150;

S4: Form the second buffer layer 180 on the first buffer layer 170;

S5: Form the device layer 190 on the second buffer layer 180.

Specifically, the first buffer layer 170 is first formed on the surface of the AlN nucleation layer 150 through a MOCVD process. The Al component of the buffer layer gradually decreases along the epitaxial growth direction, and the thickness of the AlGaN layer ranges from 100 to 5000 nm. Then, the MOCVD process is used to grow the second buffer layer 180 on the AlGaN layer, with a thickness ranging from 1000nm to 5000nm. Finally, a GaN-based device layer 190 is grown on the second buffer layer 180, that is, a HEMT device layer is grown, where the HEMT device layer includes a GaN channel layer, an AlGaN barrier layer and a GaN cap layer.

The actual process steps and growth conditions of the preparation method of the semiconductor device 200 are described below:

Step 1: Select a P-type (111) crystalline silicon substrate 110 with a thickness of 1000 μm and a resistivity of 0.005 ohm.cm;

Step 2: Use ion implantation to prepare a heavily doped Al-rich layer with a thickness of 200 nm and Al doping of 5E19/cm ³ on the surface of the above-mentioned silicon substrate 110 and temper it;

Step 3: Use MOCVD to grow a high-temperature AlN nucleation layer 150 on the surface of the above-mentioned aluminum-rich silicon layer 130, with a growth temperature of 1100°C and a thickness of 200 nm;

Step 4: Continue to grow the first buffer layer 170 on the surface of the AlN nucleation layer 150 after step 3, that is, grow the AlGaN layer. The first buffer layer 170 has a total thickness of 2000nm and contains 300nm of high Al composition Al _0.8 Ga _0.2 N. 800nm medium Al component Al _0.5 Ga _0.5 N and 900nm low Al component Al _0.2 Ga _0.8 N;

Step 5: Continue to grow a 1500nm GaN high-resistance layer on the first buffer layer 170 completed in step 4, that is, grow the second buffer layer 180 at a growth temperature of 970°C;

Step 6: Grow a HEMT device layer on the second buffer layer 180. The device layer includes: a 300nm channel layer, a 20nm Al _0.25 Ga _0.75 N barrier layer and a 3nm GaN cap layer.

To sum up, some embodiments provide semiconductor epitaxial structures 100, semiconductor devices 200 and preparation methods thereof. The aluminum-rich silicon layer 130 is formed by using an ion implantation process on one side of the silicon substrate 110, and then the aluminum-rich silicon layer 130 is formed. Stay away from silicon An AlN nucleation layer 150 is formed on one side of the substrate 110, wherein the aluminum-rich silicon layer 130 is a silicon layer heavily doped with aluminum, and the aluminum-rich silicon layer 130 covers the surface of the silicon substrate 110 to inhibit the silicon substrate. Amorphous SiN is formed on the surface of 110. By arranging the aluminum-rich silicon layer 130 in the embodiment of the present application, the silicon substrate 110 can be prevented from directly reacting with NH3 to form amorphous SiN on the surface of the silicon substrate 110 during the formation of the AlN nucleation layer 150, thereby avoiding the influence of amorphous SiN. Epitaxial growth ensures the quality of epitaxial growth.

Referring to FIGS. 1 and 3 , some embodiments provide a semiconductor epitaxial structure 100 , whose basic structure and principle and the technical effects produced are the same as those of the first embodiment. For the sake of brief description, some embodiments are not mentioned. For details, please refer to the corresponding content in the first embodiment. The difference from the first embodiment is the preparation method of the aluminum-rich silicon layer 130 .

In some embodiments, referring to FIG. 3 and FIG. 4 , the aluminum-rich silicon layer 130 is formed from the aluminum layer 131 and the silicon dioxide layer 133 after high-temperature tempering. Specifically, the aluminum layer may be first formed on the surface of the silicon substrate 110 131, and then forming a silicon dioxide layer 133 on the surface of the aluminum layer 131, and then performing high-temperature tempering, which can also form an aluminum-rich silicon layer 130 and suppress the formation of amorphous SiN on the surface of the silicon substrate 110. Among them, the silicon dioxide layer 133 can play a good protective role, and the thickness can be 10nm-30nm.

In some embodiments, an aluminum layer 131 can be formed on the surface of the silicon substrate 110 by evaporation, and then a layer of silicon dioxide can be evaporated to play a protective role. Here, the thickness of the aluminum layer 131 is less than 10 nm. , which can prevent the aluminum layer 131 from being too thick and affecting the epitaxial growth quality. Preferably, the thickness of the aluminum layer 131 here may be 3 nm, and the thickness of the silicon dioxide layer 133 may be 20 nm.

Some embodiments also provide a method for preparing the semiconductor epitaxial structure 100. The basic steps and principles and the technical effects produced are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in some embodiments, please refer to Section 1. The corresponding content in an embodiment. The difference compared with the first embodiment is the formation method of the aluminum-rich silicon layer 130 .

In some embodiments, the preparation method includes step S1: forming an aluminum-rich silicon layer 130 on the surface of the silicon substrate 110. Specifically, referring to FIG. 3 and FIG. 4 , first, the aluminum layer 131 and the silicon dioxide layer 133 are sequentially evaporated on the surface of the silicon substrate 110; then, the aluminum layer 131 and the silicon dioxide layer 133 are subjected to high-temperature tempering treatment. To form aluminum-rich silicon layer 130 .

The actual process steps and growth conditions of the preparation method of the semiconductor epitaxial structure 100 provided by some embodiments are described below:

Step 1: Select a P-type (111) crystal plane silicon substrate 110 with a thickness of 1000um and a resistivity of 0.005ohm.cm.

Step 2: Evaporate a 3nm metal Al layer on the surface of the above substrate, and then evaporate a 20nm SiO ₂ protective layer on the surface of the Al layer.

Step 3: Temper the completed silicon dioxide layer 133, decompose the silicon dioxide on the surface in a high-temperature hydrogen environment, and form an aluminum-rich silicon layer 130.

Step 4: Use MOCVD to grow a high-temperature AlN nucleation layer 150 on the surface of the aluminum-rich silicon layer 130 formed in step 3, with a growth temperature of 1100°C and a thickness of 200 nm;

Step 5: Continue to grow the first buffer layer 170 on the surface of the AlN nucleation layer 150. The first buffer layer 170 has a total thickness of 1500 nm and contains 200 nm of high Al component Al _0.8 Ga _0.2 N and 600 nm of medium Al component Al _0.5 Ga. _0.5 N and 700 nm low Al composition Al _0.2 Ga _0.8 N.

Step 6: Continue to grow a 2000nm GaN high-resistance layer on the first buffer layer 170, that is, grow the second buffer layer 180 at a growth temperature of 970°C;

Step 7: Grow a HEMT device layer on the second buffer layer 180. The device layer includes: a 200nm channel layer, a 15nm A _l0.2 Ga _0.8 N barrier layer and a 100nm P-type doped GaN cap layer.

The semiconductor epitaxial structure 100 and its preparation method provided in some embodiments utilize sequential evaporation of the aluminum layer 131 and the silicon dioxide layer and then tempering to form the aluminum-rich silicon layer 130, which can also avoid the silicon lining in the process of forming the AlN nucleation layer 150. The bottom 110 directly reacts with NH3 to form amorphous SiN on the surface of the silicon substrate 110, which prevents amorphous SiN from affecting epitaxial growth and ensures the quality of epitaxial growth.

Referring to Figure 5, some embodiments provide a semiconductor epitaxial structure 100. Its basic structure and principle and the technical effects produced are the same as those of the first embodiment or the second embodiment. For the sake of brief description, some embodiments are not mentioned. Where appropriate, reference may be made to the corresponding content in the first embodiment or the second embodiment. Compared with the first embodiment or the second embodiment, some embodiments are different in the structure and preparation method of the aluminum-rich silicon layer 130 .

In some embodiments, the aluminum-rich silicon layer 130 is patterned on the surface of the silicon substrate 110 . After forming the aluminum layer 131 and the silicon dioxide layer 133, a patterned mask can be set on the silicon dioxide layer 133, and the silicon dioxide layer 133 and the aluminum layer 131 can be etched sequentially to form patterned grooves 135 to achieve The aluminum-rich silicon layer 130 is patterned. Specifically, the aluminum-rich silicon layer 130 may be provided with patterned grooves 135 that penetrate to the silicon substrate 110 . Specifically, after the aluminum-rich silicon layer 130 is formed, a photolithography process can be used to etch nano-patterns on the silicon dioxide surface, and wet etching can be used to remove the aluminum layer 131 under the etched silicon dioxide, thereby achieving rich aluminum silicon layer 130 . Patterning of aluminum silicon layer 130 .

It should be noted that in some embodiments, by patterning the surface of the aluminum-rich silicon layer 130 and forming the patterned grooves 135, silicon nitride can be locally generated during the growth of the AlN nucleation layer 150 to form a similar pattern substrate. This further reduces interface dislocations and improves the crystal quality of subsequent epitaxial layers.

Some embodiments also provide a method for preparing the semiconductor epitaxial structure 100, which is used to prepare the aforementioned semiconductor epitaxial structure 100. The basic steps and principles and the technical effects produced are the same as those of the first embodiment. For the sake of brief description, some implementations For matters not mentioned in the examples, please refer to the corresponding contents in the first embodiment or the second embodiment. What is different from the first embodiment or the second embodiment is the formation method of the aluminum-rich silicon layer 130 .

In some embodiments, the preparation method includes step S1: forming an aluminum-rich silicon layer 130 on the surface of the silicon substrate 110. Specifically, first, the aluminum layer 131 and the silicon dioxide layer 133 are sequentially evaporated on the surface of the silicon substrate 110; then the aluminum layer 131 and the silicon dioxide layer 133 are tempered to form the aluminum-rich silicon layer 130; and then The surface of the aluminum-rich silicon layer 130 is patterned using a photolithography process, thereby forming patterned grooves 135 on the surface of the aluminum-rich silicon layer 130 .

Step 1: Select a P-type (111) crystalline silicon substrate 110 with a thickness of 1000um and a resistivity of 0.005ohm.cm;

Step 2: Evaporate a 3nm metal Al layer on the surface of the above substrate, and then evaporate a 20nm SiO ₂ protective layer on the surface of the Al layer;

Step 3: Use photolithography to etch nano-patterns on the silicon dioxide surface, use wet etching to remove the metal Al layer under the SiO ₂ protective layer, clean the epitaxial wafer and dry it for sealing;

Step 4: Temper the patterned Al nanolayer prepared in step 3 by using MOCVD at elevated temperature and decompose the SiO ₂ on the surface in a high-temperature hydrogen environment to leak out the patterned aluminum-rich silicon layer 130;

Step 5: Use MOCVD to grow a high-temperature AlN nucleation layer 150 on the surface of the aluminum-rich silicon layer 130 patterned in step 4, with a growth temperature of 1100°C and a thickness of 200 nm;

Step 6: Continue to grow the first buffer layer 170 on the surface of the AlN nucleation layer 150. The first buffer layer 170 has a total thickness of 1500 nm and contains 200 nm of high Al component Al _0.8 Ga _0.2 N and 600 nm of medium Al component Al _0.5 Ga. Low Al composition Al _0.2 Ga _0.8 N at _0.5 N and 700 nm;

Step 7: Continue to grow a 2000nm GaN high-resistance layer on the first buffer layer 170, that is, grow the second buffer layer 180 at a growth temperature of 970°C;

Step 8: Grow a HEMT device layer on the second buffer layer 180. The device layer includes: a 200nm channel layer, a 15nm Al _0.20 Ga _0.80 N barrier layer and a 100nm P-type doped GaN cap layer.

The semiconductor epitaxial structure 100 and its preparation method provided in some embodiments, by patterning the surface of the aluminum-rich silicon layer 130, can form a similar patterned substrate function when the AlN nucleation layer 150 grows, reducing the dislocation density and improving the crystal. quality.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. All are covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A HEMT device semiconductor epitaxial structure, which is characterized by including:

silicon substrate;

An aluminum-rich silicon layer provided on the silicon substrate;

A nucleation layer is provided on the aluminum-rich silicon layer.
The semiconductor epitaxial structure according to claim 1, wherein the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19/cm 3 and less than 1E22/cm 3 .
The semiconductor epitaxial structure according to claim 2, wherein the thickness of the aluminum-rich silicon layer is less than 500 nm.
The semiconductor epitaxial structure according to claim 2, wherein the aluminum-rich silicon layer is patterned and distributed on the surface of the silicon substrate.
The semiconductor epitaxial structure according to claim 3, wherein the thickness of the aluminum-rich silicon layer is 3 nm-10 nm.
The semiconductor epitaxial structure according to claim 3, wherein the thickness of the aluminum-rich silicon layer is 200nm-500nm.
A method for preparing a semiconductor epitaxial structure of a HEMT device, which is characterized by including:

providing a silicon substrate;

Using an ion implantation process to form an aluminum-rich silicon layer heavily doped with aluminum on the surface of the silicon substrate;

A nucleation layer is formed on the aluminum-rich silicon layer.
The method for preparing a semiconductor epitaxial structure according to claim 7, wherein the step of using an ion implantation process to form an aluminum-rich silicon layer heavily doped with aluminum on the surface of the silicon substrate includes: The surface is implanted with Al by ion implantation and then tempered.
The method for preparing a semiconductor epitaxial structure according to claim 8, wherein the step of forming an aluminum-rich silicon layer heavily doped with aluminum on the surface of the silicon substrate using an ion implantation process includes:

Laying a patterned mask on the silicon substrate;

Implanting aluminum atoms into the surface of the silicon substrate using an ion implantation process;

The patterned mask is removed and then tempered.
The method for preparing a semiconductor epitaxial structure according to claim 8, characterized in that the depth of Al implanted into the surface of the silicon substrate by ion implantation is less than 500 nm.
The method for preparing a semiconductor epitaxial structure according to claim 8, characterized in that the depth of Al implanted into the surface of the silicon substrate by ion implantation is 200-500 nm.
The method for preparing a semiconductor epitaxial structure according to claim 8, characterized in that, on the surface of the silicon substrate The concentration of Al implanted by ion implantation is greater than 1E19/cm 3 and less than 1E22/cm 3 .
The method for preparing a semiconductor epitaxial structure according to claim 8, characterized in that Al is ion-implanted on the surface of the silicon substrate at a temperature below 400°C.
A method for preparing a semiconductor epitaxial structure of a HEMT device,

It is characterized by including

providing a silicon substrate;

evaporate to form an aluminum layer on the silicon substrate;

evaporate to form a silicon dioxide layer on the aluminum layer;

The aluminum layer and the silicon dioxide layer are tempered to form the aluminum-rich silicon layer.
The method for preparing a semiconductor epitaxial structure according to claim 14, wherein the step of tempering the aluminum layer and the silicon dioxide layer includes:

Laying a patterned mask on the silicon dioxide layer;

Etch the silicon dioxide layer and the aluminum layer in sequence;

Remove the patterned mask to obtain the patterned aluminum layer and the silicon dioxide layer;

The remaining aluminum layer and the silicon dioxide layer are tempered to form the patterned aluminum-rich silicon layer.
The method for preparing a semiconductor epitaxial structure according to claim 14, wherein the thickness of the aluminum layer formed by evaporation on the silicon substrate is less than 10 nm.
The method for preparing a semiconductor epitaxial structure according to claim 16, wherein the aluminum layer formed by evaporation on the silicon substrate has a thickness of less than 3 nm to 10 nm.
The method for preparing a semiconductor epitaxial structure according to claim 14, wherein the thickness of the silicon dioxide layer formed by evaporation on the aluminum layer is 10 nm-30 nm.
The method for preparing a semiconductor epitaxial structure according to claim 14, wherein the doping concentration range of aluminum atoms in the formed aluminum-rich silicon layer is: greater than 1E19/cm 3 and less than 1E22/cm 3 .