WO2023229021A1

WO2023229021A1 - Semiconductor light emitting device

Info

Publication number: WO2023229021A1
Application number: PCT/JP2023/019574
Authority: WO
Inventors: 晃輝坂本
Original assignee: ローム株式会社
Priority date: 2022-05-27
Filing date: 2023-05-25
Publication date: 2023-11-30

Abstract

This semiconductor light emitting device comprises a substrate, a light emitting element mounted on the substrate, a transistor, and a first capacitor module. The first capacitor module has a first main surface facing the substrate, and a first connection electrode and a second connection electrode provided on the first main surface, and is electrically connected to the light emitting element. The first capacitor module includes a silicon substrate having a first surface and a second surface facing opposite each other, a first connection electrode provided on the first surface, and a counter electrode provided on the second surface, facing the first connection electrode.

Description

semiconductor light emitting device

The present disclosure relates to a semiconductor light emitting device.

One type of semiconductor light emitting device is a semiconductor laser device that includes a semiconductor light emitting element as a laser light source (see, for example, Patent Document 1). Such semiconductor laser devices are widely used as light source devices installed in various electronic devices.

JP2016-29718A

A semiconductor light emitting device includes, for example, a switching element and a capacitor that drive a semiconductor light emitting element. Therefore, parasitic inductance exists on the wiring path of the circuit including the semiconductor light emitting device. Parasitic inductance can affect the output characteristics of semiconductor light emitting devices.

A semiconductor light emitting device that is one aspect of the present disclosure includes a substrate, a light emitting element mounted on the substrate, a transistor mounted on the substrate and configured to drive the light emitting element, and a transistor mounted on the substrate. a capacitor module mounted on the substrate, having a main surface facing the substrate, a first connection electrode and a second connection electrode provided on the main surface, and electrically connected to the light emitting element. , the capacitor module includes a silicon substrate having a first surface and a second surface facing opposite to each other, the first connection electrode provided on the first surface, and the first connection electrode provided on the second surface. and a counter electrode that faces the connection electrode.

According to a semiconductor light emitting device that is one embodiment of the present disclosure, parasitic inductance can be reduced.

FIG. 1 is a perspective view schematically showing an exemplary semiconductor light emitting device according to a first embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor light emitting device of FIG. FIG. 3 is a perspective view schematically showing the stem and lead pin. FIG. 4 is a perspective view schematically showing the stem and lead pins as seen from a viewpoint opposite to FIG. 3. FIG. FIG. 5 is a perspective view schematically showing a semiconductor light emitting device and a drive board. FIG. 6 is a plan view schematically showing the light emitting module according to the first embodiment. FIG. 7 is a perspective view of the light emitting module of FIG. 6. 8 is a plan view showing the internal wiring structure of the substrate of the light emitting module of FIG. 6. FIG. 9 is a plan view showing the internal wiring structure of the substrate of the light emitting module of FIG. 6. FIG. FIG. 10 is a cross-sectional view taken along line 10-10 in FIG. FIG. 11 is a cross-sectional view taken along line 11-11 in FIG. FIG. 12 is a circuit diagram schematically showing the electrical configuration of the semiconductor light emitting device. FIG. 13 is a sectional view showing a light emitting module of a comparative example. FIG. 14 is a sectional view showing a light emitting module including a capacitor module of a modified example. FIG. 15 is a sectional view showing a light emitting module including a capacitor module according to a modified example. FIG. 16 is a sectional view showing a light emitting module including a capacitor module according to a modified example. FIG. 17 is a perspective view schematically showing a light emitting module including a modified example of a substrate. FIG. 18 is a plan view showing the internal wiring structure of the substrate of FIG. 17. FIG. 19 is a plan view showing the internal wiring structure of the substrate of FIG. 17. FIG. 20 is a plan view showing the internal wiring structure of the substrate of FIG. 17. 21 is a cross-sectional view of FIG. 17 taken along line 21-21 of FIG. 18. FIG. 22 is a perspective view schematically showing an exemplary semiconductor light emitting device according to the second embodiment. FIG. 23 is a plan view schematically showing the semiconductor light emitting device of FIG. 22. FIG. 24 is a plan view showing the internal wiring structure of the substrate of the light emitting module of FIG. 22. FIG. 25 is a plan view showing the internal wiring structure of the substrate of the light emitting module of FIG. 22. FIG. 26 is a cross-sectional view taken along line 26-26 in FIG. 23. FIG. 27 is a cross-sectional view taken along line 27-27 in FIG. 23.

Hereinafter, some embodiments of the semiconductor light emitting device of the present disclosure will be described with reference to the accompanying drawings. It should be noted that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure. Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects, and are not intended to rank the objects.

The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the disclosure or the application and uses of such embodiments.

(First embodiment)
The configuration of the semiconductor light emitting device 10A of the first embodiment will be described below.
FIG. 1 is a perspective view schematically showing an exemplary semiconductor light emitting device 10A according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor light emitting device 10A of FIG. 1. Note that in this disclosure, constituent members may be described based on mutually orthogonal XYZ axes shown in figures such as FIG. 1 for the purpose of explanation only. In the following, the +Z direction is defined as top, the -Z direction as bottom, the +X direction as right, and the -X direction as left.

The semiconductor light emitting device 10A shown in FIG. 1 can be used, for example, in a laser system as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging), which is an example of three-dimensional distance measurement. Note that the semiconductor light emitting device 10A may be used in a laser system for two-dimensional distance measurement.

(package structure)
First, an overview of the package structure will be explained.
As shown in FIGS. 1 and 2, the semiconductor light emitting device 10A includes a stem 20, a light emitting module 30A mounted on the stem 20, and a surrounding member 40. Stem 20 includes a base 22 and a heat sink 24 erected on base 22. The light emitting module 30A is mounted on the heat sink 24. The surrounding member 40 is provided on the base 22 so as to surround the light emitting module 30A and the heat sink 24. The structure in which the light emitting module 30A is packaged using the stem 20 and the surrounding member 40 is also called a CAN package structure.

The surrounding member 40 defines an accommodation space 42 that accommodates the light emitting module 30A. The surrounding member 40 is fixed to the base 22 of the stem 20, and together with the stem 20, the housing space 42 is hermetically sealed to form a hollow sealed structure.

In the first embodiment, the surrounding member 40 includes a cap 44 and a transparent plate 46 (see FIG. 2). Note that the light-transmitting plate 46 may be omitted depending on the use of the semiconductor light-emitting device 10A. Although the material of the cap 44 is not particularly limited, it is formed of a metal material having light-shielding properties, such as iron (Fe) or Fe alloy. In the first embodiment, the cap 44 includes a top portion 44A, a cylinder portion 44B, and a flange portion 44C, and the top portion 44A, cylinder portion 44B, and flange portion 44C are integrally formed.

The cylindrical portion 44B is formed, for example, in a cylindrical shape. The top portion 44A is located at one end (the upper end in FIGS. 1 and 2) of the cylindrical portion 44B, and the flange portion 44C is located at the other end (the lower end in FIGS. 1 and 2) of the cylindrical portion 44B. The flange portion 44C is fixed to the surface 22A of the base 22 by, for example, welding or a bonding material. The top portion 44A includes a window portion 44AW through which light emitted from the light emitting module 30A passes. The window portion 44AW is formed, for example, in a circular shape.

The light-transmitting plate 46 is fixed from the inside of the cap 44 to the top portion 44A using a bonding material or the like to close the window portion 44AW. The light-transmitting plate 46 is made of a transparent material such as glass, and transmits light passing through the window portion 44AW. Furthermore, the transparent plate 46 also serves as a sealing member that seals the housing space 42 of the light emitting module 30A surrounded by the surrounding member 40.

(Overview of light emitting module)
Next, the outline of the light emitting module 30A will be explained.
The light emitting module 30A includes a substrate 50A, a light emitting element 60, and a light emitting element drive circuit 70. The light emitting element 60 and the light emitting element driving circuit 70 are mounted on the substrate 50A. The light emitting element 60 is a laser diode (semiconductor laser element). The light emitting element drive circuit 70 includes a transistor 80 that drives the light emitting element 60. The transistor 80 is mounted on the substrate 50A as a vertical metal oxide semiconductor field effect transistor (MOSFET). In this disclosure, a MOSFET with a vertical structure is referred to as a vertical MOSFET.

In the first embodiment, the light emitting element drive circuit 70 further includes a first capacitor module 110 and a second capacitor module 120. The first and

second capacitor modules

110, 120 include silicon capacitors. The light emitting element driving circuit 70 drives the light emitting element 60 by supplying the charges accumulated in the first and

second capacitor modules

110 and 120 to the light emitting element 60 via the transistor 80 as a pulse current.

(Stem)
Next, the structure of the stem 20 will be explained.
FIG. 3 is a perspective view schematically showing the structure of the stem 20, and FIG. 4 is a perspective view of the stem 20 seen from the opposite viewpoint from FIG.

As mentioned above, the stem 20 includes a base 22 and a heat sink 24. In the first embodiment, the base 22 and the heat sink 24 are integrally formed. The stem 20 is made of a conductive material such as copper (Cu), Cu alloy, Fe, Fe alloy, or the like. Note that the base 22 and the heat sink 24 may be formed of different metals.

The base 22 has, for example, a substantially circular shape when viewed in the thickness direction of the base 22. In the present disclosure, the thickness direction of the base 22 refers to a direction (Z-axis direction) orthogonal to the surface 22A of the base 22. The size of the base 22 is not particularly limited.

The heat sink 24 is integrally provided on the surface 22A of the base 22. The heat sink 24 has, for example, a substantially fan shape when viewed in the thickness direction of the base 22. The size of the heat sink 24 is not particularly limited.

The heat sink 24 includes a planar support surface 24A, and the light emitting module 30A shown in FIGS. 1 and 2 is mounted on this support surface 24A. For example, the light emitting module 30A is bonded to the support surface 24A using a conductive bonding material (not shown), and is electrically connected to the heat sink 24 via the conductive bonding material. In the first embodiment, the heat sink 24 is electrically connected to the transistor 80 of the light emitting module 30A via a conductive bonding material. As the conductive bonding material, for example, a conductive paste such as silver (Ag) paste can be used.

The base 22 includes a plurality of through holes passing through the base 22 in the thickness direction, for example, three through

holes

26A, 26B, and 26C in the first embodiment. Each of the through

holes

26A, 26B, and 26C has, for example, a substantially circular shape when viewed in the thickness direction of the base 22. The size of each through

hole

26A, 26B, 26C is not particularly limited.

FIG. 5 is a perspective view schematically showing a mounting example of the semiconductor light emitting device 10A. The semiconductor light emitting device 10A is mounted on a drive board 910 that controls driving of the light emitting module 30A. The semiconductor light emitting device 10A includes a plurality of lead pins that electrically connect the light emitting module 30A and the drive board 910. As shown in FIGS. 3 and 4, the semiconductor light emitting device 10A of the first embodiment includes four

lead pins

142A, 142B, 142C, and 142D. In the first embodiment, lead pins 142A and 142B correspond to first lead pins, lead pin 142D corresponds to second lead pin, and lead pin 142C corresponds to third lead pin.

As shown in FIGS. 1, 3, and 4, the lead pins 142A, 142B, and 142C pass through the base 22. In the first embodiment, lead pins 142A, 142B, and 142C are inserted into through

holes

26A, 26B, and 26C of base 22, respectively. The insides of these through

holes

26A, 26B, and 26C are filled with an insulating material 144 that electrically insulates the lead pins 142A, 142B, and 142C from the base 22, respectively. The insulating material 144 is made of glass or the like, for example.

The lead pins 142A, 142B, 142C include connecting

portions

146A, 146B, 146C and

terminal portions

148A, 148B, 148C. The connecting

portions

146A, 146B, and 146C are portions that protrude from the front surface 22A of the base 22, and the

terminal portions

148A, 148B, and 148C are portions that protrude from the back surface 22B of the base 22. The lengths of the connecting

portions

146A, 146B, and 146C are not particularly limited.

As shown in FIGS. 2 and 4, the lead pin 142D includes a connecting portion 146D and a terminal portion 148D. The connecting portion 146D is provided at one end of the terminal portion 148D and is joined to the back surface 22B of the base 22. Therefore, lead pin 142D is fixed to base 22. The lead pin 142D is fixed at a position overlapping the heat sink 24 when viewed in the thickness direction of the base 22. This lead pin 142D is electrically connected to the transistor 80 of the light emitting module 30A via the base 22 and the heat sink 24.

The

terminal portions

148A, 148B, 148C, and 148D of the lead pins 142A, 142B, 142C, and 142D are used for mounting the semiconductor light emitting device 10A on the drive board 910. The lengths of the

terminal portions

148A, 148B, 148C, and 148D are not particularly limited.

Here, the lengths of the

terminal portions

148A, 148B, 148C, and 148D when the semiconductor light emitting device 10A is mounted on the drive board 910 shown in FIG. Equivalent to. As this distance increases, the

terminal portions

148A, 148B, 148C, and 148D become longer, and the thermal resistance generated at the lead pins 142A, 142B, 142C, and 142D increases. Since such thermal resistance becomes a factor in increasing the temperature of the light emitting element 60, it is desirable that the distance between the back surface 22B of the base 22 and the drive board 910 be short.

As shown in FIG. 1,

connection portions

146A, 146B, 146C of lead pins 142A, 142B, 142C are electrically connected to light emitting module 30A by

wires

152A, 152B, 152C, respectively. For example, a metal material such as gold (Au) can be used for the

wires

152A, 152B, and 152C. In the first embodiment, the connecting portion 146A is electrically connected to the transistor 80 of the light emitting module 30A by, for example, two wires 152A. Note that the number of wires 152A may be one, or three or more. The connection portion 146B is electrically connected to the transistor 80 of the light emitting module 30A by, for example, one wire 152B. The connection portion 146C is electrically connected to an external element connection pad 160 provided on the substrate 50A of the light emitting module 30A by, for example, one wire 152C.

The external element connection pad 160 is used to connect an external element to the substrate 50A (light emitting module 30A). Note that in the first embodiment, the external element connected to the external element connection pad 160 is a Schottky barrier diode (SBD) 906 (see FIG. 12) provided on the drive board 910. As will be described later, the SBD 906 is connected in antiparallel to the light emitting element 60 and functions as a protection diode for the light emitting element 60, thereby suppressing reverse current from flowing through the light emitting element 60.

FIG. 6 is a plan view schematically showing the light emitting module 30A according to the first embodiment, and FIG. 7 is a perspective view of the light emitting module 30A. 8 and 9 are plan views showing the internal wiring structure of the substrate 50A of the light emitting module 30A. 10 is a cross-sectional view taken along line 10-10 in FIG. 6, and FIG. 11 is a cross-sectional view taken along line 11-11 in FIG.

As shown in FIG. 6, the substrate 50A has a rectangular shape. The size of the substrate 50A is not particularly limited. For example, the substrate 50A has a substantially square shape having a first side surface 52A and a second side surface 52B that are parallel to each other, and a third side surface 52C and a fourth side surface 52D that are parallel to each other and connect the first side surface 52A and the second side surface 52B. have. Note that the term "parallel" used in the present disclosure includes not only cases where two objects are completely parallel to each other, but also cases where two objects are not completely parallel but substantially parallel.

A light emitting element 60 that is a laser diode, a transistor 80 that drives the light emitting element 60, a first capacitor module 110, and a second capacitor module 120 are mounted on the substrate 50A. The light emitting element 60, the transistor 80, the first capacitor module 110, and the second capacitor module 120 each have a rectangular shape in a plan view of the substrate 50A. Note that in the present disclosure, a plan view of the substrate 50A means viewing the object in the thickness direction (Y-axis direction) of the substrate 50A.

(Light emitting element)
In the first embodiment, the light emitting element 60 has a first side surface 62A and a second side surface 62B that are parallel to each other, and a third side surface that is parallel to each other that connects the first side surface 62A and the second side surface 62B in a plan view of the substrate 50A. It has a rectangular shape having a fourth side surface 62C and a fourth side surface 62D. In the light emitting element 60, the third side surface 62C and the fourth side surface 62D are shorter than the first side surface 62A and the second side surface 62B. The light emitting element 60 is arranged such that the third side surface 62C of the light emitting element 60 is parallel to and adjacent to the third side surface 52C of the substrate 50A. The light emitting element 60 is disposed at a position closer to the third side surface 52C of the substrate 50A than the center of the substrate 50A in a plan view of the substrate 50A.

As shown in FIG. 6, the light emitting element 60 includes a light emitting end surface 64 at a position of the third side surface 62C of the light emitting element 60, and a light emitting end surface in a direction substantially perpendicular to the light emitting end surface 64 (approximately +Z direction). Laser light is emitted from 64.

As shown in FIGS. 7 and 10, the light emitting element 60 includes an anode electrode 66 provided on the front surface 60A of the light emitting element 60, and a cathode electrode 68 provided on the back surface 60B of the light emitting element 60. An electrode 68 is bonded to the substrate 50A.

(transistor)
As shown in FIG. 6, in the first embodiment, the transistor 80 has a first side surface 82A and a second side surface 82B that are parallel to each other, and a first side surface 82A and a second side surface 82B that are parallel to each other in a plan view of the substrate 50A. It has a rectangular shape with a third side surface 82C and a fourth side surface 82D that are connected and parallel to each other. In the transistor 80, the third side surface 82C and the fourth side surface 82D are shorter than the first side surface 82A and the second side surface 82B. The transistor 80 is arranged such that the fourth side surface 82D of the transistor 80 is parallel to and adjacent to the fourth side surface 52D of the substrate 50A. Further, the transistor 80 is arranged such that the third side surface 82C of the transistor 80 is parallel to and adjacent to the fourth side surface 62D of the light emitting element 60.

As shown in FIGS. 7 and 10, the transistor 80 implemented as a vertical MOSFET has a source electrode 84 provided on a part of the surface 80A of the transistor 80, and a source electrode 84 provided on a part of the surface 80A of the transistor 80. A gate electrode 86 (see FIG. 7) is provided. The source electrode 84 is formed to have a larger size than the gate electrode 86. Further, the transistor 80 includes a drain electrode 88 provided almost entirely on the back surface 80B of the transistor 80, and this drain electrode 88 is joined to the substrate 50A.

As shown in FIG. 6, the gate electrode 86 of the transistor 80 is electrically connected to the connection portion 146B of the lead pin 142B by a wire 152B. A control voltage for controlling switching of the transistor 80 is supplied to the gate electrode 86 from a gate driver 908 (see FIG. 12) provided on a drive substrate 910 shown in FIG. 5 via a lead pin 142B and a wire 152B.

The source electrode 84 of the transistor 80 is electrically connected to the connection portion 146A of the lead pin 142A by a wire 152A. A ground voltage is applied to the source electrode 84 from the drive board 910 via the lead pin 142A and the wire 152A.

Further, the source electrode 84 of the transistor 80 is electrically connected to the anode electrode 66 of the light emitting element 60 by a plurality of wires 190, for example, four wires 190 in the first embodiment. These wires 190 form a wiring path connecting the transistor 80 and the light emitting element 60, and when the transistor 80 is on, current flows from the transistor 80 to the light emitting element 60 via this wiring path. Therefore, by increasing the number of wires 190 to make it easier for current to flow from the transistor 80 to the light emitting element 60, it is possible to suppress the influence of parasitic inductance. For example, the number of wires 190 is set to be greater than the number of

wires

152A and 152B. Wire 190 may be a ribbon wire. Note that in the first embodiment, the

wires

152A and 152B correspond to the first wire, and the wire 190 corresponds to the second wire.

(capacitor module)
As shown in FIGS. 6, 7, and 11, the first capacitor module 110 and the second capacitor module 120 have a generally rectangular parallelepiped shape.

As shown in FIG. 6, the first capacitor module 110 has a first side surface 111A and a second side surface 111B that are parallel to each other, and a mutually parallel connection that connects the first side surface 111A and the second side surface 111B in a plan view of the substrate 50A. It has a rectangular shape with a third side surface 111C and a fourth side surface 111D. In the first capacitor module 110, the third side surface 111C and the fourth side surface 111D are shorter than the first side surface 111A and the second side surface 111B. In the first capacitor module 110, the first side surface 111A of the first capacitor module 110 is parallel to and adjacent to the first side surface 52A of the substrate 50A, and the third side surface 111C of the first capacitor module 110 is adjacent to the first side surface 52A of the substrate 50A. It is arranged parallel to and adjacent to the side surface 52C. Further, the first capacitor module 110 is arranged such that the second side surface 111B of the first capacitor module 110 is parallel to and adjacent to the first side surface 82A of the transistor 80.

As shown in FIGS. 6 and 11, the first capacitor module 110 has a first main surface 112A and a second main surface 112B that are parallel to each other. The first capacitor module 110 is arranged so that the first main surface 112A faces the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The first main surface 112A corresponds to the main surface facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The first capacitor module 110 includes a first connection electrode 113 and a second connection electrode 114 provided on the first main surface 112A. The first connection electrode 113 and the second connection electrode 114 are arranged apart from each other. The first connection electrode 113 and the second connection electrode 114 are arranged side by side in the length direction (+Z direction) of the first capacitor module 110. These first and

second connection electrodes

113, 114 are bonded to the substrate 50A.

The second connection electrode 114 of the first capacitor module 110 is electrically connected to the drain electrode 88 of the transistor 80 via the internal wiring structure of the substrate 50A. The first connection electrode 113 of the first capacitor module 110 is electrically connected to the cathode electrode 68 of the light emitting element 60 via the internal wiring structure of the substrate 50A.

The first capacitor module 110 includes a silicon capacitor 115, a connecting portion 118, and a sealing resin 119.
Silicon capacitor 115 includes a silicon substrate 116. As shown in FIG. 2, the silicon substrate 116 is formed into a rectangular plate shape when viewed from the top of the substrate 50A. As shown in FIG. 11, the silicon substrate 116 has a first surface 116A and a second surface 116B facing oppositely to each other. The silicon capacitor 115 has a first connection electrode 113 provided on a first surface 116A of a silicon substrate 116, and a counter electrode 117 provided on a second surface 116B. The counter electrode 117 faces the first connection electrode 113 with the silicon substrate 116 in between. The first connection electrode 113 is in contact with the first surface 116A of the silicon substrate 116. The counter electrode 117 is in contact with the second surface 116B of the silicon substrate 116. This silicon capacitor 115 is a capacitor in which two electrodes are a first connection electrode 113 and a counter electrode 117 disposed with a silicon substrate 116 in between, and the coupling between the first connection electrode 113 and the counter electrode 117 is It has a capacitance value of

The counter electrode 117 is electrically connected to the second connection electrode 114 by a connection part 118. The connecting portion 118 includes a first wiring 118A electrically connected to the counter electrode 117 and a second wiring 118B electrically connecting the first wiring 118A to the second connection electrode 114. The first wiring 118A extends in the length direction of the first capacitor module 110. The second wiring 118B is a via wiring formed on the sealing resin 119 and provided in an opening 119A that exposes a part of the second connection electrode 114. As shown in FIGS. 6 and 11, the first capacitor module 110 includes a plurality of second wirings 118B.

The first capacitor module 110 includes a sealing resin 119 that seals a silicon capacitor 115 (silicon substrate 116). The sealing resin 119 is formed to seal the silicon substrate 116 and the counter electrode 117 of the silicon capacitor 115, and the connection part 118, and to expose the lower surfaces of the first connection electrode 113 and the second connection electrode 114. .

As shown in FIG. 6, the second capacitor module 120 has a first side surface 121A and a second side surface 121B that are parallel to each other, and a mutually parallel connection that connects the first side surface 121A and the second side surface 121B in a plan view of the substrate 50A. It has a rectangular shape with a third side surface 121C and a fourth side surface 121D. In the second capacitor module 120, the third side surface 121C and the fourth side surface 121D are shorter than the first side surface 121A and the second side surface 121B. In the second capacitor module 120, the second side surface 121B of the second capacitor module 120 is adjacent to and parallel to the second side surface 52B of the substrate 50A, and the third side surface 121C of the second capacitor module 120 is adjacent to the second side surface 52B of the substrate 50A. It is arranged parallel to and adjacent to the side surface 52C. Further, the second capacitor module 120 is arranged such that the first side surface 121A of the second capacitor module 120 is parallel to and adjacent to the second side surface 82B of the transistor 80.

Since the second capacitor module 120 has the same configuration as the first capacitor module 110, a cross-sectional view of the second capacitor module 120 is omitted. The members constituting the second capacitor module 120 are shown in FIG.

The second capacitor module 120 has a first main surface 122A and a second main surface 122B that are parallel to each other. The second capacitor module 120 is arranged so that the first main surface 122A faces the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The first main surface 122A corresponds to the main surface facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A. The second capacitor module 120 includes a first connection electrode 123 and a second connection electrode 124 provided on the first main surface 122A. The first connection electrode 123 and the second connection electrode 124 are arranged apart from each other. The first connection electrode 123 and the second connection electrode 124 are arranged side by side in the length direction (+Z direction) of the second capacitor module 120. These first and

second connection electrodes

123, 124 are bonded to the substrate 50A.

The second connection electrode 124 of the second capacitor module 120 is electrically connected to the drain electrode 88 of the transistor 80 via the internal wiring structure of the substrate 50A. The first connection electrode 123 of the second capacitor module 120 is electrically connected to the cathode electrode 68 of the light emitting element 60 via the internal wiring structure of the substrate 50A.

The second capacitor module 120 includes a silicon capacitor 125, a connecting portion 128, and a sealing resin 129.
Silicon capacitor 125 includes a silicon substrate 126. As shown in FIG. 2, the silicon substrate 126 is formed into a rectangular plate shape when viewed from the top of the substrate 50A. Silicon substrate 126 has first and second surfaces facing oppositely to each other. Silicon capacitor 125 has a first connection electrode 123 provided on the first surface of silicon substrate 126 and a counter electrode 127 provided on the second surface. The counter electrode 127 faces the first connection electrode 123 with the silicon substrate 126 in between. The first connection electrode 123 is in contact with the first surface of the silicon substrate 126. The counter electrode 127 is in contact with the second surface of the silicon substrate 126. This silicon capacitor 125 is a capacitor in which two electrodes are a first connection electrode 123 and a counter electrode 127 arranged with a silicon substrate 126 in between, and the coupling between the first connection electrode 123 and the counter electrode 127 is It has a capacitance value of

The counter electrode 127 is electrically connected to the second connection electrode 124 by a connection part 128. The connecting portion 128 includes a first wiring 128A electrically connected to the counter electrode 127 and a second wiring 128B electrically connecting the first wiring 128A to the second connection electrode 124. The first wiring 128A extends in the length direction of the second capacitor module 120. As shown in FIG. 6, the second capacitor module 120 includes a plurality of second wirings 128B.

The second capacitor module 120 includes a sealing resin 129 that seals the silicon capacitor 125 (silicon substrate 126). The sealing resin 129 is formed to seal the silicon substrate 126 and the counter electrode 127 of the silicon capacitor 125, and the connection portion 128, and to expose the lower surfaces of the first connection electrode 123 and the second connection electrode 124. .

In this way, the first capacitor module 110 is placed adjacent to the first side surface 82A of the transistor 80, while the second capacitor module 120 is placed adjacent to the second side surface 82B of the transistor 80. This arrangement allows the third side surface 82C of the transistor 80 to be located between the first capacitor module 110 and the second capacitor module 120, so that the transistor 80 can be arranged close to the light emitting element 60. This makes it possible to shorten the distance between the transistor 80 and the light emitting element 60 on the substrate 50A. As a result, it is possible to reduce the length of the wiring path (wire 190) connecting the light emitting element 60 and the transistor 80, thereby suppressing the influence of parasitic inductance.

The first and

second capacitor modules

110 and 120 include

silicon capacitors

115 and 125, respectively. For example, multi-layered ceramic capacitors (MLCCs) are used as small capacitors in many electronic devices. A realized capacitor (capacitor) has a parasitic resistance (equivalent series resistance: ESR) and a parasitic inductance (equivalent series inductance: ESL) with respect to an ideal capacitor.

Silicon capacitors

115 and 125 have smaller parasitic inductance (ESL) than multilayer ceramic capacitors. The parasitic resistance (ESR) of a multilayer ceramic capacitor is about 100 mΩ, and the parasitic inductance (ESL) is about 0.3 to 0.4 nH. In contrast, the parasitic resistance (ESR) of the first and

second capacitor modules

110, 120 is preferably less than 100 mΩ, for example. Preferably, the parasitic inductance (ESL) of the first and

second capacitor modules

110, 120 is less than 100 pH.

Further, the first capacitor module 110 and the second capacitor module 120 are arranged symmetrically with respect to the light emitting element 60 and the transistor 80 on the substrate 50A. Thereby, a first wiring path through which current flows from the first capacitor module 110 to the light emitting element 60 via the transistor 80, and a second wiring path through which current flows from the second capacitor module 120 to the light emitting element 60 through the transistor 80. are arranged symmetrically with respect to the light emitting element 60 and the transistor 80.

As shown in FIGS. 10 and 11, the first and

second capacitor modules

110 and 120 are formed thicker than the light emitting element 60. On the other hand, the first and

second capacitor modules

110 and 120 are formed thinner than the transistor 80. The thickness of the first and

second capacitor modules

110 and 120 is 50 μm or more and 200 μm or less. The thickness of the first and

second capacitor modules

110, 120 is, for example, 160 μm. Note that the thickness of the multilayer ceramic capacitor having the capacitance used in the light emitting module 30A is, for example, about 500 μm.

Note that the first wiring path connects the second connection electrode 114 of the first capacitor module 110 and the drain electrode 88 of the transistor 80, and the source electrode 84 of the transistor 80 and the anode electrode 66 of the light emitting element 60. It includes a connecting wire 190 and a wiring path connecting the cathode electrode 68 of the light emitting element 60 and the first connection electrode 113 of the first capacitor module 110. These wiring paths are formed by the internal wiring structure of the substrate 50A.

Further, the second wiring path connects the second connection electrode 124 of the second capacitor module 120 and the drain electrode 88 of the transistor 80, and the source electrode 84 of the transistor 80 and the anode electrode 66 of the light emitting element 60. It includes a connecting wire 190 and a wiring path connecting the cathode electrode 68 of the light emitting element 60 and the first connection electrode 123 of the second capacitor module 120. These wiring paths are formed by the internal wiring structure of the substrate 50A.

By arranging the first wiring route and the second wiring route symmetrically in this way, the magnetic flux formed by the current flowing through the first wiring route and the magnetic flux formed by the current flowing through the second wiring route are separated. begin to cancel each other out. Thereby, the parasitic inductance existing in the first wiring route and the parasitic inductance existing in the second wiring route can be reduced.

(substrate)
Next, the structure of the substrate 50A of the light emitting module 30A will be explained.
As shown in FIGS. 6 to 11, the substrate 50A is, for example, a printed wiring board, and in the first embodiment has a two-layer wiring structure as an internal wiring structure. That is, the substrate 50A of the first embodiment is a double-sided substrate. The substrate 50A includes a base material 210 having insulating properties, a first wiring layer 220 provided on a front surface 212A of the base material 210, and a second wiring layer 230 provided on a back surface 212B of the base material 210. The base material 210 is formed of an insulating material such as a resin base material, a silicon base material, a glass base material, or a ceramic base material. That is, the substrate 50A can be a resin substrate, a silicon substrate, a glass substrate, a ceramic substrate, or the like. In the first embodiment, a resin base material made of glass epoxy resin is used as the base material 210. The first wiring layer 220 and the second wiring layer 230 are made of a metal material such as Cu.

Further, as shown in FIGS. 7 to 11, the substrate 50A includes a plurality of via wirings that penetrate the base material 210 and electrically connect the first wiring layer 220 and the second wiring layer 230. In this embodiment, a first via wiring 242, a plurality (for example, six) of second via wirings 244, and a third via wiring 246 are included. These first to third via

wirings

242, 244, and 246 are made of a metal material such as Cu.

The substrate 50A also includes a first insulating layer 250 provided on the front surface 220A of the first wiring layer 220 to partially expose the first wiring layer 220, and a second insulating layer 250 provided on the back surface 230B of the second wiring layer 230. and a second insulating layer 260 that partially exposes the wiring layer 230. The first insulating layer 250 and the second insulating layer 260 are made of an insulating resin such as epoxy resin or polyimide resin. Further, the first insulating layer 250 and the second insulating layer 260 may contain fillers such as silica and alumina. Note that, in order to make the illustration easier to understand, in FIG. 7, the base material 210, the first insulating layer 250, and the second insulating layer 260 are shown by virtual lines (two-dot chain lines).

FIG. 8 is a plan view showing the first wiring layer 220 and the base material 210. Note that in FIG. 8, illustration of the first insulating layer 250 is omitted.
As shown in FIG. 8, the first wiring layer 220 includes a plurality of wirings provided on the surface 212A of the base material 210 and spaced apart from each other; in the first embodiment, the first surface side wiring 310; It includes a second front side wiring 320 and a third front side wiring 330.

The first surface-side wiring 310 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50A, and has a size that is approximately 1/3 of the area of the substrate 50A, for example. ing. The first surface-side wiring 310 includes first to

third wiring regions

312, 314, and 316. Note that the first to

third wiring regions

312, 314, and 316 are each part of the first surface side wiring 310, and the physical boundaries of the first to

third wiring regions

312, 314, and 316 are on the first surface. It does not necessarily exist in the side wiring 310.

The first wiring area 312 is a light emitting element mounting area where the cathode electrode 68 of the light emitting element 60 is mounted. The second wiring area 314 is a part of the first capacitor mounting area where the first connection electrode 113 of the first capacitor module 110 is mounted. The third wiring area 316 is a part of the second capacitor mounting area where the first connection electrode 123 of the second capacitor module 120 is mounted. Therefore, the cathode electrode 68 of the light emitting element 60 is electrically connected to the

first connection electrodes

113 and 123 of the first and

second capacitor modules

110 and 120 via the first surface wiring 310. The second wiring area 314 and the third wiring area 316 are arranged symmetrically with respect to the first wiring area 312.

The second front-side wiring 320 is arranged along the first, second, and fourth side surfaces 52A, 52B, and 52D of the substrate 50A, and is spaced apart from the first front-side wiring 310. The second surface-side wiring 320 is formed to have a size slightly smaller than about ⅔ of the area of the substrate 50A, for example. The second front side wiring 320 includes fourth to

sixth wiring regions

322, 324, and 326. Note that the fourth to

sixth wiring regions

322, 324, and 326 are each part of the second surface side wiring 320, and the physical boundaries of the fourth to

sixth wiring regions

322, 324, and 326 are on the second surface. It does not necessarily exist in the side wiring 320.

The fourth wiring region 322 is a transistor mounting region where the drain electrode 88 of the transistor 80 is mounted. The fifth wiring area 324 is a part of the first capacitor mounting area where the second connection electrode 114 of the first capacitor module 110 is mounted. The sixth wiring area 326 is a part of the second capacitor mounting area where the second connection electrode 124 of the second capacitor module 120 is mounted. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the

second connection electrodes

114 and 124 of the first and

second capacitor modules

110 and 120 via the second surface side wiring 320. The fifth wiring area 324 and the sixth wiring area 326 are arranged symmetrically with respect to the fourth wiring area 322.

The second surface side wiring 320 further includes a notch 328. This notch 328 is formed at a position adjacent to the fourth wiring area 322 (transistor mounting area) and the fifth wiring area 324 (part of the first capacitor mounting area) of the second front side wiring 320.

The third front-side wiring 330 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50A, and is spaced apart from the second front-side wiring 320. In the first embodiment, the third front-side wiring 330 is arranged adjacent to (but spaced apart from) the notch 328 of the second front-side wiring 320. The total area of the second front-side wiring 320 and the third front-side wiring 330 corresponds to about 2/3 of the area of the substrate 50A. In other words, the second front-side wiring 320 and the third front-side wiring 330 are spaced apart from each other so that the combined shape of the second front-side wiring 320 and the third front-side wiring 330 is a rectangular shape having a size approximately 2/3 of the area of the substrate 50A. There is.

The third front side wiring 330 includes a seventh wiring region 332. Note that the seventh wiring region 332 is a part of the third front-side wiring 330, and the physical boundary of the seventh wiring region 332 does not exist in the third front-side wiring 330. The seventh wiring area 332 is an external element connection area for connecting an external element to the substrate 50A (light emitting element drive circuit 70), and the seventh wiring area 332 includes an external element connection pad 160 (see FIG. 6). is placed. In the first embodiment, the anode electrode 906A of the SBD 906 (see FIG. 12) is connected to the seventh wiring region 332 (external element connection pad 160) via the lead pin 142C and the wire 152C (see FIG. 6). .

The first insulating layer 250 has first to

seventh wiring regions

312, 314, 316, 322, 324, 326, and 332 of the first to third front side wirings 310, 320, and 330 that expose the first to

seventh wiring regions

312, 314, 316, 322, 324, 326, and 332, respectively. It includes openings 251 to 257 (see FIG. 6).

A first metal plating material 362 (Fig. 6, FIG. 7, FIG. 10, and FIG. 11) are provided. As the first metal plating material 362, for example, a laminate containing nickel (Ni) and gold (Au) or a laminate containing Ni, palladium (Pd), and Au can be used. As shown in FIG. 10, the cathode electrode 68 of the light emitting element 60 is bonded to the first metal plating material 362 in the first wiring area 312 (light emitting element mounting area) by a bonding member (not shown). Furthermore, the drain electrode 88 of the transistor 80 is bonded to the first metal plating material 362 in the fourth wiring area 322 (transistor mounting area) by a bonding member (not shown). Further, as shown in FIG. 11, the first and

second connection electrodes

113 and 114 of the first capacitor module 110 are connected to the fifth and second wiring areas 324 and 314 (first capacitor mounting area) by a bonding member (not shown). are respectively joined to the first metal plating material 362. Further, although a cross-sectional view is omitted, like the first capacitor module 110, the first and

second connection electrodes

123, 124 of the second capacitor module 120 are bonded to the sixth and

third wiring regions

326, 316 by a bonding material (not shown). They are respectively bonded to the first metal plating material 362 (second capacitor mounting area). As the bonding material, a silver (Ag) paste material or a solder paste material containing tin (Su)-silver (Ag)-copper (Cu) can be used. The bonding material may be changed depending on the member to be bonded to the first metal plating material 362. For example, Ag paste material can be used to bond the light emitting element 60. Moreover, a solder paste material or an Ag paste material can be used to join the transistor 80 and the first and

second capacitor modules

110 and 120.

The above-mentioned external element connection pad 160 (FIGS. 6 and 11) is provided in the seventh wiring region 332 exposed through the seventh opening 257 of the first insulating layer 250. This external element connection pad 160 is formed of a second metal plating material. As the second metal plating material, a laminate containing Ni and Au or a laminate containing Ni, Pd, and Au can be used.

FIG. 9 is a plan view showing the second wiring layer 230 and the second insulating layer 260. Note that in FIG. 9, illustration of the first insulating layer 250, the first wiring layer 220, and the base material 210 is omitted.
As shown in FIG. 9, the second wiring layer 230 includes a plurality of wirings provided on the back surface 212B (see FIG. 7) of the base material 210 and spaced apart from each other. It includes a side wiring 410 and a second back side wiring 420.

The first backside wiring 410 is arranged along the first, second, third, and fourth side surfaces 52A, 52B, 52C, and 52D of the substrate 50A. The first back side wiring 410 is formed in a substantially gate shape, and an opening 410A is defined inside the first back side wiring 410 in plan view. The opening 410A is formed at a position corresponding to the fourth wiring area 322 (transistor mounting area) of the second front side wiring 320 in a plan view of the substrate 50A, and has a larger size than the fourth wiring area 322. are doing. The first back side wiring 410 overlaps with the first and third front side wirings 310, 330 and partially overlaps with the second front side wiring 320 in a plan view of the substrate 50A.

The second back side wiring 420 is arranged inside the opening 410A of the first back side wiring 410 along the fourth side surface 52D of the substrate 50A. The second back side wiring 420 includes an eighth wiring region 414. Note that the eighth wiring region 414 is a part of the second backside wiring 420, and the physical boundary of the eighth wiring region 414 does not exist in the second backside wiring 420. The eighth wiring region 414 is a transistor connection region for electrically connecting the drain electrode 88 of the transistor 80 to the heat sink 24 (see, for example, FIG. 1). The second back side wiring 420 overlaps with the second front side wiring 320 in a plan view of the substrate 50A.

The second insulating layer 260 includes an eighth opening 258 that exposes the eighth wiring region 414 (transistor connection region) of the second back side wiring 420. As shown in FIG. 10, a third metal plating material 364 is provided in the eighth wiring region 414 exposed from the eighth opening 258. As the third metal plating material 364, for example, a laminate containing Ni and Au or a laminate containing Ni, Pd, and Au can be used. The third metal plating material 364 is bonded to the heat sink 24 by a bonding material (not shown). As this bonding material, Ag paste material or solder paste material can be used.

Note that the second insulating layer 260 covers the back surface 230B of the second wiring layer 230 except for the eighth wiring region 414 (transistor connection region). Therefore, the first back side wiring 410 is not exposed from the second insulating layer 260 and is not electrically connected to the heat sink 24.

As shown in FIGS. 7 to 11, the first wiring layer 220 and the second wiring layer 230 are electrically connected by the above-mentioned first to third via

wirings

242, 244, and 246 that penetrate the base material 210. ing. In the first embodiment, each via

wiring

242, 244, 246 is formed, for example, in a cylindrical shape, but the shape is not particularly limited. These via

wirings

242, 244, and 246 are so-called thermal vias, and function as conductive paths between the first wiring layer 220 and the second wiring layer 230, as well as from the first wiring layer 220 to the second wiring layer 230. functions as a heat dissipation path.

The first via wiring 242 is located within the first wiring area 312 (light emitting element mounting area) and electrically connects the first front side wiring 310 and the first back side wiring 410. Therefore, the cathode electrode 68 of the light emitting element 60 and the

first connection electrodes

113, 123 of the first and

second capacitor modules

110, 120 are connected to the first back side via the first front side wiring 310 and the first via wiring 242. It is electrically connected to wiring 410.

The second via wiring 244 is located within the fourth wiring area 322 (transistor mounting area) and the eighth wiring area 414 (transistor mounting area), and is connected to the second front wiring 320 and the second back wiring 420. Connect electrically. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the heat sink 24 of the stem 20 via the second front wiring 320, the second via wiring 244, and the second back wiring 420. Further, the drain electrode 88 of the transistor 80 is electrically connected to the

second connection electrodes

114 and 124 of the first and

second capacitor modules

110 and 120 via the second surface side wiring 320. Note that the arrangement of the second via wiring 244 is not particularly limited. For example, the second via wiring 244 is evenly arranged within the fourth and

eighth wiring regions

322 and 414. In the first embodiment, for example, the second via wiring 244 is arranged in a 2×3 array.

The third via wiring 246 electrically connects the third front side wiring 330 and the first back side wiring 410. Therefore, the anode electrode 906A of the SBD 906 (see FIG. 12) connected to the external element connection pad 160 is connected to the third surface wiring 330, the third via wiring 246, the first back wiring 410, the first via wiring 242, and It is electrically connected to the

first connection electrodes

113 and 123 of the first and

second capacitor modules

110 and 120 via the first surface side wiring 310. Further, since the

first connection electrodes

113 and 123 of the first and

second capacitor modules

110 and 120 are electrically connected to the cathode electrode 68 of the light emitting element 60, the anode electrode 906A of the SBD 906 is connected to the cathode electrode 68 of the light emitting element 60. It is also electrically connected to electrode 68.

(Electrical configuration of semiconductor light emitting device)
FIG. 12 is a circuit diagram schematically showing the electrical configuration of the semiconductor light emitting device 10A.
The light emitting element drive circuit 70 includes a light emitting element 60, a transistor 80 (vertical MOSFET), a first capacitor module 110, and a second capacitor module 120, which are mounted on the substrate 50A of the light emitting module 30A. Note that in FIG. 12, the first capacitor module 110 and the second capacitor module 120 are shown as one capacitor.

The drain electrode 88 of the transistor 80 is connected to the

second connection electrodes

114, 124 of the first and

second capacitor modules

110, 120. The drain electrode 88 of the transistor 80 and the

second connection electrodes

114, 124 of the first and

second capacitor modules

110, 120 are connected to a positive electrode 904A of a constant voltage source 904 via a resistance element 902. A negative pole 904B of this constant voltage source 904 is connected to ground. In the first embodiment, the constant voltage source 904 and the resistance element 902 are provided on a drive board 910 (see FIG. 5). Then, the voltage from the constant voltage source 904 is applied to the drain of the transistor 80 via the resistance element 902, the lead pin 142D (see FIGS. 1 and 2), the base 22 and heat sink 24 of the stem 20, and the internal wiring structure of the substrate 50A. The voltage is applied to the electrode 88 and the

second connection electrodes

114, 124 of the first and

second capacitor modules

110, 120.

A source electrode 84 of the transistor 80 is connected to the anode electrode 66 of the light emitting element 60 and to ground. In the first embodiment, a ground voltage is applied from the drive substrate 910 to the source electrode 84 of the transistor 80 via the lead pin 142A (see FIGS. 1 and 2) and the wire 152A. Further, the source electrode 84 of the transistor 80 is connected to the anode electrode 66 of the light emitting element 60 via a wire 190 (see FIGS. 1 and 2).

The gate electrode 86 of the transistor 80 is connected to a gate driver 908 provided on a drive substrate 910. In the first embodiment, a control voltage is supplied from the gate driver 908 to the gate electrode 86 of the transistor 80 via the lead pin 142B (see FIGS. 1 and 6) and the wire 152B, and the on/off of the transistor 80 is controlled by this control voltage. be done.

The cathode electrode 68 of the light emitting element 60 is connected to the

first connection electrodes

113 and 123 of the first and

second capacitor modules

110 and 120. In the first embodiment, the cathode electrode 68 of the light emitting element 60 is connected to the

first connection electrodes

113, 123 of the first and

second capacitor modules

110, 120 via the internal wiring structure of the substrate 50A.

Furthermore, the cathode electrode 68 of the light emitting element 60 and the

first connection electrodes

113 and 123 of the first and

second capacitor modules

110 and 120 are connected to the anode electrode 906A of the SBD 906. In the first embodiment, the SBD 906 is provided on a drive board 910, and an anode electrode 906A of the SBD 906 is connected to an external element connection pad 160 via a lead pin 142C (see FIGS. 1 and 2) and a wire 152C. This external element connection pad 160 is connected to the cathode electrode 68 of the light emitting element 60 and the

first connection electrodes

113, 123 of the first and

second capacitor modules

110, 120 via the internal wiring structure of the substrate 50A.

A cathode electrode 906B of the SBD 906 is connected to a negative electrode 904B of a constant voltage source 904. In the first embodiment, the cathode electrode 906B of the SBD 906 is connected to the anode electrode 66 of the light emitting element 60 via the lead pin 142A (see FIGS. 1 and 2), the wire 152A, the source electrode 84 of the transistor 80, and the wire 190. It is connected to the.

When the transistor 80 is turned off by the control voltage from the gate driver 908, a closed loop circuit is formed by the constant voltage source 904, the resistance element 902, the first and

second capacitor modules

110, 120, and the SBD 906. As a result, the first and

second capacitor modules

110 and 120 are charged based on the voltage supplied from the constant voltage source 904.

When the transistor 80 is turned on by the control voltage from the gate driver 908, a closed loop circuit is formed by the transistor 80, the light emitting element 60, and the first and

second capacitor modules

110 and 120. As a result, a current (pulse current) based on the charges accumulated in the first and

second capacitor modules

110 and 120 flows to the light emitting element 60 via the transistor 80, so that a laser beam is emitted from the light emitting element 60.

(effect)
Next, the operation of the semiconductor light emitting device 10A of the first embodiment will be explained.
The semiconductor light emitting device 10A includes a substrate 50A, a light emitting element 60, a transistor 80, a first capacitor module 110, and a second capacitor module 120 mounted on the substrate 50A. The first capacitor module 110 has a first main surface 112A facing the substrate 50A, and a first connection electrode 113 and a second connection electrode 114 provided on the first main surface 112A, and has an electrical connection to the light emitting element 60. It is connected to the. The second capacitor module 120 has a first main surface 122A facing the substrate 50A, and a first connection electrode 123 and a second connection electrode 124 provided on the first main surface 122A, and has an electrical connection to the light emitting element 60. It is connected to the. The first capacitor module 110 includes a silicon substrate 116 having a first surface 116A and a second surface 116B facing opposite to each other, a first connection electrode 113 provided on the first surface 116A, and a first connection electrode 113 provided on the second surface 116B. , and a counter electrode 117 facing the first connection electrode 113. The second capacitor module 120 includes a silicon substrate 126 having a first surface and a second surface facing opposite to each other, a first connection electrode 123 provided on the first surface, and a first connection electrode 123 provided on the second surface. A counter electrode 127 facing the electrode 123 is included.

The first capacitor module 110 includes a silicon capacitor 115 composed of a silicon substrate 116, a first connection electrode 113, and a counter electrode 117. The second capacitor module 120 includes a silicon capacitor 125 that includes a silicon substrate 126 , a first connection electrode 123 , and a counter electrode 127 . The

silicon capacitors

115 and 125 have smaller parasitic inductance (ESL) than multilayer ceramic capacitors used as small capacitors. Therefore, parasitic inductance in the first and second wiring paths for the light emitting element 60 can be reduced.

The parasitic inductance that occurs in the first and second wiring paths affects the rise and fall characteristics of the pulse current supplied to the light emitting element 60. The larger the parasitic inductance, the slower the pulse current rises and falls. Therefore, by reducing the parasitic inductance, the rise and fall of the pulse current can be made steeper. The pulse current affects the output characteristics of the light emitting element 60, that is, the rise and fall characteristics of the optical output of the semiconductor light emitting device 10A. Therefore, by reducing the parasitic inductance, the rise and fall of the optical output can be made steeper. Thereby, optical output with a shorter pulse width can be obtained.

FIG. 13 is a cross-sectional view of a light emitting module of a comparative example at a position corresponding to FIG. 11. In FIG. 13, only the silicon capacitor 115 is mounted on the substrate 50A. The counter electrode 117 of the silicon capacitor 115 is electrically connected to the second surface wiring 320 (fifth wiring region 324) by a wire 191. As described above, the silicon capacitor 115 has lower resistance and lower inductance than a multilayer ceramic capacitor. However, in this comparative example, the parasitic inductance in the wire 191 connecting the silicon capacitor 115 to the second surface-side wiring 320 is the same as the parasitic inductance in the connecting

portions

118 and 128 of the first and

second capacitor modules

110 and 120 in the first embodiment. greater than inductance. Therefore, in this comparative example, it can be said that there is little merit in using the silicon capacitor 115.

The light emitting module 30A is mounted on the heat sink 24 of the stem 20, and the surrounding member 40 is provided on the base 22 of the stem 20 so as to surround the light emitting module 30A and the heat sink 24. The light emitting module 30A includes a light emitting element 60 and a light emitting element drive circuit 70, and the light emitting element drive circuit 70 includes a transistor 80 that drives the light emitting element 60. The transistor 80 is mounted as a vertical MOSFET on the substrate 50A mounted on the heat sink 24.

By employing a vertical MOSFET as the transistor 80, the source electrode 84 is arranged to overlap the drain electrode 88 in a plan view of the substrate 50A. Therefore, by employing a vertical MOSFET, the wiring path of the transistor 80 mounted on the substrate 50A can be made shorter than when a horizontal MOSFET is employed. As a result, the size of the substrate 50A can be reduced and the size of the light emitting module 30A can be reduced.

(effect)
According to the semiconductor light emitting device 10A of the first embodiment, the following effects can be obtained.
(1-1) The semiconductor light emitting device 10A includes a substrate 50A, a light emitting element 60, a transistor 80, a first capacitor module 110, and a second capacitor module 120 mounted on the substrate 50A. The first capacitor module 110 includes a first main surface 112A facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A, and a first connection electrode 113 and a second connection electrode provided on the first main surface 112A. 114 and is electrically connected to the light emitting element 60. The second capacitor module 120 includes a first main surface 122A facing the substrate 50A in the thickness direction (Y-axis direction) of the substrate 50A, and a first connection electrode 123 and a second connection electrode provided on the first main surface 122A. 124 and is electrically connected to the light emitting element 60. The first capacitor module 110 includes a silicon substrate 116 having a first surface 116A and a second surface 116B facing opposite to each other, a first connection electrode 113 provided on the first surface 116A, and a first connection electrode 113 provided on the second surface 116B. , and a counter electrode 117 facing the first connection electrode 113. The second capacitor module 120 includes a silicon substrate 126 having a first surface and a second surface facing opposite to each other, a first connection electrode 123 provided on the first surface, and a first connection electrode 123 provided on the second surface. A counter electrode 127 facing the electrode 123 is included.

According to this configuration, the parasitic inductance (ESL) in the first and

second capacitor modules

110 and 120 can be made smaller than, for example, the parasitic inductance of a multilayer ceramic capacitor. Therefore, parasitic inductance occurring in the wiring path between the cathode electrode 68 of the light emitting element 60 and the transistor 80 can be reduced. Therefore, parasitic inductance in the wiring path connecting the light emitting element 60 and the transistor 80 can be reduced.

(1-2) Parasitic inductance occurring in the wiring path affects the rise and fall characteristics of the pulse current supplied to the light emitting element 60. The larger the parasitic inductance, the slower the pulse current rises and falls. Therefore, by reducing the parasitic inductance, the rise and fall of the pulse current can be made steeper. The pulse current affects the output characteristics of the light emitting element 60, that is, the rise and fall characteristics of the optical output of the semiconductor light emitting device 10A. Therefore, by reducing the parasitic inductance, the rise and fall of the optical output can be made steeper. Thereby, optical output with a shorter pulse width can be obtained.

(1-3) By employing a vertical MOSFET as the transistor 80, current flows from the first and

second capacitor modules

110 and 120 to the light emitting element 60 via the transistor 80, compared to the case where a horizontal MOSFET is employed. Each wiring route can be shortened. Thereby, parasitic inductance occurring in each wiring route can be reduced.

(1-4) The first capacitor module 110 is mounted on the substrate 50A adjacent to the first side surface 82A of the transistor 80 when the substrate 50A is viewed from above. The second capacitor module 120 is mounted on the substrate 50A adjacent to the second side surface 82B of the transistor 80 in a plan view of the substrate 50A. Therefore, the third side surface 82C of the transistor 80 is located between the first capacitor module 110 and the second capacitor module 120. The light emitting element 60 is disposed adjacent to the third side surface 82C of the transistor 80 and is electrically connected to the transistor 80 by a plurality of wires 190. With this configuration, the transistor 80 can be placed close to the light emitting element 60. Thereby, by shortening the length of the wire 190 and shortening the wiring path through which current flows from the transistor 80 to the light emitting element 60, parasitic inductance occurring in the wiring path can be reduced.

(1-5) The first capacitor module 110 and the second capacitor module 120 are arranged symmetrically with respect to the light emitting element 60 and the transistor 80. As a result, current flows from the first wiring path from the first capacitor module 110 to the light emitting element 60 via the transistor 80 and the wire 190, and from the second capacitor module 120 to the light emitting element 60 via the transistor 80 and the wire 190. The flowing second wiring path is arranged symmetrically with respect to the light emitting element 60 and the transistor 80. In this arrangement, the magnetic flux formed by the current flowing through the first wiring path and the magnetic flux formed by the current flowing through the second wiring path cancel each other out. Thereby, the parasitic inductance existing in the first wiring route and the parasitic inductance existing in the second wiring route can be reduced.

(1-6) The light emitting element drive circuit 70 supplies current to the light emitting element 60 using the first capacitor module 110 and the second capacitor module 120. With this configuration, the current supplied to the light emitting element 60 can be increased.

(1-7) The third side surface 82C of the transistor 80 is shorter than the first side surface 82A and the second side surface 82B of the transistor 80. Further, the distance between the first capacitor module 110 and the second capacitor module 120 is greater than the length of the third side surface 82C of the transistor 80. According to this configuration, the short side (third side surface 82C) of the transistor 80 is located between the first and

second capacitor modules

110 and 120. Thereby, each wiring path through which current flows from the first and

second capacitor modules

110 and 120 to the light emitting element 60 via the transistor 80 can be shortened, and parasitic inductance occurring in each wiring path can be reduced.

(1-8) The number of wires 190 connecting transistor 80 and light emitting element 60 is greater than the number of

wires

152A, 152B connecting transistor 80 and

lead pins

142A, 142B. Thereby, current can easily flow from the transistor 80 to the light emitting element 60, and parasitic inductance can be reduced.

(1-9) The first via wiring 242 is arranged only in the first wiring area 312 (light emitting element mounting area) directly below the light emitting element 60. The first via wiring 242 is a part of the wiring route that connects the cathode electrode 68 of the light emitting element 60 to the external element connection pad 160, and electrically connects the first front side wiring 310 and the first back side wiring 410. do. Here, if a plurality of first via wirings 242 are arranged outside the first wiring area 312, the first and

second capacitor modules

110, 120 are connected from the cathode electrode 68 of the light emitting element 60 via the first surface side wiring 310. The flow of current to the

first connection electrodes

113 and 123 may be inhibited. As a result, when the number of first via wirings 242 is increased, current flows from the

second connection electrodes

114, 124 of the first and

second capacitor modules

110, 120 to the light emitting element 60 via the transistor 80 and the wire 190. is inhibited. In the first embodiment, only one first via wiring 242 is arranged in the first wiring region 312 directly below the light emitting element 60. Therefore, the flow of current to the light emitting element 60 is prevented from being obstructed by the first via wiring 242.

(Example of modification of the first embodiment)
The first embodiment described above can be modified as follows, for example. The above embodiment and each modification example below can be combined with each other as long as no technical contradiction occurs. In addition, in the following modified examples, parts common to the above embodiment are given the same reference numerals as in the above embodiment, and the explanation thereof will be omitted.

- The configurations of the first and

second capacitor modules

110 and 120 may be changed as appropriate.
14 to 16 show a light emitting module including a capacitor module 110A of a modified example, and are sectional views at a position corresponding to FIG. 11 of the first embodiment.

As shown in FIG. 14, the capacitor module 110A includes a silicon substrate 116, a first connection electrode 113, a second connection electrode 114, a counter electrode 117, and a connection portion 118. The first connection electrode 113 connects an electrode 113A provided on the first main surface 112A, a second opposing electrode 113B provided on the second surface 116B of the silicon substrate 116, and connects the electrode 113A and the second opposing electrode 113B. via wiring 113C. With this capacitor module 110A, parasitic inductance can be reduced similarly to the first embodiment described above.

As shown in FIG. 15, in the capacitor module 110B, the sealing resin 119 has a first opening 119B that exposes a part of the counter electrode 117, and a plurality of second openings that expose a part of the second connection electrode 114. 119C. The first wiring 118A and the second wiring 118B of the connection portion 118 are continuously formed along the upper surface of the sealing resin 119. In other words, the first wiring 118A is constituted by a conductive film formed on the first surface 119D of the sealing resin 119 and the inner wall surface of the first opening 119B. The second wiring 118B is composed of a conductive film formed on the inner wall surface of the plurality of second openings 119C of the sealing resin 119. With this capacitor module 110B, parasitic inductance can be reduced similarly to the first embodiment described above.

As shown in FIG. 16, the capacitor module 110C includes a silicon substrate 116, a first connection electrode 113, a second connection electrode 114, and a connection portion 118. This capacitor module 110C does not include the sealing resin 119 shown in FIG. 11.

The first connection electrode 113 and the second connection electrode 114 are arranged on the first surface 116A of the silicon substrate 116 so as to be separated from each other in the length direction of the silicon substrate 116. The connection portion 118 is provided on the second surface 116B of the silicon substrate 116 and includes a counter electrode 117 that faces the first connection electrode 113. The silicon substrate 116 has a plurality of through holes 116C that penetrate the silicon substrate 116 from the first surface 116A to the second surface 116B. The connecting portion 118 includes a first wiring 118A formed on the second surface 116B of the silicon substrate 116 and a second wiring formed in the plurality of through holes 116C to connect the first wiring 118A and the second connection electrode 114. 118B. The second wiring 118B is a through wiring that penetrates the silicon substrate 116. With this capacitor module 110C, parasitic inductance can be reduced similarly to the first embodiment described above.

- The configuration of the substrate 50A may be changed as appropriate.
17 to 21 show a light emitting module 30A1 as a modified example, and use a modified substrate 50A1. 18 to 20 are cross-sectional views showing the internal wiring structure of the substrate 50A1. 21 is a cross-sectional view of FIG. 17 taken along line 21-21 of FIG. 18.

As shown in FIGS. 17 to 21, the substrate 50A1 of the light emitting module 30A1 is, for example, a printed wiring board, and in this modified example, has a three-layer wiring structure as an internal wiring structure. In other words, the substrate 50A1 of this modification is a multilayer substrate.

The substrate 50A1 includes an insulating first base material 210A, a first wiring layer 220 provided on a surface 214A of the first base material 210A, an insulating second base material 210B, and a back surface of the second base material 210B. 216B. Further, the substrate 50A1 includes an intermediate wiring layer 240 provided on the back surface 214B of the first base material 210A and on the front surface 216A of the second base material 210B.

That is, in this modification example, the base material 210 of the first embodiment is divided into a first base material 210A and a second base material 210B, and an intermediate wiring layer is provided between the first base material 210A and the second base material 210B. 240 is located. Therefore, the substrate 50A1 of this modification can be said to have a configuration in which the intermediate wiring layer 240 is located inside the base material 210 of the first embodiment. The intermediate wiring layer 240, like the first and second wiring layers 220 and 230, is made of a metal material such as Cu.

The first base material 210A and the second base material 210B are formed of an insulating material such as a resin base material, a silicon base material, a glass base material, or a ceramic base material. In this modification, resin base materials made of glass epoxy resin are used as the first base material 210A and the second base material 210B.

The configuration of the first wiring layer 220 and the configuration of the second wiring layer 230 are similar to those in the first embodiment. Therefore, as shown in FIG. 18, the first wiring layer 220 includes first to third front-

side wirings

310, 320, and 330. The first surface side wiring 310 includes first to

third wiring regions

312, 314, 316, the second surface side wiring 320 includes fourth to

sixth wiring regions

322, 324, 326, and the third surface side wiring 330 includes a seventh wiring region 332. Further, as shown in FIG. 20, the second wiring layer 230 includes first and second backside wirings 410 and 420, and the second backside wiring 420 includes an eighth wiring region 414.

As shown in FIG. 19, the intermediate wiring layer 240 includes a first intermediate wiring 510, a second intermediate wiring 520, and a third intermediate wiring 530.
The first intermediate wiring 510 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50A1, and is formed to have a size that is approximately 1/3 of the area of the substrate 50A1, for example. There is. The first intermediate wiring 510 overlaps the first front wiring 310 and the first back wiring 410 in a plan view of the substrate 50A1.

The second intermediate wiring 520 is arranged along the first, second, and fourth side surfaces 52A, 52B, and 52D of the substrate 50A1, and is spaced apart from the first intermediate wiring 510. The second intermediate wiring 520 is formed to have a size slightly smaller than, for example, about 2/3 of the area of the substrate 50A1. In this modification example, the second intermediate wiring 520 is formed to have the same size and shape as the first front wiring 310, for example, and has a notch at the same position as the first front wiring 310 in a plan view of the substrate 50A1. 522 included. The second intermediate wiring 520 overlaps with the second front wiring 320 and the second back wiring 420, and partially overlaps with the first back wiring 410, in a plan view of the substrate 50A1.

The third intermediate wiring 530 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50A1, and is spaced apart from the second intermediate wiring 520. In this modification example, the third intermediate wiring 530 is formed, for example, in the same size and shape as the third front side wiring 330, and is adjacent to (but separated from) the notch 522 of the second intermediate wiring 520. It is located. The total area of the second intermediate wiring 520 and the third intermediate wiring 530 corresponds to about 2/3 of the area of the substrate 50A1. In other words, the second intermediate wiring 520 and the third intermediate wiring 530 are spaced apart from each other so that the combined shape of the second intermediate wiring 520 and the third intermediate wiring 530 is a rectangular shape having a size approximately 2/3 of the area of the substrate 50A1. The third intermediate wiring 530 overlaps the third front side wiring 330 and the first back side wiring 410 in a plan view of the substrate 50A1.

Similar to the first embodiment, the substrate 50A1 includes a first insulating layer 250 and a second insulating layer 260. The configuration of the first insulating layer 250 and the configuration of the second insulating layer 260 are the same as those in the first embodiment, and detailed description thereof will be omitted.

Further, as shown in FIGS. 17 to 21, similarly to the first embodiment, the substrate 50A1 penetrates through the first and

second base materials

210A and 210B, and connects the first wiring layer 220 and the second wiring layer 230. It includes first to third via

wirings

242, 244, and 246 that electrically connect these. In this modification, the first via wiring 242 electrically connects the first front wiring 310, the first intermediate wiring 510, and the first back wiring 410. The second via wiring 244 electrically connects the second front side wiring 320, the second intermediate wiring 520, and the second back side wiring 420. The third via wiring 246 electrically connects the third front side wiring 330, the third intermediate wiring 530, and the first back side wiring 410.

As shown in FIG. 17 and FIGS. 19 to 21, the substrate 50A1 further includes a plurality of (for example, four) fourth via wires 248 that electrically connect the first intermediate wire 510 and the first back side wire 410. including. The fourth via wiring 248 is made of a metal material such as Cu. Note that the arrangement of the fourth via wiring 248 is not particularly limited. For example, the fourth via wiring 248 is evenly arranged within the first intermediate wiring 510 except for the position of the first via wiring 242. In this modification, for example, the fourth via wiring 248 and the first via wiring 242 are arranged in a line.

In the substrate 50A1 of this modification, the light emitting element 60 is small. Therefore, the area of the first wiring region 312 (light emitting element mounting region) in which the light emitting element 60 is mounted is small. Therefore, there is a limit to the number of first via wirings 242 that can be arranged within the first wiring area 312, and as in the first embodiment, in this modified example as well, the first via wirings 242 are Only one is arranged in one wiring area 312. Therefore, similar to the advantage (1-9) obtained in the first embodiment described above, in this modification example as well, the flow of current to the light emitting element 60 is suppressed from being obstructed by the first via wiring 242. Ru. In this modification, the first via wiring 242 electrically connects the first front wiring 310, the first intermediate wiring 510, and the first back wiring 410. This first via wiring 242 is also used as a heat radiation path. However, when the number of first via wiring 242 is only one, there is a possibility that sufficient heat dissipation performance using first via wiring 242 cannot be obtained. In this modification, the substrate 50A1 of the light emitting module 30A1 includes a plurality (for example, four) of fourth via wires 248 that connect the first intermediate wire 510 and the first back side wire 410. These fourth via wirings 248 do not inhibit the flow of current to the light emitting element 60 as described above, and can improve heat dissipation.

(Second embodiment)
The configuration of the semiconductor light emitting device 10B of the second embodiment will be described below. In addition, regarding the semiconductor light emitting device 10B of the second embodiment, the same reference numerals are used for components common to the semiconductor light emitting device 10A of the first embodiment.

FIG. 22 is a perspective view schematically showing an exemplary semiconductor light emitting device 10B according to the second embodiment. FIG. 23 is a plan view schematically showing the semiconductor light emitting device of FIG. 22. FIG. 24 is a plan view showing the internal wiring structure of the substrate of the light emitting module of FIG. 22. FIG. 25 is a plan view showing the internal wiring structure of the substrate of the light emitting module of FIG. 22. FIG. 26 is a cross-sectional view taken along line 26-26 in FIG. 23. FIG. 27 is a cross-sectional view taken along line 27-27 in FIG. 23. Note that in FIG. 23, the sealing resin 90 is omitted for convenience of explanation. In FIGS. 26 and 27, the sealing resin 90 is indicated by a two-dot chain line. In FIGS. 26 and 27,

wires

190, 152A, and 152B are omitted for convenience of explanation.

The semiconductor light emitting device 10B of the second embodiment is a surface-mounted device. Therefore, the stem 20 and the like of the semiconductor light emitting device 10A of the first embodiment are not provided. Further, the semiconductor light emitting device 10B of the second embodiment differs from the semiconductor light emitting device 10A of the first embodiment in that the structure of the substrate 50B is different and that the semiconductor light emitting device 10B is provided with a sealing resin 90. These points will be explained in detail below.

As shown in FIG. 22, the semiconductor light emitting device 10B has a generally rectangular plate shape. The semiconductor light emitting device 10B includes a light emitting module 30B and a sealing resin 90.
The light emitting module 30B includes a substrate 50B, a light emitting element 60, and a light emitting element drive circuit 70.

(substrate)
As shown in FIGS. 23 to 27, the substrate 50B has a rectangular shape. The size of the substrate 50B is not particularly limited. The substrate 50B of the second embodiment has a rectangular shape in which the first side surface 52A and the second side surface 52B are longer than the third side surface 52C and the fourth side surface 52D.

As shown in FIG. 24, the first wiring layer 220 includes a plurality of wirings provided on the surface 212A of the base material 210 and spaced apart from each other; in the second embodiment, the first surface side wiring 310; It includes a second front-side wiring 320, a third front-side wiring 340, and a fourth front-side wiring 350.

The first surface-side wiring 310 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50B, and has a size that is approximately 1/3 of the area of the substrate 50B, for example. ing. The first surface-side wiring 310 includes first to

third wiring regions

312, 314, and 316. Note that the first to

third wiring regions

The first wiring area 312 is a light emitting element mounting area where the cathode electrode 68 of the light emitting element 60 is mounted. The second wiring area 314 is a part of the first capacitor mounting area where the second connection electrode 114 of the first capacitor module 110 is mounted. The third wiring area 316 is a part of the second capacitor mounting area where the second connection electrode 124 of the second capacitor module 120 is mounted. Therefore, the cathode electrode 68 of the light emitting element 60 is electrically connected to the

second connection electrodes

114 and 124 of the first and

second capacitor modules

The second surface-side wiring 320 is arranged at a central portion of the substrate 50B, that is, a central portion between the third side surface 52C and the fourth side surface 52D of the substrate 50B.
The second front-side wiring 320 is arranged along the first and second side surfaces 52A and 52B of the substrate 50B, and is spaced apart from the first front-side wiring 310. The second surface-side wiring 320 is formed to have a size slightly larger than, for example, about 1/2 of the area of the substrate 50B. The second front side wiring 320 includes fourth to

sixth wiring regions

322, 324, and 326. Note that the fourth to

sixth wiring regions

second connection electrodes

114 and 124 of the first and

second capacitor modules

The third front-side wiring 340 and the fourth front-side wiring 350 are arranged side by side along the fourth side surface 52D of the substrate 50B and spaced apart from each other.
The third front-side wiring 340 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50B, and is spaced apart from the second front-side wiring 320. The third front-side wiring 340 includes a seventh wiring region 342. Note that the seventh wiring region 342 is a part of the third front-side wiring 340, and a physical boundary of the seventh wiring region 342 does not exist in the third front-side wiring 340. In the seventh wiring region 342, connection pads 162 (see FIGS. 23, 26, and 27) are arranged. Note that in the second embodiment, the gate electrode 86 of the transistor 80 is connected to the seventh wiring region 342 (connection pad 162) via a wire 152B (see FIG. 23).

The fourth front-side wiring 350 is arranged along the second and fourth side surfaces 52B and 52D of the substrate 50B, and is spaced apart from the second front-side wiring 320. The fourth surface-side wiring 350 includes an eighth wiring region 352. Note that the eighth wiring region 352 is a part of the fourth front-side wiring 350, and the physical boundary of the eighth wiring region 352 does not exist in the fourth front-side wiring 350. In the eighth wiring region 352, connection pads 164 (see FIG. 23) are arranged. Note that in the second embodiment, the source electrode 84 of the transistor 80 is connected to the eighth wiring region 352 (connection pad 164) via a wire 152A (see FIG. 23).

The first insulating layer 250 has a first insulating layer 250 that exposes the first to

eighth wiring regions

312, 314, 316, 322, 324, 326, 342, 352 of the first to fourth front side wirings 310, 320, 340, 350, respectively. It includes first to eighth openings 251 to 258 (see FIG. 23).

A first metal plating material 362 (Fig. 23, FIG. 26, and FIG. 27) are provided. As the first metal plating material 362, for example, a laminate containing Ni and gold Au, or a laminate containing Ni, Pd, and Au can be used. As shown in FIG. 26, the cathode electrode 68 of the light emitting element 60 is bonded to the first metal plating material 362 in the first wiring area 312 (light emitting element mounting area) by a bonding member (not shown). Furthermore, the drain electrode 88 of the transistor 80 is bonded to the first metal plating material 362 in the fourth wiring area 322 (transistor mounting area) by a bonding member (not shown). Further, as shown in FIG. 27, the first and

second connection electrodes

113 and 114 of the first capacitor module 110 are connected to the fifth and second wiring areas 324 and 314 (first capacitor mounting area) by a bonding member (not shown). The first metal plating materials 362 are respectively joined. Further, although a cross-sectional view is omitted, similarly to the first capacitor module 110, the first and

second connection electrodes

123, 124 of the second capacitor module 120 are connected to the sixth and

third wiring regions

326, 316 by a bonding member (not shown). They are respectively bonded to the first metal plating material 362 (second capacitor mounting area). As the bonding material, an Ag paste material or a solder paste material containing Su-Ag-Cu can be used. The bonding material may be changed depending on the member to be bonded to the first metal plating material 362. For example, Ag paste material can be used to bond the light emitting element 60. Moreover, a solder paste material or an Ag paste material can be used to join the transistor 80 and the first and

second capacitor modules

110 and 120.

The aforementioned connection pads 162, 164 (FIGS. 23 and 27) are provided in the seventh and

eighth wiring regions

342, 352 exposed through the seventh and

eighth openings

257, 258 of the first insulating layer 250. ing. The

connection pads

162, 164 are formed of a second metal plating material. As the second metal plating material, a laminate containing Ni and Au or a laminate containing Ni, Pd, and Au can be used.

FIG. 25 is a plan view showing the second wiring layer 230 and the second insulating layer 260. Note that in FIG. 25, illustration of the first insulating layer 250, the first wiring layer 220, and the base material 210 is omitted.

As shown in FIG. 25, the second wiring layer 230 includes a plurality of wirings provided on the back surface 212B (see FIG. 23) of the base material 210 and spaced apart from each other. It includes a side wiring 410, a second back side wiring 420, a third back side wiring 430, and a fourth back side wiring 440.

The first backside wiring 410 is arranged along the first, second, and third side surfaces 52A, 52B, and 52C of the substrate 50B. The first back side wiring 410 is formed in a rectangular shape extending along the third side surface 52C. The first back side wiring 410 includes a first wiring region 412. Note that the first wiring region 412 is a part of the first backside wiring 410, and a physical boundary of the first wiring region 412 does not exist in the first backside wiring 410. The first back side wiring 410 overlaps with the first front side wiring 310 shown in FIG. 24 in a plan view of the substrate 50B.

The second back side wiring 420 is arranged at the center portion of the substrate 50B, that is, at the center portion between the third side surface 52C and the fourth side surface 52D of the substrate 50B. The second backside wiring 420 is arranged along the first and second side surfaces 52A and 52B of the substrate 50B, and is spaced apart from the first backside wiring 410. The second back side wiring 420 is formed to have the same size as the second front side wiring 320 shown in FIG. 24, for example. The second back side wiring 420 includes a second wiring region 422. The second back side wiring 420 overlaps with the second front side wiring 320 shown in FIG. 24 in a plan view of the substrate 50B.

The third back side wiring 430 and the fourth back side wiring 440 are arranged side by side along the fourth side surface 52D of the substrate 50B and spaced apart from each other.
The third backside wiring 430 is arranged along the first and fourth side surfaces 52A and 52D of the substrate 50B, and is spaced apart from the second backside wiring 420. The third back side wiring 430 includes a third wiring region 432. Note that the third wiring area 432 is a part of the third back side wiring 430, and the physical boundary of the third wiring area 432 does not exist in the third back side wiring 430. The third back side wiring 430 overlaps with the third front side wiring 340 in a plan view of the substrate 50B.

The fourth backside wiring 440 is arranged along the second and fourth side surfaces 52B and 52D of the substrate 50B, and is spaced apart from the second backside wiring 420. The fourth back side wiring 440 includes a fourth wiring region 442. Note that the fourth wiring area 442 is a part of the fourth back side wiring 440, and the physical boundary of the fourth wiring area 442 does not exist in the fourth back side wiring 440. The fourth back side wiring 440 overlaps with the fourth front side wiring 350 in a plan view of the substrate 50B.

The second insulating layer 260 has first to fourth openings 261 that expose the first to

fourth wiring regions

412, 422, 432, 442 of the first to fourth back side wirings 410, 420, 430, 440, respectively. 264 included. As shown in FIGS. 26 and 27, the first to

third wiring regions

412, 422, and 432 exposed through the first to third openings 261 to 263 of the second insulating layer 260 are coated with third metal plating. A material 364 is provided. Although not shown, a third metal plating material 364 is provided in the fourth wiring region 442 exposed from the fourth opening 264 shown in FIG. 25, similar to the third wiring region 432. . The third metal plating material 364 of the first to

fourth wiring regions

412, 422, 432, and 442 is bonded to the pad of the drive board by a bonding material (not shown). Therefore, the first to fourth back side wirings 410, 420, 430, 440 and the third metal plating material 364 constitute mounting electrodes of the semiconductor light emitting device 10B. As the third metal plating material 364, a laminate containing Ni and Au or a laminate containing Ni, Pd, and Au can be used. As the bonding material, for example, a solder paste material containing Su--Ag--Cu can be used.

As shown in FIGS. 23 to 27, the first wiring layer 220 and the second wiring layer 230 are electrically connected to each other by the above-mentioned first to fourth via

wirings

242, 244, 246, and 248 that penetrate the base material 210. It is connected. In the second embodiment, each via

wiring

242, 244, 246, 248 is formed, for example, in a cylindrical shape, but the shape is not particularly limited. These via

wirings

242, 244, 246, and 248 are so-called thermal vias, and function as conductive paths between the first wiring layer 220 and the second wiring layer 230, and also serve as conductive paths from the first wiring layer 220 to the second wiring layer. It functions as a heat dissipation path to 230.

first connection electrodes

113, 123 of the first and

second capacitor modules

The second via wiring 244 is located within the fourth wiring area 322 (transistor mounting area) and electrically connects the second front side wiring 320 and the second back side wiring 420. Therefore, the drain electrode 88 of the transistor 80 is electrically connected to the second back side wiring 420 via the second front side wiring 320 and the second via wiring 244. Further, the drain electrode 88 of the transistor 80 is electrically connected to the

second connection electrodes

114 and 124 of the first and

second capacitor modules

second wiring regions

322 and 422. In the second embodiment, for example, the second via wiring 244 is arranged in a 2×3 array.

The third via wiring 246 electrically connects the third front side wiring 340 and the third back side wiring 430. Therefore, the gate electrode 86 of the transistor 80 is electrically connected to the third back side wiring 430 via the wire 152B, the third front side wiring 340, and the third via wiring 246 shown in FIG. Note that the arrangement of the third via wiring 246 is not particularly limited. For example, the two third via wirings 246 are arranged side by side along the fourth side surface 52D of the substrate 50B.

The fourth via wiring 248 electrically connects the fourth front side wiring 350 and the fourth back side wiring 440. Therefore, the source electrode 84 of the transistor 80 is electrically connected to the fourth back side wiring 440 via the wire 152A, the fourth front side wiring 350, and the fourth via wiring 248 shown in FIG. Note that the arrangement of the fourth via wiring 248 is not particularly limited. For example, the two fourth via wirings 248 are arranged side by side along the fourth side surface 52D of the substrate 50B.

(Sealing resin)
As shown in FIGS. 22, 26, and 27, the sealing resin 90 is formed to cover the surface of the substrate 50B. The sealing resin 90 seals the light emitting element 60, the transistor 80, the first and

second capacitor modules

110, 120, and each

wire

190, 152A, 152B (see FIG. 23) mounted on the surface of the substrate 50B. The sealing resin 90 is made of a translucent resin material. As this resin material, epoxy resin, acrylic resin, etc. can be used.

(effect)
According to the semiconductor light emitting device 10B of the second embodiment, the following effects can be obtained.
(2-1) Effects (1-1) to (1-7) and (1-9) in the semiconductor light emitting device 10A of the first embodiment can be obtained.

(2-2) The semiconductor light emitting device 10B of the second embodiment is a surface-mounted light emitting module. Therefore, it can be mounted on a circuit board in the same way as the circuit elements forming the gate driver 908 shown in FIG. 12.

(Example of change)
The above embodiment can be modified and implemented as follows. Further, the above embodiment and the following modifications can be implemented in combination with each other within a technically consistent range.

- The

first connection electrodes

113 and 123 of the first and

second capacitor modules

110 and 120 may be mounted on the

substrates

50A and 50B so as to be electrically connected to the drain electrode 88 of the transistor 80.

- In the first embodiment, the number of lead pins 142D fixed to the back surface 22B of the base 22 and electrically connected to the heat sink 24 is not limited to one.
- One or more capacitor modules may be used instead of the first and

second capacitor modules

110, 120.

- The number of second via wirings 244 is not limited to six, and can be any other number. In other words, the number of second via wirings 244 can be one or more.
- The number of fourth via wirings 248 is not limited to four, and can be any other number. In other words, the number of second via wirings 248 can be one or more.

- The number of intermediate wiring layers 240 is not limited to one. A plurality of intermediate wiring layers 240 may be interposed inside the base material 210.
- A protection diode (for example, SBD906) connected in antiparallel to the light emitting element 60 may be mounted on the light emitting module 30A (for example, the substrate 50A). By integrating the SBD 906 provided on the drive board 910 into the light emitting module 30A, the drive board 910 can be downsized and the size of the entire system can be reduced.

- A gate driver 908 that controls the driving of the transistor 80 may be mounted on the light emitting module 30A (for example, the substrate 50A). By integrating the gate driver 908 provided on the drive board 910 into the light emitting module 30A, the drive board 910 can be downsized and the size of the entire system can be reduced.

As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."
As used in this disclosure, the term "on" includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that in embodiments the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer.

The Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are different from each other in that "upper" and "lower" in the Z-axis direction described herein are "upper" and "lower" in the vertical direction. Not limited to one thing. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

(Additional note)
The technical ideas that can be understood from this disclosure are described below. Note that, not for the purpose of limitation but for the purpose of aiding understanding, the reference numerals of the corresponding components in the embodiments are attached to the components described in the supplementary notes. Reference numerals are shown by way of example to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

(Additional note 1)
Boards (50A, 50B),
a light emitting element (60) mounted on the substrate (50A, 50B);
a transistor (80) mounted on the substrate (50A, 50B) and configured to drive the light emitting element (60);
a main surface (112A, 122A) mounted on the substrate (50A, 50B) and facing the substrate (50A, 50B) in the thickness direction (Y) of the substrate (50A, 50B); A capacitor module (110, 122A) having a first connection electrode (113, 123) and a second connection electrode (114, 124) provided in the light emitting element (60), and electrically connected to the light emitting element (60). 120) and
Equipped with
The capacitor module (110, 120) includes:
a silicon substrate (116, 126) having a first surface and a second surface facing oppositely to each other;
the first connection electrode (113, 123) provided on the first surface;
a counter electrode (117, 127) provided on the second surface and facing the first connection electrode (113, 123);
including,
Semiconductor light emitting device.

(Additional note 2)
The semiconductor according to supplementary note 1, wherein the first connection electrode (113, 123) and the second connection electrode (114, 124) are spaced apart in a direction parallel to the main surface (112A, 122A). Light emitting device.

(Additional note 3)
The capacitor module (110, 120) includes a connection part (118, 128) that connects the counter electrode (117, 127) to the second connection electrode (114, 124), according to appendix 1 or 2. Semiconductor light emitting device.

(Additional note 4)
The connection portion (118, 128) connects the first wiring (118A, 128A) connected to the counter electrode (117, 127) and the first wiring (118A, 128A) to the second connection electrode (114, 124), and a second wiring (118B, 128B) connected to the semiconductor light emitting device according to appendix 3.

(Appendix 5)
The semiconductor light emitting device according to appendix 4, wherein a plurality of the second wirings (118B, 128B) are provided.

(Appendix 6)
The semiconductor light emitting device according to appendix 4 or 5, wherein the second wiring (118B, 128B) is a through wiring that penetrates the silicon substrate (116, 126).

(Appendix 7)
The semiconductor light emitting device according to any one of attachments 4 to 6, wherein the capacitor module (110, 120) includes a sealing resin (119, 129) that seals the silicon substrate (116, 126).

(Appendix 8)
The semiconductor light emitting device according to appendix 7, wherein the second wiring (118B, 128B) is a via wiring provided in an opening formed in the sealing resin (119, 129).

(Appendix 9)
The semiconductor light emitting device according to any one of Supplementary Notes 1 to 8, wherein the thickness of the capacitor module (110, 120) is equal to or less than the thickness of the transistor (80).

(Appendix 10)
The semiconductor light emitting device according to any one of appendices 1 to 9, wherein the transistor (80) is a vertical MOSEFT.

(Appendix 11)
The semiconductor light emitting device according to any one of Supplementary Notes 1 to 10, wherein two capacitor modules (110, 120) are mounted on the substrate (50A, 50B).

(Appendix 12)
The semiconductor light emitting device according to any one of Supplementary notes 1 to 11, including a protection diode mounted on the substrate (50A, 50B) and connected to the light emitting element (60).

(Appendix 13)
The semiconductor light emitting device according to any one of attachments 1 to 12, wherein the substrate (50A, 50B) is a resin substrate, a silicon substrate, a glass substrate, or a ceramic substrate.

(Appendix 14)
The semiconductor light emitting device according to any one of attachments 1 to 13, wherein the substrate (50A, 50B) is a double-sided substrate or a multilayer substrate.

(Appendix 15)
a stem (20) including a conductive base (22) and a conductive heat sink (24) on which the substrate (50A, 50B) is mounted;
a plurality of lead pins (142A to 142D) provided on the base (22);
The semiconductor light emitting device according to any one of Supplementary Notes 1 to 14, comprising:

(Appendix 16)
The substrate (50A, 50B) is a semiconductor light emitting device according to any one of appendices 1 to 15, including a mounting electrode provided on a surface opposite to the surface on which the light emitting element (60) is mounted. Device.

(Appendix 17)
The semiconductor light-emitting device according to appendix 16, further comprising a transparent sealing resin (90) that covers the light-emitting element (60) as well as the surface on which the light-emitting element (60) is mounted.

The above description is merely an example. Those skilled in the art will recognize that many more possible combinations and permutations are possible beyond those listed for the purpose of describing the techniques of the present disclosure. This disclosure is intended to cover all alternatives, variations, and modifications falling within the scope of this disclosure, including the claims.

10A, 10B semiconductor light emitting device 20 stem 22 base 24 heat sink 30A, 30A1, 30B light emitting module 40 surrounding member 42 housing space 50A, 50A1, 50B substrate 60 light emitting element 66 anode electrode 68 cathode electrode 70 light emitting element drive circuit 80 transistor 84 source electrode 86 Gate electrode 88 Drain electrode 90 Sealing resin 110 First capacitor module 110A to 110C Capacitor module 111A First side surface 111B Second side surface 111C Third side surface 111D Fourth side surface 112A First main surface 112B Second main surface 113 First connection Electrode 113A Electrode 113B Second opposing electrode 113C Via wiring 114 Second connection electrode 115 Silicon capacitor 116 Silicon substrate 116A First surface 116B Second surface 116C Through hole 117 Opposing electrode 118 Connection portion 118A First wiring 118B Second wiring 119 Sealing Resin 119A Opening 119B First opening 119C Second opening 119D First surface 120 Second capacitor module 121A First side 121B Second side 121C Third side 121D Fourth side 122A First main surface 122B Second main surface 123 First connection Electrode 124 Second connection electrode 125 Silicon capacitor 126 Silicon substrate 127 Counter electrode 128 Connection part 128A First wiring 128B Second wiring 129 Sealing resin 142A to 142D Lead pin 144 Insulating material 152A to 152C Wire 160 External element connection pad 162 Connection pad 164 Connection pad 190, 191 Wire 210 Base material 210A First base material 210B Second base material 220 First wiring layer 230 Second wiring layer 240 Intermediate wiring layer 242 First via wiring 244 Second via wiring 246 Third via wiring 248 4 via wiring 250 First insulating layer 260 Second insulating layer 310 First surface side wiring 320 Second surface side wiring 330 Third surface side wiring 340 Third surface side wiring 350 Fourth surface side wiring 362 First metal plating material 364 Third metal plating material 410 First back side wiring 420 Second back side wiring 430 Third back side wiring 440 Fourth back side wiring 530 Third intermediate wiring 902 Resistance element 904 Constant voltage source 906 Schottky barrier diode (SBD)
908 Gate driver 910 Drive board

Claims

A substrate and
a light emitting element mounted on the substrate;
a transistor mounted on the substrate and configured to drive the light emitting element;
It is mounted on the substrate and has a main surface facing the substrate in the thickness direction of the substrate, and a first connection electrode and a second connection electrode provided on the main surface, and electrically connects the light emitting element. a capacitor module connected to the
Equipped with
The capacitor module includes:
a silicon substrate having a first surface and a second surface facing oppositely to each other;
the first connection electrode provided on the first surface;
a counter electrode provided on the second surface and facing the first connection electrode;
including,
Semiconductor light emitting device.
The semiconductor light emitting device according to claim 1, wherein the first connection electrode and the second connection electrode are arranged apart from each other in a direction parallel to the main surface.
3. The semiconductor light emitting device according to claim 1, wherein the capacitor module includes a connection part that connects the counter electrode to the second connection electrode.
The semiconductor light emitting device according to claim 3, wherein the connection portion includes a first wiring connected to the counter electrode and a second wiring connecting the first wiring to the second connection electrode.
5. The semiconductor light emitting device according to claim 4, wherein a plurality of said second wirings are provided.
6. The semiconductor light emitting device according to claim 4, wherein the second wiring is a through wiring that penetrates the silicon substrate.
The semiconductor light emitting device according to any one of claims 4 to 6, wherein the capacitor module includes a sealing resin that seals the silicon substrate.
8. The semiconductor light emitting device according to claim 7, wherein the second wiring is a via wiring provided in an opening formed in the sealing resin.
The semiconductor light emitting device according to any one of claims 1 to 8, wherein the thickness of the capacitor module is less than or equal to the thickness of the transistor.
The semiconductor light emitting device according to any one of claims 1 to 9, wherein the transistor is a vertical MOSEFT.
The semiconductor light emitting device according to any one of claims 1 to 10, wherein two capacitor modules are mounted on the substrate.
The semiconductor light emitting device according to any one of claims 1 to 11, further comprising a protection diode mounted on the substrate and connected to the light emitting element.
The semiconductor light emitting device according to any one of claims 1 to 12, wherein the substrate is a resin substrate, a silicon substrate, a glass substrate, or a ceramic substrate.
The semiconductor light emitting device according to any one of claims 1 to 13, wherein the substrate is a double-sided substrate or a multilayer substrate.
a stem including a conductive base and a conductive heat sink on which the substrate is mounted;
a plurality of lead pins provided on the base;
The semiconductor light emitting device according to any one of claims 1 to 14, comprising:
16. The semiconductor light emitting device according to claim 1, wherein the substrate includes a mounting electrode provided on a surface opposite to a surface on which the light emitting element is mounted.
17. The semiconductor light emitting device according to claim 16, further comprising a translucent sealing resin that covers the light emitting element as well as the surface on which the light emitting element is mounted.