WO2023228616A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023228616A1
WO2023228616A1 PCT/JP2023/014850 JP2023014850W WO2023228616A1 WO 2023228616 A1 WO2023228616 A1 WO 2023228616A1 JP 2023014850 W JP2023014850 W JP 2023014850W WO 2023228616 A1 WO2023228616 A1 WO 2023228616A1
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Prior art keywords
layer
oxide semiconductor
semiconductor layer
semiconductor device
crystal region
Prior art date
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PCT/JP2023/014850
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English (en)
French (fr)
Japanese (ja)
Inventor
創 渡壁
将志 津吹
俊成 佐々木
尊也 田丸
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Japan Display Inc
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Japan Display Inc
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Application filed by Japan Display Inc filed Critical Japan Display Inc
Priority to CN202380038114.2A priority Critical patent/CN119137750A/zh
Priority to KR1020247037054A priority patent/KR102947178B1/ko
Priority to JP2024522967A priority patent/JPWO2023228616A1/ja
Priority to DE112023001478.7T priority patent/DE112023001478T5/de
Publication of WO2023228616A1 publication Critical patent/WO2023228616A1/ja
Priority to US18/934,397 priority patent/US20250063761A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • One embodiment of the present invention relates to a semiconductor device.
  • one embodiment of the present invention relates to a semiconductor device in which an oxide semiconductor is used for a channel.
  • a semiconductor device using an oxide semiconductor for a channel has a simple structure and can be manufactured using a low-temperature process, like a semiconductor device using amorphous silicon for a channel. Further, it is known that a semiconductor device in which an oxide semiconductor is used for a channel has higher mobility than a semiconductor device in which amorphous silicon is used for a channel.
  • JP 2021-141338 Publication Japanese Patent Application Publication No. 2014-099601 JP 2021-153196 Publication Japanese Patent Application Publication No. 2018-006730 Japanese Patent Application Publication No. 2016-184771 JP 2021-108405 Publication
  • an insulating layer formed under conditions containing more oxygen contains many defects. In this case, electrons are trapped in defects in the insulating layer, resulting in variations in electrical characteristics or characteristics in reliability tests of the semiconductor device.
  • the insulating layer does not contain much oxygen, and oxygen cannot be sufficiently supplied from the insulating layer to the oxide semiconductor layer. Therefore, it is required to realize a structure that can repair oxygen vacancies formed in an oxide semiconductor layer while reducing defects in an insulating layer that cause characteristics fluctuations of a semiconductor device.
  • a semiconductor device with high mobility can be obtained by relatively increasing the ratio of indium contained in the oxide semiconductor layer.
  • the ratio of indium contained in the oxide semiconductor layer is high, oxygen vacancies are likely to be formed in the oxide semiconductor layer. Therefore, in order to achieve high mobility while maintaining high reliability, it is necessary to devise the structure of the oxide semiconductor layer and the insulating layer around the oxide semiconductor layer.
  • One of the objects of an embodiment of the present invention is to provide a semiconductor device having high mobility and high reliability.
  • a semiconductor device includes a metal oxide layer containing aluminum on an insulating surface, and an oxide semiconductor layer on the metal oxide layer, and the oxide semiconductor layer has a metal oxide layer and a metal oxide layer. a first crystal region in contact with the first crystal region; and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer; differs from the above in at least one of crystal structure and crystal orientation.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention.
  • 1 is a plan view showing the configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view illustrating a crystal structure of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view illustrating a crystal structure of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a plan view showing an outline of a display device according to an embodiment of the present invention.
  • FIG. 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.
  • FIG. 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention.
  • FIG. 2 is a plan view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention.
  • FIG. 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. 1 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. 3 is a graph showing electrical characteristics of a semiconductor device of an example. 3 is a graph showing a reliability test of a semiconductor device of an example. It is a cross-sectional TEM image of a semiconductor device of an example.
  • FIG. 24A is a schematic diagram for explaining the cross-sectional TEM image of FIG. 24A. It is an electron beam diffraction image of a semiconductor device of an example.
  • 7 is a graph showing electrical characteristics of a semiconductor device of a comparative example.
  • 7 is a graph showing a reliability test of a semiconductor device of a comparative example.
  • It is a cross-sectional TEM image of a semiconductor device of a comparative example.
  • It is an electron beam diffraction image of a semiconductor device of a comparative example.
  • the direction from the substrate toward the oxide semiconductor layer is referred to as upward. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as downward or downward.
  • the terms “upper” and “lower” are used in the description; however, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a direction different from that shown in the drawings.
  • the expression “an oxide semiconductor layer on a substrate” merely explains the vertical relationship between the substrate and the oxide semiconductor layer as described above; Other members may also be arranged.
  • Upper or lower refers to the stacking order in a structure in which multiple layers are stacked, and when expressed as a pixel electrode above a transistor, it means a positional relationship in which the transistor and pixel electrode do not overlap in plan view. You can. On the other hand, when expressed as a pixel electrode vertically above a transistor, it means a positional relationship in which the transistor and the pixel electrode overlap in plan view.
  • Display device refers to a structure that displays images using an electro-optic layer.
  • the term display device may refer to a display panel that includes an electro-optic layer, or may refer to a structure in which display cells are equipped with other optical components (e.g., polarizing components, backlights, touch panels, etc.).
  • the "electro-optic layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless a technical contradiction arises. Therefore, the embodiments to be described later will be explained by exemplifying a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as display devices. It can be applied to a display device including an optical layer.
  • ⁇ includes A, B, or C
  • ⁇ includes any one of A, B, and C
  • ⁇ includes one selected from the group consisting of A, B, and C
  • ⁇ includes multiple combinations of A to C, unless otherwise specified.
  • these expressions do not exclude cases where ⁇ includes other elements.
  • a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 14.
  • semiconductor devices in addition to transistors used in display devices, semiconductor devices according to the embodiments described below can be used in integrated circuits (ICs) such as microprocessors (Micro-Processing Units: MPUs), or memory circuits. Good too.
  • ICs integrated circuits
  • MPUs Micro-Processing Units
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device 10 according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing the configuration of the semiconductor device 10 according to an embodiment of the present invention.
  • the semiconductor device 10 is provided on a substrate 100.
  • the semiconductor device 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. including. Note that when the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as the source/drain electrode 200.
  • the gate electrode 105 is provided on the substrate 100. Gate insulating layer 110 and gate insulating layer 120 are provided on substrate 100 and gate electrode 105. A metal oxide layer 130 is provided on the gate insulating layer 120. Metal oxide layer 130 is in contact with gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Among the main surfaces of the oxide semiconductor layer 140, the surface in contact with the metal oxide layer 130 is referred to as a lower surface 142. The side surface of the metal oxide layer 130 substantially coincides with the side surface of the oxide semiconductor layer 140.
  • no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100.
  • the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140 are aligned on a straight line, but the configuration is not limited to this.
  • the angle of the side surface of the metal oxide layer 130 with respect to the main surface of the substrate 100 may be different from the angle of the side surface of the oxide semiconductor layer 140.
  • At least one side surface of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.
  • the gate electrode 160 faces the oxide semiconductor layer 140.
  • Gate insulating layer 150 is provided between oxide semiconductor layer 140 and gate electrode 160.
  • the gate insulating layer 150 is in contact with the oxide semiconductor layer 140.
  • the surface in contact with the gate insulating layer 150 is referred to as an upper surface 141.
  • the surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143.
  • Insulating layers 170 and 180 are provided on gate insulating layer 150 and gate electrode 160. Openings 171 and 173 reaching the oxide semiconductor layer 140 are provided in the insulating layers 170 and 180.
  • Source electrode 201 is provided inside opening 171 .
  • the source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171.
  • Drain electrode 203 is provided inside opening 173.
  • the drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.
  • the gate electrode 105 has a function as a bottom gate of the semiconductor device 10 and a function as a light shielding film for the oxide semiconductor layer 140.
  • the gate insulating layer 110 has a function as a barrier film that blocks impurities that diffuse from the substrate 100 toward the oxide semiconductor layer 140.
  • the gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom gate.
  • the metal oxide layer 130 is a layer containing a metal oxide mainly composed of aluminum, and has a function as a gas barrier film that blocks gases such as oxygen and hydrogen.
  • the oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH.
  • the channel region CH is a region of the oxide semiconductor layer 140 that is vertically below the gate electrode 160.
  • the source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is a region closer to the source electrode 201 than the channel region CH.
  • the drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is a region closer to the drain electrode 203 than the channel region CH.
  • the oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor.
  • the oxide semiconductor layer 140 in the source region S and drain region D has physical properties as a conductor.
  • the gate electrode 160 has a function as a light shielding film for the top gate of the semiconductor device 10 and the oxide semiconductor layer 140.
  • the gate insulating layer 150 has a function as a gate insulating layer for the top gate, and has a function of releasing oxygen through heat treatment in the manufacturing process.
  • the insulating layers 170 and 180 have a function of insulating the gate electrode 160 and the source/drain electrode 200 and reducing the parasitic capacitance between them.
  • the operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105.
  • the gate electrode 105 when the gate electrode 105 is simply used as a light shielding film, a specific voltage may not be supplied to the gate electrode 105 and the gate electrode 105 may be in a floating state. In other words, the gate electrode 105 may simply be called a "light shielding film".
  • the semiconductor device 10 may be a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer. good.
  • the above configuration is just one embodiment, and the present invention is not limited to the above configuration.
  • the planar pattern of the metal oxide layer 130 is substantially the same as the planar pattern of the oxide semiconductor layer 140 in plan view.
  • a lower surface 142 of the oxide semiconductor layer 140 is covered with a metal oxide layer 130.
  • the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130.
  • the width of the gate electrode 105 is larger than the width of the gate electrode 160.
  • the D1 direction is a direction that connects the source electrode 201 and the drain electrode 203, and is a direction that indicates the channel length L of the semiconductor device 10.
  • the length in the D1 direction of the region where the oxide semiconductor layer 140 and the gate electrode 160 overlap (channel region CH) is the channel length L
  • the width of the channel region CH in the D2 direction is the channel width W. be.
  • the present embodiment illustrates a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130
  • the present invention is not limited to this configuration.
  • a portion of the lower surface 142 of the oxide semiconductor layer 140 does not need to be in contact with the metal oxide layer 130.
  • the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH is covered with the metal oxide layer 130, and all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D is covered with the metal oxide layer. 130 may not be covered. That is, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and drain region D does not need to be in contact with the metal oxide layer 130.
  • a part of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH is not covered with the metal oxide layer 130, and the other part of the lower surface 142 is in contact with the metal oxide layer 130. Good too.
  • Gate insulating layer 150 may be patterned.
  • the gate insulating layer 150 may be patterned to expose the oxide semiconductor layer 140 in the source region S and drain region D. That is, the gate insulating layer 150 in the source region S and drain region D may be removed, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact with each other in these regions.
  • FIG. 2 illustrates a configuration in which the source/drain electrode 200 does not overlap the gate electrode 105 and the gate electrode 160 in plan view
  • the configuration is not limited to this.
  • the source/drain electrode 200 may overlap with at least one of the gate electrode 105 and the gate electrode 160.
  • the above configuration is just one embodiment, and the present invention is not limited to the above configuration.
  • a rigid substrate having light-transmitting properties is used, such as a glass substrate, a quartz substrate, a sapphire substrate, or the like. If the substrate 100 needs to have flexibility, a substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate, etc., is used as the substrate 100.
  • a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 100.
  • the semiconductor device 10 is a top-emission type display, the substrate 100 does not need to be transparent, so an impurity that reduces the transparency of the substrate 100 may be used.
  • the substrate 100 may be a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate. A substrate without this is used.
  • General metal materials are used for the gate electrode 105, the gate electrode 160, and the source/drain electrodes 200.
  • these materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), and tungsten (W). ), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof are used.
  • the above materials may be used in a single layer or in a stacked layer.
  • gate electrode 160 and the source/drain electrodes 200 may be made of the same metal material or may be made of different metal materials.
  • the gate electrode 160 may not contain aluminum, and the source/drain electrodes 200 may contain aluminum.
  • a general insulating material is used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180.
  • these insulating layers include silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), and silicon oxide.
  • Inorganic insulating layers such as aluminum nitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), and aluminum nitride (AlN x ) are used.
  • SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a smaller proportion (x>y) than oxygen (O).
  • SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).
  • an insulating layer containing oxygen among the above insulating layers is used.
  • an inorganic insulating layer such as silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) is used.
  • the gate insulating layer 120 an insulating layer having a function of releasing oxygen through heat treatment is used.
  • the temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is 600° C. or lower, 500° C. or lower, 450° C. or lower, or 400° C. or lower. That is, for example, when a glass substrate is used as the substrate 100, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10.
  • the gate insulating layer 150 an insulating layer with few defects is used.
  • the gate insulating layer The oxygen composition ratio in No. 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer.
  • silicon oxide ( SiOx ) is used for each of the gate insulating layer 150 and the insulating layer 180
  • the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 150 is the same as that of the oxide used as the insulating layer 180.
  • a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating layer 150.
  • a metal oxide containing aluminum as a main component is used as the metal oxide layer 130 and the metal oxide layer 190 used in the manufacturing process as described later.
  • the metal oxide layer 130 (or the metal oxide layer 190) may be made of aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ), or the like.
  • An inorganic insulating layer is used.
  • a metal oxide layer containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide layer 130 (or metal oxide layer 190) is 1% or more of the entire metal oxide layer 130 (or metal oxide layer 190). It means something.
  • the proportion of aluminum contained in the metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 130. good.
  • the above ratio may be a mass ratio or a weight ratio.
  • the oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Therefore, although the details will be described later, when OS annealing is performed, aluminum contained in the metal oxide layer 130 is diffused into the oxide semiconductor layer 140. Therefore, the oxide semiconductor layer 140 includes a region with a high aluminum concentration near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. The aluminum concentration can be detected, for example, by SIMS (Secondary Ion Mass Spectrometry) analysis.
  • the oxide semiconductor layer 140 a metal oxide having semiconductor characteristics is used.
  • an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 140.
  • the ratio of indium to two or more metals is 50% or more.
  • gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoid are used for the oxide semiconductor layer 140. Elements other than the above may be used for the oxide semiconductor layer 140.
  • the oxide semiconductor layer 140 has crystallinity.
  • the crystalline oxide semiconductor layer 140 has fewer oxygen vacancies than the amorphous oxide semiconductor layer.
  • the crystalline oxide semiconductor layer 140 may include an amorphous region, the proportion of the amorphous region in the oxide semiconductor layer 140 is smaller than the proportion of the crystalline region in the oxide semiconductor layer 140.
  • the ratio of crystalline regions in the oxide semiconductor layer 140 is 70% or more, preferably 80% or more, and more preferably 90% or more.
  • FIG. 3 is a schematic cross-sectional view illustrating the crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to an embodiment of the present invention.
  • the oxide semiconductor layer 140 includes a first crystal region 144 having a first crystal structure and a second crystal region 145 having a second crystal structure.
  • the first crystal region 144 is formed only near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the first crystal region 144 is formed in contact with the metal oxide layer 130 and does not exist at a position away from the metal oxide layer 130.
  • One first crystal region 144 may be formed in the oxide semiconductor layer 140, or a plurality of first crystal regions 144 may be formed.
  • the second crystal region 145 is in contact with the metal oxide layer 130 and the first crystal region 144 and is formed to cover the first crystal region 144 .
  • the first crystal region 144 is surrounded by the metal oxide layer 130 and the second crystal region 145, and there is no crystal between the first crystal region 144 and the second crystal region 145. Grain boundaries are formed.
  • the first crystal region 144 is formed only near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 and does not exist at a position away from the metal oxide layer 130.
  • the proportion of the first crystal region 144 in the oxide semiconductor layer 140 is significantly smaller than the proportion of the second crystal region 145 in the oxide semiconductor layer 140.
  • the area of the first crystal region 144 is significantly smaller than the area of the second crystal region. That is, most of the oxide semiconductor layer 140 is formed by the second crystal region 145, and the crystal structure of the oxide semiconductor layer 140 is the same as the second crystal structure of the second crystal region 145.
  • the second crystal structure of the second crystal region 145 is, for example, a bixbite structure, a corundum structure, a spinel structure, or a homologous structure.
  • the bixbite structure is one of the stable crystal structures of indium oxide.
  • the corundum structure and the spinel structure are one of the stable crystal structures of the aluminum oxide or gallium oxide structure.
  • the homologous structure is one of the stable crystal structures of indium gallium zinc oxide.
  • the second crystal structure changes depending on the composition of elements contained in the second crystal region 145. Note that the homologous structure is expressed using a certain index m (m is a natural number) in the composition formula, and can take various periodic structures.
  • the second crystal structure is preferably a bixbite structure, a corundum structure, or a spinel structure rather than a homologous structure.
  • the first crystal structure of the first crystal region 144 may be the same as or different from the second crystal structure of the second crystal region 145.
  • the crystal orientation of the first crystal region 144 is different from the crystal orientation of the second crystal region 145 in a cross-sectional view of the oxide semiconductor layer 140. That is, the oxide semiconductor layer 140 includes at least two regions with different crystallinity (a first crystal region 144 and a second crystal region 145), and there is no crystal between the first crystal region 144 and the second crystal region 145. Grain boundaries are formed.
  • the reason why the first crystal region 144 is formed in the oxide semiconductor layer 140 is as follows. As described above, when OS annealing is performed on the oxide semiconductor layer 140 in contact with the metal oxide layer 130, aluminum contained in the metal oxide layer 130 is diffused into the oxide semiconductor layer 140. Near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, a first crystal region 144 is formed using diffused aluminum as a crystal nucleus. However, since the diffusion rate of diffused aluminum in the oxide semiconductor layer 140 is not so high, the first crystal region 144 does not undergo large crystal growth. Therefore, a second crystal region 145 is formed using the first crystal region 144 that has grown to a certain size as a crystal nucleus.
  • the first crystal region 144 includes aluminum diffused from the metal oxide layer 130, the aluminum concentration in the first crystal region 144 is higher than the aluminum concentration in the second crystal region 145. Further, since the diffused aluminum easily combines with oxygen, the electrical conductivity of the first crystal region 144 may be lower than the electrical conductivity of the second crystal region.
  • the crystalline region of the oxide semiconductor layer also contains a considerable amount of oxygen vacancies. Therefore, even in a crystalline oxide semiconductor layer, it is preferable that oxygen vacancies are further reduced.
  • the second crystal region 145 grows crystals using the first crystal region 144 as a crystal nucleus, and the first crystal region 144 functions as a so-called buffer region. Therefore, compared to a crystal region directly grown from the metal oxide layer 130 or the gate insulating layer 120, oxygen vacancies are more reduced in the second crystal region 145 of the oxide semiconductor layer 140. Furthermore, since the first crystal region 144 functions as a buffer region between the metal oxide layer 130 and the second crystal region 145, the interface state density of the oxide semiconductor layer 140 is reduced.
  • FIG. 4 is a schematic cross-sectional view illustrating the crystal structure of the oxide semiconductor layer 140A of the semiconductor device 10 according to an embodiment of the present invention.
  • the oxide semiconductor layer 140A includes a first crystal region 144A having a first crystal structure and a second crystal region 145A having a second crystal structure.
  • the first crystal region 144A contains aluminum diffused from the metal oxide layer 130 and is formed as a layer at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the second crystal region 145A is not in contact with the metal oxide layer 130. Further, in the thickness direction of the oxide semiconductor layer, the thickness of the second crystal region 145A is greater than the thickness of the first crystal region 144A. Even in this case, since the first crystal region 144A functions as a buffer region (buffer layer), oxygen vacancies in the second crystal region 145A are reduced and the interface state density of the oxide semiconductor layer 140A is reduced. be done.
  • the oxide semiconductor layer 140 When the ratio of indium in the oxide semiconductor layer is 50% or more, the oxide semiconductor layer has crystallinity. However, even in a crystalline oxide semiconductor layer, if oxygen vacancies are formed in a crystal region of the oxide semiconductor layer, sufficient electrical characteristics and reliability cannot be obtained.
  • the oxide semiconductor layer 140 includes a first crystal region 144 that functions as a buffer layer and a second crystal region 145 with reduced oxygen vacancies. Therefore, oxygen vacancies and interface state density in the oxide semiconductor layer 140 are reduced, and the semiconductor device 10 has high mobility and high reliability.
  • FIG. 5 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 6 to 14 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • a method of manufacturing the semiconductor device 10 in which aluminum oxide is used as the metal oxide layers 130 and 190 will be described.
  • a gate electrode 105 is formed as a bottom gate on the substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ("Bottom" in step S2001 in FIG. 3).
  • GI/GE formation For example, silicon nitride is formed as the gate insulating layer 110.
  • silicon oxide is formed as the gate insulating layer 120.
  • the gate insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method. One or both of the gate insulating layers 110 and 120 may be referred to as a "first insulating layer".
  • the gate insulating layer 110 can block impurities that diffuse toward the oxide semiconductor layer 140 from the substrate 100 side, for example.
  • the silicon oxide used as the gate insulating layer 120 is silicon oxide that has a physical property of releasing oxygen through heat treatment.
  • a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 ("OS/AlOx film formation" in step S2002 in FIG. 5).
  • gate insulating layers 110 and 120 may be formed on the substrate 100, and a metal oxide layer 130 may be formed on the gate insulating layers 110 and 120.
  • the metal oxide layer 130 may be formed over the substrate 100, and the oxide semiconductor layer 140 may be formed over the metal oxide layer 130.
  • the oxide semiconductor layer 140 is formed so as to be in contact with the metal oxide layer 130.
  • the metal oxide layer 130 and the oxide semiconductor layer 140 are formed by sputtering or atomic layer deposition (ALD).
  • the thickness of the metal oxide layer 130 is 1 nm or more and 100 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 30 nm or less, or 1 nm or more and 10 nm or less.
  • aluminum oxide is used as the metal oxide layer 130.
  • Aluminum oxide has high gas barrier properties.
  • aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120 and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 140. do.
  • the thickness of the oxide semiconductor layer 140 is 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less.
  • an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 140.
  • the oxide semiconductor layer 140 before heat treatment (OS annealing) described below is amorphous.
  • the oxide semiconductor layer 140 after film formation and before OS annealing is preferably in an amorphous state (a state in which the crystalline component of the oxide semiconductor is small).
  • the conditions for forming the oxide semiconductor layer 140 are preferably such that the oxide semiconductor layer 140 immediately after being formed does not crystallize as much as possible.
  • the oxide semiconductor layer 140 is formed by a sputtering method, the oxide semiconductor layer 140 is formed while the temperature of the object to be formed (the substrate 100 and the structure formed thereon) is controlled. Filmed.
  • the temperature of the object to be film-formed increases with the film-forming process.
  • microcrystals are included in the oxide semiconductor layer 140 immediately after film-forming. The microcrystals inhibit crystallization during subsequent OS annealing.
  • film formation may be performed while cooling the object to be film-formed.
  • the temperature of the surface of the object to be film-formed (hereinafter referred to as "film-forming temperature”) is 100°C or lower, 70°C or lower, 50°C or lower, or 30°C or lower.
  • the object to be film-formed may be cooled from the surface opposite to the surface to be film-formed.
  • the oxide semiconductor layer 140 containing few crystal components can be formed immediately after the film formation.
  • a pattern of the oxide semiconductor layer 140 is formed ("OS pattern formation" in step S2003 in FIG. 5).
  • a resist mask is formed over the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask.
  • Wet etching may be used to etch the oxide semiconductor layer 140, or dry etching may be used.
  • etching may be performed using an acidic etchant.
  • oxalic acid or hydrofluoric acid may be used as the etchant.
  • oxide semiconductor layer 140 After patterning the oxide semiconductor layer 140, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 ("OS annealing" in step S2004 in FIG. 5).
  • OS annealing is performed on the oxide semiconductor layer 140 ("OS annealing" in step S2004 in FIG. 5).
  • the oxide semiconductor layer 140 is crystallized by this OS annealing.
  • the OS annealing is performed, aluminum contained in the metal oxide layer 130 is diffused into the oxide semiconductor layer 140, and a first crystal region 144 is formed near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. .
  • a second crystal region 145 is formed using the first crystal region 144 as a crystal nucleus.
  • a pattern of the metal oxide layer 130 is formed ("AlOx pattern formation" in step S2005 in FIG. 5).
  • the metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. Wet etching or dry etching may be used to etch the metal oxide layer 130. For example, diluted hydrofluoric acid (DHF) is used for wet etching.
  • DHF diluted hydrofluoric acid
  • a gate insulating layer 150 is formed on the oxide semiconductor layer 140 ("GI formation" in step S2006 in FIG. 5).
  • silicon oxide is formed as the gate insulating layer 150.
  • Gate insulating layer 150 is formed by a CVD method.
  • the gate insulating layer 150 may be formed at a film forming temperature of 350° C. or higher.
  • the thickness of the gate insulating layer 150 is 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less.
  • a process of implanting oxygen into a part of the gate insulating layer 150 may be performed.
  • the gate insulating layer 150 is sometimes referred to as a "second insulating layer.”
  • a metal oxide layer 190 is formed on the gate insulating layer 150 (“AlOx film formation” in step S2007 in FIG. 22).
  • Metal oxide layer 190 is formed by a sputtering method. The deposition of metal oxide layer 190 implants oxygen into gate insulating layer 150 .
  • the thickness of the metal oxide layer 190 is 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less.
  • aluminum oxide is used as the metal oxide layer 190.
  • Aluminum oxide has high gas barrier properties.
  • aluminum oxide used as the metal oxide layer 190 suppresses outward diffusion of oxygen implanted into the gate insulating layer 150 during the formation of the metal oxide layer 190.
  • the process gas used in sputtering remains in the metal oxide layer 190.
  • Ar may remain in the metal oxide layer 190. The remaining Ar can be detected by SIMS analysis of the metal oxide layer 190.
  • Oxygen released from the gate insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130. Therefore, oxygen is difficult to be supplied to the lower surface 142 of the oxide semiconductor layer 140. Oxygen released from the gate insulating layer 120 diffuses into the gate insulating layer 150 provided on the gate insulating layer 120 from the region where the metal oxide layer 130 is not formed, and passes through the gate insulating layer 150 to the oxide semiconductor. Layer 140 is reached. As a result, oxygen released from the gate insulating layer 120 is difficult to be supplied to the lower surface 142 of the oxide semiconductor layer 140 and is mainly supplied to the side surfaces 143 and the upper surface 141 of the oxide semiconductor layer 140.
  • oxygen released from the gate insulating layer 150 is supplied to the top surface 141 and side surfaces 143 of the oxide semiconductor layer 140 by the oxidation annealing.
  • hydrogen may be released from the gate insulating layers 110 and 120 by the above oxidation annealing, the hydrogen is blocked by the metal oxide layer 130.
  • the oxidation annealing process suppresses the supply of oxygen to the bottom surface 142 of the oxide semiconductor layer 140 where the amount of oxygen vacancies is small, while suppressing the supply of oxygen to the top surface 141 and the bottom surface 142 of the oxide semiconductor layer 140 where the amount of oxygen vacancies is large.
  • Oxygen can be supplied to the side surface 143.
  • the oxygen implanted into the gate insulating layer 150 is blocked by the metal oxide layer 190, so that it is suppressed from being released into the atmosphere. Therefore, by the oxidation annealing, the oxygen is efficiently supplied to the oxide semiconductor layer 140, and oxygen vacancies are repaired.
  • the metal oxide layer 190 is etched (removed) ("AlOx removal" in step S2009 in FIG. 5).
  • Wet etching or dry etching may be used to etch the metal oxide layer 190.
  • DHF diluted hydrofluoric acid
  • the metal oxide layer 190 formed on the entire surface is removed.
  • the removal of the metal oxide layer 190 is performed without using a mask.
  • the etching removes all of the metal oxide layer 190 in the region overlapping with the oxide semiconductor layer 140 formed in one pattern, at least in plan view.
  • a gate electrode 160 is formed on the gate insulating layer 150 ("GE formation" in step S2010 in FIG. 5).
  • the gate electrode 160 is formed by a sputtering method or an atomic layer deposition method, and is patterned through a photolithography process. As described above, the gate electrode 160 is formed so as to be in contact with the gate insulating layer 150 exposed by removing the metal oxide layer 190.
  • the gate insulating layer 150 includes regions with different thicknesses. Specifically, the gate insulating layer 150 includes a first region that overlaps with the gate electrode 160 and a second region that does not overlap with the gate electrode 160. The first region overlaps with the channel region CH of the oxide semiconductor layer 140. The second region overlaps with the source region S or drain region D of the oxide semiconductor layer 140. The thickness of the second region is smaller than the thickness of the first region.
  • the resistance of the source region S and drain region D of the oxide semiconductor layer 140 is reduced (“SD resistance reduction” in step S2011 in FIG. 5).
  • impurities are implanted into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation.
  • argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 140 by ion implantation.
  • Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, so that the resistance of the oxide semiconductor layer 140 is reduced. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 functioning as the channel region CH of the semiconductor device 10, impurities are not implanted into the oxide semiconductor layer 140 in the channel region CH.
  • insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 ("interlayer film formation" in step S2012 in FIG. 5).
  • the insulating layers 170 and 180 are formed by CVD.
  • silicon nitride is formed as the insulating layer 170
  • silicon oxide is formed as the insulating layer 180.
  • the materials used for the insulating layers 170 and 180 are not limited to those described above.
  • the thickness of the insulating layer 170 is 50 nm or more and 500 nm or less.
  • the thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.
  • openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ("contact opening" in step S2013 in FIG. 5).
  • the oxide semiconductor layer 140 in the source region S is exposed through the opening 171.
  • the oxide semiconductor layer 140 in the drain region D is exposed through the opening 173.
  • the semiconductor shown in FIG. The device 10 is completed.
  • the mobility is 50 cm 2 /Vs or more in the range where the channel length L of the channel region CH is 2 ⁇ m or more and 4 ⁇ m or less, and the channel width of the channel region CH is 2 ⁇ m or more and 25 ⁇ m or less. , 55 cm 2 /Vs or more, or 60 cm 2 /Vs or more can be obtained.
  • the mobility in this embodiment is the field effect mobility in the saturation region of the semiconductor device 10, which means that the potential difference (Vd) between the source electrode and the drain electrode is different from the voltage (Vg) supplied to the gate electrode in the semiconductor device 10. It means the maximum value of field effect mobility in a region larger than the value (Vg - Vth) minus the threshold voltage (Vth) of the device 10.
  • FIG. 15 is a plan view showing an outline of a display device according to an embodiment of the present invention.
  • the display device 20 includes an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340.
  • the array substrate 300 and the counter substrate 320 are bonded together by a seal portion 310.
  • a seal portion 310 In the liquid crystal region 22 surrounded by the seal portion 310, a plurality of pixel circuits 301 are arranged in a matrix.
  • the liquid crystal region 22 is a region that overlaps a liquid crystal element 311, which will be described later, in plan view.
  • the seal area 24 in which the seal part 310 is provided is an area around the liquid crystal area 22.
  • the FPC 330 is provided in the terminal area 26.
  • the terminal area 26 is an area where the array substrate 300 is exposed from the counter substrate 320, and is provided outside the seal area 24.
  • the outside of the seal area 24 means the outside of the area where the seal part 310 is provided and the area surrounded by the seal part 310.
  • IC chip 340 is provided on FPC 330.
  • the IC chip 340 supplies signals for driving each pixel circuit 301.
  • FIG. 16 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.
  • a source driver circuit 302 is provided at a position adjacent to the liquid crystal region 22 in which the pixel circuit 301 is arranged in the D1 direction (column direction), and A gate driver circuit 303 is provided at an adjacent position (in the row direction).
  • the source driver circuit 302 and the gate driver circuit 303 are provided in the seal area 24 described above.
  • the area where the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the seal area 24, and may be any area outside the area where the pixel circuit 301 is provided.
  • a source wiring 304 extends from the source driver circuit 302 in the D1 direction, and is connected to a plurality of pixel circuits 301 arranged in the D1 direction.
  • a gate wiring 305 extends from the gate driver circuit 303 in the D2 direction, and is connected to the plurality of pixel circuits 301 arranged in the D2 direction.
  • a terminal section 306 is provided in the terminal region 26.
  • the terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307.
  • the terminal portion 306 and the gate driver circuit 303 are connected by a connection wiring 307.
  • the semiconductor device 10 shown in the first embodiment is used as a transistor included in a pixel circuit 301, a source driver circuit 302, and a gate driver circuit 303.
  • FIG. 17 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.
  • the pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311.
  • the semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203.
  • Gate electrode 160 is connected to gate wiring 305.
  • Source electrode 201 is connected to source wiring 304.
  • Drain electrode 203 is connected to storage capacitor 350 and liquid crystal element 311.
  • the electrode designated by the symbol "201" is referred to as a source electrode
  • the electrode designated by the symbol "203" is referred to as a drain electrode.
  • An electrode that functions as an electrode and is designated by the symbol "203" may function as a source electrode.
  • FIG. 18 is a cross-sectional view of a display device according to an embodiment of the present invention.
  • the display device 20 is a display device using the semiconductor device 10.
  • the semiconductor device 10 may be used in a peripheral circuit including the source driver circuit 302 and the gate driver circuit 303.
  • the configuration of the semiconductor device 10 is the same as the semiconductor device 10 shown in FIG. 1, so the description will be omitted.
  • An insulating layer 360 is provided on the source electrode 201 and drain electrode 203.
  • a common electrode 370 that is commonly provided to a plurality of pixels is provided on the insulating layer 360.
  • An insulating layer 380 is provided on the common electrode 370.
  • An opening 381 is provided in the insulating layers 360 and 380.
  • a pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. Pixel electrode 390 is connected to drain electrode 203.
  • a wiring layer 162 is provided as the same layer as the gate electrode 160.
  • the wiring layer 162 includes the same material as the gate electrode 160.
  • the wiring layer 162 is provided on an insulating layer corresponding to the gate insulating layer 150.
  • a metal oxide layer 190 is also formed on the insulating layer, and oxidation annealing is performed.
  • the aluminum concentration in the region of the insulating layer that does not overlap with the wiring layer 162 is lower than the aluminum concentration in the region of the insulating layer that overlaps with the wiring layer 162.
  • FIG. 19 is a plan view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention.
  • the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in plan view and a non-overlapping region that does not overlap with the pixel electrode 390.
  • a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region.
  • the gradation of the pixel is determined by operating the liquid crystal molecules included in the liquid crystal element 311 due to this horizontal electric field.
  • FIGS. 20 and 21 A display device using a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 20 and 21.
  • a configuration will be described in which the semiconductor device 10 described in the first embodiment is applied to a circuit of an organic EL display device.
  • the outline and circuit configuration of the display device 20 are the same as those shown in FIGS. 15 and 16, so a description thereof will be omitted.
  • FIG. 20 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.
  • the pixel circuit 301 includes elements such as a drive transistor 11, a selection transistor 12, a storage capacitor 210, and a light emitting element DO.
  • the drive transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10.
  • a source electrode of the selection transistor 12 is connected to a signal line 211, and a gate electrode of the selection transistor 12 is connected to a gate line 212.
  • the source electrode of the drive transistor 11 is connected to the anode power supply line 213, and the drain electrode of the drive transistor 11 is connected to one end of the light emitting element DO.
  • the other end of the light emitting element DO is connected to a cathode power line 214.
  • the gate electrode of the drive transistor 11 is connected to the drain electrode of the selection transistor 12.
  • the storage capacitor 210 is connected to the gate electrode and drain electrode of the drive transistor 11.
  • the signal line 211 is supplied with a gradation signal that determines the light emission intensity of the light emitting element DO.
  • the gate line 212 is supplied with a signal for selecting a pixel row in which the above-mentioned gradation signal is to be written.
  • FIG. 21 is a cross-sectional view of a display device according to an embodiment of the present invention.
  • the structure of the display device 20 shown in FIG. 21 is similar to the display device 20 shown in FIG. 18, but the structure above the insulating layer 360 of the display device 20 of FIG. The structure is different from that above 360.
  • the description of the configurations similar to those of the display device 20 in FIG. 18 will be omitted, and the differences between the two will be described.
  • the display device 20 has a pixel electrode 390, a light emitting layer 392, and a common electrode 394 (light emitting element DO) above the insulating layer 360.
  • the pixel electrode 390 is provided on the insulating layer 360 and inside the opening 381.
  • An insulating layer 362 is provided on the pixel electrode 390.
  • An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to the light emitting area. That is, the insulating layer 362 defines pixels.
  • a light emitting layer 392 and a common electrode 394 are provided on the pixel electrode 390 exposed through the opening 363.
  • a pixel electrode 390 and a light emitting layer 392 are provided individually for each pixel.
  • the common electrode 394 is provided in common to a plurality of pixels. Different materials are used for the light emitting layer 392 depending on the display color of the pixel.
  • the semiconductor device described in the first embodiment is applied to a liquid crystal display device and an organic EL display device
  • the semiconductor device may be applied to a self-luminous display device or an electronic paper type display device other than an EL display device.
  • the semiconductor device described above can be applied to anything from small to medium-sized display devices to large-sized display devices without any particular limitation.
  • the semiconductor device 10 described in the first embodiment was manufactured, and the semiconductor device 10 was evaluated. Further, as a comparative example, a semiconductor device in which the metal oxide layer 130 in contact with the oxide semiconductor layer 140 was not provided, that is, a semiconductor device in which the oxide semiconductor layer 140 was in contact with the gate insulating layer 120 was manufactured.
  • an aluminum oxide layer is formed as a metal oxide layer 190 by a sputtering method, and after oxidation annealing, an aluminum oxide layer is formed. layer removed.
  • FIG. 22 is a graph showing the electrical characteristics of the semiconductor device 10 of the example. Further, FIG. 27 is a graph showing the electrical characteristics of a semiconductor device of a comparative example. Table 1 shows the measurement conditions for the electrical characteristics shown in FIGS. 22 and 27.
  • FIGS. 22 and 27 show not only the electrical characteristics (Id-Vg characteristics) but also the mobility (see the dotted lines in FIGS. 22 and 27).
  • the vertical axis for drain current (Id) is shown on the left side of the graph, and the vertical axis for mobility calculated from the drain current is shown on the right side of the graph.
  • the electrical characteristics of the semiconductor device 10 of the example exhibit so-called normally-off (enhancement type) characteristics in which the drain current Id begins to flow when the gate voltage Vg is higher than 0V.
  • the mobility calculated from the electrical characteristics is 59 cm 2 /Vs.
  • the electrical characteristics of the semiconductor device of the comparative example also exhibit so-called normally-off (enhancement type) characteristics.
  • the mobility calculated from the electrical characteristics is 34 cm 2 /Vs.
  • the mobility of the semiconductor device 10 of the example was approximately twice that of the semiconductor device of the comparative example, and it was found that the semiconductor device 10 of the example had high mobility.
  • FIG. 23 is a graph showing a reliability test of the semiconductor device 10 of the example. Further, FIG. 28 is a graph showing the reliability of the semiconductor device of the comparative example.
  • the measurement conditions for the reliability test shown in FIGS. 23 and 28 are as shown in Table 2. That is, as a reliability test, reliability was evaluated using Negative Bias Temperature Illumination Stress (NBTIS).
  • NTIS Negative Bias Temperature Illumination Stress
  • FIGS. 23 and 28 electrical characteristics measured at stress times of 0 sec, 100 sec, 500 sec, 1000 sec, 1500 sec, 2000 sec, and 3600 sec are displayed in an overlapping manner.
  • the time before stress application is 0 sec
  • the time after stress application is 3600 sec.
  • the electrical characteristics before stress application (0 sec) are shown by a thick dotted line
  • the electrical characteristics after stress application (3600 sec) are shown by a thick solid line.
  • the electrical characteristics before and after stress application hardly change in the NBTIS test.
  • the change in threshold voltage before and after stress application was -0.05V. That is, after stress application, the threshold voltage moved only 0.05V in the negative direction. Furthermore, it exhibited normally-off characteristics even after stress was applied.
  • the reliability of the semiconductor device 10 of the example was stable, and it was found that the semiconductor device 10 of the example had high reliability.
  • FIG. 24A is a cross-sectional TEM image of the semiconductor device 10 of the example.
  • FIG. 24B is a schematic diagram for explaining the cross-sectional TEM image of FIG. 24A.
  • FIG. 29 is a cross-sectional TEM image of a semiconductor device of a comparative example.
  • FIG. 24A shows a cross-sectional TEM image of the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 in the semiconductor device 10 of the example.
  • FIG. 29 shows a cross-sectional TEM image near the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 in a semiconductor device of a comparative example.
  • FIG. 24A two different crystal regions can be observed in the semiconductor device 10 of the example. Specifically, as shown in FIG. 24B, in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, a first crystal region 144 in contact with the metal oxide layer 130 and a second crystal region covering the first crystal region 144 are formed. 145 can be confirmed.
  • the oxide semiconductor layer 140 has crystallinity, but most of the oxide semiconductor layer 140 is located near the interface between the gate insulating layer 120 and the oxide semiconductor layer 140. No crystalline region different from the crystalline region occupying .
  • Electron beam diffraction measurement 25 and 26 are electron beam diffraction images of the semiconductor device 10 of the example.
  • FIG. 25 shows an electron diffraction image of the oxide semiconductor layer 140 at a position away from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, and FIG. An electron beam diffraction image near the interface with layer 140 is shown.
  • FIGS. 30 and 31 are electron beam diffraction images of semiconductor devices of comparative examples.
  • FIG. 30 shows an electron diffraction image of the oxide semiconductor layer 140 at a position away from the interface between the gate insulating layer 120 and the oxide semiconductor layer 140, and FIG. An electron beam diffraction image near the interface with layer 140 is shown.
  • FIG. 25 clear spots due to the crystal structure can be confirmed. Therefore, it was found that the oxide semiconductor layer 140 (second crystal region 145) in the semiconductor device 10 of the example had a crystal structure.
  • FIG. 26 spots different from the spots confirmed in FIG. 25 can be confirmed. It is presumed that the spots observed in FIG. 26 are caused by the crystal structure of the first crystal region 144. Therefore, in the semiconductor device 10 of the example, it was found that the first crystal region 144 near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 has a different crystal structure or crystal orientation from the second crystal region 145. Ta.
  • FIG. 30 clear spots due to the crystal structure can be confirmed. Therefore, it was found that the oxide semiconductor layer 140 in the semiconductor device of the comparative example also had a crystal structure. Further, the same spots as the spots confirmed in FIG. 30 can be confirmed in FIG. 31 as well. Therefore, in the semiconductor device of the comparative example, as in the cross-sectional TEM image of FIG. The area could not be confirmed.
  • the semiconductor device 10 of the example As can be seen from the cross-sectional TEM observation and electron diffraction results, in the semiconductor device 10 of the example, most of the oxide semiconductor layer 140 is located near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. A first crystal region 144 having crystallinity different from that of the second crystal region 145 is formed. The semiconductor device 10 in which the first crystal region 144 is formed has high mobility and high reliability, as described above.

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