WO2023226845A1 - 图像数据传输方法、装置和电子设备 - Google Patents

图像数据传输方法、装置和电子设备 Download PDF

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Publication number
WO2023226845A1
WO2023226845A1 PCT/CN2023/094723 CN2023094723W WO2023226845A1 WO 2023226845 A1 WO2023226845 A1 WO 2023226845A1 CN 2023094723 W CN2023094723 W CN 2023094723W WO 2023226845 A1 WO2023226845 A1 WO 2023226845A1
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Prior art keywords
image data
address
transmission
row
information
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English (en)
French (fr)
Inventor
谢梓敏
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/0007—Image acquisition
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement

Definitions

  • the present application belongs to the field of communication technology, and specifically relates to an image data transmission method, device and electronic equipment.
  • the image processing module processes image data in units of pixel blocks as needed, while the image data collected by the camera is transmitted and stored in rows.
  • the high-performance scalable interface Advanced eXtensible Interface, AXI
  • the first address of each burst transmission needs to be set according to the way the data in the memory is stored in rows, but at the same time it needs to be set according to the required Make necessary adjustments to the format of the data block.
  • a burst of data is transmitted for 8 clocks, which is equivalent to reading 64 pixels of data in a row each time. These data are stored in a continuous interval starting from the specified address, but this method requires the preparation of additional data. Storage space, back up the read data of 64 pixels per row, and then convert it into 8 ⁇ 8 data blocks for processing; in another way, assuming that a burst transmission only processes the data of 1 clock, which is equivalent to Read the data of 8 pixels in one row each time, then send the storage address of the next row of data through the address channel, and continue to read the data of 8 pixels in the next row, but this method requires sending the address information multiple times to read each row.
  • the data of 8 pixels is composed of an 8 ⁇ 8 data block, causing the overall transmission efficiency to be too low.
  • the purpose of the embodiments of the present application is to provide an image data transmission method, device and electronic equipment that can solve the problem of low transmission efficiency in the related art when image data blocks are transmitted without increasing cache storage space.
  • embodiments of the present application provide an image data transmission method, which method includes:
  • the image data is transmitted according to the first address information and the address offset of each transmission, wherein, after each row of image data is transmitted, the first address of the row is added to the address offset to skip. Go to the first address of the next line and transmit the next line of image data.
  • an image data transmission device including:
  • the first acquisition module is used to acquire image data format information
  • the first determination module is used to determine the address offset according to the image data format information
  • the second acquisition module is used to obtain the first address information of each transmission of image data
  • a transmission module configured to transmit image data according to the first address information of each transmission and the address offset, wherein, after each row of image data is transmitted, the first address of the row plus the address offset is used. Shift to jump to the first address of the next line and transmit the next line of image data.
  • inventions of the present application provide an electronic device.
  • the electronic device includes a processor and a memory.
  • the memory stores programs or instructions that can be run on the processor.
  • the programs or instructions are processed by the processor.
  • the processor is executed, the steps of the image data transmission method described in the first aspect are implemented.
  • embodiments of the present application provide a readable storage medium.
  • Programs or instructions are stored on the readable storage medium.
  • the image data transmission as described in the first aspect is implemented. Method steps.
  • inventions of the present application provide a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is used to run programs or instructions to implement the first aspect.
  • the image data transmission method is used to run programs or instructions to implement the first aspect.
  • embodiments of the present application provide a computer program product.
  • the program product is stored In the storage medium, the program product is executed by at least one processor to implement the image data transmission method as described in the first aspect.
  • the image data format information is obtained; the address offset is determined according to the image data format information; the first address information of each transmission of the image data is obtained; and the first address information of each transmission is obtained and the The address offset is used to transmit image data.
  • the first address of the line is added to the address offset to jump to the first address of the next line and the next line of image is transmitted. data.
  • the address offset it can automatically jump to the transmission address of the next line of image data based on the first address information and address offset during transmission, thereby achieving continuous transmission of multiple lines of image data without increasing cache storage. While saving space, it improves the transmission efficiency of image data blocks.
  • Figure 1a is one of the schematic diagrams of the AXI bus transmitting image data with different burst transmission lengths provided by the embodiment of the present application;
  • Figure 1b is the second schematic diagram of the AXI bus transmitting image data with different burst transmission lengths provided by the embodiment of the present application;
  • Figure 2 is an example diagram of image processing from the upper left to the lower right in units of 8 ⁇ 8 pixel blocks provided by the embodiment of the present application;
  • Figure 3 is an example diagram of the image data of the camera provided by the embodiment of the present application being transmitted and stored in units of one line;
  • Figure 4 is an example diagram in which the JPEG image compression provided by the embodiment of the present application is processed in units of 8 ⁇ 8 pixel blocks;
  • Figure 5 is an example diagram in which the AXI bus provided by the embodiment of the present application jumps in each row to transmit image data to meet the format requirements of the pixel block;
  • Figure 6 is a flow chart of an image data transmission method provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of the AXI address space mapping module in the data flow provided by the embodiment of this application.
  • Figure 8 is a schematic diagram of the AXI address space mapping module provided by the embodiment of this application.
  • Figure 9 The embodiment of this application provides address mapping based on AXI address information and continuously reads 8 lines. Example plot of image data;
  • Figure 10 is a schematic structural diagram of an image data transmission device provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the module structure of the electronic device provided by the embodiment of the present application.
  • Figure 12 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application.
  • first, second, etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in orders other than those illustrated or described herein, and that "first,” “second,” etc. are distinguished Objects are usually of one type, and the number of objects is not limited. For example, the first object can be one or multiple.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the related objects are in an "or” relationship.
  • Figure 2 is an example of processing from the upper left to the lower right of the image in units of 8 ⁇ 8 data blocks.
  • the image data collected by the camera is transmitted in units of each line of data according to the Camera Serial Interface 2 (CSI-2) specification.
  • CSI-2 Camera Serial Interface 2
  • the image data transmitted from the camera is saved to the memory, it is generally saved line by line in the manner recommended by the specification. After all the data in one line is stored, the next line is saved. For example, in Figure 3, the entire row of data in the first row is processed first, then the data in the next row is processed, and then the data in the third row is processed, row by row from the upper left to the lower right.
  • the image data will be transmitted and processed between different modules, as well as between modules and memories as needed.
  • the AXI bus is a widely used bus protocol for data transmission between the chip's internal processing module and memory.
  • the AXI bus is often used for data transmission. For example, image data is read from the memory and sent to the image processing module for processing, or image data output by the image processing module is written into the memory.
  • the AXI bus has an address channel and a data channel.
  • the address channel specifies the first address of the memory to be accessed.
  • the data channel continuously writes or reads data in sequence from the first address set by the address channel. In burst transmission mode, data of multiple clock cycles can be transmitted on the data channel to improve the efficiency of data transmission.
  • JPEG Joint Photographic Experts Group
  • the Joint Photographic Experts Group (JPEG) image processing module is an example of processing image data according to data blocks.
  • JPEG is a widely used still image compression standard.
  • the compressed image is processed in units of 8 ⁇ 8 pixel blocks, from the upper left to the lower right of the image.
  • the method mentioned in this application is not only applicable to JPEG, but also to all modules that need to process data according to image data blocks.
  • the first address of each burst transmission needs to be set according to the way the data in the memory is stored in rows, but at the same time, necessary adjustments need to be made according to the format of the required data block.
  • the following description takes an 8 ⁇ 8 data block as an example. Other data blocks can also be processed in a similar manner.
  • the AXI bus when processing the 8 ⁇ 8 data block in the upper left corner in Figure 5, the AXI bus must first read the 8 pixel data in row 1 starting from column 1, and then jump to transmit the 8 pixels in row 2 starting from column 1. pixels of data, and so on until the 8 pixels of data starting from the 8th row and 1st column are transmitted. When the 8 pixel data of rows 1 to 8 are all transmitted, the data transmission of the 8 ⁇ 8 pixel block is completed.
  • the pixel depth of image data has various specifications such as 8, 10, 12, 14, and 16.
  • AXI data channel The data bit width is currently 64 or 128 bits, and burst transmission can perform data transmission of multiple clocks such as 4, 8, 16, etc.
  • Figure 1a and Figure 1b are simple example diagrams of AXI reading image data. Taking the pixel depth of image data as an 8-bit depth as an example, the data of 8 pixels in a row is 64 bits. Assuming that the data bit width of AXI is 64 bits, then to transmit image data with 8 bit depth and 8 pixels per line, only one clock transmission is required for each burst transmission. In Figure 1a, AXI transmits 8 clocks of data in a burst, which is equivalent to reading 64 pixels of data in a row each time.
  • the embodiments of this application provide a solution for efficiently transmitting image data blocks based on the order in which the image data blocks are processed and stored in the memory, as well as the transmission characteristics of the AXI address and data channel, thereby achieving the goal of eliminating the need for additional cache storage. While using space, the purpose is to improve the efficiency of image data block transmission.
  • Figure 6 is a flow chart of an image data transmission method provided by an embodiment of the present application. As shown in Figure 6, the method includes the following steps:
  • Step 601 Obtain image data format information.
  • the embodiment of the present application can be applied to the scenario of transmitting image data blocks on the AXI bus.
  • the address mapping space is converted. After reading the pixel data required for each row of data, the address jumps to the address of the next row of data and continues to read the pixel data required for the next row, thereby achieving continuous reading of image data processing. The data for the required data block.
  • an AXI address space mapping module can be added between the AXI bus data transmission processing module and the register.
  • the address space mapping is performed, thereby continuously reading Get the data of the data block required by the image processing module.
  • the internal structure diagram and data flow information of the AXI address space mapping module can be shown in Figure 8.
  • the image data format information can first be obtained to determine the address offset based on the image data format information. Specifically, relevant image data format information, such as the size of the transmitted image data block, pixel depth, and the number of pixels in each row, can be obtained during the initial configuration.
  • the AXI address space mapping module when initializing and configuring related modules including the image processing module at the application layer, the AXI address space mapping module also obtains image data format information, including image data block size, data type, pixel depth, and pixels for each row. Number, address space to store each pixel component of each row, etc.
  • Step 602 Determine the address offset according to the image data format information.
  • the AXI address mapping module can calculate the number of clocks required to complete the transmission of pixel data required for each row, and the address offset of each row of image data in the memory, that is, the pixels required for each row After the data is transferred, the address required to jump to the next line is used.
  • the Y/Cb/Cr components can be similarly processed by component.
  • the image data format information includes pixel depth and the number of pixels in each line;
  • the step 602 includes:
  • the address offset is determined based on the product of the pixel depth and the number of pixels in each row.
  • the image data format information includes the pixel depth and the number of pixels in each row, then the address offset can be determined based on the product of the pixel depth and the number of pixels in each row.
  • each row of the image has 128 pixels
  • the data of each pixel component is stored in a designated address space, and the pixels of each row are stored continuously
  • the amount of data in one line of each pixel component is 8 bits Shift 1024 bits, that is, add 1024 bits to the first address, and then transmit the next line of image data.
  • the address offset can be quickly determined based on the product of the pixel depth and the number of pixels in each row, thereby achieving continuous transmission of multiple rows of image data.
  • the image data format information includes address space information occupied by pixels in each row;
  • Determining the address offset according to the image data format information includes:
  • the address space size of each row is determined as the address offset.
  • the image data format information may include address space information occupied by each row of pixels, that is, when the pixels of different rows of each component are not stored in continuous address intervals without interruption, but each row is designated.
  • address space is one row, the address offset can be directly determined based on the address space size of each row.
  • each row is specified to have a 2048-bit address space, then each row will only occupy the specified 2048-bit address.
  • the first 1024 bits of the space so when jumping to the next line of transmission, an offset of 2048 bits needs to be added, and the address offset can be determined to be 2048 bits.
  • the address offset can be determined based on the specified address space size occupied by the pixels in each row, thereby achieving continuous transmission of multiple rows of image data.
  • Step 603 Obtain the first address information of each transmission of image data.
  • the AXI address space mapping module can obtain the first address of each burst transmission from the AXI bus address channel.
  • the transmission includes reading memory data or writing data to the memory.
  • data of one or more clock cycles can be transmitted at a time.
  • One image data block includes multiple lines of data.
  • the transmission of one line of data requires one or more clock cycles.
  • the number of times required to complete the transmission of an image data block is also different.
  • the number of clock cycles in one transmission can transmit one image data block, only one burst transmission is required to transmit one image data block.
  • Transmitting a block of image data requires multiple burst transfers.
  • the method further includes:
  • the step 603 includes:
  • the number of transmissions required to transmit an image data block can be determined based on the number of clock cycles of each burst transmission, the size of the image data block and the transmission data bit width, and then the number of transmissions required for each transmission can be obtained based on the number of transmissions.
  • First address information the number of transmissions required to transmit an image data block can be determined based on the number of clock cycles of each burst transmission, the size of the image data block and the transmission data bit width, and then the number of transmissions required for each transmission can be obtained based on the number of transmissions.
  • the number of clock cycles for each burst transmission processing of AXI can be determined. This information can usually be preset by the system, and then the number of clock cycles for one transmission processing, image data block size information and transmission data bit width can be determined. The number of data lines that can be transmitted by burst transmission, and then the number of transmissions required to transmit an image data block is calculated.
  • each clock cycle processes 64 bits of data, which is equivalent to 8 pixels of data. quantity, that is to say, one row of data can be processed in one clock cycle. If AXI handles 4 clock cycles per burst transfer, then 4 lines of data can be transferred at one time, and it takes 2 transfers to transfer an 8 ⁇ 8 image data block. In this way, starting from the first address specified by the first burst transmission, the first clock cycle transmits the data of 8 pixels of the specified row, then adds the 1024-bit offset to the first address, and reads the 8 pixels of the next row.
  • AXI sends the first address of the fifth row again through the address channel, starts the second transmission, continues to read the subsequent 4 rows of data, and completes the reading of the 8 ⁇ 8 data block.
  • AXI processes 8 clock cycles for each burst transfer, then AXI only needs to send address information once to read 8 lines of data, that is, one image data block only needs to be transferred once.
  • the number of transmissions required to transmit an image data block can be determined, and the first address information of each transmission can be obtained to ensure the smooth progress of image data transmission.
  • determining the number of transmissions required to transmit an image data block based on the number of clock cycles and the image data block size and transmission data bit width in the image data format information includes:
  • the number of transmissions required to transmit one image data block is determined based on the number of pixels processed per clock cycle and the number of clock cycles.
  • the image data format information may include pixel depth, image data block size and transmission data bit width, so that the processing of each clock cycle can be determined based on the pixel depth, image data block size and transmission data bit width.
  • the number of pixels processed per clock cycle and the number of clock cycles processed in one transmission can be combined to determine the number of transmissions required to transmit an image data block.
  • each clock cycle can process 64 bits of data, which is equivalent to the amount of data of 8 pixels. , that is to say, one row of data can be processed in one clock cycle. If AXI handles 4 clock cycles per burst transfer, then 4 lines of data can be transferred at one time, and it takes 2 transfers to transfer an 8 ⁇ 8 image data block.
  • the 64-bit data processed by each clock is only equivalent to the amount of data of 4 pixels. At this time, each row of 8 pixels of data requires 2 clock cycles to be processed. If AXI handles 4 clock cycles per burst transfer, then only 2 lines of data can be transferred at a time, and 4 times are required to transfer an 8 ⁇ 8 image data block.
  • the number of transmissions required to transmit one image data block can be determined more accurately.
  • Step 604 According to the first address information of each transmission and the address offset, perform a graph Image data transmission, wherein after each line of image data is transmitted, the first address of the line plus the address offset is used to jump to the first address of the next line to transmit the next line of image data.
  • the image data transmission module in the AXI address space mapping module transmits image data according to the memory address specified by the address space mapping.
  • the address space mapping is performed according to the characteristics of the image data block being processed, and the data required by the current row is processed starting from the first address, instead of following the default continuous increment method of the AXI bus.
  • similar line-by-line processing is performed until the data of one image data block is transmitted.
  • step 604 includes:
  • the image data of the j-th row where the first address information is located is transmitted, i is an integer greater than or equal to 1, and j is a positive integer;
  • the row where the first address information is located can be transmitted based on the first address information of the i-th transmission. After completing the image data transmission of this row, you can add the address offset to the first address of the i-th transmission and jump to transmit the image data of the next row, and so on, each time a row of image data is transmitted , add the address offset to the address of the row, and transmit the image data of the next row until the i-th transmission is completed.
  • the first address information of the i+1th transmission can be obtained, and the i+1th transmission is completed in a similar manner to the i-th transmission until one image data block is completed. transmission.
  • each image data block can be transmitted in sequence according to the transmission method of one image data block introduced in the embodiment of this application.
  • the image data block size is 8 ⁇ 8
  • the data bit width of AXI and memory is 64 bits
  • the image is 8 bits deep
  • each line of the image has 128 pixels
  • the data of each pixel component is stored in the specified address space.
  • the pixels of each row are stored continuously.
  • each clock cycle processes 64 bits of data, which is equivalent to the amount of data of 8 pixels.
  • AXI processes 4 clock cycles for each burst transfer, then starting from the specified first address, the first clock cycle transmits the data of 8 pixels of the specified row, then the first address is added to the 1024-bit offset, and the next read One line of 8 pixels of data, and so on, read 4 lines of data of 8 pixels each. After that, AXI sends the first address of the fifth row again through the address channel, continues to read the subsequent 4 rows of data, and completes the reading of the 8 ⁇ 8 data block.
  • AXI handles 8 clock cycles per burst transfer, then AXI only needs to send address information once to read 8 rows of data.
  • the depth of the image is 16 bits under the above conditions, and other conditions remain unchanged, then the 64-bit data processed by each clock is only equivalent to the amount of data of 4 pixels. At this time, 8 pixels of data per row require 2 clocks. Processing completed.
  • each row will occupy only The first 1024 bits of the specified 2048-bit address space, so when jumping to the next line, an offset of 2048 bits needs to be added.
  • an example diagram of 8 ⁇ 8 data block processing is used to illustrate the difference between the implementation of the embodiment of the present application and the existing technology. It is assumed here that the data bit width of AXI and memory is 64 bits, and the image is 8 bits deep. , burst transfer reads data for 8 clock cycles each time. In the example in Figure 9, starting from the address of the first row, AXI will increase the address by default and continuously read the data of 64 pixels in the first row. In the example in Figure 9, through address mapping processing, after reading the data of 8 pixels in the first row, the next clock cycle will jump to the address of the second row to read the 8 pixels in the second row. By analogy, 8 pixels of each of the 8 rows of data are read to form an 8 ⁇ 8 data block. In this way, only one burst transmission is needed to complete the processing of an 8 ⁇ 8 data block, and the transmission efficiency is greatly improved.
  • the embodiment of the present application adds an AXI address space mapping module between the AXI bus data transmission processing module and the memory, and performs address space mapping when the AXI bus processing module accesses the memory, thereby achieving continuous reading of the data of the data blocks required for image processing. , to achieve the purpose of improving the efficiency of image data block transmission based on AXI bus transmission without increasing the storage space for cache.
  • the image data transmission method in the embodiment of the present application obtains image data format information; determines the address offset according to the image data format information; obtains the first address information of each transmission of image data; and obtains the first address information of each transmission according to the first address of each transmission.
  • the address information and the address offset are used to transmit image data. After each row of image data is transmitted, the first address of the row is added to the address offset to jump to the first address of the next row. Transfer the next line of image data.
  • determining the address offset it can automatically jump to the transmission address of the next line of image data based on the first address information and address offset during transmission, thereby achieving continuous transmission of multiple lines of image data without increasing cache storage. While saving space, it improves the transmission efficiency of image data blocks.
  • the execution subject may be an image data transmission device.
  • an image data transmission device performing an image data transmission method is used as an example to illustrate the image data transmission device provided by the embodiment of the present application.
  • the image data transmission device 1000 includes:
  • the first acquisition module 1001 is used to acquire image data format information
  • the first determination module 1002 is used to determine the address offset according to the image data format information
  • the second acquisition module 1003 is used to acquire the first address information of each transmission of image data
  • the transmission module 1004 is used to transmit image data according to the first address information of each transmission and the address offset. Wherein, after each row of image data is transmitted, the first address of the row is added to the address. Offset to jump to the first address of the next line and transmit the next line of image data.
  • the image data format information includes pixel depth and the number of pixels in each line;
  • the first determining module 1002 is configured to determine the address according to the product of the pixel depth and the number of pixels in each row.
  • the image data format information includes address space information occupied by pixels in each row;
  • the first determination module 1002 includes:
  • a first determination unit configured to determine the address space size of each row based on the address space information occupied by the pixels of each row;
  • a second determination unit is configured to determine the address space size of each row as the address offset.
  • the image data transmission device 1000 also includes:
  • the second determination module is used to determine the number of clock cycles for each transmission and processing of image data
  • the second acquisition module 1003 includes:
  • a third determination unit configured to determine the number of transmissions required to transmit an image data block based on the number of clock cycles and the image data block size and transmission data bit width in the image data format information
  • the obtaining unit is used to obtain the first address information of each transmission in the number of transmissions.
  • the third determining unit includes:
  • a first determination subunit configured to determine the number of pixels processed in each clock cycle based on the pixel depth in the image data format information, the image data block size and the transmission data bit width;
  • the second determination subunit is configured to determine the number of transmissions required to transmit an image data block based on the number of pixels processed per clock cycle and the number of clock cycles.
  • the transmission module 1004 includes:
  • the first transmission unit is used to transmit the image data of the j-th row where the first address information is located according to the first address information transmitted in the i-th time, where i is an integer greater than or equal to 1, and j is a positive integer;
  • the second transmission unit is used to add the first address information of the i-th transmission to the address offset to obtain the first address information of the j+1th row;
  • the image data transmission device in the embodiment of the present application obtains image data format information; determines the address offset according to the image data format information; obtains the first address information of each transmission of image data; and obtains the first address information of each transmission according to the first address of each transmission.
  • the address information and the address offset are used to transmit image data. After each row of image data is transmitted, the first address of the row is added to the address offset to jump to the first address of the next row. Transfer the next line of image data.
  • determining the address offset it can automatically jump to the transmission address of the next line of image data based on the first address information and address offset during transmission, thereby achieving continuous transmission of multiple lines of image data without increasing cache storage. While saving space, it improves the transmission efficiency of image data blocks.
  • the image data transmission device in the embodiment of the present application may be an electronic device or a component in the electronic device, such as an integrated circuit or chip.
  • the electronic device may be a terminal or other devices other than the terminal.
  • the electronic device can be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle-mounted electronic device, a mobile Internet device (MID), or an augmented reality (Augmented Reality, AR)/virtual reality (Virtual Reality, VR) ) equipment, robots, wearable devices, ultra-mobile personal computers (Ultra-Mobile Personal Computer, UMPC), netbooks or personal digital assistants (Personal Digital Assistant, PDA), etc., and can also be servers, network attached storage (Network Attached Storage, NAS), personal computer (Personal Computer, PC), television (Television, TV), teller machine or self-service machine, etc., the embodiments of this application are not specifically limited.
  • Network Attached Storage Network Attached Storage
  • PC Personal Computer
  • TV Television
  • the image data transmission device in the embodiment of the present application may be a device with an operating system.
  • the operating system can be an Android operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of this application.
  • the image data transmission device provided by the embodiment of the present application can implement the method embodiment in Figure 6 To avoid repetition, the various processes will not be described here.
  • this embodiment of the present application also provides an electronic device 1100, including a processor 1101 and a memory 1102.
  • the memory 1102 stores programs or instructions that can be run on the processor 1101.
  • the program or instruction is executed by the processor 1101, each step of the above image data transmission method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, the details will not be described here.
  • the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.
  • Figure 12 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of the present application.
  • the electronic device 1200 includes but is not limited to: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, processor 1210, etc. part.
  • the electronic device 1200 may also include a power supply (such as a battery) that supplies power to various components.
  • the power supply may be logically connected to the processor 1210 through a power management system, thereby managing charging, discharging, and function through the power management system. Consumption management and other functions.
  • the structure of the electronic device shown in Figure 12 does not constitute a limitation of the electronic device.
  • the electronic device may include more or less components than shown in the figure, or combine certain components, or arrange different components, which will not be described again here. .
  • processor 1210 is used for:
  • the image data is transmitted according to the first address information and the address offset of each transmission, wherein, after each row of image data is transmitted, the first address of the row is added to the address offset to skip. Go to the first address of the next line and transmit the next line of image data.
  • the image data format information includes pixel depth and the number of pixels in each line;
  • the processor 1210 is further configured to determine the address offset based on the product of the pixel depth and the number of pixels in each row.
  • the image data format information includes address space information occupied by pixels in each row;
  • Processor 1210 also used for:
  • the address space size of each row is determined as the address offset.
  • processor 1210 is also used to:
  • processor 1210 is also used to:
  • the number of transmissions required to transmit one image data block is determined based on the number of pixels processed per clock cycle and the number of clock cycles.
  • processor 1210 is also used to:
  • the image data of the j-th row where the first address information is located is transmitted, i is an integer greater than or equal to 1, and j is a positive integer;
  • the electronic device in the embodiment of the present application obtains image data format information; determines the address offset according to the image data format information; obtains the first address information of each transmission of image data; and obtains the first address information of each transmission according to the first address information of each transmission. and the address offset, to transmit image data. After each row of image data is transmitted, the first address of the row is added to the address offset to jump to the first address of the next row, and the next row is transmitted. A row of image data. In this way, by determining the address offset, the During transmission, it automatically jumps to the transmission address of the next line of image data based on the first address information and address offset, thereby achieving continuous transmission of multiple lines of image data, which can improve the transmission efficiency of image data blocks without increasing the storage space for cache. .
  • the input unit 1204 may include a graphics processor (Graphics Processing Unit, GPU) 12041 and a microphone 12042.
  • the graphics processor 12041 is responsible for the image capture device (GPU) in the video capture mode or the image capture mode. Process the image data of still pictures or videos obtained by cameras (such as cameras).
  • the display unit 1206 may include a display panel 12061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 1207 includes at least one of a touch panel 12071 and other input devices 12072 .
  • Touch panel 12071 also known as touch screen.
  • the touch panel 12071 may include two parts: a touch detection device and a touch controller.
  • Other input devices 12072 may include but are not limited to physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be described again here.
  • Memory 1209 may be used to store software programs as well as various data.
  • the memory 1209 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, Image playback function, etc.) etc.
  • memory 1209 may include volatile memory or nonvolatile memory, or memory 1209 may include both volatile and nonvolatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory.
  • Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synch link DRAM, SLDRAM) and Direct Rambus RAM (DRRAM).
  • RAM Random Access Memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • synchronous dynamic random access memory Synchronous DRAM, SDRAM
  • Double data rate synchronous dynamic random access memory Double Data Rate SDRAM, DDRSDRAM
  • Enhanced SDRAM, ESDRAM synchronous dynamic random access memory
  • Synch link DRAM, SLDRAM Direct Rambus RAM
  • Memory 1209 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.
  • the processor 1210 may include one or more processing units; optionally, the processor 1210 integrates an application processor and a modem processor, where the application processor mainly handles operations related to the operating system, user interface, application programs, etc., Modem processors mainly process wireless communication signals, such as baseband processors. It can be understood that the above modem processor may not be integrated into the processor 1210.
  • Embodiments of the present application also provide a readable storage medium.
  • Programs or instructions are stored on the readable storage medium.
  • the program or instructions are executed by a processor, each process of the above image data transmission method embodiment is implemented, and can achieve The same technical effects are not repeated here to avoid repetition.
  • the processor is the processor in the electronic device described in the above embodiment.
  • the readable storage medium includes computer readable storage media, such as computer read-only memory ROM, random access memory RAM, magnetic disk or optical disk, etc.
  • An embodiment of the present application further provides a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is used to run programs or instructions to implement the above embodiments of the image data transmission method. Each process can achieve the same technical effect. To avoid repetition, we will not go into details here.
  • chips mentioned in the embodiments of this application may also be called system-on-chip, system-on-a-chip, system-on-a-chip or system-on-chip, etc.
  • Embodiments of the present application provide a computer program product.
  • the program product is stored in a storage medium.
  • the program product is executed by at least one processor to implement each process of the above image data transmission method embodiment, and can achieve the same technology. The effect will not be described here to avoid repetition.
  • the methods of the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is better. implementation.
  • the technical solution of the present application can be embodied in the form of a computer software product that is essentially or contributes to the existing technology.
  • the computer software product is stored in a storage medium (such as ROM/RAM, disk , optical disk), including several instructions to cause a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of this application.

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Abstract

本申请公开了一种图像数据传输方法、装置和电子设备，属于通信技术领域。获取图像数据格式信息；根据所述图像数据格式信息，确定地址偏移量；获取图像数据每次传输的首地址信息；根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。

Description

图像数据传输方法、装置和电子设备
相关申请的交叉引用
本申请主张在2022年5月24日在中国提交的中国专利申请No.202210573879.3的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于通信技术领域，具体涉及一种图像数据传输方法、装置和电子设备。
背景技术
一些场景中，图像处理模块会根据需要以像素块为单位对图像数据进行处理，而摄像头采集的图像数据是按行进行传输和存储的。当采用高性能可扩展接口(Advanced eXtensible Interface，AXI)对图像数据进行搬运时，每次突发传输的首地址，需要按照存储器中数据按行存储的方式进行设置，但同时又需要按照所需数据块的格式进行必要的调整。
一种方式中，假设一次突发传输8个时钟的数据，相当于每次读取一行中64个像素的数据，这些数据存储在指定地址开始的连续区间中，但该方式需要准备额外的数据存储空间，对读取的每行64个像素的数据进行备份，再转换成8×8的数据块进行处理；另一种方式中，假设一次突发传输只处理1个时钟的数据，相当于每次读取一行中8个像素的数据，然后通过地址通道发送下一行数据的存储地址，继续读取下一行8个像素的数据，但该方式需要多次发送地址信息读取每一行所需的8个像素的数据，从而组成8×8的数据块，导致整体的传输效率太低。
可见，相关技术中图像数据块传输时，在不增加缓存存储空间的情况下，存在传输效率较低的问题。
发明内容
本申请实施例的目的是提供一种图像数据传输方法、装置和电子设备，能够解决相关技术中图像数据块传输时，在不增加缓存存储空间的情况下，存在的传输效率较低的问题。
第一方面，本申请实施例提供了一种图像数据传输方法，该方法包括：
获取图像数据格式信息；
根据所述图像数据格式信息，确定地址偏移量；
获取图像数据每次传输的首地址信息；
根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
第二方面，本申请实施例提供了一种图像数据传输装置，包括：
第一获取模块，用于获取图像数据格式信息；
第一确定模块，用于根据所述图像数据格式信息，确定地址偏移量；
第二获取模块，用于获取图像数据每次传输的首地址信息；
传输模块，用于根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
第三方面，本申请实施例提供了一种电子设备，该电子设备包括处理器和存储器，所述存储器存储可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如第一方面所述的图像数据传输方法的步骤。
第四方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面所述的图像数据传输方法的步骤。
第五方面，本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如第一方面所述的图像数据传输方法。
第六方面，本申请实施例提供一种计算机程序产品，该程序产品被存储 在存储介质中，该程序产品被至少一个处理器执行以实现如第一方面所述的图像数据传输方法。
在本申请实施例中，获取图像数据格式信息；根据所述图像数据格式信息，确定地址偏移量；获取图像数据每次传输的首地址信息；根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。这样，通过确定地址偏移量，可在传输时根据首地址信息和地址偏移量自动跳转至下一行图像数据的传输地址，从而实现连续传输多行图像数据，能够在不增加缓存用存储空间的同时，提升图像数据块的传输效率。
附图说明
图1a是本申请实施例提供的AXI总线以不同突发传输长度传输图像数据的示意图之一；
图1b是本申请实施例提供的AXI总线以不同突发传输长度传输图像数据的示意图之二；
图2是本申请实施例提供的以8×8的像素块为单位从左上到右下进行图像处理的示例图；
图3是本申请实施例提供的摄像头的图像数据以一行为单位进行传输和存储的示例图；
图4是本申请实施例提供的JPEG图像压缩按照8×8像素块单位进行处理的示例图；
图5是本申请实施例提供的AXI总线在每一行中跳转进行图像数据传输以满足像素块的格式要求的示例图；
图6是本申请实施例提供的图像数据传输方法的流程图；
图7本申请实施例提供的AXI地址空间映射模块在数据流中的示意图；
图8本申请实施例提供的AXI地址空间映射模块的概要示意图；
图9本申请实施例提供的根据AXI地址信息进行地址映射连续读取8行 图像数据的示例图；
图10本申请实施例提供的图像数据传输装置的结构示意图；
图11本申请实施例提供的电子设备的模块结构示意图；
图12本申请实施例提供的电子设备的硬件结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
为使本申请实施例更为清楚，下面结合若干示例对本申请实施例的技术背景进行简单介绍：
图像处理芯片在进行图像处理的过程中，在一些场景中需要以图像数据块的方式对图像数据进行处理。例如，图2是一个以8×8数据块为单位，从图像左上到右下进行处理的示例。
而摄像头采集的图像数据，按照相机串行接口2(Camera Serial Interface 2，CSI-2)规范是以每行数据作为单位进行传输。从摄像头传输出来的图像数据保存到存储器中时，一般也按照规范所建议的方式逐行进行保存，一行数据全部存储后再保存下一行。比如图3中，先处理第一行的整行数据，再处理下一行的数据，再处理第三行的数据，依次从左上到右下逐行进行。
在图像处理芯片对图像数据进行处理的过程中，根据需要会将图像数据在不同模块，以及模块与存储器之间进行传输与处理。
AXI总线是一种广泛应用的、用于芯片内部处理模块与存储器之间数据传输的总线协议。图像数据块在图像处理模块与存储器之间进行传输时，也经常使用AXI总线进行数据的传输。比如从存储器中读取图像数据送给图像处理模块进行处理，或者将图像处理模块输出的图像数据写入存储器中。
AXI总线有地址通道和数据通道，地址通道指定要访问的存储器的首地址，数据通道从地址通道设定的首地址按顺序连续写入或读取数据。在突发传输模式下，能够在数据通道上传输多个时钟周期的数据，提高数据传输的效率。
其中，联合图像专家小组(Joint Photographic Experts Group，JPEG)图像处理模块就是一个按照数据块对图像数据进行处理的例子，JPEG是一种广泛应用的静止图像压缩标准，在标准模式下，如图4所示，其对压缩图像的处理是以8×8的像素块为单位，从图像的左上到右下按块进行处理。色彩空间YCbCr根据图像数据类型，所处理的像素块单元还可能会是16×8(YCbCr＝4:2:2)或16×16(YCbCr＝4:2:0)等，但每一个成分在处理时都会以8×8像素块为单位进行。当然本申请所提及的方法不仅适用于JPEG，也同时适用于所有需要按照图像数据块进行数据处理的模块。
当采用AXI总线对图像数据进行搬运时，每一次突发传输的首地址，需要按照存储器中数据按行存储的方式进行设置，但同时又需要按照所需要的数据块的格式进行必要的调整。下面以8×8数据块为例子进行说明，其他数据块也可以按照类似的方式进行处理。
比如图5中处理左上角的8×8数据块时，AXI总线必须先读取第1行从第1列开始的8个像素的数据，然后跳转传输第2行从第1列开始的8个像素的数据，依此类推一直到传输第8行第1列开始的8个像素的数据。当第1～8行的8个像素数据都传输好时，便完成了8×8像素块的数据传输。
图像数据的像素深度有8、10、12、14、16等多种规格。AXI数据通道 的数据位宽目前比较常用的是64或者128比特，突发传输可以执行4、8、16等多个时钟的数据传输。
图1a和图1b是AXI读取图像数据时的简单示例图。以图像数据的像素深度为8比特深度为例，此时一行中8个像素的数据是64比特。假设AXI的数据位宽为64比特，那么传输8比特深度、每行8个像素的图像数据，每次突发传输只需要执行1个时钟的传输。图1a中AXI一次突发传输8个时钟的数据，相当于每次读取一行中64个像素的数据，这些数据存储在指定地址开始的连续区间中；而图1b中的突发传输一次只处理1个时钟的数据，相当于每次读取一行中8个像素的数据，然后通过地址通道发送下一行数据的存储地址，继续读取下一行8个像素的数据。
从图1a和图1b的示例中，可知采用图1a中的方法一次突发传输可以读取多个数据，能够提高AXI数据传输的效率，但需要准备额外的数据存储空间，将读取的每行64个像素的数据进行备份，再转换成8×8的数据块送入图像处理模块进行处理。而如果采用图1b中的方法，每次突发传输只读取每一行8个像素的数据，通过多次发送地址信息读取每一行所需的8个像素的数据，从而组成8×8的数据块，但此时每个突发传输只传输一个时钟周期而且每次都需要传输地址信息，整体的传输效率太低。
本申请实施例根据图像数据块在处理时和在存储器中存放时的顺序，以及AXI地址和数据通道的传输特点，提供了一种高效传输图像数据块的方案，从而达到在不增加缓存用存储空间的同时，提升图像数据块传输效率的目的。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的图像数据传输方法进行详细地说明。
请参见图6，图6为本申请实施例提供的图像数据传输方法的流程图，如图6所示，该方法包括以下步骤：
步骤601、获取图像数据格式信息。
本申请实施例可应用于AXI总线上传输图像数据块的场景。
本申请实施例中，可根据AXI地址通道指定的首地址信息，在实际访问 存储器的时候进行地址映射空间的转换，每读取一行数据所需的像素数据之后，跳转地址到下一行数据的地址继续读取下一行所需的像素数据，从而实现连续读取图像数据处理所需数据块的数据。
具体地，如图7所示，可在AXI总线数据传输处理模块与存期器之间增加AXI地址空间映射模块，在AXI总线数据传输处理模块访问存储器时，进行地址空间的映射，从而连续读取图像处理模块所需数据块的数据。其中，AXI地址空间映射模块的内部结构图和数据流信息可以如图8所示。
为实现地址空间的映射，首先可获取图像数据格式信息，以根据所述图像数据格式信息，确定地址偏移量。具体地，可在初始化配置时，获取相关的图像数据格式信息，如传输的图像数据块大小、像素深度和每行的像素个数等信息。
例如，可在应用层对包括图像处理模块在内的相关模块进行初始化配置时，AXI地址空间映射模块也相应取得图像数据格式信息，包括图像数据块大小、数据类型、像素深度、每一行的像素数、存储每一行各像素成分的地址空间等。
步骤602、根据所述图像数据格式信息，确定地址偏移量。
AXI地址映射模块根据获得的这些图像数据格式信息，可以计算出完成每一行所需像素数据传输需要的时钟数，以及每一行图像数据在存储器中的地址偏移量，即每一行所需的像素数传输后，跳转到下一行时所需要要跳转的地址。另外根据图像数据类型，Y/Cb/Cr成分可按照成分进行类似的处理。
可选地，所述图像数据格式信息包括像素深度和每行的像素个数；
所述步骤602包括：
根据所述像素深度和每行的像素个数的乘积，确定所述地址偏移量。
即一种实施方式中，所述图像数据格式信息包括像素深度和每行的像素个数，则可以根据所述像素深度和每行的像素个数的乘积，确定地址偏移量。
例如，图像像素深度为8比特深度，图像每一行有128个像素，各个像素成分的数据各自存放在指定的地址空间中，而且各行的像素连续存放，那 么可确定每个像素成分一行的数据量为8比特×128像素＝1024比特，从而可确定地址偏移量为1024比特，在传输图像数据时，每传输完一行图像数据，可以将传输地址偏移1024比特，即将首地址加上1024比特后，再传输下一行的图像数据。
这样，通过该实施方式，可在各行像素连续存放的情况下基于像素深度和每行的像素个数的乘积，快速确定地址偏移量，进而实现连续传输多行图像数据。
可选地，所述图像数据格式信息包括每行像素占用的地址空间信息；
所述根据所述图像数据格式信息，确定地址偏移量，包括：
根据所述每行像素占用的地址空间信息，确定每行的地址空间大小；
将所述每行的地址空间大小确定为所述地址偏移量。
另一种实施方式中，所述图像数据格式信息可包括每行像素占用的地址空间信息，即当每一个成分的不同行的像素，不是不间断地存储在连续地址区间中，而是指定每一行的地址空间时，可根据每行的地址空间大小，直接确定地址偏移量。
例如，每一个成分的不同行的像素，不是不间断地存储在1024比特的连续地址区间中，而是指定每一行都有2048比特的地址空间，那么每一行都会在只占用指定的2048比特地址空间的前1024比特，从而在跳转到下一行传输时需要增加2048比特的偏移量，即可确定地址偏移量为2048比特。
这样，通过该实施方式，可在各行像素不连续存放的情况下，基于指定的每行像素占用的地址空间大小，确定地址偏移量，进而实现连续传输多行图像数据。
步骤603、获取图像数据每次传输的首地址信息。
该步骤中，AXI地址空间映射模块可以从AXI总线地址通道取得每一次突发传输的首地址，所述传输包括读取存储器数据或向存储器写入数据。需说明的是，本申请实施例中，一次可以传输一个或多个时钟周期的数据，一个图像数据块包括多行数据，一行数据的传输需要一个或多个时钟周期，随 着一次传输的时钟周期数的不同，完成一个图像数据块的传输所需的次数也相应不同。当一次传输的时钟周期数能够传输完一个图像数据块时，传输一个图像数据块只需要进行一次突发传输，当一次传输的时钟周期数只能够传输完一个图像数据块中的若干行时，传输一个图像数据块需要进行多次突发传输。
可选地，所述步骤603之前，所述方法还包括：
确定图像数据每次传输处理的时钟周期数；
所述步骤603包括：
根据所述时钟周期数和所述图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数；
获取所述传输次数中每次传输的首地址信息。
一种实施方式中，可以根据每次突发传输的时钟周期数、图像数据块大小及传输数据位宽确定传输一个图像数据块所需的传输次数，进而可基于传输次数，获取每次传输的首地址信息。
具体地，可确定AXI每次突发传输处理的时钟周期数，该信息通常可以由系统预设，然后可根据一次传输处理的时钟周期数、图像数据块大小信息及传输数据位宽，确定一次突发传输所能传输的数据行数，进而计算出传输一个图像数据块所需要的传输次数。
例如，假设图像数据块大小为8×8，AXI和存储器的数据位宽都为64比特，图像像素深度为8比特，这时每一个时钟周期处理64比特的数据，相当于8个像素的数据量，也就是说一个时钟周期能处理一行数据。如果AXI每次突发传输处理4个时钟周期，那么一次可以传输4行数据，传输一个8×8的图像数据块需要传输2次。这样，从第一次突发传输指定的首地址开始，第一个时钟周期传输指定行的8个像素的数据，然后将首地址加上1024比特偏移量，读取下一行的8个像素的数据，依此类推读取4行数据的各8个像素。此后AXI再次通过地址通道发送第五行的首地址，开始第二次传输，继续读取后续4行数据，完成8×8数据块的读取。
如果AXI每次突发传输处理8个时钟周期，那么AXI只需要发送一次地址信息，就可以读取8行数据，即一个图像数据块只需传输一次。
这样，通过该实施方式，可以确定传输一个图像数据块所需的传输次数，进而获取每次传输的首地址信息，保证图像数据传输的顺利进行。
进一地，所述根据所述时钟周期数和所述图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数，包括：
根据所述图像数据格式信息中的像素深度、所述图像数据块大小和所述传输数据位宽，确定每个时钟周期处理的像素数；
根据所述每个时钟周期处理的像素数和所述时钟周期数，确定传输一个图像数据块所需的传输次数。
该实施方式中，所述图像数据格式信息可包括像素深度、图像数据块大小和传输数据位宽，从而可根据所述像素深度、图像数据块大小和传输数据位宽，确定每个时钟周期处理的像素数，进而可结合所述每个时钟周期处理的像素数和一次传输处理的时钟周期数，确定传输一个图像数据块所需的传输次数。
例如，假设图像数据块大小为8×8，AXI和存储器的数据位宽都为64比特，图像像素深度为8比特，每一个时钟周期能处理64比特的数据，相当于8个像素的数据量，也就是说一个时钟周期能处理一行数据。如果AXI每次突发传输处理4个时钟周期，那么一次可以传输4行数据，传输一个8×8的图像数据块需要传输2次。
如果图像像素深度是16比特，那么每个时钟处理的64比特数据只相当于4个像素的数据量，这时每一行8个像素的数据需要2个时钟周期才能处理完成。如果AXI每次突发传输处理4个时钟周期，那么一次只能传输2行数据，传输一个8×8的图像数据块便需要传输4次。
这样，通过该实施方式，可以更为准确地确定传输一个图像数据块所需的传输次数。
步骤604、根据所述每次传输的首地址信息和所述地址偏移量，进行图 像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
该步骤中，AXI地址空间映射模块中的图像数据传输模块，按照地址空间映射所指定的存储器地址，进行图像数据的传输。
具体地，本申请实施例中，在实际访问存储器时，不是按照AXI总线默认的连续递增的方式，而是按照处理的图像数据块的特点进行地址空间映射，从首地址开始处理好当行所需的像素数据后，根据地址偏移量，跳转至下一行的地址(即下一行的地址＝上一行起始地址+一行数据的地址偏移量)，继续处理下一行所需的像素数据，逐行处理直到完成一次突发传输的所有传输时钟。再根据下次传输的首地址信息和地址偏移量，进行类似的逐行处理，直至传输完一个图像数据块的数据。
可选地，所述步骤604包括：
根据第i次传输的首地址信息，传输所述首地址信息所在的第j行的图像数据，i为大于或等于1的整数，j为正整数；
将所述第i次传输的首地址信息加上所述地址偏移量，得到第j+1行的首地址信息；
根据所述第j+1行的首地址信息，传输所述第j+1行的图像数据；
其中，每传输完一行图像数据，将该行的首地址加上所述地址偏移量，开始下一行的图像数据传输，直至完成第i次传输。
即在根据每次传输的首地址信息和地址偏移量，进行图像数据的传输时，对于第i次突发传输，可以根据第i次传输的首地址信息，传输所述首地址信息所在行的图像数据，完成该行图像数据传输后，可以将所述第i次传输的首地址加上地址偏移量，跳转至传输下一行的图像数据，依此类推，每传输完一行图像数据，将该行的地址加上所述地址偏移量，传输下一行的图像数据，直至第i次传输完成。在第i次传输非末次传输的情况下，可以获取第i+1次传输的首地址信息，并按照与第i次传输类似的方式，完成第i+1次传输，直至完成一个图像数据块的传输。
这样，通过该实施方式，能够保证按序完成每次图像数据传输。
需说明的是，对于需要传输多个图像数据块的场景，可按照本申请实施例中介绍的一个图像数据块的传输方式来依次完成每个图像数据块的传输。
假设图像数据块大小为8×8，AXI和存储器的数据位宽都为64比特，图像为8比特深度，图像每一行有128个像素，各个像素成分的数据各自存放在指定的地址空间中，而且各行的像素连续存放。这时每一个时钟周期处理64比特的数据，相当于8个像素的数据量。每个像素成分一行的数据量为8比特×128像素＝1024比特。
如果AXI每次突发传输处理4个时钟周期，那么从指定的首地址开始，第一个时钟周期传输指定行的8个像素的数据，然后首地址加上1024比特偏移量，读取下一行的8个像素的数据，依此类推读取4行数据的各8个像素。此后AXI再次通过地址通道发送第五行的首地址，继续读取后续4行数据，完成8×8数据块的读取。
如果AXI每次突发传输处理8个时钟周期，那么AXI只需要发送一次地址信息，就可以读取8行数据。
如果以上条件中，图像的深度是16比特，其他条件不变，那么每个时钟处理的64比特数据只相当于4个像素的数据量，这时每一行8个像素的数据需要2个时钟才能处理完成。
如果以上条件中，每一个成分的不同行的像素在存储时，不是不间断地在1024比特的连续地址区间中，而是指定每一行都有2048比特的地址空间，那么每一行都会在只占用指定的2048比特地址空间的前1024比特，从而跳转到下一行时需要增加2048比特的偏移量。
需说明的是，实际的地址映射控制可以根据系统需要进行更多的组合调整，但地址映射实现按行跳转以读取所需数据块单元的思想是一致的。这里也不对图像右边缘、下边缘等情况进行额外说明，系统实现时可以按照需要自行调整。如果图像处理模块与AXI总线是异步时钟关系，中间的跨时钟域处理需要进行的数据缓存也不在此赘述。
下面结合图9，以一个8×8数据块处理的示例图来说明本申请实施例实施方式与现有技术的区别，这里假设AXI和存储器的数据位宽都为64比特，图像为8比特深度，突发传输每次读取8个时钟周期的数据。在图9的示例中，从第一行的地址开始，AXI默认会将地址按照递增的方式，连续读取第一行64个像素的数据。而在图9的示例中，通过地址映射处理，在读取第一行的8个像素的数据后，下一个时钟周期会跳转到第二行的地址读取第二行的8个像素，依此类推读取8行数据的各8个像素，从而构成8×8的数据块，这样只需一次突发传输即可完成对一个8×8数据块的处理，传输效率大大提高。
本申请实施例通过在AXI总线数据传输处理模块与存储器之间增加AXI地址空间映射模块，在AXI总线处理模块访问存储器时进行地址空间的映射，从而实现连续读取图像处理所需数据块的数据，达到在不增加缓存用存储空间的同时，提升基于AXI总线传输的图像数据块传输效率的目的。
本申请实施例中的图像数据传输方法，获取图像数据格式信息；根据所述图像数据格式信息，确定地址偏移量；获取图像数据每次传输的首地址信息；根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。这样，通过确定地址偏移量，可在传输时根据首地址信息和地址偏移量自动跳转至下一行图像数据的传输地址，从而实现连续传输多行图像数据，能够在不增加缓存用存储空间的同时，提升图像数据块的传输效率。
本申请实施例提供的图像数据传输方法，执行主体可以为图像数据传输装置。本申请实施例中以图像数据传输装置执行图像数据传输方法为例，说明本申请实施例提供的图像数据传输装置。
请参见图10，图10为本申请实施例提供的图像数据传输装置的结构示意图，如图10所示，图像数据传输装置1000包括：
第一获取模块1001，用于获取图像数据格式信息；
第一确定模块1002，用于根据所述图像数据格式信息，确定地址偏移量；
第二获取模块1003，用于获取图像数据每次传输的首地址信息；
传输模块1004，用于根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
可选地，所述图像数据格式信息包括像素深度和每行的像素个数；
第一确定模块1002用于根据所述像素深度和每行的像素个数的乘积，确定所述地址。
可选地，所述图像数据格式信息包括每行像素占用的地址空间信息；
第一确定模块1002包括：
第一确定单元，用于根据所述每行像素占用的地址空间信息，确定每行的地址空间大小；
第二确定单元，用于将所述每行的地址空间大小确定为所述地址偏移量。
可选地，图像数据传输装置1000还包括：
第二确定模块，用于确定图像数据每次传输处理的时钟周期数；
第二获取模块1003包括：
第三确定单元，用于根据所述时钟周期数和所述图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数；
获取单元，用于获取所述传输次数中每次传输的首地址信息。
可选地，所述第三确定单元，包括：
第一确定子单元，用于根据所述图像数据格式信息中的像素深度、所述图像数据块大小和所述传输数据位宽，确定每个时钟周期处理的像素数；
第二确定子单元，用于根据所述每个时钟周期处理的像素数和所述时钟周期数，确定传输一个图像数据块所需的传输次数。
可选地，传输模块1004包括：
第一传输单元，用于根据第i次传输的首地址信息，传输所述首地址信息所在的第j行的图像数据，i为大于或等于1的整数，j为正整数；
第二传输单元，用于将所述第i次传输的首地址信息加上所述地址偏移量，得到第j+1行的首地址信息；
根据所述第j+1行的首地址信息，传输所述第j+1行的图像数据；
其中，每传输完一行图像数据，将该行的首地址加上所述地址偏移量，开始下一行的图像数据传输，直至完成第i次传输。
本申请实施例中的图像数据传输装置，获取图像数据格式信息；根据所述图像数据格式信息，确定地址偏移量；获取图像数据每次传输的首地址信息；根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。这样，通过确定地址偏移量，可在传输时根据首地址信息和地址偏移量自动跳转至下一行图像数据的传输地址，从而实现连续传输多行图像数据，能够在不增加缓存用存储空间的同时，提升图像数据块的传输效率。
本申请实施例中的图像数据传输装置可以是电子设备，也可以是电子设备中的部件，例如集成电路或芯片。该电子设备可以是终端，也可以为除终端之外的其他设备。示例性的，电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、移动上网装置(Mobile Internet Device，MID)、增强现实(Augmented Reality，AR)/虚拟现实(Virtual Reality，VR)设备、机器人、可穿戴设备、超级移动个人计算机(Ultra-Mobile Personal Computer，UMPC)、上网本或者个人数字助理(Personal Digital Assistant，PDA)等，还可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(Personal Computer，PC)、电视机(Television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的图像数据传输装置可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
本申请实施例提供的图像数据传输装置能够实现图6的方法实施例实现 的各个过程，为避免重复，这里不再赘述。
可选地，如图11所示，本申请实施例还提供一种电子设备1100，包括处理器1101和存储器1102，存储器1102上存储有可在所述处理器1101上运行的程序或指令，该程序或指令被处理器1101执行时实现上述图像数据传输方法实施例的各个步骤，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括上述所述的移动电子设备和非移动电子设备。
图12为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备1200包括但不限于：射频单元1201、网络模块1202、音频输出单元1203、输入单元1204、传感器1205、显示单元1206、用户输入单元1207、接口单元1208、存储器1209、以及处理器1210等部件。
本领域技术人员可以理解，电子设备1200还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器1210逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图12中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，处理器1210，用于：
获取图像数据格式信息；
根据所述图像数据格式信息，确定地址偏移量；
获取图像数据每次传输的首地址信息；
根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
可选地，所述图像数据格式信息包括像素深度和每行的像素个数；
处理器1210，还用于根据所述像素深度和每行的像素个数的乘积，确定所述地址偏移量。
可选地，所述图像数据格式信息包括每行像素占用的地址空间信息；
处理器1210，还用于：
根据所述每行像素占用的地址空间信息，确定每行的地址空间大小；
将所述每行的地址空间大小确定为所述地址偏移量。
可选地，处理器1210，还用于：
确定图像数据每次传输处理的时钟周期数；
根据所述时钟周期数和所述图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数；
获取所述传输次数中每次传输的首地址信息。
可选地，处理器1210，还用于：
根据所述图像数据格式信息中的像素深度、所述图像数据块大小和所述传输数据位宽，确定每个时钟周期处理的像素数；
根据所述每个时钟周期处理的像素数和所述时钟周期数，确定传输一个图像数据块所需的传输次数。
可选地，处理器1210，还用于：
根据第i次传输的首地址信息，传输所述首地址信息所在的第j行的图像数据，i为大于或等于1的整数，j为正整数；
将所述第i次传输的首地址信息加上所述地址偏移量，得到第j+1行的首地址信息；
根据所述第j+1行的首地址信息，传输所述第j+1行的图像数据；
其中，每传输完一行图像数据，将该行的首地址加上所述地址偏移量，开始下一行的图像数据传输，直至完成第i次传输。
本申请实施例中的电子设备，获取图像数据格式信息；根据所述图像数据格式信息，确定地址偏移量；获取图像数据每次传输的首地址信息；根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。这样，通过确定地址偏移量，可在 传输时根据首地址信息和地址偏移量自动跳转至下一行图像数据的传输地址，从而实现连续传输多行图像数据，能够在不增加缓存用存储空间的同时，提升图像数据块的传输效率。
应理解的是，本申请实施例中，输入单元1204可以包括图形处理器(Graphics Processing Unit，GPU)12041和麦克风12042，图形处理器12041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元1206可包括显示面板12061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板12061。用户输入单元1207包括触控面板12071以及其他输入设备12072中的至少一种。触控面板12071，也称为触摸屏。触控面板12071可包括触摸检测装置和触摸控制器两个部分。其他输入设备12072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器1209可用于存储软件程序以及各种数据。存储器1209可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器1209可以包括易失性存储器或非易失性存储器，或者，存储器1209可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link  DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器1209包括但不限于这些和任意其它适合类型的存储器。
处理器1210可包括一个或多个处理单元；可选的，处理器1210集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器1210中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述图像数据传输方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器ROM、随机存取存储器RAM、磁碟或者光盘等。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现上述图像数据传输方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以实现如上述图像数据传输方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情 况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (17)

  1. 一种图像数据传输方法，包括：
    获取图像数据格式信息；
    根据所述图像数据格式信息，确定地址偏移量；
    获取图像数据每次传输的首地址信息；
    根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
  2. 根据权利要求1所述的方法，其中，所述图像数据格式信息包括像素深度和每行的像素个数；
    所述根据所述图像数据格式信息，确定地址偏移量，包括：
    根据所述像素深度和每行的像素个数的乘积，确定地址偏移量。
  3. 根据权利要求1所述的方法，其中，所述图像数据格式信息包括每行像素占用的地址空间信息；
    所述根据所述图像数据格式信息，确定地址偏移量，包括：
    根据所述每行像素占用的地址空间信息，确定每行的地址空间大小；
    将所述每行的地址空间大小确定为所述地址偏移量。
  4. 根据权利要求1所述的方法，其中，所述获取图像数据每次传输的首地址信息之前，所述方法还包括：
    确定图像数据每次传输处理的时钟周期数；
    所述获取图像数据每次传输的首地址信息，包括：
    根据所述时钟周期数和所述图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数；
    获取所述传输次数中每次传输的首地址信息。
  5. 根据权利要求4所述的方法，其中，所述根据所述时钟周期数和所述 图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数，包括：
    根据所述图像数据格式信息中的像素深度、所述图像数据块大小和所述传输数据位宽，确定每个时钟周期处理的像素数；
    根据所述每个时钟周期处理的像素数和所述时钟周期数，确定传输一个图像数据块所需的传输次数。
  6. 根据权利要求1至5中任一项所述的方法，其中，所述根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，包括：
    根据第i次传输的首地址信息，传输所述第i次传输的首地址信息所在的第j行的图像数据，i为大于或等于1的整数，j为正整数；
    将所述第i次传输的首地址信息加上所述地址偏移量，得到第j+1行的首地址信息；
    根据所述第j+1行的首地址信息，传输所述第j+1行的图像数据；
    其中，每传输完一行图像数据，将该行的首地址加上所述地址偏移量，开始下一行的图像数据传输，直至完成第i次传输。
  7. 一种图像数据传输装置，包括：
    第一获取模块，用于获取图像数据格式信息；
    第一确定模块，用于根据所述图像数据格式信息，确定地址偏移量；
    第二获取模块，用于获取图像数据每次传输的首地址信息；
    传输模块，用于根据所述每次传输的首地址信息和所述地址偏移量，进行图像数据的传输，其中，每传输完一行图像数据，使用该行的首地址加上所述地址偏移量，以跳转至下一行的首地址，传输下一行图像数据。
  8. 根据权利要求7所述的图像数据传输装置，其中，所述图像数据格式信息包括像素深度和每行的像素个数；
    所述第一确定模块用于根据所述像素深度和每行的像素个数的乘积，确定所述地址。
  9. 根据权利要求7所述的图像数据传输装置，其中，所述图像数据格式 信息包括每行像素占用的地址空间信息；
    所述第一确定模块，包括：
    第一确定单元，用于根据所述每行像素占用的地址空间信息，确定每行的地址空间大小；
    第二确定单元，用于将所述每行的地址空间大小确定为所述地址偏移量。
  10. 根据权利要求7所述的图像数据传输装置，其中，所述图像数据传输装置还包括：
    第二确定模块，用于确定图像数据每次传输处理的时钟周期数；
    所述第二获取模块包括：
    第三确定单元，用于根据所述时钟周期数和所述图像数据格式信息中的图像数据块大小及传输数据位宽，确定传输一个图像数据块所需的传输次数；
    获取单元，用于获取所述传输次数中每次传输的首地址信息。
  11. 根据权利要求10所述的图像数据传输装置，其中，所述第三确定单元，包括：
    第一确定子单元，用于根据所述图像数据格式信息中的像素深度、所述图像数据块大小和所述传输数据位宽，确定每个时钟周期处理的像素数；
    第二确定子单元，用于根据所述每个时钟周期处理的像素数和所述时钟周期数，确定传输一个图像数据块所需的传输次数。
  12. 根据权利要求7至11中任一项所述的图像数据传输装置，其中，所述传输模块包括：
    第一传输单元，用于根据第i次传输的首地址信息，传输所述首地址信息所在的第j行的图像数据，i为大于或等于1的整数，j为正整数；
    第二传输单元，用于将所述第i次传输的首地址信息加上所述地址偏移量，得到第j+1行的首地址信息；
    根据所述第j+1行的首地址信息，传输所述第j+1行的图像数据；
    其中，每传输完一行图像数据，将该行的首地址加上所述地址偏移量，开始下一行的图像数据传输，直至完成第i次传输。
  13. 一种电子设备，包括处理器和存储器，所述存储器存储可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求1至6中任一项所述的图像数据传输方法的步骤。
  14. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1至6中任一项所述的图像数据传输方法的步骤。
  15. 一种芯片，包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如权利要求1至6中任一项所述的图像数据传输方法的步骤。
  16. 一种计算机程序产品，所述程序产品被存储在非易失的存储介质中，所述程序产品被至少一个处理器执行以实现如权利要求1至6中任一项所述的图像数据传输方法的步骤。
  17. 一种通信设备，其中，被配置为执行如权利要求1至6中任一项所述的图像数据传输方法的步骤。
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