WO2023221597A1

WO2023221597A1 - Storage array and working method for storage array

Info

Publication number: WO2023221597A1
Application number: PCT/CN2023/078656
Authority: WO
Inventors: 赵杰; 刘少鹏; 李�昊; 杨汝辉; 贾秀峰; 张敏; 张恒; 吕杭炳; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2022-05-16
Filing date: 2023-02-28
Publication date: 2023-11-23
Also published as: CN117116318A

Abstract

The present application discloses a storage array and a working method for the storage array. The storage array comprises a plurality of memory cells, a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction, and a plurality of plate lines extending in the column direction. A first end of a first ferroelectric capacitor of each memory cell in an j-th column of memory cells is connected to a j-th bit line, and a second end of a first transistor of each memory cell in the j-th column of memory cells is connected to one of the plurality of plate lines. The solution of the present application can prevent the memory cells from bearing an unnecessary high voltage during reading, reduce the number of times that the ferroelectric capacitors in the memory cells bear a high voltage, and facilitate prolonging of the service life of the storage array.

Description

Storage arrays and how storage arrays work

This application claims priority to the Chinese patent application filed with the China Patent Office on May 16, 2022, with application number 202210530995.7 and the application name "Storage Array and Working Method of Storage Array", the entire content of which is incorporated into this application by reference. middle.

Technical field

The present application relates to the field of semiconductor devices, and in particular, to a memory array and a working method of the memory array.

Background technique

Ferroelectric random access memory (FeRAM) is a device that utilizes the properties of ferroelectric materials for storage.

FeRAM includes a storage array composed of multiple memory cells, and write and read operations adopt full-row writing and full-row reading. During the read process, the ferroelectric capacitors in all memory cells in the same row need to withstand the high voltage when reading data and the high voltage when writing data back. Even if there is no need to read data in all memory cells in the row, the ferroelectric capacitors in all memory cells in the row still need to experience high voltage when reading data and high voltage when writing data back. This will cause the ferroelectric capacitor to experience too many voltage cycles, affecting the performance of the ferroelectric capacitor and thus affecting the service life of FeRAM.

Contents of the invention

This application provides a storage array and a working method of the storage array, which can prevent the storage unit from being subjected to unnecessary high voltage during the reading process, reduce the number of times that the ferroelectric capacitor in the storage unit is subjected to high voltage, and is conducive to improving the service life of the storage array. .

In a first aspect, a memory array is provided, including: a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction, and a plurality of plate lines extending along a column direction, a plurality of Each memory cell in the memory cells includes a first transistor and a first ferroelectric capacitor, a first terminal of the first transistor is connected to a second terminal of the first ferroelectric capacitor, wherein the i-th row of the plurality of memory cells stores The gate terminal of the first transistor of each memory unit in the unit is connected to the i-th word line among the plurality of word lines, i is a positive integer, and the j-th column memory unit among the plurality of memory units The first end of a ferroelectric capacitor is connected to the j-th bit line among the plurality of bit lines, j is a positive integer, and the second end of the first transistor of each memory cell in the j-th column memory unit is connected to the plurality of plate lines. One of the board lines is connected, the first terminal of the first transistor is the source terminal, and the second terminal of the first transistor is the drain terminal, or the first terminal of the first transistor is the drain terminal, and the second terminal of the first transistor is source.

According to the solution of the embodiment of the present application, the extending direction of the plate line and the extending direction of the word line are perpendicular to each other. The memory cells sharing the plate line and the memory cells sharing the word line are not exactly the same. This structure can only be used for those who need to read information. The memory cells read information without reading the entire row of memory cells. During the information reading process, only the ferroelectric capacitors of the memory cells that need to read information can withstand high voltages. The ferroelectric capacitors of other memory cells do not withstand high voltages. , avoiding the entire row of stored single The element needs to withstand high voltage during the reading process, which reduces the number of times the ferroelectric capacitor has to withstand high voltage, which is beneficial to ensuring the service life of the storage array.

In addition, a column of memory cells can share a board line, which is beneficial to reducing the number of board lines and reducing the area occupied by the connection between the board line and the memory unit, thereby increasing the effective storage area and improving storage density. Moreover, the high-potential signal sources required by the board lines can be deployed in peripheral circuits, avoiding the deployment of power supplies between memory cells, which in turn helps increase the effective storage area and improve storage density.

The i-th row of storage units may be any row of storage units among multiple storage units. The jth column storage unit may be any column storage unit among multiple storage units. The i-th word line can be any word line among the plurality of word lines, and the j-th bit line can be any bit line among the plurality of bit lines.

In connection with the first aspect, in some implementations of the first aspect, the second end of the first transistor of each memory cell in the j-th column of memory cells is connected to the j-th plate line among the plurality of plate lines.

For example, multiple storage units are arranged in rows I and columns J. The storage array may include K strip lines. I is an integer greater than 1, J is an integer greater than 1, and K is an integer greater than 1. For example, J is equal to K. In this case, the first transistor of each memory unit in the J column memory unit among the plurality of memory cells is connected to the plate line corresponding to the J column memory unit. That is, there is a one-to-one correspondence between J columns of storage cells and J plate lines.

Combined with the first aspect, in some implementations of the first aspect, J is greater than K. In this case, multiple columns of memory cells among the plurality of memory cells share one of the K plate lines.

In the embodiment of the present application, multiple columns of memory cells can share a board line, further reducing the number of board lines, further increasing the effective storage area and improving storage density.

In conjunction with the first aspect, in some implementations of the first aspect, the second end of the first transistor of each memory unit in the k-th column memory unit among the plurality of memory units is connected to each memory unit in the j-th column memory unit. The second terminal of the first transistor of the unit shares one of the plurality of plate lines, k is a positive integer, and j is not equal to k.

In conjunction with the first aspect, in some implementations of the first aspect, the j-th column memory unit and the k-th column memory unit are symmetrically distributed with one of the multiple shared board lines as an axis.

In this way, the area required for wiring between the memory unit and the board line in the memory unit can be reduced, and the effective storage area can be further increased.

In conjunction with the first aspect, in some implementations of the first aspect, multiple bit lines are respectively connected to multiple amplifiers.

In connection with the first aspect, in some implementations of the first aspect, the plurality of bit lines are connected to at least one amplifier through a multiplexer, and the number of the at least one amplifier is greater than or equal to at least one of the plurality of plate lines. The number of columns of connected storage cells.

In this way, multiple column bit lines correspond to one SA, which reduces the number of SAs and can increase the effective storage area, that is, increase the density of memory cells.

A second aspect provides a memory, including a storage array and a storage controller of the first aspect or any possible implementation of the first aspect, and the storage controller and the storage array are electrically connected.

A third aspect provides an electronic device, including the memory of the second aspect and a circuit board. The memory is disposed on the circuit board and is electrically connected to the circuit board.

In the fourth aspect, a working method of a storage array is provided. The storage array includes: multiple storage units, along the row direction A plurality of extended word lines, a plurality of bit lines extending along the column direction, and a plurality of plate lines extending along the column direction, each memory unit in the plurality of memory cells includes a first transistor and a first ferroelectric capacitor, the first The first end of the transistor is connected to the second end of the first ferroelectric capacitor, wherein the gate end of the first transistor of each memory cell in the i-th row of memory cells in the plurality of memory cells is connected to the first transistor in the plurality of word lines. i word lines are connected, i is a positive integer, and the first end of the first ferroelectric capacitor of each memory cell in the j-th column memory unit among the plurality of memory cells is connected to the j-th bit line among the plurality of bit lines. , j is a positive integer, the second end of the first transistor of each memory unit in the jth column memory unit is connected to one of the plurality of plate lines, the first end of the first transistor is the source end, and the first transistor The second end of the first transistor is the drain end, or the first end of the first transistor is the drain end, and the second end of the first transistor is the source end. The method includes: applying a first voltage signal to the i-th word line to cause the The first transistor of each memory cell in the i-row memory cell is turned on; a second voltage signal is applied to one of the plurality of plate lines, and a third voltage signal is applied to the bit line connected to the target memory cell to read Taking the information stored in the target storage unit, the potential of the second voltage signal is higher than the potential of the third voltage signal, and the target storage unit is the intersection of the storage unit connected to one of the plurality of plate lines and the i-th row of storage cells. Centralized storage unit.

In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second end of the first transistor of each memory unit in the j-th column memory unit is connected to the j-th plate line among the plurality of plate lines, and the method includes : Apply a second voltage signal on the j-th plate line to read the information stored in the target storage unit. The target storage unit is a storage unit at the intersection with the j-th column storage unit and the i-th row storage unit.

In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second end of the first transistor of each memory unit in the k-th column memory unit among the plurality of memory units is connected to each memory unit in the j-th column memory unit. The second terminal of the first transistor of the unit shares one of the multiple plate lines, k is a positive integer, and j is not equal to k. The method includes: applying a second voltage to one of the shared multiple plate lines. signal to read the information stored in the target storage unit. The target storage unit is the storage unit at the intersection with the j-th column storage unit, the k-th column storage unit and the i-th row storage unit.

Combined with the fourth aspect, in some implementations of the fourth aspect, the j-th column memory unit and the k-th column memory unit are symmetrically distributed with one of the multiple shared board lines as an axis.

Combined with the fourth aspect, in some implementations of the fourth aspect, multiple bit lines are respectively connected to multiple amplifiers.

In conjunction with the fourth aspect, in some implementations of the fourth aspect, the plurality of bit lines are connected to at least one amplifier through a multiplexer, and the number of the at least one amplifier is greater than or equal to at least one of the plurality of plate lines. The number of columns of connected storage cells.

The technical effects that can be achieved by any possible implementation method in any one of the above-mentioned second to fourth aspects can be described with reference to the technical effects that can be achieved by any possible implementation method in any one of the above-mentioned first aspects. Duplication will not be discussed.

Description of the drawings

Figure 1 is a schematic diagram of the storage principle of FeRAM;

Figure 2 is a schematic diagram of a memory cell in the FeRAM memory array;

Figure 3 is a schematic diagram of a write operation of FeRAM;

Figure 4 is a schematic diagram of a FeRAM read operation;

Figure 5 is a schematic structural diagram of a storage array;

Figure 6 is a schematic structural diagram of another storage array;

Figure 7 is a schematic structural diagram of yet another storage array;

Figure 8 is a schematic diagram of a write operation of a storage array;

Figure 9 is a schematic diagram of a read operation of a storage array;

Figure 10 is a schematic structural diagram of yet another storage array;

Figure 11 is a schematic structural diagram of yet another storage array;

Figure 12 is a schematic flow chart of a working method of a storage array.

Detailed ways

The technical solutions in this application will be described below with reference to the accompanying drawings.

Ferroelectric materials can undergo spontaneous polarization under an electric field, and the polarization direction can be adjusted with the action of an external electric field. The polarization state is retained after the electric field disappears. FeRAM utilizes this property of ferroelectric materials to store data.

Figure 1 shows a schematic diagram of the memory principle of FeRAM. The abscissa in Figure 1 is the voltage V or the electric field intensity E, the ordinate can be the polarization intensity P or the polarization charge Q, Pr is the residual polarization intensity, and Vc is the coercive field of the ferroelectric capacitor. As the electric field strength increases, the polarization intensity also increases until saturation. When the direction of the external electric field changes, the polarization direction will also change. Different polarization directions can be used to represent information "0" and information "1". For example, as shown in Figure 1, when the potential of the upper plate of the ferroelectric capacitor is lower than the potential of the lower plate, the polarization direction of the ferroelectric capacitor is downward. At this time, the stored information can be considered to be "1"; ferroelectric capacitor When the potential of the upper plate of the capacitor is higher than the potential of the lower plate, the polarization direction of the ferroelectric capacitor is upward. At this time, the stored information can be considered to be "0".

The circuit structure of FeRAM is the basis for ensuring that FeRAM achieves correct read and write functions. The memory cells in FeRAM memory arrays are usually one transistor one capacitor (1T1C) structure or two transistor two capacitor (2T2C) structure.

Figure 2 is a schematic diagram of a memory cell in a FeRAM memory array. As shown in Figure 2(a), the 1T1C structure includes a transistor and a ferroelectric capacitor. The gate terminal of the transistor is connected to the word line (WL), the drain terminal of the transistor is connected to the bit line (BL), one end of the ferroelectric capacitor is connected to the source terminal of the transistor, and the other end of the ferroelectric capacitor is connected to the plate line (plate line, PL). WL is used to control the gating and turning off of the transistor. Applying corresponding potentials to BL and PL can write information in the ferroelectric capacitor or read information from the ferroelectric capacitor.

As shown in (b) of Figure 2, the 2T2C structure includes two transistors and two ferroelectric capacitors. The 2T2C structure can be viewed as two adjacent 1T1C structures, sharing the same word lines and plate lines, but storing opposite data. For example, one ferroelectric capacitor stores information "1", and the other ferroelectric capacitor stores information "0". Specifically, the gate terminals of the two transistors are connected to the same word line WL. The drain terminal of one of the transistors is connected to the bit line BL, and the source terminal of the transistor is connected to one terminal of one of the ferroelectric capacitors. The drain terminal of the other transistor is connected to the bit line BL', and the source terminal of the transistor is connected to one terminal of another ferroelectric capacitor. Two ferroelectric capacitors are connected to the same plate line PL. In other words, the memory cells of the 2T2C structure are connected to WL, BL, BL’ and PL. WL is used to control the gating and turning off of transistors. By applying corresponding potentials to BL, BL’ and PL, information can be written in or read from the ferroelectric capacitor.

In order to facilitate understanding and description, the following description takes the memory unit having a 1T1C structure as an example, which does not limit the solution of the embodiment of the present application.

FeRAM includes multiple memory cells, multiple word lines, multiple bit lines, and multiple plate lines. Among them, the word lines and plate lines extend in the lateral direction, and the bit lines extend in the longitudinal direction. Memory cells in the same row share word lines, memory cells in the same row share plate lines, and memory cells in the same column share bit lines. In other words, the gate terminals of the transistors of all memory cells in the same row are connected to the same word line, and the ferroelectric capacitors of all memory cells in the same row are connected to the same plate. The drain ends of the transistors of all memory cells in the same column are connected to the same bit line. Memory cells sharing the same word line share the same plate line.

For example, the memory array shown in Figures 3 and 4 includes three rows and four columns of memory cells, three rows of word lines WL0, WL1, and WL2, four columns of bit lines BL0, BL1, BL2, and BL3, and three rows of plate lines PL0 and PL1. and PL2. The three rows of memory cells are respectively connected to three rows of word lines, the three rows of memory cells are respectively connected to three rows of plate lines, and the four columns of memory cells are respectively connected to four columns of bit lines.

When it is necessary to write information "1" to the unit to be written, the word line connected to the unit to be written is connected to a high potential, that is, the gate terminal of the transistor in the unit to be written is connected to a high potential, and the transistor in the unit to be written is connected to a high potential. The bit line connected to the unit to be written is connected to high potential, the plate line connected to the unit to be written is connected to low potential, the ferroelectric capacitor in the unit to be written is forward polarized, and the information "1" is written to the unit to be written. written into the unit.

Figure 3 shows a schematic diagram of a write operation. For example, as shown in (a) of FIG. 3 , the cells to be written include the first row of memory cells. When it is necessary to write information "1" to the first row of memory cells, WL0 is connected to the high potential VDD, and the transistors in the memory cells of this row are turned on. BL0, BL1, BL2 and BL3 are connected to high potential VDD, PL0 is connected to low potential VSS, for example, 0V, the ferroelectric capacitor in the first row of memory cells is forward polarized, and information "1" is written into the first row of memory cells. .

When it is necessary to write information "0" into the unit to be written, the word line connected to the unit to be written is connected to a high potential, that is, the gate terminal of the transistor in the unit to be written is connected to a high potential, and the transistor in the unit to be written is connected to a high potential. The bit line connected to the unit to be written is connected to a low potential, the plate line connected to the unit to be written is connected to a high potential, the ferroelectric capacitor in the unit to be written is reversely polarized, and the information "0" is written to the unit to be written. written into the unit. In addition, since the memory cells in the same row share a word line, when the word line connected to the unit to be written is connected to a high potential, the transistor in the memory unit in the same row as the unit to be written is turned on, and the memory unit in the row The ferroelectric capacitors withstand the potential of their respective bit lines and plate lines. Since the memory cells in the same row share a board line, when the board line connected to the unit to be written is connected to a high potential, the ferroelectric capacitors in the memory cells in the same row as the unit to be written need to withstand the high voltage on the board line. Potential. If the bit line connected to the memory cell in this row is low, information "0" is written into the memory cell in this row. In order to prevent the information of a memory cell that has stored information "1" from being rewritten as information "0", the bit lines connected to other memory cells in the same row as the cell to be written are connected to a high potential.

For example, as shown in (b) of FIG. 3 , the units to be written are the second storage unit and the third storage unit in the first row. When writing information "0" to the cell to be written, WL0 is connected to the high potential VDD, and the transistors in the memory cells of this row are turned on. BL1 and BL2 are connected to low potential VSS, for example, 0V, PL0 is connected to high potential VDD, the ferroelectric capacitors in the second and third memory cells in the first row are reversely polarized, and the information "0" is written into these two storage units. In addition, in order to prevent the information of the memory cells that have stored information "1" from being rewritten as information "0", BL0 and BL3 need to be connected to the high potential VDD.

When it is necessary to read information from the unit to be read, the bit line connected to the unit to be read is connected to 0V for pre-discharge, and then the word line connected to the unit to be read is connected to high potential. A high potential pulse is applied to the connected board wires. If the information stored in the unit to be read is "0", when the information is read, the polarization direction of the ferroelectric capacitor in the unit to be read will not change and the charge Q0 will be released. The released charge Q0 is distributed between the ferroelectric capacitor of the unit to be read and the bit line connected to the unit to be read, and the voltage of the bit line increases. The voltage of the bit line at this time is V0. If the information stored in the unit to be read is "1", when the information is read, the polarization direction of the ferroelectric capacitor in the unit to be read is changed by the external electric field, from forward polarization to reverse polarization. Release charge Q1. The released charge Q1 contains polarization flip charge, Q1>Q0. The voltage on the bit line increases. At this time, the voltage of the bit line is V1, V1>V0. The sense amplifier (SA) connected to the bit line detects the voltage of the bit line, compares the voltage of the bit line with the reference potential Vref, and based on the comparison As a result, it can be determined that the information stored in the unit to be read is information "0" or information "1". For example, if the voltage of the bit line connected to the unit to be read exceeds Vref, the information stored in the unit to be read is information "1"; if the voltage of the bit line connected to the unit to be read does not exceed Vref, the information stored in the unit to be read is "1". Take the information stored in the unit as information "0".

Since the reading process is a "destructive reading", that is, the reading operation may change the information originally stored in the unit to be read. For example, if the information stored in the unit to be read is information "1", when the information is read, the polarization direction of the ferroelectric capacitor in the unit to be read will be changed, and the information stored in the unit to be read will be rewritten. is information "0". After the read operation is completed, the information originally stored in the unit to be read, that is, the information stored in the unit to be read when the read operation starts, needs to be written back to the unit to be read according to the above process of the write operation.

Figure 4 shows a schematic diagram of a read operation. In (a) of Figure 4, each column BL is connected to one SA. During the reading process, the entire row of memory cells needs to be read simultaneously each time. For example, as shown in Figure 4, when you need to read the information stored in the first row of memory cells, connect BL0, BL1, BL2 and BL3 to 0V for pre-discharge, then connect WL0 to high potential, and apply a high potential pulse to PL0. The voltages of BL0, BL1, BL2 and BL3 are read out through the four SAs and compared with the reference voltage to obtain the information stored in the first row of memory cells.

In (b) of Figure 4, multiple columns of BL are connected to one SA, that is, four columns of BL are connected to one SA through a data selector (multiplexer, MUX). During the reading process, the information of one storage unit can be read in the 4 columns. For example, the unit to be read is the first memory cell in the first row. When it is necessary to read the information stored in the unit to be read, connect BL0 to 0V for pre-discharge, then connect WL0 to high potential, and apply a high potential pulse to PL0. , read the voltage on BL0 through SA and compare it with the reference voltage to obtain the information stored in the first memory cell of the first row.

Limited by the endurance cycle of the ferroelectric capacitor, the whole row reading method shown in Figure 4 will affect the service life of FeRAM. Durability refers to the ability of ferroelectric materials to maintain polarization strength after experiencing multiple voltage cycles. Durability is a key parameter in assessing the reliability of ferroelectric materials. The endurance of FeRAM is about 10 ^12-14 voltage cycles. The durability of FeRAM refers to the durability of the ferroelectric capacitors in FeRAM. That is, the ferroelectric capacitor in FeRAM cannot maintain the polarization intensity after experiencing 10 ^12-14 voltage cycles, resulting in the inability to store information.

Specifically, in the structure shown in (a) of Figure 4, each column BL is connected to a SA structure. Even if the information in the entire row of storage cells does not need to be read, all the storage units in the row will still be read. unit information. The ferroelectric capacitors of the memory cells in the row that do not need to be read will also experience high voltages during the reading process and high voltages during the write-back process. As a result, the number of times the ferroelectric capacitors actually experience high voltages is much higher than the number of times the ferroelectric capacitors need to be read. The number of times it is taken affects the reliability of ferroelectric capacitors. In the structure shown in Figure 4(b), multiple columns of BL are connected to one SA. The ferroelectric capacitance of the unread memory cells in this row will still experience high voltage during the read process and high voltage during the write-back process. High voltage causes the number of times the ferroelectric capacitor actually experiences high voltage to be much higher than the number of times the ferroelectric capacitor is read, which also affects the reliability of the ferroelectric capacitor.

In other words, the method of reading the entire row will cause the ferroelectric capacitors in the entire row of memory cells to experience high voltage during the reading process and high voltage during the write-back process, affecting the service life of FeRAM.

Assuming that the read and write cycle of FeRAM is 50ns, for a 256×1024-scale storage array, if the entire row reading method is to meet the 10-year life requirement of the memory, the durability needs to be greater than 10 ¹⁶ voltage cycles. In fact, the durability cycle of ferroelectric capacitors is about 10 ^12-14 voltage cycles, which cannot meet this life requirement.

Embodiments of the present application provide a storage array that can avoid reading the entire row, which is beneficial to ensuring the service life of the storage array.

The memory array includes a plurality of memory cells, a plurality of word lines extending in the row direction, a plurality of bit lines extending in the column direction, and a plurality of plate lines extending in the column direction. The plurality of memory cells are arranged along rows and columns. Each of the plurality of storage units stores The unit includes a first transistor and a first ferroelectric capacitor. The first terminal of the first transistor is connected to the second terminal of the first ferroelectric capacitor.

The gate terminal of the first transistor of each memory cell in the first part of the memory cells is connected to one of the plurality of word lines. The first part of the memory cells includes a plurality of memory cells in the same row in the memory array.

The first end of the first ferroelectric capacitor of each memory cell in the second part of the memory cells is connected to one of the plurality of bit lines. The second part of the memory cells includes a plurality of memory cells in the same column in the memory array.

The second terminal of the first transistor of each memory cell in the second portion of memory cells is connected to one of the plurality of plate lines.

It should be noted that in the embodiment of the present application, the row direction and the column direction are relative concepts and are only used to define two mutually perpendicular directions. Row direction may also be called landscape orientation. Column direction may also be called portrait orientation. That is to say, the plurality of signal lines extending in the row direction are parallel to each other, and the plurality of signal lines extending in the column direction are parallel to each other. The signal lines extending in the row direction and the signal lines extending in the column direction are perpendicular to each other. The plurality of memory cells in the memory array are distributed in rows and columns, that is, the plurality of memory cells are distributed in a direction parallel to the extension direction of the signal line and perpendicular to the extension direction of the signal line.

Different signal lines in the embodiments of this application refer to mutually independent signal lines.

Each memory cell in the memory array includes a first transistor and a first ferroelectric capacitor. A memory cell is connected to at least three signal lines, namely word lines, bit lines and plate lines. Specifically, in a memory cell, the gate terminal of the first transistor is connected to the word line, the first terminal of the first ferroelectric capacitor is connected to the bit line, and the second terminal of the first ferroelectric capacitor is connected to the first terminal of the first transistor. terminals are connected, and the second terminal of the first transistor is connected to the board line.

Word lines are used to control the on and off of transistors. The plate lines and bit lines work together on the ferroelectric capacitor to complete read and write operations. Bit lines are used to transmit electrical signals. For detailed description, please refer to the previous article and will not be repeated here.

It should be understood that the “first end” and “second end” of the first ferroelectric capacitor are only used to distinguish the two ends of the first ferroelectric capacitor and have no other limiting effect. The “first terminal” and “second terminal” of the first transistor are only used to distinguish the source terminal and the drain terminal of the first transistor and have no other limiting role. For example, the first terminal of the first transistor is the source terminal, and the second terminal of the first transistor is the drain terminal. In this case, the second terminal of the first ferroelectric capacitor is connected to the source terminal of the first transistor, and the drain terminal of the first transistor is connected to the plate line. For another example, the first terminal of the first transistor is the drain terminal, and the second terminal of the first transistor is the source terminal. In this case, the second terminal of the first ferroelectric capacitor is connected to the drain terminal of the first transistor, and the source terminal of the first transistor is connected to the plate line.

Each of the plurality of word lines is connected to a memory cell, each of the plurality of bit lines is connected to a memory cell, and each of the plurality of plate lines is connected to a memory cell. connect. In one implementation, each word line is connected to different memory cells, each bit line is connected to different memory cells, and each plate line is connected to different memory cells.

In order to facilitate understanding and description, in the embodiment of the present application, the second end of the first ferroelectric capacitor is connected to the drain end of the first transistor, and the source end of the first transistor is connected to the plate line as an example to illustrate the solution of the embodiment of the present application. , does not limit the solutions of the embodiments of this application.

The gate terminal of the first transistor of each memory cell in the first part of the memory cells is connected to one of the plurality of word lines, which refers to the gate terminal of the first transistor of each memory cell in the first part of the memory cells. The connected word lines are the same.

The first end of the first ferroelectric capacitor of each memory cell in the second part of the memory cells is connected to one of the plurality of bit lines, which means that the first end of the first ferroelectric capacitor of each memory cell in the second part of the memory cells is connected to one of the plurality of bit lines. The first terminal of a ferroelectric capacitor is connected to the same bit line.

The second end of the first transistor of each memory cell in the second part of the memory cells is connected to one of the plurality of plate lines, which means that the first transistor of each memory cell in the second part of the memory cells The second end of the board is connected to The lines are the same.

The first portion of memory cells may include all or part of the memory cells in the same row. The second portion of memory cells may include all or part of the memory cells in the same column.

For example, the first part of the storage units may include the i-th row of storage units, and the second part of the storage units may include the j-th column of storage units.

In this case, the gate end of the first transistor of each memory cell in the i-th row of memory cells in the memory array is connected to the i-th word line among the plurality of word lines, where i is a positive integer; The first end of the first ferroelectric capacitor of each memory cell in the j-th column memory unit is connected to the j-th bit line among the plurality of bit lines, j is a positive integer; the first ferroelectric capacitor of each memory unit in the j-th column memory unit is connected to The second end of a transistor is connected to one of the plurality of plate lines, the first end of the first transistor is the source end, the second end of the first transistor is the drain end, or the first end of the first transistor is The drain terminal and the second terminal of the first transistor are the source terminal.

The i-th row of storage cells can be any row of storage cells in the storage array. The jth column storage unit can be any column storage unit in the storage array. The i-th word line can be any word line among the plurality of word lines, and the j-th bit line can be any bit line among the plurality of bit lines.

The first transistor of each memory cell in the i-th row of memory cells is connected to the i-th word line, which can also be understood as the word line to which the gate terminals of the first transistors of all memory cells in the same row in the memory array are connected. They may be the same, and the word lines connected to the gate terminals of the first transistors in memory cells in different rows are different. The first end of the first ferroelectric capacitor of each memory cell in the j-th column is connected to the j-th bit line among the plurality of bit lines, which can also be understood as the first ferroelectric capacitor of all memory cells in the same column. The bit lines connected to the electric capacitors may be the same, and the bit lines connected to the first ferroelectric capacitors of memory cells in different columns are different. The second end of the first transistor of each memory cell in the j-th column is connected to one of the plurality of plate lines, which can be understood as the plate line to which the first transistors of all memory cells in the same column are connected. can be the same. It should be noted that when the i in the i-th word line takes different values, it represents different word lines. That is, the i in the i-th word line with different values is only used to define different word lines and does not determine the arrangement of the word lines. The order does not constitute a limitation. When j in the j-th bit line takes different values, it represents different bit lines. That is, different values of j in the j-th word line are only used to define different bit lines, but do not limit the arrangement order of the bit lines.

In a possible implementation, the first transistors in each memory unit in the first part of the memory units are connected to different board lines.

In other words, the first transistors in the memory cells sharing the same word line are respectively connected to different plate lines.

Multiple storage units in the storage array are arranged in rows I and columns J. The plurality of storage units are I*J storage units. The storage array may include K strip lines. I is an integer greater than 1, J is an integer greater than 1, and K is an integer greater than 1.

Optionally, the second end of the first transistor of each memory cell in the j-th column memory cell is connected to the j-th plate line among the K plate lines.

For example, J is equal to K. In this case, the first transistor of each memory unit in the J column memory unit in the memory array is connected to the plate line corresponding to the J column memory unit. That is, there is a one-to-one correspondence between J columns of storage cells and J plate lines.

As an example, a memory unit includes a transistor and a ferroelectric capacitor (ie, a first transistor and a first ferroelectric capacitor). A memory cell is connected to a word line, a bit line and a plate line respectively. Each row of memory cells is connected to the word line corresponding to the row of memory cells, each column of memory cells is connected to the corresponding bit line of the column of memory cells, and each column of memory cells is connected to the corresponding plate line of the column of memory cells. Memory cells in different rows correspond to different word lines. storage units in different columns The corresponding bit lines are different. Memory cells in different columns correspond to different board lines.

That is to say, memory cells in different rows are connected to different word lines, memory cells in different columns are connected to different plate lines, and memory cells in different columns are connected to different bit lines. In this case, each column plate line corresponds to each column bit line on a one-to-one basis.

FIG. 5 shows a schematic structural diagram of a storage array 500 provided by an embodiment of the present application. As shown in FIG. 5 , the memory array 500 includes 16 4×4 memory cells, 4 word lines, 4 bit lines, and 4 plate lines. The four word lines are WL0, WL1, WL2 and WL3 respectively. The four bit lines are BL0, BL1, BL2 and BL3 respectively. The four plate lines are PL0, PL1, PL2 and PL3 respectively. The word line is a horizontal trace, the bit line is a vertical trace, and the board line is a vertical trace. In the memory array shown in FIG. 5, a memory cell includes a transistor (ie, a first transistor) and a ferroelectric capacitor (ie, a first ferroelectric capacitor).

In the memory array shown in FIG. 5 , the word lines connected to the gate terminals of the transistors in the same row of memory cells are the same word line, that is, the memory cells in the same row are connected to the same word line. The source ends of the transistors in the same column of memory cells are connected to the same plate line, that is, the memory cells of the same column are connected to the same plate line. The ferroelectric capacitors in the same column of memory cells are connected to the same bit line, that is, the memory cells of the same column are connected to the same bit line. Memory cells in different columns are connected to different plate lines, memory cells in different columns are connected to different bit lines, and memory cells in different rows are connected to different word lines.

It should be understood that the memory array shown in Figure 5 is only a schematic diagram of a memory array provided by the embodiment of the present application. The number of devices shown in the figure does not limit the solution of the embodiment of the present application. For example, the memory array in Figure 5 The array includes 16 4×4 memory cells. In practical applications, the memory array can include memory cells of other sizes. The number of word lines, bit lines and plate lines can be adjusted according to the size of the memory cells. The embodiments of this application This is not limited.

In another possible implementation, the first transistors of some of the first memory cells are connected to the same board lines.

That is to say, some of the memory cells among the multiple memory cells sharing the same word line share the same plate line. In other words, among multiple memory cells sharing the same word line, at least some of the memory cells are connected to different board lines. This structure may also be called a structure in which the PL is shared by segments.

Optionally, J is greater than K. In this case, multiple columns of memory cells in the memory array share one of the K plate lines.

In other words, the first transistors in the multiple columns of memory cells are connected to the same board lines.

As an example, a memory unit includes a transistor and a ferroelectric capacitor (ie, a first transistor and a first ferroelectric capacitor). Each row of memory cells is connected to the word line corresponding to the row of memory cells, each column of memory cells is connected to the corresponding bit line of the column of memory cells, and each column of memory cells is connected to the corresponding plate line of the column of memory cells. Memory cells in different rows correspond to different word lines. Memory cells in different columns correspond to different bit lines. The board lines corresponding to the memory cells in different columns may be the same.

That is to say, the memory cells in different rows are connected to different word lines, the memory cells in different columns are connected to different bit lines, and the memory cells in different columns are connected to the same plate lines. In this case, it can be understood that multiple columns of bit lines correspond to one column of plate lines.

In this way, the number of board lines can be reduced and the effective storage area can be increased.

Optionally, the second end of the first transistor of each memory cell in the kth column of memory cells in the memory array shares a plurality of plate lines with the second end of the first transistor of each memory cell in the jth column of memory cells. For a plate line in , k is a positive integer, and j is not equal to k.

That is to say, the first transistor in the k-th column memory cell and the first transistor in the j-th column memory cell are connected to the same plate line.

For example, J is equal to 2 ^t K, t is a positive integer, and the first transistors of every 2 ^t columns of memory cells share one plate line. For example, t is 1, that is, the first transistors of every two columns of memory cells share one plate line. The bit lines connected to the first ferroelectric capacitors of every two columns of memory cells may be two bit lines. In this case, one board line corresponds to two bit lines. For another example, t is 2, that is, the first transistors of every four columns of memory cells share one plate line. The bit lines connected to the first ferroelectric capacitors of every four columns of memory cells may be four bit lines. In this case, one board line corresponds to 4 bit lines. It should be understood that the above are only examples and do not limit the solutions of the embodiments of the present application.

Optionally, the gate end of the first transistor of some of the first partial memory cells is connected to one of the plurality of plate lines, and the partial memory cells are symmetrically distributed with the plate line as the axis.

Exemplarily, a first transistor in a plurality of columns of memory cells in a memory array is connected to a plate line. The multi-column memory cells may be symmetrically distributed with the plate line as an axis. That is, multiple columns of memory cells sharing a board line can be symmetrically distributed with the board line as the axis.

For example, J is equal to 2 ^t K, t is a positive integer, and every 2 ^t columns of memory cells are symmetrically distributed with a shared plate line as the axis.

Taking t equal to 1 as an example, each two columns of memory cells are symmetrically distributed with a shared board line as the axis.

For example, the memory cells in the jth column and the memory cells in the kth column are symmetrically distributed with the shared board line as the axis.

As shown in FIG. 6 , the memory array 600 includes 16 4×4 memory cells, 4 word lines, 4 bit lines, and 2 plate lines. The four word lines are WL0, WL1, WL2 and WL3 respectively. The four bit lines are BL0, BL1, BL2 and BL3 respectively. The two plate lines are PL0 and PL1 respectively. The word line is a horizontal trace, the bit line is a vertical trace, and the board line is a vertical trace. The memory cells in the same row are connected to the same word line, the memory cells in the same column are connected to the same bit line, and every two columns of memory cells are connected to the same plate line. The memory cells in every two columns are connected to the same plate lines, the memory cells in different columns are connected to different bit lines, and the memory cells in different rows are connected to different word lines. Specifically, in Figure 6, the memory cells in the first to fourth rows are connected to WL0, WL1, WL2, and WL3 respectively, and the memory cells in the first to fourth columns are connected to BL0, BL1, BL2, and BL3 respectively. The memory cells in the column and the second column are connected to the plate line PL0, and the memory cells in the third column and the memory cells in the fourth column are connected to the plate line PL1. That is, BL0 and BL1 correspond to PL0, and BL2 and BL3 correspond to PL1. The memory cells in the first column and the memory cells in the second column are symmetrically distributed with PL0 as the axis, and the memory cells in the third column and the memory cells in the fourth column are symmetrically distributed with PL1 as the axis.

The main difference between Figure 5 and Figure 6 is that in Figure 6, every two columns of memory cells share a board line, while in Figure 5, each column of memory cells is connected to a different board line. For other descriptions of Figure 6, please refer to the relevant description of Figure 5. To avoid duplication, they will not be described again here.

It should be understood that the memory array shown in Figure 6 is only a schematic diagram of a memory array provided by the embodiment of the present application. The number of devices shown in the figure does not limit the solution of the embodiment of the present application. For example, the memory array in Figure 6 The array includes 16 4×4 memory cells. In practical applications, the memory array can include memory cells of other sizes. The number of word lines, bit lines and plate lines can be adjusted according to the size of the memory cells. The embodiments of this application This is not limited.

As shown in FIG. 7 , the memory array 700 includes 4×4N 16N memory cells, 4 word lines, 4N bit lines, and 2 plate lines. N is an integer greater than 1. The 4 word lines are WL0, WL1, WL2 and WL3 respectively. The 4N bit lines are BL0 to BL4N-1 respectively. The 2 plate lines are PL0 and PL1 respectively. The word lines are routed horizontally, and the bit lines are routed vertically. The board lines are routed vertically. N is a positive integer.

In the memory array 700 shown in Figure 7, memory cells in the same row are connected to the same word line, memory cells in the same column are connected to the same bit line, and every 2N bit lines correspond to one plate line, or in other words, every 2N columns Storage units share 1 board line. The 2N columns of memory cells sharing board lines are symmetrically distributed. Specifically, the memory cells in the 1st to 2N columns share the plate line PL0, and the memory cells in the 2N column are axially symmetrically distributed with the plate line PL0 as the axis. The memory cells in the 2N+1th column to the 4Nth column share the plate line PL1, and the memory cells in the 2N column are axially symmetrically distributed with the plate line PL1 as the axis.

It should be understood that the memory array shown in Figure 7 is only a schematic diagram of a memory array provided by the embodiment of the present application. The number of devices shown in the figure does not limit the solution of the embodiment of the present application. For example, the memory array in Figure 7 The array includes 16N memory cells of 4×4N. In practical applications, the memory array can include memory cells of other sizes. The number of word lines, bit lines and plate lines can be adjusted according to the size of the memory cells. The embodiments of this application This is not limited.

The writing process of the memory unit in the embodiment of the present application is similar to the writing process of the conventional memory unit. For example, in the case where the memory unit in the memory array of the embodiment of the present application includes a transistor and a ferroelectric capacitor, the information writing process is similar to the information writing process of the memory unit with a 1T1C structure. For ease of understanding and description, the information writing process is illustrated below by taking the memory unit including a transistor and a ferroelectric capacitor as an example.

When it is necessary to write information "1" to the first unit to be written, the word line connected to the first unit to be written is connected to a high potential, that is, the gate terminal of the transistor in the first unit to be written is connected to a high potential. A transistor in the cell to be written is turned on. The bit line connected to the first unit to be written is connected to a high potential, the plate line connected to the first unit to be written is connected to a low potential, the ferroelectric capacitor in the first unit to be written is forward polarized, and the information is "1" is written into the first unit to be written. The bit lines connected to other memory cells sharing the word line with the first unit to be written can be connected to a low potential, and the plate lines connected to other memory cells can be connected to a low potential.

In the embodiment of the present application, the high potential connected to the word line can be understood as the potential that causes the transistor to turn on. The low potential connected to the word line can be understood as the potential that turns off the transistor. In one possible implementation, the high potential and low potential connected to the bit line and the plate line are relative concepts. For example, if the potential on the bit line is higher than the potential on the plate line, it can be considered that the bit line is connected to a high potential. The board wire is connected to low potential. In another possible implementation, the high potential and low potential connected to each signal line can be set values. For example, the high potential connected to the bit line and the plate line can be the power supply voltage VDD, and the low potential connected to the bit line or the plate line can be 0V.

It should be noted that the first unit to be written in the embodiment of the present application may include one storage unit or may include multiple storage units, which is not limited in the embodiment of the present application. The "first" in "the first unit to be written" is only used to limit that the unit to be written currently needs to be written with information "1", and has no other limiting effect. In other words, the storage unit that currently needs to be written with information “1” can be called the “first unit to be written”.

When it is necessary to write information "0" to the second unit to be written, the word line connected to the second unit to be written is connected to a high potential, that is, the gate terminal of the transistor in the second unit to be written is connected to a high potential. The transistor in the second unit to be written is turned on. The bit line connected to the second unit to be written is connected to a low potential, the plate line connected to the second unit to be written is connected to a high potential, the ferroelectric capacitor in the second unit to be written is reverse polarized, and the information is "0" is written into the second unit to be written. In addition, when the word line connected to the second cell to be written is connected to a high potential, the transistors in other memory cells sharing the same word line with the second cell to be written are turned on, and the ferroelectric capacitances of other memory cells bear the The potentials on the corresponding bit lines and plate lines. If the second cell to be written shares the same plate line with some of the other memory cells sharing the same word line, the bit lines connected to the memory cells sharing the same plate line are connected to a high potential. This can prevent the information of the storage unit that has stored information "1" from being overwritten with information "0". For memory cells that share the same word line and do not share the same plate line as the second cell to be written, the connected bit line can be connected to a low potential, and the connected plate line can be connected to a low potential.

It should be noted that the second unit to be written in the embodiment of the present application may include one storage unit or may include multiple storage units, which is not limited in the embodiment of the present application. The "second" in the "second unit to be written" is only used to limit that the unit to be written currently needs to be written with information "0", and has no other limiting effect. In other words, the memory unit that currently needs to be written with information "0" can be called the "second unit to be written." The second unit to be written and the first unit to be written may be the same or different.

In the embodiment of the present application, writing information into a storage unit means writing information into the ferroelectric capacitor of the storage unit. The information stored in the memory unit is the information stored in the ferroelectric capacitor of the memory unit.

Figure 8 shows a schematic diagram of a write operation. The writing operation of the storage array in the embodiment of the present application will be described below with reference to FIG. 8 .

For example, as shown in (a) of FIG. 8 , information "1" needs to be written to the first memory unit and the second memory unit of the second row. The first storage unit and the second storage unit in the second row are the first units to be written. Connect the word line WL1 connected to the memory cells in the second row to VDD, and the transistors in the memory cells in the second row are turned on. The bit line BL0 connected to the first memory cell in the second row is connected to VDD, and the bit line BL1 connected to the second memory cell in the second row is connected to VDD. The first memory unit and the second memory unit in the second row share the same board line PL0, and PL0 is connected to 0V. The ferroelectric capacitors in these two memory cells are forward polarized. Information "1" is written into the first memory cell and the second memory cell in the second row. For the memory cells in the second row except the first memory cell and the second memory cell, the connected bit lines, namely BL2 and BL3, are connected to 0V, and the connected plate line, namely PL1, is connected to 0V. For another example, as shown in (b) of FIG. 8 , information "0" is written to the second memory cell in the second row. Connect the word line WL1 connected to the memory cells in the second row to VDD, and the transistors in the memory cells in the second row are turned on. The bit line BL1 connected to the second memory cell in the second row is connected to 0V. The plate line PL0 connected to the second memory cell in the second row is connected to VDD. The ferroelectric capacitor in this memory cell is reversely polarized, and information "0" is written into the second memory cell in the second row. The first memory cell in the second row and the second memory cell in the second row share plate line PL0. In order to prevent the information "1" stored in the first memory cell of the second row from being overwritten, the bit line BL0 connected to the first memory cell of the second row is connected to VDD. For the memory cells in the second row except the first memory cell and the second memory cell, the connected bit lines, namely BL2 and BL3, are connected to 0V, and the connected plate line, namely PL1, is connected to 0V.

It should be understood that the write operation in FIG. 8 is only explained by taking the storage array shown in FIG. 6 as an example, and does not limit the solution of the embodiment of the present application.

The storage array also includes at least one sense amplifier. The at least one sense amplifier is used to determine the information stored in the unit to be read during the process of reading information.

Specifically, SA is used to read the electrical signal on the bit line connected to the unit to be read, and determine the information stored in the unit to be read based on the electrical signal.

For example, the electrical signal may be a voltage signal.

The unit to be read may include one storage unit or multiple storage units, which is not limited in this embodiment of the present application.

Optionally, a plurality of sense amplifiers correspond to the plurality of bit lines one-to-one, and the plurality of sense amplifiers are respectively connected to the corresponding bit lines. In this case, the number of sense amplifiers is the same as the number of bit lines.

In actual circuit design, the width of SA is larger than the width of the memory cell. The way each BL corresponds to an SA will affect the effective storage area in the storage array. In this embodiment of the present application, multiple BLs may correspond to one SA.

Optionally, the storage array further includes at least one sense amplifier, and the plurality of bit lines are connected to the at least one sense amplifier through a multiplexer.

Specifically, the at least one sense amplifier is respectively connected to the output terminal of at least one multiplexer, and the plurality of bit lines are respectively connected to the input terminal of the at least one multiplexer. The number of at least one sense amplifier is greater than or equal to the number of columns of memory cells connected to at least one board line. During the reading process, the at least one multiplexer controls the connection relationship between the at least one sense amplifier and the plurality of bit lines.

A multiplexer (MUX) can be called a data selector.

For example, the number of SAs may be equal to the number of columns in which the units to be read are located during the reading process. The cells to be read may include the intersection of memory cells connected to plate lines to which high potential pulses are applied and memory cells connected to word lines to which high potential is applied.

The reading process of the memory unit in the embodiment of the present application is similar to the reading process of the conventional memory unit. For example, in the case where the memory unit in the memory array of the embodiment of the present application includes a transistor and a ferroelectric capacitor, the information reading process is similar to the information reading process of the memory unit with a 1T1C structure. In order to facilitate understanding and description, the following takes the memory unit including a transistor and a ferroelectric capacitor as an example to illustrate the information reading process.

When it is necessary to read information from the unit to be read, the bit line connected to the unit to be read is connected to 0V for pre-discharge, and then the word line connected to the unit to be read is connected to high potential, that is, the bit line connected to the unit to be read is connected to high potential. The gate terminal of the transistor is connected to a high potential, and the transistor in the unit to be read is turned on. A high potential pulse is applied to the board line to which the unit to be read is connected. The sense amplifier can determine the information stored in the unit to be read based on the voltage on the bit line to which the unit to be read is connected.

An exemplary description is given below, taking the unit to be read as including a storage unit as an example. If the information stored in the unit to be read is "0", when the information is read, the polarization direction of the ferroelectric capacitor in the unit to be read will not change and the charge Q0 will be released. The released charge Q0 is distributed between the ferroelectric capacitor of the unit to be read and the bit line connected to the unit to be read, and the voltage of the bit line increases. At this time, the voltage of the bit line connected to the unit to be read is V0. If the information stored in the unit to be read is "1", when the information is read, the polarization direction of the ferroelectric capacitor in the unit to be read is changed by the external electric field, from forward polarization to reverse polarization. Charge Q1 is released and the voltage on the bit line increases. At this time, the voltage of the bit line connected to the unit to be read is V1. The released charge Q1 contains polarization flip charge, Q1>Q0, correspondingly, V1>V0. The SA connected to the bit line detects the voltage of the bit line, and compares the voltage of the bit line with the reference potential Vref. Based on the comparison result, it can be determined whether the information stored in the unit to be read is information "0" or information "1". For example, if the voltage of the bit line connected to the unit to be read exceeds Vref, the information stored in the unit to be read is information "1"; if the voltage of the bit line connected to the unit to be read does not exceed Vref, the information stored in the unit to be read is "1". Take the information stored in the unit as information "0".

The bit lines connected to other memory cells other than the unit to be read can be connected to a low potential, and the plate lines connected to other memory cells other than the unit to be read can be connected to a low potential. After the reading is completed, the original information is written back to the unit to be read. For other memory cells that share the board line with the unit to be read, since the transistors are not turned on, the ferroelectric capacitor does not need to withstand the high voltage on the board line. Using the solution of the embodiment of the present application, only the ferroelectric capacitor in the unit to be read needs to withstand the high voltage during the reading and writing back processes, and the ferroelectric capacitors in other memory units do not need to experience unnecessary high voltage.

The reading operation of the memory array in the embodiment of the present application will be described below with reference to FIG. 9 .

For example, as shown in (a) of FIG. 9 , four bit lines can be connected to four SAs respectively, but (a) of FIG. 9 does not show all SAs. When it is necessary to store information from the first storage unit and the second storage unit in the second row, the first storage unit and the second storage unit in the second row are the units to be read. The bit line BL0 connected to the first memory cell in the second row is precharged to 0V, and the bit line BL1 connected to the second memory cell in the second row is precharged to 0V. Save the second line The word line WL1 connected to the memory cell is connected to VDD, and the transistor in the second row of memory cells is turned on. The first memory unit and the second memory unit in the second row share the same plate line PL0, and PL0 is connected to a high potential pulse. SA connected to BL0 compares the detected voltage V1 on BL0 with the reference voltage, and determines that the information stored in the first memory cell of the second row is information "1". SA connected to BL1 compares the detected voltage V0 on BL1 with the reference voltage and determines that the information stored in the second memory cell of the second row is information "0". During the read process, the first and second memory cells in the second row are read, and only the ferroelectric capacitors in the first and second memory cells in the second row need to withstand the read High voltage on the plate line during the process. The ferroelectric capacitors in other memory cells do not need to experience unnecessary high voltages.

For another example, as shown in (b) of Figure 9, four bit lines are connected to two SAs through a multiplexer. When it is necessary to read the information stored in the first storage unit and the second storage unit of the second row, connect BL0 to one of the SAs through a multiplexer, and connect BL1 to the other SA. The specific reading process is the same as (a) in Figure 9 and will not be described again here.

It should be understood that the above description only takes a memory unit including a transistor and a ferroelectric capacitor as an example, and does not limit the solution of the embodiment of the present application. For example, a memory cell may also include two transistors and two ferroelectric capacitors. As another example, a memory cell may include two transistors and a ferroelectric capacitor.

The following is an example of a memory cell including two transistors and two ferroelectric capacitors.

A memory cell includes a first transistor, a second transistor, a first ferroelectric capacitor and a second ferroelectric capacitor.

The gate terminal of the second transistor of each memory cell in the first part of the memory cells is connected to one of the plurality of word lines. The first part of the memory cells includes a plurality of memory cells in the same row in the memory array.

The first end of the second ferroelectric capacitor of each memory cell in the second part of the memory cells is connected to one of the plurality of bit lines. The second part of the memory cells includes a plurality of memory cells in the same column in the memory array. .

The second end of the second ferroelectric capacitor of each memory cell in the second part of the memory cells is connected to one of the plurality of plate lines through the second transistor.

One memory cell is connected to at least four signal lines, namely at least one word line, at least one plate line and two bit lines. The gate terminal of the first transistor and the gate terminal of the second transistor may be connected to the same word line, or may be connected to different word lines. A first terminal of the first ferroelectric capacitor is connected to a bit line, and a first terminal of the second ferroelectric capacitor is connected to another bit line. The second end of the first ferroelectric capacitor is connected to a plate line through the first transistor, and the second end of the second ferroelectric capacitor is connected to the same plate line through the second transistor, or may be connected to different plate lines.

For example, the word lines connected to the gate terminals of the first transistors of all memory cells in the same row in the memory array may be the same. The word lines connected to the gate terminals of the second transistors of all memory cells in the same row may be the same. The bit lines connected to the first ends of the first ferroelectric capacitors of all memory cells in the same column may be the same. The bit lines connected to the first ends of the second ferroelectric capacitors of all memory cells in the same column may be the same. The plate lines to which the first ferroelectric capacitors of all memory cells in the same column are connected through the first transistors may be the same. The plate lines connected by the first transistors to the second ferroelectric capacitors of all memory cells in the same column may be the same.

In a possible implementation, the first transistors in each memory unit in the first part of the memory units are connected to different board lines. The second transistors in each memory cell in the first part of the memory cells are connected to different board lines.

That is to say, the first transistors sharing the same word line are respectively connected to different plate lines. The second transistors sharing the same word line are respectively connected to different plate lines.

For example, the word lines connected to each row of memory cells in the memory array are different. The bit lines connected to each column of memory cells different. The memory cells in each column are connected to different board lines.

Specifically, the second end of the first ferroelectric capacitor in each column memory unit in the memory array is connected to the plate line corresponding to the first ferroelectric capacitor in each column memory unit through the first transistor in each column memory unit. The plate lines corresponding to the first ferroelectric capacitors in each column of memory cells are different. The second end of the second ferroelectric capacitor in each column memory unit in the memory array is connected to the plate line corresponding to the second ferroelectric capacitor in each column memory unit through the second transistor in each column memory unit. The plate lines corresponding to the second ferroelectric capacitors in each column of memory cells are different.

In other words, the first transistors in each column of memory cells in the memory array are connected to different board lines. The second transistors in each column of memory cells in the memory array are connected to different board lines.

Figure 10 shows a schematic structural diagram of a storage array 1000 provided by an embodiment of the present application. As shown in FIG. 10 , the memory array 1000 includes 16 4×4 memory cells, 4 word lines, 8 bit lines, and 4 plate lines. The four word lines are WL0, WL1, WL2 and WL3 respectively. The eight bit lines are BL0, BL0’, BL1, BL1’, BL2, BL2’, BL3 and BL3’ respectively. The four plate lines are PL0, PL1, PL2 and PL3. The word line is a horizontal trace, the bit line is a vertical trace, and the board line is a vertical trace. In the memory array shown in FIG. 10, one memory cell includes two transistors (ie, a first transistor and a second transistor) and two ferroelectric capacitors (ie, a first ferroelectric capacitor and a second ferroelectric capacitor).

In the memory array shown in FIG. 10 , the word lines connected to the gate terminals of the transistors in the same row of memory cells are the same word line, that is, the memory cells in the same row are connected to the same word line. The source ends of the transistors in the same column of memory cells are connected to the same plate line, that is, the memory cells of the same column are connected to the same plate line. The bit line connected to the first ferroelectric capacitor in the same column of memory cells is the same bit line, and the bit line connected to the second ferroelectric capacitor in the same column of memory cells is the same bit line. Memory cells in different columns are connected to different plate lines, memory cells in different columns are connected to different bit lines, and memory cells in different rows are connected to different word lines.

It should be understood that the memory array shown in Figure 10 is only a schematic diagram of a memory array provided by an embodiment of the present application. The number of devices shown in the figure does not limit the solution of the embodiment of the present application. For example, the memory array in Figure 10 The array includes 4×4 memory cells. In practical applications, the memory array can include memory cells of other sizes. The number of word lines, bit lines and plate lines can be adjusted according to the size of the memory cells. This is not the case in the embodiments of the present application. Make limitations.

In another possible implementation, the first transistors of some of the first memory cells are connected to the same board lines. The second transistors of some of the first memory cells are connected to the same board lines.

That is to say, some of the first transistors sharing the same word line are connected to the same plate line. Some of the second transistors sharing the same word line are connected to the same plate line.

For example, the word lines connected to each row of memory cells in the memory array are different. The bit lines connected to each column of memory cells are different. The board lines connected to memory cells in different columns can be the same.

Specifically, the second ends of the first ferroelectric capacitors in the multiple columns of memory cells in the memory array are respectively connected to a plate line through the first transistors in the multiple columns of memory cells. The second ends of the second ferroelectric capacitors in the multiple columns of memory cells in the memory array are respectively connected to a plate line through the second transistors in the multiple columns of memory cells.

In other words, the first transistors in the multiple columns of memory cells are connected to the same board lines. The second transistors in the multi-column memory cells are connected to the same plate lines. The number of columns of the multi-column memory cells is less than the number of columns of memory cells in the memory array.

As shown in FIG. 11 , the memory array 1100 includes 16 4×4 memory cells, 4 word lines, 4 bit lines, and 2 plate lines. The four word lines are WL0, WL1, WL2 and WL3 respectively. The eight bit lines are BL0, BL0', BL1, BL1', BL2, BL2', BL3 and BL3' respectively. The two plate lines are PL0 and PL1 respectively. The word lines are horizontal traces and the bit lines are Longitudinal wiring, board wiring is vertical wiring. The memory cells in the same row are connected to the same word line, the first ferroelectric capacitor in the memory cells in the same column is connected to the same bit line, the second ferroelectric capacitor in the memory cells in the same column is connected to the same bit line, every two columns The storage units are connected to the same board line. The memory cells in every two columns are connected to the same plate lines, the memory cells in different columns are connected to different bit lines, and the memory cells in different rows are connected to different word lines. Specifically, in Figure 11, the first to fourth rows of memory cells are connected to WL0, WL1, WL2 and WL3 respectively. The first ferroelectric capacitors in the memory cells in the first to fourth columns are connected to BL0, BL1, BL2 and BL3 respectively, and the second ferroelectric capacitors in the memory cells in the first to fourth columns are connected to BL0' and BL1' respectively. , BL2' and BL3' are connected. The memory cells in the first and second columns are connected to the plate line PL0, and the memory cells in the third and fourth columns are connected to the plate line PL1. The memory cells in the first column and the memory cells in the second column are symmetrically distributed with PL0 as the axis, and the memory cells in the third column and the memory cells in the fourth column are symmetrically distributed with PL1 as the axis.

The main difference between Figure 10 and Figure 11 is that in Figure 11 every two columns of memory cells share a board line, while in Figure 10 each column of memory cells are connected to different board lines. For other descriptions of Figure 11, please refer to the relevant descriptions of Figure 10. To avoid duplication, they will not be described again here.

It should be understood that the memory array shown in Figure 11 is only a schematic diagram of a memory array provided by the embodiment of the present application. The number of devices shown in the figure does not limit the solution of the embodiment of the present application. For example, the memory array in Figure 11 The array includes 16 4×4 memory cells. In practical applications, the memory array can include memory cells of other sizes. The number of word lines, bit lines and plate lines can be adjusted according to the size of the memory cells. The embodiments of this application This is not limited. In FIG. 11 , every two columns of memory cells share a board line. In practical applications, more columns of memory cells may share a board line. This is not limited in the embodiment of the present application.

In the case where the memory unit in the memory array of the embodiment of the present application includes two transistors and two ferroelectric capacitors, the information writing and reading process is similar to the information writing and reading process of the memory unit with a 2T2C structure. To avoid duplication, they will not be described again here.

According to the solution of the embodiment of the present application, the extending direction of the plate line and the extending direction of the word line are perpendicular to each other. The memory cells sharing the plate line and the memory cells sharing the word line are not exactly the same. This structure can only be used for those who need to read information. The memory cells read information without reading the entire row of memory cells. During the information reading process, only the ferroelectric capacitors of the memory cells that need to read information can withstand high voltages. The ferroelectric capacitors of other memory cells do not withstand high voltages. , avoids the situation where the entire row of memory cells needs to withstand high voltage during the reading process, reduces the number of times the ferroelectric capacitor withstands high voltage, and is beneficial to ensuring the service life of the storage array. Specifically, the word line connected to the memory unit that needs to read information is connected to a high potential, the transistor in the memory unit that needs to read information is turned on, and the board line connected to the memory unit that needs to read information can be connected to a high voltage pulse. , the word lines connected to other memory cells sharing the board line with the memory cell that needs to read information are not connected to high potential, that is, the transistors in other memory cells are not turned on, and the ferroelectric capacitors in other memory cells will not withstand High voltage on the board line. In this way, it is avoided that the entire row of memory cells needs to withstand high voltage during the reading process, and the number of times the ferroelectric capacitor is subjected to high voltage is reduced, which is beneficial to ensuring the service life of the memory array.

In addition, in the embodiment of the present application, multiple columns of memory cells can share a board line, further reducing the number of board lines, further increasing the effective storage area and improving storage density.

It should be noted that the storage arrays in Figures 5 to 11 are only examples. During specific implementation, those skilled in the art It should be understood by the operator that the memory arrays in Figures 5 to 11 may also include other devices necessary for normal operation. At the same time, based on specific needs, those skilled in the art should understand that the storage arrays in Figures 5 to 11 may also include hardware devices that implement other additional functions.

Figure 12 shows a working method of a storage array provided by an embodiment of the present application. The method 1200 can be applied to the previous storage arrays, for example, the storage arrays in Figures 5 to 11. For detailed description, please refer to the previous Description: In order to avoid duplication, when describing the method 1200, part of the description is appropriately omitted.

The memory array includes a plurality of memory cells, a plurality of word lines extending in the row direction, a plurality of bit lines extending in the column direction, and a plurality of plate lines extending in the column direction. Each memory unit in the plurality of memory cells includes a third A transistor and a first ferroelectric capacitor, the first terminal of the first transistor is connected to the second terminal of the first ferroelectric capacitor, wherein the first transistor of each memory unit in the i-th row memory unit in the plurality of memory units The gate end of is connected to the i-th word line among the plurality of word lines, i is a positive integer, and the first end of the first ferroelectric capacitor of each memory cell in the j-th column memory unit among the plurality of memory cells is connected to the plurality of word lines. The jth bit line among the bit lines is connected, j is a positive integer, the second end of the first transistor of each memory cell in the jth column memory unit is connected to one of the plurality of plate lines, and the first transistor The first terminal of the first transistor is the source terminal and the second terminal of the first transistor is the drain terminal. Alternatively, the first terminal of the first transistor is the drain terminal and the second terminal of the first transistor is the source terminal.

Method 1200 includes steps 1210 to 1220.

1210. Apply a first voltage signal on the i-th word line to turn on the first transistor of each memory cell in the i-th row of memory cells.

1220. Apply a second voltage signal to one of the plurality of plate lines, and apply a third voltage signal to the bit line connected to the target storage unit to read the information stored in the target storage unit. The second voltage signal The potential is higher than the potential of the third voltage signal, and the target memory cell is a memory cell at the intersection of the memory cell connected to one of the plurality of plate lines and the i-th row memory cell.

For example, the target storage unit may be the unit to be read mentioned above.

The first voltage signal can be understood as a voltage signal that causes the first transistor to turn on. For example, the first voltage signal may be the high potential signal connected to the word line mentioned above.

The second voltage signal and the third voltage signal are voltage signals used for reading stored information. For example, the second voltage signal may be the high-potential pulse signal connected to the board line mentioned above. The third voltage signal may be the low-potential signal connected to the bit line mentioned above.

Optionally, the second end of the first transistor of each memory cell in the j-th column memory cell is connected to the j-th plate line among the plurality of plate lines, and the method includes: applying a second voltage to the j-th plate line signal to read the information stored in the target storage unit, which is the storage unit at the intersection with the j-th column storage unit and the i-th row storage unit.

Optionally, the second end of the first transistor of each memory unit in the k-th column memory unit among the plurality of memory units shares multiple lines with the second end of the first transistor of each memory unit in the j-th column memory unit. One of the plate lines, k is a positive integer, and j is not equal to k. The method includes: applying a second voltage signal to one of the shared multiple plate lines to read the information stored in the target storage unit. , the target storage unit is the storage unit in the intersection with the j-th column storage unit, the k-th column storage unit and the i-th row storage unit.

Optionally, the j-th column memory unit and the k-th column memory unit are symmetrically distributed with one of the multiple shared plate lines as an axis.

Optionally, multiple bit lines are respectively connected to multiple amplifiers.

Optionally, the plurality of bit lines are connected to at least one amplifier through a multiplexer, and the number of at least one amplifier It is greater than or equal to the number of columns of memory cells connected to at least one of the plurality of plate lines.

For specific examples of method 1200, reference can be made to the relevant description in Figure 9, which will not be described again here.

An embodiment of the present application also provides a memory, including the aforementioned storage array and a storage controller, and the storage controller and the storage array are electrically connected. For example, the storage array may be any of the storage arrays in FIG. 5 to FIG. 11 .

An embodiment of the present application also provides an electronic device, including the aforementioned memory and a circuit board. The memory is disposed on the circuit board and is electrically connected to the circuit board.

It should be understood that the term "and/or" in this article is only an association relationship describing related objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, and A and B exist simultaneously. , there are three cases of B alone, where A and B can be singular or plural. In addition, the character "/" in this article generally indicates that the related objects are an "or" relationship, but it may also indicate an "and/or" relationship. For details, please refer to the previous and later contexts for understanding.

In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

Prefixes such as "first" and "second" are used in the embodiments of this application only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects.

It should be understood that in the various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application. The implementation process constitutes any limitation.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should cover within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A memory array, characterized in that it includes: a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction, and a plurality of plate lines extending along a column direction, the plurality of Each of the memory cells includes a first transistor and a first ferroelectric capacitor, a first terminal of the first transistor is connected to a second terminal of the first ferroelectric capacitor, wherein,

The gate terminal of the first transistor of each memory cell in the i-th row of memory cells in the plurality of memory cells is connected to the i-th word line in the plurality of word lines, where i is a positive integer,

The first end of the first ferroelectric capacitor of each memory cell in the j-th column memory unit among the plurality of memory cells is connected to the j-th bit line among the plurality of bit lines, where j is a positive integer,

The second end of the first transistor of each memory cell in the jth column of memory cells is connected to one of the plurality of plate lines, the first end of the first transistor is a source end, and the first end of the first transistor is a source end. The second terminal of a transistor is a drain terminal, or the first terminal of the first transistor is a drain terminal, and the second terminal of the first transistor is a source terminal.
The memory array according to claim 1, wherein the second end of the first transistor of each memory cell in the j-th column of memory cells is connected to the j-th plate line among the plurality of plate lines.
The memory array according to claim 1, wherein the second end of the first transistor of each memory unit in the k-th column memory unit among the plurality of memory cells is connected to the second end of the first transistor of each memory unit in the j-th column memory unit. The second terminals of the first transistors of the memory cells share one of the plurality of plate lines, k is a positive integer, and j is not equal to k.
The memory array according to claim 3, wherein the j-th column memory cells and the k-th column memory cells are symmetrically distributed with one of the shared multiple plate lines as an axis.
The memory array according to any one of claims 1 to 4, wherein the plurality of bit lines are respectively connected to a plurality of amplifiers.
The memory array according to any one of claims 1 to 4, characterized in that the plurality of bit lines are connected to at least one amplifier through a multiplexer, and the number of the at least one amplifier is greater than or equal to the The number of columns of memory cells connected to at least one of the multiple board lines.
A memory, characterized in that it includes the storage array and a storage controller according to any one of claims 1 to 6, and the storage controller is electrically connected to the storage array.
An electronic device, characterized by comprising the memory as claimed in claim 7 and a circuit board, the memory being disposed on the circuit board and electrically connected to the circuit board.
A working method of a memory array, characterized in that the memory array includes a plurality of memory cells, a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction, and a plurality of plates extending in a column direction. line, each memory cell in the plurality of memory cells includes a first transistor and a first ferroelectric capacitor, a first terminal of the first transistor is connected to a second terminal of the first ferroelectric capacitor, wherein, The gate terminal of the first transistor of each memory cell in the i-th row of memory cells in the plurality of memory cells is connected to the i-th word line in the plurality of word lines, i is a positive integer, and the plurality of The first end of the first ferroelectric capacitor of each memory cell in the j-th column of memory cells is connected to the j-th bit line among the plurality of bit lines, j is a positive integer, and the j-th column The second end of the first transistor of each memory unit in the memory unit is connected to one of the plurality of plate lines, the first end of the first transistor is a source end, and the second end of the first transistor The terminal is a drain terminal, or the first terminal of the first transistor is a drain terminal, and the second terminal of the first transistor is a source terminal, The methods include:

Applying a first voltage signal to the i-th word line to turn on the first transistor of each memory cell in the i-th row of memory cells;

A second voltage signal is applied to one of the plurality of plate lines, and a third voltage signal is applied to the bit line connected to the target memory unit to read the information stored in the target memory unit, the The potential of the second voltage signal is higher than the potential of the third voltage signal, and the target memory cell is a memory cell at the intersection of a memory cell connected to one of the plurality of plate lines and the i-th row of memory cells.
The method of claim 9, wherein the second end of the first transistor of each memory unit in the j-th column memory unit is connected to the j-th plate line among the plurality of plate lines, so The methods include:

A second voltage signal is applied to the j-th plate line to read the information stored in the target storage unit, which is the intersection of the j-th column storage unit and the i-th row storage unit. storage unit.
The method of claim 9, wherein the second terminal of the first transistor of each memory unit in the k-th column of the plurality of memory cells is connected to each of the j-th column memory cells. The second end of the first transistor of the memory unit shares one of the plurality of plate lines, k is a positive integer, j is not equal to k, and the method includes:

A second voltage signal is applied to one of the shared plurality of plate lines to read the information stored in the target storage unit. The target storage unit is a storage unit of the jth column and the kth column. The storage unit in the intersection of the storage unit and the i-th row storage unit.
The method of claim 11, wherein the j-th column memory unit and the k-th column memory unit are symmetrically distributed with one of the shared multiple plate lines as an axis.
The method according to any one of claims 9 to 12, characterized in that the plurality of bit lines are respectively connected to a plurality of amplifiers.
The method according to any one of claims 9 to 12, characterized in that the plurality of bit lines are connected to at least one amplifier through a multiplexer, and the number of the at least one amplifier is greater than or equal to the plurality of amplifiers. The number of columns of memory cells connected to at least one of the strip lines.