CN117116318A

CN117116318A - Memory array and working method thereof

Info

Publication number: CN117116318A
Application number: CN202210530995.7A
Authority: CN
Inventors: 赵杰; 刘少鹏; 李�昊; 杨汝辉; 贾秀峰; 张敏; 张恒; 吕杭炳; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2023-11-24
Also published as: WO2023221597A1

Abstract

The application discloses a memory array and a working method of the memory array, wherein the memory array comprises a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction and a plurality of strip lines extending along the column direction, a first end of a first ferroelectric capacitor of each memory cell in a j-th column of memory cells is connected with the j-th bit line, and a second end of a first transistor of each memory cell in the j-th column of memory cells is connected with one strip line in the plurality of strip lines. The scheme of the application can avoid the memory cell bearing unnecessary high voltage in the reading process, reduce the times of bearing high voltage by the ferroelectric capacitor in the memory cell, and is beneficial to prolonging the service life of the memory array.

Description

Memory array and working method thereof

Technical Field

The present application relates to the field of semiconductor devices, and in particular, to a memory array and a method for operating the memory array.

Background

Ferroelectric random access memory (ferroelectric random access memory, feRAM) is a device that utilizes the properties of ferroelectric materials for storage.

The FeRAM includes a memory array composed of a plurality of memory cells, and the write and read operations adopt a mode of writing in an entire row and reading in an entire row. In the reading process, the ferroelectric capacitors in all the memory cells in the same row need to bear high voltage when reading data and high voltage when writing back data. Even in the case where it is not necessary to read data in all memory cells in the row, the ferroelectric capacitors in all memory cells in the row still need to experience a high voltage when reading data and a high voltage when writing back data. This can cause the ferroelectric capacitor to experience excessive voltage cycles, affecting the performance of the ferroelectric capacitor and thus the useful life of the FeRAM.

Disclosure of Invention

The application provides a memory array and a working method of the memory array, which can avoid the memory cell bearing unnecessary high voltage in the reading process, reduce the times of bearing high voltage by a ferroelectric capacitor in the memory cell and are beneficial to prolonging the service life of the memory array.

In a first aspect, there is provided a memory array comprising: the memory device comprises a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction and a plurality of strip lines extending along the column direction, wherein each memory cell in the plurality of memory cells comprises a first transistor and a first ferroelectric capacitor, a first end of the first transistor is connected with a second end of the first ferroelectric capacitor, a gate end of the first transistor of each memory cell in an ith row of the plurality of memory cells is connected with an ith word line in the plurality of word lines, i is a positive integer, a first end of the first ferroelectric capacitor of each memory cell in a jth column of the plurality of memory cells is connected with a jth bit line in the plurality of bit lines, j is a positive integer, a second end of the first transistor of each memory cell in the jth column is connected with one strip line in the plurality of strip lines, a first end of the first transistor is a source end, a second end of the first transistor is a drain end, or a first end of the first transistor is a drain end, and a second end of the first transistor is a source end of the second transistor is a source end.

According to the scheme of the embodiment of the application, the extending direction of the plate line and the extending direction of the word line are mutually perpendicular, the memory cells sharing the plate line and the memory cells sharing the word line are not completely identical, the structure can only read information of the memory cells needing to read information, but not need to read the whole row of memory cells, the ferroelectric capacitors of the memory cells needing to read information only bear high voltage in the process of reading information, the ferroelectric capacitors of other memory cells do not bear high voltage, the situation that the whole row of memory cells need to bear high voltage in the process of reading is avoided, the times that the ferroelectric capacitors bear high voltage are reduced, and the service life of the memory array is facilitated to be ensured.

In addition, one row of storage units can share one strip line, which is beneficial to reducing the number of the strip lines, and simultaneously reducing the area occupied by the connecting lines between the strip lines and the storage units, thereby increasing the effective storage area and improving the storage density. In addition, the high-potential signal source required by the plate line can be deployed in the peripheral circuit, so that the power supply is prevented from being deployed between the storage units, the effective storage area is increased, and the storage density is improved.

The i-th row of memory cells may be any row of memory cells among the plurality of memory cells. The jth column of memory cells may be any column of memory cells in the plurality of memory cells. The ith word line may be any one of a plurality of word lines, and the jth bit line may be any one of a plurality of bit lines.

With reference to the first aspect, in certain implementations of the first aspect, the second end of the first transistor of each memory cell in the j-th column of memory cells is connected to a j-th slat line of the plurality of slat lines.

Illustratively, the plurality of memory cells are arranged in I-rows and J-columns. The memory array may include K slat lines. I is an integer greater than 1, J is an integer greater than 1, and K is an integer greater than 1. For example, J is equal to K, in which case the first transistor of each of the J columns of memory cells is connected to the plate line corresponding to the J columns of memory cells. I.e., the J rows of memory cells are in one-to-one correspondence with the J slat lines.

With reference to the first aspect, in certain implementations of the first aspect, J is greater than K. In this case, a plurality of columns of memory cells among the plurality of memory cells share one of the K slat lines.

In the embodiment of the application, a plurality of rows of storage units can share one strip line, so that the number of the strip lines is further reduced, the effective storage area can be further increased, and the storage density is improved.

With reference to the first aspect, in certain implementations of the first aspect, the second end of the first transistor of each memory cell in a kth column of memory cells in the plurality of memory cells shares a slat of the plurality of slat lines with the second end of the first transistor of each memory cell in a jth column of memory cells, k being a positive integer, j being unequal to k.

With reference to the first aspect, in certain implementations of the first aspect, the jth column of memory cells and the kth column of memory cells are symmetrically distributed about a slat line of the shared plurality of slat lines.

Thus, the area required for wiring between the memory cell and the plate line in the memory cell can be reduced, and the effective memory area can be further increased.

With reference to the first aspect, in some implementations of the first aspect, the plurality of bit lines are respectively connected to a plurality of amplifiers.

With reference to the first aspect, in some implementations of the first aspect, the plurality of bit lines are connected to at least one amplifier through a multiplexer, and a number of the at least one amplifier is greater than or equal to a number of columns of memory cells to which at least one of the plurality of slat lines is connected.

Thus, the plurality of columns of bit lines correspond to one SA, the number of the SAs is reduced, and the effective storage area, namely the storage unit density, can be improved.

In a second aspect, there is provided a memory comprising a memory array and a memory controller of any one of the possible implementations of the first aspect or the first aspect, the memory controller and the memory array being electrically connected.

In a third aspect, an electronic device is provided, including the memory of the second aspect and a circuit board, where the memory is disposed on the circuit board and electrically connected to the circuit board.

In a fourth aspect, a method for operating a memory array is provided, the memory array comprising: the method includes the steps of a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction, and a plurality of strip lines extending along the column direction, wherein each memory cell in the plurality of memory cells includes a first transistor and a first ferroelectric capacitor, a first end of the first transistor is connected to a second end of the first ferroelectric capacitor, wherein a gate end of the first transistor of each memory cell in an ith row of the plurality of memory cells is connected to an ith word line in the plurality of word lines, i is a positive integer, a first end of the first ferroelectric capacitor of each memory cell in a jth column of the plurality of memory cells is connected to a jth bit line in the plurality of bit lines, j is a positive integer, a second end of the first transistor of each memory cell in the jth column is connected to a strip line in the plurality of bit lines, a first end of the first transistor is a source end, a second end of the first transistor is a drain end, or a first end of the first transistor is a drain end, a first end of the first transistor is a source end of the second transistor is a source end, and the method includes: applying a first voltage signal on the i-th word line to turn on a first transistor of each memory cell in the i-th row of memory cells; and applying a second voltage signal to one of the plurality of slat lines, and applying a third voltage signal to a bit line connected to the target memory cell to read information stored in the target memory cell, wherein the second voltage signal has a higher potential than the third voltage signal, and the target memory cell is a memory cell in an intersection of a memory cell connected to the one of the plurality of slat lines and the i-th row of memory cells.

With reference to the fourth aspect, in some implementations of the fourth aspect, the second terminal of the first transistor of each memory cell in the j-th column of memory cells is connected to a j-th slat line of the multiple slat lines, the method includes: a second voltage signal is applied to the j-th slat line to read information stored in a target memory cell, which is a memory cell in an intersection with the j-th column of memory cells and the i-th row of memory cells.

With reference to the fourth aspect, in some implementations of the fourth aspect, the second terminal of the first transistor of each memory cell in a kth column of memory cells in the plurality of memory cells shares a strip line of the plurality of strip lines with the second terminal of the first transistor of each memory cell in a jth column of memory cells, k being a positive integer, j being not equal to k, the method includes: a second voltage signal is applied to one of the shared multi-strip lines to read information stored in a target memory cell that is a memory cell in an intersection with a j-th column of memory cells, a k-th column of memory cells, and an i-th row of memory cells.

With reference to the fourth aspect, in some implementations of the fourth aspect, the j-th column of memory cells and the k-th column of memory cells are symmetrically distributed about a slat line of the shared plurality of slat lines.

With reference to the fourth aspect, in some implementations of the fourth aspect, the plurality of bit lines are respectively connected to a plurality of amplifiers.

With reference to the fourth aspect, in some implementations of the fourth aspect, the plurality of bit lines are connected to at least one amplifier through a multiplexer, and a number of the at least one amplifier is greater than or equal to a number of columns of memory cells to which at least one of the plurality of slat lines is connected.

The technical effects that may be achieved by any possible implementation manner of any one of the second aspect to the fourth aspect may be correspondingly described with reference to the technical effects that may be achieved by any one of the possible implementation manners of any one of the first aspect, and the descriptions will not be repeated.

Drawings

FIG. 1 is a schematic diagram of the memory principle of a FeRAM;

FIG. 2 is a schematic diagram of one memory cell in a FeRAM memory array;

FIG. 3 is a schematic diagram of a FeRAM write operation;

FIG. 4 is a schematic diagram of a read operation of FeRAM;

FIG. 5 is a schematic block diagram of a memory array;

FIG. 6 is a schematic block diagram of another memory array;

FIG. 7 is a schematic block diagram of yet another memory array;

FIG. 8 is a schematic diagram of a write operation of a memory array;

FIG. 9 is a schematic diagram of a read operation of a memory array;

FIG. 10 is a schematic block diagram of yet another memory array;

FIG. 11 is a schematic block diagram of yet another memory array;

FIG. 12 is a schematic flow chart of a method of operation of a memory array.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

The ferroelectric material can generate spontaneous polarization under the electric field, the polarization direction can be adjusted along with the action of an external electric field, and the polarization state is reserved after the electric field disappears. FeRAM utilizes this property of ferroelectric material to store data.

Fig. 1 shows a schematic diagram of the storage principle of FeRAM. The abscissa in fig. 1 is the voltage V or the electric field strength E, the ordinate may be the polarization strength P or the polarization charge Q, pr is the remnant polarization strength, and Vc is the coercive field of the ferroelectric capacitor. As the electric field strength increases, the polarization strength also increases until saturation. When the direction of the external electric field changes, the polarization direction also changes. Different polarization directions may be used to represent information "0" and information "1". For example, as shown in fig. 1, when the potential of the upper plate of the ferroelectric capacitor is lower than that of the lower plate, the polarization direction of the ferroelectric capacitor is downward, and the stored information can be considered to be "1" at this time; when the potential of the upper electrode plate of the ferroelectric capacitor is higher than that of the lower electrode plate, the polarization direction of the ferroelectric capacitor is upward, and the stored information can be considered as 0.

The circuit structure of the FeRAM is the basis for ensuring that the FeRAM realizes the correct read-write function. Memory cells in FeRAM memory arrays are typically either a one transistor one capacitor (one transistor one capacitor,1T 1C) structure or a two transistor two capacitor (two transistor two capacitor,2T 2C) structure.

Fig. 2 is a schematic diagram of one memory cell in a FeRAM memory array. As shown in fig. 2 (a), the 1T1C structure includes one transistor and one ferroelectric capacitor. A gate terminal of the transistor is connected with a Word Line (WL), a drain terminal of the transistor is connected with a Bit Line (BL), one terminal of the ferroelectric capacitor is connected with a source terminal of the transistor, and the other terminal of the ferroelectric capacitor is connected with a Plate Line (PL). WL is used to control the transistor to be turned on and off, and information can be written in or read from the ferroelectric capacitor by applying corresponding potentials at BL and PL.

As shown in fig. 2 (b), the 2T2C structure includes two transistors and two ferroelectric capacitors. The 2T2C structure can be considered as two adjacent 1T1C structures sharing the same word line and plate line, but storing opposite data. For example, one of the ferroelectric capacitors stores information "1", and the other ferroelectric capacitor stores information "0". Specifically, the gate terminals of the two transistors are connected to the same word line WL. The drain terminal of one of the transistors is connected to the bit line BL and the source terminal of the transistor is connected to one terminal of one of the ferroelectric capacitors. The drain terminal of the other transistor is connected to the bit line BL' and the source terminal of the other transistor is connected to one terminal of the other ferroelectric capacitor. The two ferroelectric capacitors are connected to the same slat line PL. That is, the memory cells of the 2T2C structure are connected to WL, BL' and PL. WL is used to control the gating and switching off of the transistors, and information can be written in or read from the ferroelectric capacitors by applying corresponding potentials at BL, BL' and PL.

For easy understanding and description, the following description will take a 1T1C structure as an example of the memory cell, and the scheme of the embodiment of the present application is not limited.

The FeRAM includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of strip lines. Wherein the word lines and the plate lines extend in a lateral direction and the bit lines extend in a longitudinal direction. Memory cells on the same row share word lines, memory cells on the same row share plate lines, and memory cells on the same column share bit lines. In other words, the gate terminals of the transistors of all the memory cells on the same row are connected to the same word line, the ferroelectric capacitors of all the memory cells on the same row are connected to the same strip line, and the drain terminals of the transistors of all the memory cells on the same column are connected to the same bit line. Memory cells sharing the same word line share the same lath line.

For example, the memory array shown in fig. 3 and 4 includes three rows and four columns of memory cells, three rows of word lines WL0, WL1 and WL2,4 columns of bit lines BL0, BL1, BL2 and BL3, and 3 rows of plate lines PL0, PL1 and PL2. The three rows of memory cells are respectively connected with three rows of word lines, the three rows of memory cells are respectively connected with three rows of plate lines, and the four columns of memory cells are respectively connected with four columns of bit lines.

When the information '1' needs to be written into the unit to be written, the word line connected with the unit to be written is connected with high potential, namely, the gate end of the transistor in the unit to be written is connected with high potential, the transistor in the unit to be written is conducted, the bit line connected with the unit to be written is connected with high potential, the plate line connected with the unit to be written is connected with low potential, the ferroelectric capacitor in the unit to be written is positively polarized, and the information '1' is written into the unit to be written.

Fig. 3 shows a schematic diagram of a write operation. For example, as shown in fig. 3 (a), the cells to be written include a first row of memory cells. When it is necessary to write information "1" to the first row of memory cells, WL0 is connected to the high potential VDD, and the transistors in the row of memory cells are turned on. BL0, BL1, BL2 and BL3 are connected to the high potential VDD, PL0 is connected to the low potential VSS, e.g., 0V, the ferroelectric capacitors in the first row of memory cells are positively polarized, and information "1" is written into the first row of memory cells.

When the information '0' needs to be written into the unit to be written, the word line connected with the unit to be written is connected with high potential, namely, the gate end of the transistor in the unit to be written is connected with high potential, the transistor in the unit to be written is conducted, the bit line connected with the unit to be written is connected with low potential, the plate line connected with the unit to be written is connected with high potential, the ferroelectric capacitor in the unit to be written is reversely polarized, and the information '0' is written into the unit to be written. In addition, since the memory cells in the same row share one word line, under the condition that the word line connected with the memory cells to be written is connected with high potential, the transistors in the memory cells in the same row with the memory cells to be written are conducted, and the ferroelectric capacitors in the memory cells in the row bear the potentials on the bit line and the plate line which are respectively corresponding to the ferroelectric capacitors. Since the memory cells in the same row share a plate line, under the condition that the plate line connected with the unit to be written is connected with high potential, the ferroelectric capacitors in the memory cells in the same row with the unit to be written are required to bear the high potential on the plate line. If the bit line to which the row of memory cells is connected is low, information "0" is written into the row of memory cells. In order to avoid that the information of the memory cell having stored the information "1" is rewritten to the information "0", the bit line connected to the other memory cell in the same row as the cell to be written is set to a high potential.

For example, as shown in fig. 3 (b), the cells to be written are the second memory cell and the third memory cell of the first row. When writing information "0" to the cell to be written, WL0 is connected to the high potential VDD, and the transistors in the row of memory cells are turned on. BL1 and BL2 are connected to a low potential VSS, e.g., 0V, and PL0 is connected to a high potential VDD, and ferroelectric capacitors in the second and third memory cells in the first row are reverse polarized, and information "0" is written into both memory cells. In addition, in order to avoid that the information of the memory cell having stored the information "1" is rewritten to the information "0", BL0 and BL3 need to be connected to the high potential VDD.

When information is required to be read from the unit to be read, the bit line connected with the unit to be read is connected with 0V for pre-discharging, then the word line connected with the unit to be read is connected with high potential, and high potential pulse is applied to the plate line connected with the unit to be read. If the information stored in the cell to be read is "0", the polarization direction of the ferroelectric capacitor in the cell to be read is not changed when the information is read, and the charge Q0 is released. The released charge Q0 is distributed over the ferroelectric capacitor of the cell to be read and the bit line to which the cell to be read is connected, and the voltage of the bit line is raised. The voltage of the bit line at this time is V0. If the information stored in the cell to be read is "1", the polarization direction of the ferroelectric capacitor in the cell to be read is changed by an external electric field from forward polarization to reverse polarization, and the charge Q1 is released. The released charge Q1 contains polarization inversion charge, Q1 > Q0. The voltage on the bit line increases, and at this time, the voltage on the bit line is V1, V1 > V0. The Sense Amplifier (SA) connected with the bit line detects the voltage of the bit line, compares the voltage of the bit line with the reference potential Vref, and can determine whether the information stored in the unit to be read is information 0 or 1 according to the comparison result. For example, if the voltage of the bit line connected to the unit to be read exceeds Vref, the information stored in the unit to be read is information "1"; if the voltage of the bit line connected with the unit to be read does not exceed Vref, the information stored in the unit to be read is information '0'.

Since the read process is a "destructive read," i.e., the read operation may change the information originally stored in the cell to be read. For example, if the information stored in the cell to be read is "1", the polarization direction of the ferroelectric capacitor in the cell to be read is changed when the information is read, and the information stored in the cell to be read is rewritten to "0". After the reading operation is finished, the information originally stored in the unit to be read, namely the information stored in the unit to be read when the reading operation is started, needs to be written back into the unit to be read according to the writing operation process.

Fig. 4 shows a schematic diagram of a read operation. In fig. 4 (a), each column BL is connected to one SA, respectively. In the reading process, the whole row of memory cells needs to be read at the same time. For example, as shown in fig. 4, when it is necessary to read information stored in the memory cells of the first row, BL0, BL1, BL2 and BL3 are pre-discharged at 0V, WL0 is then high, a high potential pulse is applied to PL0, and voltages of BL0, BL1, BL2 and BL3 are read out through the 4 SAs and compared with a reference voltage to obtain information stored in the memory cells of the first row.

In fig. 4 (b), a plurality of columns BL are connected to one SA, that is, 4 columns BL are connected to one SA through a data selector (MUX). During the reading process, information of one memory cell can be read in the 4 columns. For example, when the cell to be read is the first memory cell in the first row and the information stored in the cell to be read needs to be read, pre-discharging BL0 with 0V, connecting WL0 with high potential, applying high potential pulse on PL0, reading out the voltage on BL0 through SA, and comparing with the reference voltage to obtain the information stored in the first memory cell in the first row.

The manner of reading the entire row as shown in fig. 4 affects the useful life of the FeRAM, limited by the endurance (endurance) period of the ferroelectric capacitor. Durability refers to the ability of a ferroelectric material to retain polarization strength after being subjected to multiple voltage cycles. Durability is a key parameter in evaluating the reliability of ferroelectric materials. The durability of FeRAM is about 10 ^12-14 A voltage cycle. The durability of FeRAM refers to the durability of ferroelectric capacitors in FeRAM. I.e. ferroelectric capacitance in FeRAM is experiencing 10 ^12-14 After a single voltage cycle, the polarization cannot be maintained, which in turn results in information being unable to be stored.

Specifically, in the structure shown in fig. 4 (a), each column BL is connected to one SA, and even if the information in the entire row of memory cells does not need to be read out, the information of all the memory cells in the row is still read out. The ferroelectric capacitor of the memory cell in the row which does not need to be read also experiences high voltage in the reading process and high voltage in the writing back process, so that the frequency of actually experiencing high voltage by the ferroelectric capacitor is far higher than the frequency of needing to be read by the ferroelectric capacitor, and the reliability of the ferroelectric capacitor is affected. In the structure shown in fig. 4 (b), the ferroelectric capacitor of the memory cell that is not read in the row is still subjected to high voltage during the reading process and high voltage during the writing back process, so that the number of times the ferroelectric capacitor actually experiences high voltage is much higher than the number of times the ferroelectric capacitor is read, and the reliability of the ferroelectric capacitor is also affected.

That is, the way of reading the whole row can make the ferroelectric capacitor in the whole row of memory cells go through the high voltage in the reading process and the high voltage in the writing back process, which affects the service life of the FeRAM.

Assuming that the read-write cycle of FeRAM is 50ns, for a 256×1024-scale memory array, if the whole row reading mode is required to meet the 10-year lifetime requirement of the memory, the endurance needs to be greater than 10 ¹⁶ A voltage cycle. Whereas in practice the endurance cycle of the ferroelectric capacitor is about 10 ^12-14 The life requirement cannot be met for a single voltage cycle.

The embodiment of the application provides a storage array, which can avoid a whole row reading mode and is beneficial to ensuring the service life of the storage array.

The memory array includes a plurality of memory cells, a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction, and a plurality of slat lines extending in the column direction. The plurality of memory cells are arranged along rows and columns. Each memory cell of the plurality of memory cells includes a first transistor and a first ferroelectric capacitor. The first terminal of the first transistor is connected to the second terminal of the first ferroelectric capacitor.

The gate terminal of the first transistor of each of the first portion of memory cells is connected to one of the plurality of word lines, the first portion of memory cells including a plurality of memory cells in a same row in the memory array.

The first ferroelectric capacitor of each memory cell in the second portion is connected to one of the plurality of bit lines at a first end, and the second portion includes a plurality of memory cells in the same column in the memory array.

The second terminal of the first transistor of each of the second portion of memory cells is connected to one of the plurality of strip lines.

It should be noted that, in the embodiment of the present application, the row direction and the column direction are relative concepts, and are only used to define two directions perpendicular to each other. The row direction may also be referred to as the lateral direction. The column direction may also be referred to as the longitudinal direction. That is, the plurality of signal lines extending in the row direction are parallel to each other, and the plurality of signal lines extending in the column direction are parallel to each other. The signal lines extending in the row direction and the signal lines extending in the column direction are perpendicular to each other. The plurality of memory cells in the memory array are distributed in rows and columns, i.e., the plurality of memory cells are distributed in a direction parallel to the extending direction of the signal lines and in a direction perpendicular to the extending direction of the signal lines.

The different signal lines in the embodiment of the application refer to mutually independent signal lines.

Each memory cell in the memory array includes a first transistor and a first ferroelectric capacitor. A memory cell is connected to at least three signal lines, namely, a word line, a bit line, and a plate line, respectively. Specifically, in a memory cell, a gate terminal of a first transistor is connected to a word line, a first terminal of a first ferroelectric capacitor is connected to a bit line, a second terminal of the first ferroelectric capacitor is connected to a first terminal of the first transistor, and a second terminal of the first transistor is connected to a plate line.

The word line is used to control the transistor on and off. The plate line and the bit line act together on the ferroelectric capacitor to complete the read-write operation. The bit lines are used to transmit electrical signals. For specific description, reference is made to the foregoing, and no further description is given here.

It should be understood that the "first end" and "second end" of the first ferroelectric capacitor are used only to distinguish the two ends of the first ferroelectric capacitor, and have no other limiting effect. The "first end" and "second end" of the first transistor are only used to distinguish the source end and the drain end of the first transistor, and have no other limiting effect. For example, the first terminal of the first transistor is a source terminal, and the second terminal of the first transistor is a drain terminal. In this case, the second terminal of the first ferroelectric capacitor is connected to the source terminal of the first transistor, and the drain terminal of the first transistor is connected to the plate line. For another example, the first end of the first transistor is a drain end, and the second end of the first transistor is a source end. In this case, the second terminal of the first ferroelectric capacitor is connected to the drain terminal of the first transistor, and the source terminal of the first transistor is connected to the plate line.

Each of the plurality of word lines is coupled to a memory cell, each of the plurality of bit lines is coupled to a memory cell, and each of the plurality of strip lines is coupled to a memory cell. In one implementation, the memory cells to which each word line is connected are different, the memory cells to which each bit line is connected are different, and the memory cells to which each plate line is connected are different.

For convenience of understanding and description, in the embodiment of the present application, the case that the second terminal of the first ferroelectric capacitor is connected to the drain terminal of the first transistor and the source terminal of the first transistor is connected to the plate line is taken as an example to describe the scheme of the embodiment of the present application, and the scheme of the embodiment of the present application is not limited.

The gate terminal of the first transistor of each of the first portion of memory cells is connected to one of the plurality of word lines, meaning that the word line to which the gate terminal of the first transistor of each of the first portion of memory cells is connected is the same.

The first end of the first ferroelectric capacitor of each memory cell in the second portion of memory cells is connected to one of the plurality of bit lines, meaning that the bit line to which the first end of the first ferroelectric capacitor of each memory cell in the second portion of memory cells is connected is the same.

The second end of the first transistor of each memory cell in the second portion of memory cells is connected to one of the plurality of plate lines, meaning that the plate line to which the second end of the first transistor of each memory cell in the second portion of memory cells is connected is the same.

The first portion of memory cells may include all or a portion of memory cells in the same row. The second portion of memory cells may include all or a portion of memory cells in the same column.

Illustratively, the first portion of memory cells may include an ith row of memory cells and the second portion of memory cells may include a jth column of memory cells.

In this case, the gate terminal of the first transistor of each memory cell in the ith row of memory cells in the memory array is connected to the ith word line of the plurality of word lines, i being a positive integer; the first end of the first ferroelectric capacitor of each memory cell in the j-th column of memory cells in the memory array is connected with the j-th bit line in the plurality of bit lines, and j is a positive integer; the second end of the first transistor of each memory cell in the j-th column of memory cells is connected with one of the multiple slat lines, the first end of the first transistor is a source end, the second end of the first transistor is a drain end, or the first end of the first transistor is a drain end, and the second end of the first transistor is a source end.

The ith row of memory cells may be any row of memory cells in the memory array. The jth column of memory cells may be any column of memory cells in a memory array. The ith word line may be any one of a plurality of word lines, and the jth bit line may be any one of a plurality of bit lines.

The first transistor of each memory cell in the ith row of memory cells is connected to the ith word line, and it is also understood that the word lines connected to the gate terminals of the first transistors of all memory cells in the same row in the memory array may be the same, and the word lines connected to the gate terminals of the first transistors in different rows of memory cells may be different. The first end of the first ferroelectric capacitor of each memory cell in the j-th column of memory cells is connected to the j-th bit line of the plurality of bit lines, and it is also understood that the bit lines to which the first ferroelectric capacitors of all memory cells in the same column are connected may be the same, and the bit lines to which the first ferroelectric capacitors of memory cells in different columns are connected may be different. The second end of the first transistor of each memory cell in the j-th column of memory cells is connected to one of the plurality of plate lines, it being understood that the plate lines to which the first transistors of all memory cells in the same column are connected may be identical. When i in the i-th word line takes different values, i represents different word lines, i.e., i in the i-th word line takes different values only for defining different word lines, and the arrangement order of the word lines is not limited. When j in the jth bit line takes different values, j representing different bit lines, namely, different values of j in the jth word line are only used for limiting different bit lines, and the arrangement sequence of the bit lines is not limited.

In one possible implementation, the plate lines to which the first transistors in each of the first portion of memory cells are connected are different.

In other words, the first transistors in the memory cells sharing the same word line are connected to different plate lines, respectively.

The plurality of memory cells in the memory array are arranged in I rows and J columns. The plurality of memory cells is i×j memory cells. The memory array may include K slat lines. I is an integer greater than 1, J is an integer greater than 1, and K is an integer greater than 1.

Optionally, the second terminal of the first transistor of each memory cell in the j-th column of memory cells is connected to a j-th slat line of the K slat lines.

For example, J is equal to K, in which case the first transistor of each of the J columns of memory cells in the memory array is connected to the plate line corresponding to the J columns of memory cells. I.e., the J rows of memory cells are in one-to-one correspondence with the J slat lines.

Taking as an example a memory cell comprising a transistor and a ferroelectric capacitor, i.e. a first transistor and a first ferroelectric capacitor. A memory cell is connected to a word line, a bit line, and a plate line, respectively. Each row of memory cells is connected with a word line corresponding to the row of memory cells, each column of memory cells is connected with a bit line corresponding to the column of memory cells, and each column of memory cells is connected with a plate line corresponding to the column of memory cells. The word lines corresponding to the memory cells of different rows are different. Bit lines corresponding to memory cells in different columns are different. The plate lines corresponding to the memory cells in different columns are different.

That is, the word lines to which the memory cells of different rows are connected are different, the plate lines to which the memory cells of different columns are connected are different, and the bit lines to which the memory cells of different columns are connected are different. In this case, each column plate line corresponds to each column bit line one by one.

Fig. 5 shows a schematic block diagram of a memory array 500 according to an embodiment of the present application. As shown in fig. 5, the memory array 500 includes 4×4 16 memory cells, 4 word lines, 4 bit lines, and 4 stripe lines. The 4 word lines are WL0, WL1, WL2 and WL3, respectively. The 4 bit lines are BL0, BL1, BL2 and BL3, respectively. The 4 slat lines are PL0, PL1, PL2 and PL3, respectively. The word lines are transverse wires, the bit lines are longitudinal wires, and the plate lines are longitudinal wires. In the memory array shown in fig. 5, one memory cell includes one transistor (i.e., a first transistor) and one ferroelectric capacitor (i.e., a first ferroelectric capacitor).

In the memory array shown in fig. 5, the word lines connected to the gate terminals of the transistors in the same row of memory cells are the same word line, i.e., the same row of memory cells are connected to the same word line. The source terminals of the transistors in the same row of memory cells are connected to the same plate line, i.e. the same row of memory cells are connected to the same plate line. The bit lines connected with the ferroelectric capacitors in the same column of memory cells are the same bit line, namely the same column of memory cells are connected with the same bit line. The plate lines connected with the memory cells of different columns are different, the bit lines connected with the memory cells of different columns are different, and the word lines connected with the memory cells of different rows are different.

It should be understood that the memory array shown in fig. 5 is only a schematic diagram of a memory array provided by an embodiment of the present application, and the number of devices shown in the drawing is not limited to the solution of the embodiment of the present application, for example, the memory array in fig. 5 includes 4×4 16 memory cells, and in practical applications, the memory array may include other scale memory cells, and the number of word lines, bit lines and plate lines may be adjusted according to the scale of the memory cells, which is not limited by the embodiment of the present application.

In another possible implementation, the plate lines to which the first transistors of the partial memory cells in the first partial memory cells are connected are the same.

That is, some of the memory cells sharing the same word line share the same lath line. In other words, at least some of the memory cells sharing the same word line are different in the plate line to which the memory cells are connected. This structure may also be referred to as a segment common PL structure.

Optionally, J is greater than K. In this case, a plurality of columns of memory cells in the memory array share one of the K slat lines.

Alternatively, the plate lines to which the first transistors in the plurality of columns of memory cells are connected are the same.

Taking as an example a memory cell comprising a transistor and a ferroelectric capacitor, i.e. a first transistor and a first ferroelectric capacitor. Each row of memory cells is connected with a word line corresponding to the row of memory cells, each column of memory cells is connected with a bit line corresponding to the column of memory cells, and each column of memory cells is connected with a plate line corresponding to the column of memory cells. The word lines corresponding to the memory cells of different rows are different. Bit lines corresponding to memory cells in different columns are different. The plate lines corresponding to the memory cells of different columns may be identical.

That is, the word lines to which memory cells of different rows are connected are different, the bit lines to which memory cells of different columns are connected are different, and the plate lines to which memory cells of different columns are connected may be the same. In this case, it is understood that a plurality of columns of bit lines corresponds to one column of plate lines.

Thus, the number of the plate wires can be reduced, which is beneficial to improving the effective storage area.

Optionally, the second terminal of the first transistor of each memory cell in a kth column of memory cells in the memory array shares a strip line of the multiple strip lines with the second terminal of the first transistor of each memory cell in a jth column of memory cells, k being a positive integer, j being unequal to k.

That is, the first transistor in the k-th column memory cell and the first transistor in the j-th column memory cell are connected to the same plate line.

Illustratively, J is equal to 2 ^t K, t is a positive integer, every 2 ^t The first transistors of the column of memory cells share a strip line. For example, t is 1, i.e., the first transistors of each two columns of memory cells share a strip line. The bit lines connected to the first ferroelectric capacitors of every two columns of memory cells may be two bit lines. In this case, one slat line corresponds to two bit lines. For another example, t is 2, i.e., the first transistors of every 4 columns of memory cells share a strip line. The bit lines to which the first ferroelectric capacitors of every 4 columns of memory cells are connected may be 4 bit lines. In this case, one slat line corresponds to 4 bit lines. It should be understood that the foregoing is only exemplary, and is not intended to limit the scope of the embodiments of the present application.

Optionally, the gate terminal of the first transistor of the partial memory cells in the first partial memory cell is connected to one of the plurality of plate lines, and the partial memory cells are symmetrically distributed with the plate line as an axis.

Illustratively, a first transistor in a plurality of columns of memory cells in the memory array is connected to a strip line. The plurality of rows of memory cells may be symmetrically distributed about the plate line. That is, a plurality of rows of memory cells sharing a plate line may be symmetrically distributed about the plate line.

For example, J is equal to 2 ^t K, t is a positive integer, every 2 ^t The row memory units are symmetrically distributed by taking a shared slat line as an axis.

Taking t as 1 as an example, every two rows of memory cells are symmetrically distributed by taking a shared slat line as an axis.

For example, the jth column of memory cells and the kth column of memory cells are symmetrically distributed about a shared plate line.

As shown in fig. 6, the memory array 600 includes 4×4 16 memory cells, 4 word lines, 4 bit lines, and 2 strip lines. The 4 word lines are WL0, WL1, WL2 and WL3, respectively. The 4 bit lines are BL0, BL1, BL2 and BL3, respectively. The 2 slat lines are PL0 and PL1, respectively. The word lines are transverse wires, the bit lines are longitudinal wires, and the plate lines are longitudinal wires. The same row of memory cells is connected to the same word line, the same column of memory cells is connected to the same bit line, and every two columns of memory cells are connected to the same strip line. The plate lines connected with the memory cells in every two columns are the same, the bit lines connected with the memory cells in different columns are different, and the word lines connected with the memory cells in different rows are different. Specifically, in fig. 6, the first to fourth rows of memory cells are connected to WL0, WL1, WL2 and WL3, respectively, the first to fourth columns of memory cells are connected to BL0, BL1, BL2 and BL3, respectively, the first and second columns of memory cells are connected to the plate line PL0, and the third and fourth columns of memory cells are connected to the plate line PL1. I.e. BL0 and BL1 correspond to PL0, BL2 and BL3 correspond to PL1. The first column of memory cells and the second column of memory cells are symmetrically distributed by taking PL0 as an axis, and the third column of memory cells and the fourth column of memory cells are symmetrically distributed by taking PL1 as an axis.

The difference between fig. 5 and fig. 6 is that each two columns of memory cells in fig. 6 share a strip line, and each column of memory cells in fig. 5 is connected to a different strip line, and other descriptions of fig. 6 may refer to the related descriptions of fig. 5, which are not repeated here.

It should be understood that the memory array shown in fig. 6 is only a schematic diagram of a memory array provided by an embodiment of the present application, and the number of devices shown in the drawing is not limited to the solution of the embodiment of the present application, for example, the memory array in fig. 6 includes 4×4 16 memory cells, and in practical applications, the memory array may include memory cells of other sizes, and the number of word lines, bit lines and plate lines may be adjusted according to the size of the memory cells, which is not limited by the embodiment of the present application.

As shown in fig. 7, the memory array 700 includes 16N memory cells of 4×4N, 4 word lines, 4N bit lines, and 2 strip lines. N is an integer greater than 1. The 4 word lines are WL0, WL1, WL2 and WL3, respectively. The 4N bit lines are BL0 through BL4N-1, respectively. The 2 slat lines are PL0 and PL1, respectively. The word lines are transverse wires, the bit lines are longitudinal wires, and the plate lines are longitudinal wires. N is a positive integer.

In the memory array 700 shown in fig. 7, the same row of memory cells is connected to the same word line, the same column of memory cells is connected to the same bit line, and each 2N bit lines corresponds to 1 lath line, or each 2N columns of memory cells share 1 lath line. The 2N columns of memory cells sharing the plate line are symmetrically distributed. Specifically, the 1 st to 2 nd columns of memory cells share the plate line PL0, and the 2N columns of memory cells are axisymmetrically distributed with the plate line PL0 as an axis. The 2n+1st column to 4 th column of memory cells share the plate line PL1, and the 2N columns of memory cells are axisymmetrically distributed with the plate line PL1 as an axis.

It should be understood that the memory array shown in fig. 7 is only a schematic diagram of a memory array provided by an embodiment of the present application, and the number of devices shown in the drawing is not limited to the solution of the embodiment of the present application, for example, the memory array in fig. 7 includes 16N memory cells of 4×4n, in practical applications, the memory array may include memory cells of other sizes, and the number of word lines, bit lines and plate lines may be adjusted according to the size of the memory cells, which is not limited by the embodiment of the present application.

The writing process of the memory cell in the embodiment of the application is similar to that of a conventional memory cell. Illustratively, in the case where the memory cells in the memory array of the embodiment of the present application include one transistor and one ferroelectric capacitor, the information writing process is similar to that of the memory cells of the 1T1C structure. For ease of understanding and description, the writing process of information will be exemplarily described below taking a memory cell including one transistor and one ferroelectric capacitor as an example.

When the information "1" needs to be written into the first to-be-written unit, the word line connected with the first to-be-written unit is connected with high potential, namely the gate terminal of the transistor in the first to-be-written unit is connected with high potential, and the transistor in the first to-be-written unit is conducted. The bit line connected with the first unit to be written is connected with high potential, the plate line connected with the first unit to be written is connected with low potential, the ferroelectric capacitor in the first unit to be written is polarized in the forward direction, and information '1' is written into the first unit to be written. The bit lines connected to other memory cells sharing a word line with the first to-be-written cell may be connected to a low potential, and the plate lines connected to other memory cells may be connected to a low potential.

In the embodiment of the present application, the high potential to which the word line is connected is understood as the potential that makes the transistor conductive. The low potential to which the word line is connected can be understood as the potential that turns off the transistor. In one possible implementation, the high and low potentials to which the bit line and the plate line are connected are relative concepts, e.g., the potential on the bit line is higher than the potential on the plate line, i.e., the bit line is considered to be connected high and the plate line is connected low. In another possible implementation, the high and low voltages on the signal lines may be set values. For example, the high potential connected to the bit line and the plate line may be the power supply voltage VDD, and the low potential connected to the bit line or the plate line may be 0V.

It should be noted that, in the embodiment of the present application, the first unit to be written may include one memory cell, or may include a plurality of memory cells, which is not limited in the embodiment of the present application. The "first" of the "first to-be-written units" is only used for limiting that the to-be-written unit currently needs to be written with the information "1", and has no other limiting effect. In other words, the memory cell currently required to be written with the information "1" may be referred to as a "first to-be-written cell".

When the information '0' needs to be written into the second unit to be written, the word line connected with the second unit to be written is connected with high potential, namely the gate of the transistor in the second unit to be written is connected with high potential, and the transistor in the second unit to be written is conducted. The bit line connected with the second unit to be written is connected with low potential, the plate line connected with the second unit to be written is connected with high potential, the ferroelectric capacitor in the second unit to be written is polarized reversely, and information '0' is written into the second unit to be written. In addition, under the condition that the word line connected with the second unit to be written is connected with high potential, the transistors in other memory units sharing the same word line with the second unit to be written are conducted, and the ferroelectric capacitors of the other memory units bear the potentials on the corresponding bit line and the corresponding plate line. If the second cell to be written shares the same plate line with part of the memory cells in other memory cells sharing the same word line, the bit line connected with the memory cells sharing the same plate line is connected with high potential. This can prevent the information of the memory cell that has stored the information "1" from being rewritten to the information "0". The memory cells sharing the same word line as the second cell to be written, and not sharing the same plate line, the connected bit line may be connected to a low potential, and the connected plate line may be connected to a low potential.

It should be noted that, in the embodiment of the present application, the second unit to be written may include one memory unit, or may include a plurality of memory units, which is not limited in the embodiment of the present application. The "second" of the "second to-be-written units" is only used for limiting that the to-be-written unit currently needs to be written with the information "0", and has no other limiting effect. In other words, the memory cell currently required to be written with the information "0" may be referred to as "second to-be-written cell". The second unit to be written may be the same as or different from the first unit to be written.

In the embodiment of the application, the information is written into the memory cell, namely, the information is written into the ferroelectric capacitor of the memory cell. The information stored in the memory cell is the information stored in the ferroelectric capacitor of the memory cell.

Fig. 8 shows a schematic diagram of a write operation. The write operation of the memory array in the embodiment of the present application is described below with reference to fig. 8.

For example, as shown in fig. 8 (a), it is necessary to write information "1" to the first memory cell and the second memory cell of the second row. The first memory cell and the second memory cell in the second row are the first to-be-written cell. The word line WL1 to which the memory cells of the second row are connected is connected to VDD, and the transistors in the memory cells of the second row are turned on. The bit line BL0 connected to the 1 st memory cell of the 2 nd row is connected to VDD, and the bit line BL1 connected to the second memory cell of the second row is connected to VDD. The first memory cell and the second memory cell of the second row share the same slat line PL0, PL0 being connected to 0V. The ferroelectric capacitors in the two memory cells are positively polarized. Information "1" is written in the first memory cell and the second memory cell of the second row. The second row has the bit lines connected, BL2 and BL3, to 0V, and the plate line connected, PL1, to 0V, except for the first and second memory cells. As another example, as shown in fig. 8 (b), information "0" is written to the second memory cell in the second row. The word line WL1 to which the memory cells of the second row are connected is connected to VDD, and the transistors in the memory cells of the second row are turned on. The bit line BL1 connected to the second memory cell of the second row is connected to 0V. The plate line PL0 to which the second memory cell of the second row is connected to VDD, and the ferroelectric capacitor in the memory cell is reversely polarized, and information "0" is written into the second memory cell of the second row. The second row first memory cell and the second row second memory cell share the plate line PL0. In order to avoid that the information "1" stored in the first memory cell of the second row is rewritten, the bit line BL0 connected to the first memory cell of the second row is connected to VDD. The second row has the bit lines connected, BL2 and BL3, to 0V, and the plate line connected, PL1, to 0V, except for the first and second memory cells.

It should be understood that the write operation of fig. 8 is only illustrated by way of example of the memory array shown in fig. 6, and is not limited to the scheme of the embodiment of the present application.

The memory array further includes at least one sense amplifier. The at least one sense amplifier is used to determine information stored in the cell to be read during reading of the information.

Specifically, the SA is configured to read an electrical signal on a bit line connected to a cell to be read, and determine information stored in the cell to be read according to the electrical signal.

For example, the electrical signal may be a voltage signal.

The unit to be read may include one memory unit or may include a plurality of memory units, which is not limited in the embodiment of the present application.

Optionally, a plurality of sense amplifiers are in one-to-one correspondence with the plurality of bit lines, and the plurality of sense amplifiers are respectively connected to the corresponding bit lines. In this case, the number of sense amplifiers is the same as the number of bit lines.

In practical circuit designs, the width of the SA is greater than the width of the memory cell. The manner in which each BL corresponds to one SA affects the effective memory area in the memory array. In the embodiment of the present application, a plurality of BLs may correspond to one SA.

Optionally, the memory array further comprises at least one sense amplifier, the plurality of bit lines being connected to the at least one sense amplifier through a multiplexer.

Specifically, the at least one sense amplifier is respectively connected to the output terminals of the at least one multiplexer, and the plurality of bit lines are respectively connected to the input terminals of the at least one multiplexer. The number of the at least one sense amplifier is greater than or equal to the number of columns of memory cells to which the at least one slat line is connected. During the reading process, the connection relationship between the at least one sense amplifier and the plurality of bit lines is controlled by the at least one multiplexer.

The Multiplexer (MUX) may be referred to as a data selector.

For example, the number of SAs may be equal to the number of columns in which cells to be read are located during reading. The cell to be read may include an intersection of a memory cell connected to a plate line to which a high potential pulse is applied and a memory cell connected to a word line connected to a high potential.

The reading process of the memory cell in the embodiment of the application is similar to that of a conventional memory cell. Illustratively, in the case where the memory cells in the memory array of the embodiment of the present application include one transistor and one ferroelectric capacitor, the information reading process is similar to that of the memory cells of the 1T1C structure. For ease of understanding and description, the reading process of information will be exemplarily described below taking a memory cell including one transistor and one ferroelectric capacitor as an example.

When information is required to be read from the unit to be read, the bit line connected with the unit to be read is connected with 0V for pre-discharging, and then the word line connected with the unit to be read is connected with high potential, namely the gate of the transistor in the unit to be read is connected with high potential, and the transistor in the unit to be read is conducted. A high potential pulse is applied to the plate line to which the cell to be read is connected. The sense amplifier may determine the information stored in the cell to be read based on the voltage on the bit line to which the cell to be read is connected.

The following is an exemplary description of the cell to be read comprising a memory cell. If the information stored in the cell to be read is "0", the polarization direction of the ferroelectric capacitor in the cell to be read is not changed when the information is read, and the charge Q0 is released. The released charge Q0 is distributed over the ferroelectric capacitor of the cell to be read and the bit line to which the cell to be read is connected, and the voltage of the bit line is raised. At this time, the voltage of the bit line connected to the cell to be read is V0. If the information stored in the cell to be read is "1", the polarization direction of the ferroelectric capacitor in the cell to be read is changed by an external electric field, from forward polarization to reverse polarization, releasing the charge Q1, and the voltage on the bit line increases. At this time, the voltage of the bit line connected to the cell to be read is V1. The released charge Q1 contains polarization inversion charge, Q1 > Q0, and correspondingly V1 > V0. The SA connected with the bit line detects the voltage of the bit line, compares the voltage of the bit line with the reference potential Vref, and can determine whether the information stored in the unit to be read is 0 or 1 according to the comparison result. For example, if the voltage of the bit line connected to the unit to be read exceeds Vref, the information stored in the unit to be read is information "1"; if the voltage of the bit line connected with the unit to be read does not exceed Vref, the information stored in the unit to be read is information '0'.

The bit lines connected to other memory cells outside the cell to be read may be connected to a low potential, and the plate lines connected to other memory cells outside the cell to be read may be connected to a low potential. After the reading is finished, the original information is written back to the unit to be read. The ferroelectric capacitor does not need to bear the high voltage on the plate line because the transistor is not conducted in other memory cells sharing the plate line with the cell to be read. By adopting the scheme of the embodiment of the application, only the ferroelectric capacitors in the unit to be read need to bear the high voltage in the reading and writing back processes, and the ferroelectric capacitors in other memory units do not need to experience unnecessary high voltage.

The read operation of the memory array in the embodiment of the present application is described below with reference to fig. 9.

For example, as shown in fig. 9 (a), 4 bit lines may be connected to 4 SAs, respectively, and fig. 9 (a) does not show all SAs. When information is required to be stored in the first storage unit and the second storage unit of the second row, the first storage unit and the second storage unit of the second row are the units to be read. The bit line BL0 connected to the first memory cell of the second row is precharged to 0V, and the bit line BL1 connected to the second memory cell of the second row is precharged to 0V. The word line WL1 to which the memory cells of the second row are connected is connected to VDD, and the transistors in the memory cells of the second row are turned on. The first memory cell and the second memory cell of the second row share the same plate line PL0, and PL0 is pulsed high. The SA connected to BL0 compares the detected voltage V1 at BL0 with a reference voltage and determines that the information stored in the first memory cell of the second row is information "1". The SA connected to BL1 compares the detected voltage V0 at BL1 with a reference voltage and determines that the information stored in the second memory cell of the second row is "0". During the reading process, the first memory cell and the second memory cell in the second row are read, and only the ferroelectric capacitors in the first memory cell and the second memory cell in the second row need to bear the high voltage on the plate line during the reading process. The ferroelectric capacitors in the other memory cells do not need to experience unnecessarily high voltages.

As another example, as shown in fig. 9 (b), 4 bit lines are connected to 2 SAs through multiplexers. When the information stored in the first memory cell and the second memory cell of the second row needs to be read, BL0 is connected with one SA through a multiplexer, and BL1 is connected with the other SA. The specific reading process is the same as that of fig. 9 (a), and will not be described here again.

It should be understood that the foregoing description is only given by taking as an example that one memory cell includes one transistor and one ferroelectric capacitor, and is not limited to the scheme of the embodiment of the present application. For example, one memory cell may further include two transistors and two ferroelectric capacitors. For another example, a memory cell may include two transistors and a ferroelectric capacitor.

An example in which one memory cell includes two transistors and two ferroelectric capacitors is described below.

One memory cell includes a first transistor, a second transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor.

The gate terminal of the second transistor of each of the first portion of memory cells is connected to one of the plurality of word lines, and the first portion of memory cells includes a plurality of memory cells in a same row in the memory array.

The first end of the second ferroelectric capacitor of each memory cell in the second part of memory cells is connected with one bit line in a plurality of bit lines, and the second part of memory cells comprises a plurality of memory cells in the same column in the memory array.

The second terminal of the second ferroelectric capacitor of each of the second portion of memory cells is connected to one of the plurality of lath lines through a second transistor.

A memory cell is connected to at least four signal lines, namely at least one word line, at least one strip line, and two bit lines. The gate terminal of the first transistor and the gate terminal of the second transistor may be connected to the same word line or may be connected to different word lines. The first end of the first ferroelectric capacitor is connected with one bit line, and the first end of the second ferroelectric capacitor is connected with the other bit line. The second end of the first ferroelectric capacitor is connected with one slat line through the first transistor, and the second end of the second ferroelectric capacitor is connected with the same slat line through the second transistor, or can be connected with different slat lines.

For example, the word lines connected to the gate terminals of the first transistors of all memory cells in the same row in the memory array may be identical. The word lines to which the gate terminals of the second transistors of all memory cells in the same row are connected may be identical. The bit lines to which the first terminals of the first ferroelectric capacitors of all memory cells in the same column are connected may be identical. The bit lines to which the first terminals of the second ferroelectric capacitors of all memory cells in the same column are connected may be identical. The plate line to which the first ferroelectric capacitors of all memory cells in the same column are connected through the first transistor may be the same. The plate lines to which the second ferroelectric capacitors of all memory cells in the same column are connected through the first transistors may be identical.

In one possible implementation, the plate line to which the first transistor in each of the first portion of memory cells is connected is different. The plate lines to which the second transistors in each of the memory cells in the first portion are connected are different.

That is, the first transistors sharing the same word line are connected to different plate lines, respectively. The second transistors sharing the same word line are connected to different plate lines, respectively.

Illustratively, the word lines to which each row of memory cells in the memory array are connected are different. The bit lines to which each column of memory cells are connected are different. The plate lines to which the memory cells of each column are connected are different.

Specifically, the second end of the first ferroelectric capacitor in each column of memory cells in the memory array is connected to the plate line corresponding to the first ferroelectric capacitor in each column of memory cells through the first transistor in each column of memory cells. The plate lines corresponding to the first ferroelectric capacitors in each column of memory cells are different. The second end of the second ferroelectric capacitor in each column of memory cells in the memory array is connected with the corresponding plate line of the second ferroelectric capacitor in each column of memory cells through the second transistor in each column of memory cells. The plate lines corresponding to the second ferroelectric capacitors in each column of memory cells are different.

Alternatively, the plate line to which the first transistor in each column of memory cells in the memory array is connected is different. The plate lines to which the second transistors in each column of memory cells in the memory array are connected are different.

Fig. 10 shows a schematic block diagram of a memory array 1000 according to an embodiment of the present application. As shown in fig. 10, the memory array 1000 includes 4×4 16 memory cells, 4 word lines, 8 bit lines, and 4 strip lines. The 4 word lines are WL0, WL1, WL2 and WL3, respectively. The 8 bit lines are BL0, BL0', BL1', BL2', BL3 and BL3', respectively. The 4 slat lines are PL0, PL1, PL2 and PL3, respectively. The word lines are transverse wires, the bit lines are longitudinal wires, and the plate lines are longitudinal wires. In the memory array shown in fig. 10, one memory cell includes two transistors (i.e., a first transistor and a second transistor) and two ferroelectric capacitors (i.e., a first ferroelectric capacitor and a second ferroelectric capacitor).

In the memory array shown in fig. 10, the word lines connected to the gate terminals of the transistors in the same row of memory cells are the same word line, i.e., the same row of memory cells are connected to the same word line. The source terminals of the transistors in the same row of memory cells are connected to the same plate line, i.e. the same row of memory cells are connected to the same plate line. The bit lines connected with the first ferroelectric capacitors in the same column of memory cells are the same bit lines, and the bit lines connected with the second ferroelectric capacitors in the same column of memory cells are the same bit lines. The plate lines connected with the memory cells of different columns are different, the bit lines connected with the memory cells of different columns are different, and the word lines connected with the memory cells of different rows are different.

It should be understood that the memory array shown in fig. 10 is only a schematic diagram of a memory array provided by an embodiment of the present application, and the number of devices shown in the drawing is not limited to the solution of the embodiment of the present application, for example, the memory array in fig. 10 includes 4×4 memory cells, and in practical applications, the memory array may include memory cells of other scales, and the number of word lines, bit lines, and plate lines may be adjusted according to the scale of the memory cells, which is not limited by the embodiment of the present application.

In another possible implementation, the plate lines to which the first transistors of the partial memory cells in the first partial memory cells are connected are the same. The plate lines to which the second transistors of the partial memory cells in the first partial memory cells are connected are the same.

That is, some of the first transistors sharing the same word line are connected to the same plate line. Some of the second transistors sharing the same word line are connected to the same plate line.

Illustratively, the word lines to which each row of memory cells in the memory array are connected are different. The bit lines to which each column of memory cells are connected are different. The plate lines to which the memory cells of different columns are connected may be identical.

Specifically, the second ends of the first ferroelectric capacitors in the memory cells in the plurality of columns of the memory array are respectively connected with a strip line through the first transistors in the plurality of columns of the memory cells. The second ends of the second ferroelectric capacitors in the memory cells of the plurality of columns of the memory array are respectively connected with a strip line through the second transistors in the memory cells of the plurality of columns.

Alternatively, the plate lines to which the first transistors in the plurality of columns of memory cells are connected are the same. The plate lines to which the second transistors in the multi-column memory cells are connected are the same. The number of columns of memory cells in the plurality of columns is less than the number of columns of memory cells in the memory array.

As shown in fig. 11, the memory array 1100 includes 4×4 16 memory cells, 4 word lines, 4 bit lines, and 2 stripe lines. The 4 word lines are WL0, WL1, WL2 and WL3, respectively. The 8 bit lines are BL0, BL0', BL1', BL2', BL3 and BL3', respectively. The 2 slat lines are PL0 and PL1, respectively. The word lines are transverse wires, the bit lines are longitudinal wires, and the plate lines are longitudinal wires. The memory cells in the same row are connected with the same word line, the first ferroelectric capacitors in the memory cells in the same column are connected with the same bit line, the second ferroelectric capacitors in the memory cells in the same column are connected with the same bit line, and every two memory cells in the same column are connected with the same slat line. The plate lines connected with the memory cells in every two columns are the same, the bit lines connected with the memory cells in different columns are different, and the word lines connected with the memory cells in different rows are different. Specifically, in fig. 11, the first to fourth rows of memory cells are connected to WL0, WL1, WL2, and WL3, respectively. The first ferroelectric capacitors in the first to fourth columns of memory cells are connected to BL0, BL1, BL2 and BL3, respectively, and the second ferroelectric capacitors in the first to fourth columns of memory cells are connected to BL0', BL1', BL2 'and BL3', respectively. The first and second columns of memory cells are connected to plate line PL0, and the third and fourth columns of memory cells are connected to plate line PL1. The first column of memory cells and the second column of memory cells are symmetrically distributed by taking PL0 as an axis, and the third column of memory cells and the fourth column of memory cells are symmetrically distributed by taking PL1 as an axis.

The difference between fig. 10 and fig. 11 is that each two columns of memory cells in fig. 11 share a strip line, and each column of memory cells in fig. 10 is connected to a different strip line, and other descriptions of fig. 11 may refer to the related descriptions of fig. 10, which are not repeated here.

It should be understood that the memory array shown in fig. 11 is only a schematic diagram of a memory array provided by an embodiment of the present application, and the number of devices shown in the drawing is not limited to the solution of the embodiment of the present application, for example, the memory array in fig. 11 includes 4×4 16 memory cells, and in practical applications, the memory array may include memory cells of other sizes, and the number of word lines, bit lines and plate lines may be adjusted according to the size of the memory cells, which is not limited by the embodiment of the present application. In fig. 11, each two rows of memory cells share a strip line, and in practical applications, more rows of memory cells may share a strip line.

In the case where the memory cells in the memory array of the embodiment of the present application include two transistors and two ferroelectric capacitors, the information writing and reading process is similar to that of the memory cells of the 2T2C structure. In order to avoid repetition, a description thereof is omitted.

According to the scheme of the embodiment of the application, the extending direction of the plate line and the extending direction of the word line are mutually perpendicular, the memory cells sharing the plate line and the memory cells sharing the word line are not completely identical, the structure can only read information of the memory cells needing to read information, but not need to read the whole row of memory cells, the ferroelectric capacitors of the memory cells needing to read information only bear high voltage in the process of reading information, the ferroelectric capacitors of other memory cells do not bear high voltage, the situation that the whole row of memory cells need to bear high voltage in the process of reading is avoided, the times that the ferroelectric capacitors bear high voltage are reduced, and the service life of the memory array is facilitated to be ensured. Specifically, the word line connected to the memory cell to be read is connected to a high potential, the transistor in the memory cell to be read is turned on, the plate line connected to the memory cell to be read may be connected to a high voltage pulse, the word line connected to other memory cells sharing the plate line with the memory cell to be read is not connected to a high potential, that is, the transistor in the other memory cells is not turned on, and the ferroelectric capacitor in the other memory cells does not bear the high voltage on the plate line. Therefore, the situation that the whole row of memory cells need to bear high voltage in the reading process is avoided, the times that the ferroelectric capacitor bears high voltage are reduced, and the service life of the memory array is guaranteed.

In addition, in the embodiment of the application, a plurality of rows of storage units can share one plate line, so that the number of the plate lines is further reduced, the effective storage area can be further increased, and the storage density is improved.

It should be noted that the memory arrays in fig. 5-11 are only examples, and those skilled in the art will appreciate that the memory arrays in fig. 5-11 may also include other devices necessary to achieve proper operation during the implementation. Also, as will be appreciated by those skilled in the art, the memory arrays of FIGS. 5-11 may also include hardware devices that perform other additional functions, as desired.

Fig. 12 illustrates a method for operating a memory array according to an embodiment of the present application, where the method 1200 may be applied to a memory array in the foregoing, for example, the memory arrays in fig. 5 to 11, and the detailed description may refer to the foregoing description, and in order to avoid repetition, a part of the description is omitted when describing the method 1200.

The memory array comprises a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction and a plurality of strip lines extending along the column direction, wherein each memory cell in the plurality of memory cells comprises a first transistor and a first ferroelectric capacitor, a first end of the first transistor is connected with a second end of the first ferroelectric capacitor, a gate end of the first transistor of each memory cell in an ith row of the plurality of memory cells is connected with an ith word line in the plurality of word lines, i is a positive integer, a first end of the first ferroelectric capacitor of each memory cell in a jth column of the plurality of memory cells is connected with a jth bit line in the plurality of bit lines, j is a positive integer, a second end of the first transistor of each memory cell in the jth column of the plurality of memory cells is a source end, a second end of the first transistor is a drain end, or a first end of the first transistor is a drain end, and a second end of the first transistor is a source end of the first transistor is a drain end.

Method 1200 includes steps 1210 through 1220.

1210, a first voltage signal is applied to the ith word line to turn on a first transistor of each memory cell in the ith row of memory cells.

1220, applying a second voltage signal to one of the plurality of plate lines, and applying a third voltage signal to a bit line to which the target memory cell is connected, to read information stored in the target memory cell, the second voltage signal having a higher potential than the third voltage signal, the target memory cell being a memory cell in an intersection of a memory cell connected to the one of the plurality of plate lines and the i-th row of memory cells.

The target storage unit may be, for example, a unit to be read in the foregoing.

The first voltage signal may be understood as a voltage signal that renders the first transistor conductive. For example, the first voltage signal may be a high voltage signal to which the word line is connected in the foregoing.

The second voltage signal and the third voltage signal are voltage signals for reading the stored information. For example, the second voltage signal may be a high potential pulse signal connected to the plate line. The third voltage signal may be a low voltage signal connected to the bit line.

Optionally, the second terminal of the first transistor of each memory cell in the j-th column of memory cells is connected to a j-th strip line of the plurality of strip lines, the method comprising: a second voltage signal is applied to the j-th slat line to read information stored in a target memory cell, which is a memory cell in an intersection with the j-th column of memory cells and the i-th row of memory cells.

Optionally, the second terminal of the first transistor of each memory cell in a kth column of the plurality of memory cells shares a slat line of the plurality of slat lines with the second terminal of the first transistor of each memory cell in a jth column of memory cells, k being a positive integer, j being unequal to k, the method comprising: a second voltage signal is applied to one of the shared multi-strip lines to read information stored in a target memory cell that is a memory cell in an intersection with a j-th column of memory cells, a k-th column of memory cells, and an i-th row of memory cells.

Optionally, the j-th row of memory cells and the k-th row of memory cells are symmetrically distributed with respect to one of the plurality of shared slat lines.

Optionally, a plurality of bit lines are respectively connected to the plurality of amplifiers.

Optionally, the plurality of bit lines are connected to at least one amplifier through a multiplexer, the number of at least one amplifier being greater than or equal to the number of columns of memory cells to which at least one of the plurality of bit lines is connected.

Specific examples of the method 1200 may be referred to in connection with the description of fig. 9, and are not described in detail herein.

The embodiment of the application also provides a memory, which comprises the memory array and the memory controller, wherein the memory controller is electrically connected with the memory array. For example, the memory array may be any of the memory arrays of fig. 5-11.

The embodiment of the application also provides electronic equipment, which comprises the memory and the circuit board, wherein the memory is arranged on the circuit board and is electrically connected with the circuit board.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural. In addition, the character "/" herein generally indicates that the associated object is an "or" relationship, but may also indicate an "and/or" relationship, and may be understood by referring to the context.

In the present application, "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

In the embodiment of the application, prefix words such as "first" and "second" are adopted, and only for distinguishing different description objects, no limitation is imposed on the position, sequence, priority, quantity or content of the described objects.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory array, comprising: a plurality of memory cells, a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction, and a plurality of strip lines extending in a column direction, each memory cell of the plurality of memory cells comprising a first transistor and a first ferroelectric capacitor, a first terminal of the first transistor being connected to a second terminal of the first ferroelectric capacitor, wherein,

The gate terminal of the first transistor of each memory cell in the ith row of memory cells in the plurality of memory cells is connected to the ith word line in the plurality of word lines, i is a positive integer,

the first end of the first ferroelectric capacitor of each memory cell in the j-th column of memory cells is connected with the j-th bit line of the plurality of bit lines, j is a positive integer,

the second end of the first transistor of each memory cell in the j-th column of memory cells is connected with one of the multi-strip-line, the first end of the first transistor is a source end, the second end of the first transistor is a drain end, or the first end of the first transistor is a drain end, and the second end of the first transistor is a source end.

2. The memory array of claim 1, wherein the second terminal of the first transistor of each memory cell in the j-th column of memory cells is connected to a j-th one of the plurality of lath lines.

3. The memory array of claim 1, wherein the second terminal of the first transistor of each of the k-th column of memory cells shares a strip line of the plurality of strip lines with the second terminal of the first transistor of each of the j-th column of memory cells, k being a positive integer, j being not equal to k.

4. The memory array of claim 3 wherein the j-th column of memory cells and the k-th column of memory cells are symmetrically distributed about one of the shared multi-lath lines.

5. The memory array of any one of claims 1 to 4, wherein the plurality of bit lines are respectively connected to a plurality of amplifiers.

6. The memory array of any one of claims 1 to 4, wherein the plurality of bit lines are connected to at least one amplifier through a multiplexer, the at least one amplifier being greater than or equal to a number of columns of memory cells to which at least one of the plurality of slat lines is connected.

7. A memory comprising the memory array of any one of claims 1 to 6 and a memory controller, the memory controller and the memory array being electrically connected.

8. An electronic device comprising the memory of claim 7 and a circuit board, the memory disposed on and electrically connected to the circuit board.

9. The working method of the memory array is characterized in that the memory array comprises a plurality of memory cells, a plurality of word lines extending along a row direction, a plurality of bit lines extending along a column direction and a plurality of strip lines extending along the column direction, each memory cell in the plurality of memory cells comprises a first transistor and a first ferroelectric capacitor, a first end of the first transistor is connected with a second end of the first ferroelectric capacitor, a gate end of the first transistor of each memory cell in an ith row of the plurality of memory cells is connected with an ith word line in the plurality of word lines, i is a positive integer, a first end of the first ferroelectric capacitor of each memory cell in a jth column of the plurality of memory cells is connected with a jth bit line in the plurality of bit lines, j is a positive integer, a second end of the first transistor of each memory cell in the jth column of the memory cells is connected with a second end of the first ferroelectric capacitor, a first end of the first transistor is a source end of the first transistor, a second end of the first transistor is a drain end of the first transistor, and a drain end of the first transistor is a drain end of the first transistor, and a drain end of the first transistor is a drain end of the first transistor is a drain end of the first source.

Applying a first voltage signal on the i-th word line to turn on a first transistor of each memory cell in the i-th row of memory cells;

and applying a second voltage signal to one of the plurality of slat lines, and applying a third voltage signal to a bit line connected to a target memory cell to read information stored in the target memory cell, wherein the second voltage signal has a higher potential than the third voltage signal, and the target memory cell is a memory cell in an intersection of a memory cell connected to one of the plurality of slat lines and an i-th row of memory cells.

10. The method of claim 9, wherein the second end of the first transistor of each memory cell in the j-th column of memory cells is connected to a j-th slat line of the plurality of slat lines, the method comprising:

and applying a second voltage signal on the jth slat line to read information stored in a target memory cell, wherein the target memory cell is a memory cell in an intersection with a jth column of memory cells and the ith row of memory cells.

11. The method of claim 9, wherein the second terminal of the first transistor of each of the kth column of memory cells shares a strip line of the plurality of strip lines with the second terminal of the first transistor of each of the jth column of memory cells, k being a positive integer, j being unequal to k, the method comprising:

Applying a second voltage signal on one of the plurality of shared slat lines to read information stored in a target memory cell that is a memory cell in an intersection with a jth column of memory cells, a kth column of memory cells, and the ith row of memory cells.

12. The method of claim 11, wherein the j-th column of memory cells and the k-th column of memory cells are symmetrically distributed about one of the shared multi-lath lines.

13. The method according to any one of claims 9 to 12, wherein the plurality of bit lines are respectively connected to a plurality of amplifiers.

14. The method of any one of claims 9 to 12, wherein the plurality of bit lines are connected to at least one amplifier through a multiplexer, the at least one amplifier being greater than or equal to a number of columns of memory cells to which at least one of the plurality of bit lines is connected.