WO2023217261A1

WO2023217261A1 - Display panel and display device

Info

Publication number: WO2023217261A1
Application number: PCT/CN2023/093801
Authority: WO
Inventors: 台玉可; 王世君; 王继国; 王洋; 刘屹; 杨心澜; 魏旃; 丁腾飞; 吕广爽; 陈公达; 齐胜美; 梁海瑶; 彭洲; 张盛丰
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2022-05-12
Filing date: 2023-05-12
Publication date: 2023-11-16
Also published as: CN115206253A

Abstract

A display substrate and a display device. The display substrate comprises a plurality of sub-pixels arranged in M rows and N groups; each group of sub-pixels comprise two columns of sub-pixels; M pairs of gate lines are in one-to-one correspondence with the M rows of sub-pixels; each of N data lines (141) corresponds to two adjacent groups of sub-pixels; two adjacent groups of sub-pixels corresponding to a same data line (141) are respectively a first group of sub-pixels (31) and a second group of sub-pixels (32); pixel electrodes (142) of an odd-numbered row of sub-pixels in the first group of sub-pixels (31) and pixel electrodes (142) of an even-numbered row of sub-pixels in the second group of sub-pixels (32) are connected to corresponding data lines (141). The display substrate further comprises a common electrode layer (16) and a plurality of first compensation wires (171a); the plurality of first compensation wires (171a) correspond to one row of sub-pixels; the first compensation wires (171a) are located between two adjacent data lines (141) and located between two adjacent columns of sub-pixels in a corresponding row of sub-pixels; the first compensation wires (171a) are connected to the common electrode layer (16) by means of first via holes (41).

Description

Display panels and display devices

This application claims priority to the Chinese patent application submitted to the China Patent Office on May 12, 2022, with the application number 202210519210.6 and the invention title "A display substrate and display device". Its content should be understood as being incorporated by reference. into this application.

Technical field

Embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular, to a display substrate and a display device.

Background technique

Liquid crystal display devices (LCDs) are widely used in modern information equipment, such as monitors, televisions, mobile phones, and digital products, due to their advantages of light weight, low power consumption, low radiation, and portability. In order to narrow the frame of the display device and increase the screen-to-body ratio, a dual gate structure is used to drive sub-pixels. In the dual-gate structure, two gate lines are provided in one pixel, each gate line corresponds to a different sub-pixel, and the same data line is used between the two sub-pixels. Such a design can halve the data lines, thus halving the number of data driver chips, achieving cost savings.

In the current dual-gate structure, R, G, and B sub-pixels in the same row are connected to different gate lines. When the power supply conditions in the data lines are different, it will cause display differences between adjacent pixel columns, resulting in vertical lines or shaking heads. bad.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including a substrate and a plurality of sub-pixels located on one side of the substrate and arranged in M rows and N groups. Each group of sub-pixels includes two columns of sub-pixels. The display substrate It also includes M pairs of gate lines, which correspond to M rows of sub-pixels one-to-one. The pair of gate lines include a first gate line and a second gate line extending along the first direction. The first gate line and the second gate line Set separately On opposite sides of the corresponding row of sub-pixels and between two adjacent rows of sub-pixels, the first direction is the direction of the row;

The display substrate also includes N data lines. Each data line corresponds to two adjacent groups of sub-pixels. The adjacent two groups of sub-pixels corresponding to the same data line are respectively the first group of sub-pixels and the second group of sub-pixels. , the pixel electrodes of the odd-numbered rows of sub-pixels in the first group of sub-pixels are connected to the corresponding data lines, and the pixel electrodes of the even-numbered rows of sub-pixels in the second group of sub-pixels are connected to the corresponding data lines;

The display substrate also includes an electrode compensation layer and a common electrode layer disposed on one side of the substrate. A first insulating layer is disposed between the electrode compensation layer and the common electrode layer. The electrode compensation layer includes a plurality of first compensation lines, and a plurality of third compensation lines. A compensation line corresponds to a row of sub-pixels. The first compensation line is located between two adjacent data lines and between two adjacent columns of sub-pixels in the corresponding row of sub-pixels. The first compensation line passes through the first The first via hole of the insulation layer is connected to the common electrode layer.

In some possible implementations, the plurality of first compensation traces are not connected to each other in the electrode compensation layer.

In some possible implementations, the first via hole is located at one end of the first compensation trace, and the orthographic projection of the first via hole on the substrate is located on the substrate of two adjacent gate lines of two adjacent rows of sub-pixels. between the front projections, the first compensation trace includes a first extension section and a second extension section, the first extension section is located between two adjacent sub-pixels, and the second extension section connects the first extension section and the first via hole, There is no overlapping area between the first via hole and the extension line of the first extension section.

In some possible implementations, the display substrate further includes a second via hole penetrating the first insulating layer. The other end of the first compensation trace is connected to the common electrode layer through the second via hole. The second via hole is on the substrate. The orthographic projection is located between the orthographic projections of two adjacent gate lines of two adjacent rows of sub-pixels on the substrate. The first compensation line also includes a third extension section, and the third extension section connects the first extension section and the third extension section. There is no overlapping area between the second via hole and the extension line of the first extension section.

In some possible implementations, the display substrate further includes a preset light-shielding area, and the second extension section is located in the preset light-shielding area.

In some possible implementations, the first compensation trace includes a first extension section, the first extension section is located between two adjacent sub-pixels and extends along the second direction, and the orthographic projection of the first via hole on the substrate is located at Between two adjacent rows of sub-pixels, the orthographic projection of the first via hole on the substrate and the orthographic projection of the first extension section on the substrate at least partially overlap.

In some possible implementations, the first compensation trace also includes a fourth extension section. The fourth extension section is located between two adjacent rows of sub-pixels. The fourth extension section is not parallel to the first extension section. The first via hole The orthographic projection on the substrate at least partially overlaps the orthographic projection of the fourth extension on the substrate.

In some possible implementations, the display substrate further includes a third via hole penetrating the first insulating layer. The third via hole is located at an end of the first extension section away from the first via hole. The third via hole is located on the substrate. The orthographic projection is located between two adjacent sub-pixels and between the orthographic projections of the two gate lines of the corresponding row of sub-pixels on the substrate.

In some possible implementations, the electrode compensation layer and the data line are located on the same layer.

In some possible implementations, it also includes a first conductive layer, a second insulating layer, a second conductive layer, a first insulating layer and a common electrode layer arranged in sequence on one side of the substrate, and the electrode compensation layer and the gate line are located The first conductive layer, the data line is located on the second conductive layer, the first compensation line includes a first extension section, the first extension section is located between two adjacent sub-pixels and extends along the second direction, the first extension section is located in the corresponding row Between the two gate lines of the sub-pixel, the orthographic projection of the first via hole on the substrate is located between two adjacent sub-pixels and between the orthographic projection of the two gate lines of the corresponding row of sub-pixels on the substrate, The number of the first via hole is at least one, the first via hole penetrates the second insulating layer and the first insulating layer, and the first extension section is connected to the common electrode layer through at least one first via hole.

In some possible implementations, the data lines include a first portion of wiring corresponding to odd-numbered rows of sub-pixels and a second portion of wiring corresponding to even-numbered rows, and the first portion of wiring is located in the corresponding first group of sub-pixels. Between two adjacent columns of sub-pixels, the second part of the wiring is located between the two adjacent columns of sub-pixels of the corresponding second group of sub-pixels. The data line also includes a third part of the wiring, and the third part of the wiring is located in two adjacent rows. Between two adjacent gate lines of a sub-pixel, a first portion of wiring and a second portion of wiring corresponding to two adjacent rows of sub-pixels are connected through a third portion of wiring.

In some possible implementations, the data line is located between two adjacent groups of sub-pixels, and the data line extends along a second direction, and the second direction is the direction of the column.

In some possible implementations, each row of sub-pixels is configured as multiple pixel units. The pixel units include sequentially adjacent first color sub-pixels, second color sub-pixels and third color sub-pixels. The sub-pixels in the same row The pixel electrodes of the first color sub-pixels are all connected to the same gate line, the pixel electrodes of the second color sub-pixels in the same row of sub-pixels are all connected to another gate line, and the pixel electrodes of two adjacent pixel units in the same row of sub-pixels are connected to the same gate line. The pixel electrodes of the third color sub-pixels are respectively connected to different gate lines.

In a second aspect, an embodiment of the disclosure provides a display device, including the display substrate in any embodiment of the disclosure.

Other aspects will be apparent after reading and understanding the drawings and detailed description.

Figure overview

In the drawings, unless otherwise specified, the same reference numbers refer to the same or similar parts or elements throughout the several figures. The drawings are not necessarily to scale.

Figure 1 is a schematic diagram of a dual-gate structure used in a display substrate;

Figure 2 is a schematic diagram of a pixel using a double gate structure;

Figure 3 is a schematic diagram of a display substrate using a double-gate structure in an embodiment of the present disclosure;

Figure 4 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in an embodiment of the present disclosure;

Figure 5a is a schematic cross-sectional view of A-A in Figure 4 in one embodiment;

Figure 5b is a schematic cross-sectional view of B-B in Figure 4 in one embodiment;

Figure 6 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure;

Figure 7 is a schematic cross-sectional view of A-A in Figure 6 in one embodiment;

Figure 8 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure;

Figure 9 is a schematic cross-sectional view of A-A in Figure 8 in one embodiment;

Figure 10 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure;

Figure 11 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure;

Figure 12 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure;

Figure 13 is a schematic cross-sectional view along line A-A in Figure 12 .

Elaborate

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will realize, various methods may be used without departing from the spirit or scope of the present disclosure. The described embodiments may be modified according to the formula, and different embodiments may be combined arbitrarily without conflict. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.

Figure 1 is a schematic diagram of a display substrate using a double gate structure, and Figure 2 is a schematic diagram of a pixel using a double gate structure. The double-gate structure shown in Figures 1 and 2 can be called the double-gate structure of the ordinary (Column) architecture. As shown in Figures 1 and 2, in the Column architecture, one row of sub-pixels corresponds to two gate lines, respectively. The gate line 121 and the second gate line 122 each correspond to a different sub-pixel. For example, in FIGS. 1 and 2 , one pixel unit may include a first color sub-pixel R, a second color sub-pixel G, and a third color sub-pixel B. For a pixel unit, the first color sub-pixel R and the third color sub-pixel B correspond to one gate line, and the second color sub-pixel G corresponds to another gate line. The first color sub-pixel R and the second color sub-pixel G use the same data line 141, and the third color sub-pixel B uses the same data line 141 as the first color sub-pixel R in the adjacent pixel unit. Using the Column architecture shown in Figures 1 and 2, the data line 141 can be halved, and the number of data driver chips can be halved, thereby achieving cost savings. However, since the pixel electrodes 142 of the first color sub-pixel R, the second color sub-pixel G, and the third color sub-pixel B in the same row are connected to different gate lines, when the power supply conditions of the data lines 141 are different, adjacent Display differences between pixel columns cause vertical lines or shaking head patterns.

Here, the pixel electrode 142 is connected to the gate line, which should be understood to mean that the pixel electrode 142 is connected to the gate line through a thin film transistor. For example, the gate electrode of the thin film transistor is connected to the gate line, and the first electrode of the thin film transistor is connected to the pixel electrode 142 . The pixel electrode 142 is connected to the data line 141. It should be understood that the pixel electrode 142 is connected to the data line 141 through a thin film transistor. For example, the second electrode of the thin film transistor is connected to the data line 141, and the first electrode of the thin film transistor is connected to the pixel electrode 142. . The first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, the first electrode may be the drain electrode, and the second electrode may be the source electrode.

FIG. 3 is a schematic diagram of a display substrate using a dual-gate structure according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram of a pixel in which the display substrate adopts a double-gate structure in an embodiment of the present disclosure. FIG. 5a is a schematic cross-sectional view of AA in FIG. 4 in one embodiment, and FIG. 5b is a schematic cross-sectional view of BB in FIG. 4 in one embodiment. As shown in Figures 3, 4, and 5a, the display substrate may include a substrate 11 and a plurality of sub-pixels located on the substrate 11. The plurality of sub-pixels are arranged in M rows and N groups, and each group of sub-pixels includes two columns of sub-pixels. You can set the direction of the rows as the first direction X, and the direction of the columns as the second direction Y. M and N are positive integers greater than or equal to 1.

In an exemplary embodiment, the display substrate may further include M pairs of gate lines and N data lines 141, which are located on the same side of the substrate 11 but on different layers. M pairs of gate lines correspond to M rows of sub-pixels one-to-one, and the pair of gate lines may include a first gate line 121 and a second gate line 122 extending along the first direction X. The first gate line 121 and the second gate line 122 are respectively provided on opposite sides of the corresponding row of sub-pixels, and are located between two adjacent rows of sub-pixels, as shown in FIGS. 3 and 4 . In FIGS. 3 and 4 , the gate line located on the upper side of the row sub-pixel may be the first gate line 121 , and the gate line located on the lower side of the row sub-pixel may be the second gate line 122 .

As shown in FIG. 3 , each row of sub-pixels can be configured as multiple pixel units, and one pixel unit includes sequentially adjacent first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels. For example, the first color sub-pixel may be a red sub-pixel R, the second color sub-pixel may be a green sub-pixel G, and the third color sub-pixel may be a blue sub-pixel B. The color settings of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel are not limited to R, G, and B. The color of the sub-pixel in each pixel unit can be set as needed.

In an exemplary embodiment, as shown in FIGS. 3 and 4 , the pixel electrodes 142 of the first color subpixels in the same row of subpixels are all connected to the same gate line, and the second color subpixels in the same row of subpixels are connected to the same gate line. The pixel electrodes 142 of the pixel electrodes 142 are all connected to another gate line, and the pixel electrodes 142 of the third color sub-pixels in two adjacent pixel units in the same row of sub-pixels are connected to different gate lines respectively. For example, in FIG. 3 , the pixel electrodes 142 of the first color subpixels in the same row of subpixels are all connected to the first gate line 121 , and the pixel electrodes 142 of the second color subpixels in the same row of subpixels are all connected to the second color subpixels. Gate lines 122 are connected. The third color sub-pixel in the first pixel unit is connected to the second gate line 122, and the third color sub-pixel in the second pixel unit is connected to the first gate line 121.

In an exemplary embodiment, as shown in FIGS. 3 and 4 , the display substrate may further include N data lines 141 , each data line 141 corresponding to two adjacent groups of sub-pixels. The two adjacent groups of sub-pixels corresponding to the same data line 141 may be the first group of sub-pixels 31 and the second group of sub-pixels 32 respectively. The pixel electrodes 142 of the odd-numbered rows of sub-pixels in the first group of sub-pixels 31 correspond to The data lines 141 are connected, and the pixel electrodes 142 of the even-numbered row sub-pixels in the second group of sub-pixels 32 are connected to the corresponding data lines 141 .

The above-mentioned first group of sub-pixels 31 and second group of sub-pixels 32 are relative to the corresponding data lines. For example, when corresponding to the i-th data line, one group of sub-pixels is the first group of sub-pixels. correspond For the i+1th data line, this group of sub-pixels may be the second group of sub-pixels.

The pixel connection method shown in Figure 3 can be called Z architecture pixels. The technical solution using Z architecture pixels can avoid display differences caused by different charging of adjacent data lines 141 and avoid vertical or shaking head marks.

When using a double-gate structure, in order to ensure the pixel charging rate, as shown in FIG. 4 , the display substrate may also include an electrode compensation layer disposed on one side of the substrate 11 , and the electrode compensation layer may include a plurality of common electrode compensation lines 171 . The common electrode compensation line 171 may be located between two adjacent data lines 141 and between two adjacent columns of sub-pixels.

In an exemplary embodiment, as shown in FIGS. 5a and 5b , the display substrate further includes a first conductive layer, a second insulating layer 13 , a second conductive layer, and a first insulating layer sequentially disposed on one side of the substrate 11 15. Electrode compensation layer, third insulating layer 18 and common electrode layer 16. The first gate line 121 and the second gate line 122 are located in the first conductive layer, the data line 141 and the pixel electrode 142 are located in the second conductive layer, and the electrode compensation layer is a different layer from the first conductive layer and a different layer from the second conductive layer. The electrode compensation layer includes a common electrode compensation line 171 . The common electrode compensation line 171 is connected to the common electrode layer 16 through a via hole penetrating the third insulating layer 18 .

In the embodiment shown in FIG. 2 , the common electrode compensation line 171 can be located on the same layer as the data line 141 . The display substrate does not need to separately provide an electrode compensation layer and the third insulating layer 18 . The common electrode layer 16 is provided on the first insulating layer 15 Above, the common electrode compensation line 171 may be connected to the common electrode layer 16 through the first via hole 41 penetrating the first insulation layer 15 .

FIG. 6 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure. FIG. 7 is a schematic diagram of the A-A cross-section of FIG. 6 in one embodiment. As shown in FIGS. 6 and 7 , the display substrate also includes a first conductive layer, a second insulating layer 13 , a second conductive layer, a first insulating layer 15 and a common electrode layer 16 that are sequentially disposed on one side of the substrate 11 . The first gate line 121 and the second gate line 122 are located on the first conductive layer, and the data line 141, the pixel electrode 142 and the electrode compensation layer are all located on the second conductive layer. The electrode compensation layer may include a plurality of common electrode compensation lines 171 . The common electrode compensation line 171 may be located between two adjacent data lines 141 and between two adjacent columns of sub-pixels. The common electrode compensation line 171 is connected to the common electrode layer 16 through the first via hole 41 penetrating the first insulation layer 15 .

As shown in FIG. 6 , the data line 141 includes a first portion of wiring 141a corresponding to the odd-numbered rows of sub-pixels and a second portion of wiring 141b corresponding to the even-numbered rows. The first portion of wiring 141a is located on the opposite side. Between two adjacent columns of sub-pixels in the corresponding first group of sub-pixels 31, the second portion of wiring 141b is located between two adjacent columns of sub-pixels in the corresponding second group of sub-pixels 32. The data line 141 also includes a third portion of wiring 141c. The third portion of wiring 141c is located between two adjacent gate lines of two adjacent rows of sub-pixels. For example, the third portion of wiring 141c is located between two adjacent rows of sub-pixels. between the second gate line 122a and the first gate line 121b. The first partial wiring 141a and the second partial wiring 141b corresponding to two adjacent rows of sub-pixels are connected by a third partial wiring 141c. Therefore, the data line 141 in FIG. 6 has a "bow-shaped" routing.

In an exemplary embodiment, as shown in FIGS. 6 and 7 , the common electrode compensation line 171 may include a plurality of first compensation lines 171 a corresponding to one row of sub-pixels, and the first compensation lines 171 a The wiring 171a is located between two adjacent data lines 141 and between two adjacent columns of sub-pixels in the corresponding row of sub-pixels. The first compensation trace 171 a may be connected to the common electrode layer 16 through the first via hole 41 penetrating the first insulation layer 15 .

For example, as shown in FIG. 6 , the common electrode compensation line 171 may also include a second compensation line 171b, and the second compensation line 171b is located between two adjacent gate lines of two adjacent rows of sub-pixels. The second compensation wiring 171b connects the first compensation wiring 171a corresponding to two adjacent rows of sub-pixels. Therefore, the common electrode compensation line 171 in FIG. 6 has a "bow-shaped" routing.

In the embodiment shown in FIG. 6 , not only the third partial wiring 141c of the data line 141 is provided between two adjacent gate lines of two adjacent rows of sub-pixels, but also the second compensation line of the common electrode compensation line 171 is provided. Trace 171b. The embodiment shown in FIG. 6 does not increase the number of masks compared to the embodiment shown in FIG. 2 . FIG. 8 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure. FIG. 9 is a schematic diagram of the AA cross-section of FIG. 8 in one embodiment. In one implementation, as shown in FIG. 8 , the pixel connection method in the display substrate adopts a Z-architecture pixel technology solution. As shown in FIGS. 8 and 9 , the display substrate also includes an electrode compensation layer and a common electrode layer 16 disposed on one side of the substrate 11 , and a first insulating layer 15 is disposed between the electrode compensation layer and the common electrode layer 16 . The electrode compensation layer includes a plurality of electrode compensation lines, and the electrode compensation lines are located between two adjacent data lines 141 . The electrode compensation line may include a plurality of first compensation lines 171a. The plurality of first compensation lines 171a correspond to a row of sub-pixels. The first compensation lines 171a are located between two adjacent data lines 141 and are located in the corresponding row of sub-pixels. Between two adjacent columns of sub-pixels in the pixel, the first compensation wiring 171a is connected to the common electrode layer 16 through the first via hole 41 penetrating the first insulation layer 15 .

According to the technical solution of the embodiment of the present disclosure, by arranging a plurality of first compensation lines 171a, the common electrode signal can be compensated for the common electrode layer 16 to ensure the charging rate of the pixels and improve the display effect.

For example, the substrate 11 can be a glass substrate or a flexible substrate. The material of the substrate 11 can be set as needed and is not limited here.

In one implementation, as shown in FIG. 9 , the electrode compensation layer and the data line 141 are located on the same layer, that is, the first compensation wiring 171 a and the data line 141 are located on the same layer. This setting method will not increase the number of masks for the display substrate and will not increase production costs.

In one implementation, as shown in FIGS. 8 and 9 , the plurality of first compensation traces 171a are not connected to each other in the electrode compensation layer. The first compensation trace 171a is connected to the common electrode layer 16 through the corresponding first via hole 41. Therefore, it is no longer necessary to provide the second compensation trace 171b in the electrode compensation layer. Compared with the embodiment shown in Figure 6, in the embodiment shown in Figure 8, the distance between two adjacent gate lines (the second gate line 122a and the first gate line 121b) of two adjacent rows of sub-pixels is greatly reduced. , can improve the pixel aperture ratio of the display device, and can meet the needs and design needs of small and medium-sized display products that require higher pixel resolution.

In one implementation, as shown in FIG. 8 , the data line 141 includes a first portion of wiring 141a corresponding to the odd-numbered rows of sub-pixels and a second portion of wiring 141b corresponding to the even-numbered rows. The first portion of wiring 141a is located at Between two adjacent columns of sub-pixels in the corresponding first group of sub-pixels 31, the second portion of wiring 141b is located between two adjacent columns of sub-pixels in the corresponding second group of sub-pixels 32. The data line 141 also includes a third portion of wiring 141c. The third portion of wiring 141c is located between two adjacent gate lines of two adjacent rows of sub-pixels. For example, the third portion of wiring 141c is located between two adjacent rows of sub-pixels. between the second gate line 122a and the first gate line 121b. The first partial wiring 141a and the second partial wiring 141b corresponding to two adjacent rows of sub-pixels are connected by a third partial wiring 141c. Therefore, the data line 141 in Figure 8 also has a "bow-shaped" routing.

In one embodiment, as shown in FIG. 9 , the display substrate further includes a first conductive layer, a second insulating layer 13 , a second conductive layer, a first insulating layer 15 and a common layer arranged sequentially on one side of the substrate 11 Electrode layer 16. The first gate line 121 and the second gate line 122 are located on the first conductive layer, and the data line 141, the pixel electrode 142 and the electrode compensation layer are all located on the second conductive layer.

The display substrate may further include a thin film transistor. The thin film transistor may include a gate electrode, an active layer, a source electrode and a drain electrode. The gate electrode may be located on the first conductive layer, and the source electrode and the drain electrode may be located on the first conductive layer. Two conductive layers. The active layer can be arranged as needed. For example, the active layer can be arranged between the second insulating layer 13 and the second conductive layer, and both the source electrode and the drain electrode are connected to the active layer.

For example, as shown in FIG. 8 , the display substrate may include a plurality of first thin film transistors 61 , the plurality of first thin film transistors 61 correspond to a plurality of sub-pixels one by one, and the first thin film transistors 61 are connected to the pixel electrodes of the corresponding sub-pixels. . The orthographic projection of the first thin film transistor 61 on the substrate 11 is located between two adjacent rows of sub-pixels. Therefore, the first thin film transistor 61 does not occupy the sub-pixel area for setting the pixel electrode, and the pixel aperture ratio can be improved.

In one implementation, as shown in FIG. 8 , the first via hole 41 may be located at one end of the first compensation trace 171 a, and the orthographic projection of the first via hole 41 on the substrate 11 may be located at two adjacent rows of sub-pixels. between the orthographic projections of two adjacent gate lines on the substrate 11. For example, in FIG. 8 , the orthographic projection of the first via hole 41 on the substrate 11 is located between the orthographic projections of the second gate line 122 a and the first gate line 121 b of two adjacent rows of sub-pixels on the substrate 11 . between. For example, as shown in FIG. 8 , there is no overlapping area between the orthographic projection of the first via hole 41 on the substrate 11 and the orthographic projection of the first thin film transistor 61 on the substrate 11 . Therefore, the first via hole 41 can avoid the first thin film transistor 61

In an exemplary embodiment, the first compensation trace 171a includes a first extension section a1 and a second extension section a2. The first extension section a1 is located between two adjacent sub-pixels. The first extension section a1 can be along the second direction. extend. The second extension section a2 connects the first extension section a1 and the first via hole 41 . There is no overlapping area between the extension lines of the first via hole 41 and the first extension section a1. That is to say, the second extension section a2 is not parallel to the first extension section a1.

In the embodiment shown in FIG. 6 , the first compensation trace 171a extends along the second direction, and the first via hole 41 is located on the first compensation trace 171a. Therefore, in order for the first via hole 41 to avoid the third side of the data line 141, The partial wiring 141c can increase the distance between the second gate line 122 and the first gate line 121. In the embodiment shown in FIG. 8 , the first extension section a1 extends along the second direction, the second extension section a2 is not parallel to the first extension section a1 , and there is no intersection between the first via hole 41 and the extension line of the first extension section a1 . overlapping area. Therefore, the first via hole 41 is located on one side (for example, the right side) of the first extension section a1, which allows the first via hole 41 to avoid the third part of the wiring 141c of the data line 141, thus reducing the size of the second gate line. 122 and the first gate line 121, thereby reducing the distance between adjacent rows of sub-pixels, which is beneficial to improving the pixel aperture ratio of the display product.

In one embodiment, as shown in FIG. 8 , the display substrate further includes a penetrating first insulating layer 15 The other end of the first compensation trace 171a is connected to the common electrode layer 16 through the second via hole 42. The orthographic projection of the second via hole 42 on the substrate 11 is located between the orthographic projections of two adjacent gate lines on the substrate 11 of two adjacent rows of sub-pixels. The first compensation trace 171a also includes a third extension section a3. The third extension section a3 connects the first extension section a1 and the second via hole 42. The second via hole 42 does not overlap with the extension line of the first extension section a1. area. In such a structure, both ends of the first compensation trace 171a are connected to the common electrode layer 16 through the first via hole 41 and the second via hole 42 respectively, which can reduce the connection between the first compensation trace 171a and the common electrode layer 16 resistance to improve product performance.

In one embodiment, as shown in FIG. 8 , the first via hole 41 and the second via hole 42 are located on the same side of the corresponding first extension section a1. For example, in FIG. 8 , the first via hole 41 and the second via hole 42 are both located on the right or left side of the first extension section a1 .

For example, the positions of the second extension section a2 in the first compensation trace 171a corresponding to two adjacent rows of sub-pixels are opposite. For example, in Figure 8, in the first compensation trace 171a corresponding to the odd-numbered row sub-pixel, the first via hole 41 and the second via hole 42 are both located on the right side of the first extension section a1. Therefore, the second extension section a2 and The third extension sections a3 all extend toward the right side of the corresponding first extension section a1; in the first compensation traces 171a corresponding to the even-numbered rows of sub-pixels, the first via hole 41 and the second via hole 42 are located in the first extension section a1 Therefore, the second extension section a2 and the third extension section a3 both extend toward the left side of the corresponding first extension section a1.

Therefore, as shown in FIG. 8 , both the first via holes 41 corresponding to the sub-pixels in the odd rows and the second via holes 42 corresponding to the sub-pixels in the even rows can avoid the third part of the wiring 141 c of the data line 141 , which is beneficial to the data line 141 The third part of the trace is set to 141c.

In one embodiment, as shown in FIG. 8 , the display substrate may further include a preset light-shielding area 50 , the second extension section a2 is located in the preset light-shielding area 50 and/or the third extension section a3 is located in the preset light-shielding area 50 Inside. For example, the display substrate can be used in a liquid crystal display device. The liquid crystal display device can include the display substrate in the embodiment of the present disclosure, and a color filter substrate aligned with the display substrate. A black matrix can be disposed on the color filter substrate. The black matrix Orthographic projections on the display substrate may be between adjacent rows of sub-pixels and between adjacent columns of sub-pixels. A preset light-shielding area 50 is provided in the display substrate. After the display substrate and the color filter substrate are assembled, the preset light-shielding area 50 corresponds to the black matrix in the color filter substrate. The second extension section a2 is arranged in the preset light shielding area 50 and/or the third extension section a3 is arranged in the preset light shielding area 50, so that the second extension section a2 and/or the third extension section a3 can be blocked by the black matrix. , to avoid the second extension The segment a2 and the third extended segment a3 affect the light transmittance of the display device.

FIG. 10 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure. In one implementation, as shown in FIG. 10 , the data line 141 is located between two adjacent groups of sub-pixels. The data line 141 may extend along the second direction between two adjacent groups of sub-pixels. With such a structure, the data lines 141 between adjacent rows of sub-pixels are connected straight lines, and there is no need to set a third part of the wiring 141c between adjacent gate lines of adjacent rows of sub-pixels, which can further reduce the number of adjacent rows of sub-pixels. The distance between two adjacent gate lines of a row of sub-pixels is beneficial to improving the aperture ratio of the display product.

In one implementation, as shown in FIG. 10 , the first compensation trace 171a may include a first extension section a1, the first extension section a1 is located between two adjacent sub-pixels and extends along the second direction. The orthographic projection of the first via hole 41 on the substrate 11 is located between two adjacent rows of sub-pixels. The orthographic projection of the first via hole 41 on the substrate 11 is the same as the orthographic projection of the first extension section a1 on the substrate 11 At least partially overlap. In the embodiment shown in FIG. 10 , since the data line 141 is a straight line extending along the second direction, the first via hole 41 no longer needs to avoid the data line 141 . Therefore, the first via hole 41 can be placed on the substrate 11 The orthographic projection on the substrate 11 is set to at least partially overlap with the orthographic projection of the first extension section a1 on the substrate 11 , so that the distance between adjacent rows of sub-pixels can be further reduced and the pixel aperture ratio can be further improved.

For example, the orthographic projection of the first via hole 41 on the substrate 11 is located between two adjacent gate lines of two adjacent rows of sub-pixels. This ensures that the first via hole 41 is located in the preset light shielding area 50. Avoid affecting the light transmittance of the display substrate.

For example, as shown in Figure 10, in two adjacent rows of sub-pixels, two first extension sections a1 located between the same two columns of sub-pixels can be The electrode compensation layer is interconnected. For example, in Figure 10, the first extended section a1-a in the adjacent odd-numbered row sub-pixels and the first extended section a1-b in the even-numbered row sub-pixels are located between the same two columns of sub-pixels. In the odd-numbered rows, When there is no same layer of conductive material between the first extended section a1-a in the sub-pixels and the first extended section a1-b in the even-numbered rows of sub-pixels, the first extended section a1-a in the odd-numbered rows of sub-pixels The first extended section a1-b in the even-numbered rows of sub-pixels may be connected to each other.

For example, as shown in FIG. 10 , two first extension sections a1 that are connected to each other in the electrode compensation layer share the first via hole 41 . In this way, the number of first via holes 41 can be reduced.

For example, when there is the same layer of conductive material between the first extension section a1 in the odd-numbered rows of sub-pixels and the first extension section a1 in the even-numbered rows of sub-pixels, the first extension section a1 in the odd-numbered rows of sub-pixels and the first extension section a1 in the even-numbered subpixels The second extension section a2 in the row sub-pixel is not connected in the electrode compensation layer.

In one implementation, as shown in Figure 10, the first compensation trace 171a also includes a fourth extension section a4. The fourth extension section a4 is located between two adjacent rows of sub-pixels. The fourth extension section a4 is connected to the first The extension section a1 is not parallel, and the orthographic projection of the first via hole 41 on the substrate 11 and the orthographic projection of the fourth extension section a4 on the substrate 11 at least partially overlap. By arranging the fourth extension section a4, the compensation load of the first compensation line 171a can be increased, and the influence of the segmented arrangement of the electrode compensation line on the common electrode compensation signal can be avoided.

For example, the fourth extension section a4 may be located between two adjacent gate lines of two adjacent rows of sub-pixels. The direction of the fourth extension section a4 is not parallel to the direction of the first extension section a1. For example, the direction of the fourth extension section a4 may be perpendicular to the direction of the first extension section a1.

In the embodiment shown in FIG. 10 , the first compensation line 171a and the data line 141 are located on the same layer.

FIG. 11 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure. In one embodiment, as shown in FIG. 11 , the display substrate may further include a third via hole 43 , and the third via hole 43 penetrates the first insulating layer 15 . The third via hole 43 is located at one end of the first extension section a1 away from the first via hole 41 . The orthographic projection of the third via hole 43 on the substrate 11 is located between two adjacent sub-pixels and is located on both sides of the corresponding row of sub-pixels. Between the orthographic projections of the grating lines on the substrate 11.

For example, as shown in FIG. 11 , the first compensation trace 171a and the data line 141 are located on the same layer.

FIG. 12 is a schematic diagram of a pixel in which the display substrate adopts a double gate structure in another embodiment of the present disclosure. Figure 13 is a schematic cross-sectional view along line A-A in Figure 12 . In one embodiment, as shown in FIGS. 12 and 13 , the display substrate includes a first conductive layer, a second insulating layer 13 , a second conductive layer, and a first insulating layer 15 that are sequentially disposed on one side of the substrate 11 and common electrode layer 16. The electrode compensation layer and the gate line are located on the first conductive layer, and the data line 141 is located on the second conductive layer. The first compensation trace 171a includes a first extension section a1. The first extension section a1 is located between two adjacent sub-pixels and extends along the second direction. The first extension section a1 is located between the two gate lines of the corresponding row of sub-pixels. The orthographic projection of the first via hole 41 on the substrate 11 is located between two adjacent sub-pixels and located between the two gate lines of the corresponding row of sub-pixels. (the first gate line 121a and the second gate line 122a) between orthographic projections on the substrate 11. The number of the first via hole 41 is at least one. The first via hole 41 penetrates the second insulation layer 13 and the first insulation layer 15 . The first extension section a1 is connected to the common electrode layer 16 through at least one first via hole 41 .

The embodiments shown in Figures 11 and 12 can be applied to medium and large size display products. The first extension section a1 is connected to the common electrode layer 16 through two via holes, which can reduce the distance between the first compensation trace 171a and the common electrode layer 16. Connection resistance between common electrode layers 16.

The display substrate in the embodiment of the present disclosure can be applied to non-TDDI (Touch and Display Driver Integration, touch and display driver integration) dual-gate display products.

The preparation process of the display substrate according to the embodiment of the present disclosure will be described below with reference to the embodiments of FIG. 8 and FIG. 9 . It can be understood that the "patterning" mentioned in this article, when the patterned material is an inorganic material or metal, includes coating of photoresist, mask exposure, development, etching, and stripping lithography. Glue and other processes. When the patterned material is an organic material, "patterning" includes mask exposure, development and other processes. The evaporation, deposition, coating, coating, etc. mentioned in this article are all mature in related technologies. Preparation Process.

The preparation process of the display substrate may include the following steps.

The first gate line 121, the second gate line 122 and the gate electrode of the thin film transistor are formed on one side of the substrate 11. As shown in FIGS. 8 and 9 , the process may include: forming a first metal film on one side of the substrate 11 , patterning the first metal film, and forming the first gate line 121 and the second gate line 121 at a preset position. The gate line 122 and the gate electrode of the thin film transistor. The layer where the first gate line 121, the second gate line 122 and the gate electrode of the thin film transistor are located is the first conductive layer.

The second insulating layer 13 is formed on the side of the first conductive layer facing away from the substrate 11, as shown in FIGS. 8 and 9.

An active layer of the thin film transistor is formed on a side of the second insulating layer 13 facing away from the substrate 11 . The active layer is not shown in Figures 8 and 9.

The first compensation wiring 171a, the data line 141, the source and drain electrodes of the thin film transistor, and the pixel electrode 142 are formed on a side of the active layer facing away from the substrate 11. As shown in FIGS. 8 and 9 , this step may include: forming a second metal film on a side of the active layer facing away from the substrate 11 , patterning the second metal film, and forming a first compensation film at a preset position. The wiring 171a, the data line 141, and the source and drain electrodes of the thin film transistor; form a pixel electrode 142 film on the side of the first compensation wiring 171a, the data line 141 away from the substrate 11, and pattern the pixel electrode 142 film Processing, the pixel electrode 142 is formed at a preset position, and the pixel electrode 142 is located in the area where the sub-pixel is located. The orthographic projection of the pixel electrode 142 on the substrate 11 does not overlap with the orthographic projection of the first compensation line 171 a and the data line 141 on the substrate 11 . The pixel electrode 142 may be connected to one of the source electrode and the drain electrode. The layer where the first compensation line 171a, the data line 141, the source electrode and the drain electrode of the thin film transistor and the pixel electrode 142 are located is the second conductive layer.

A first insulating layer 15 is formed on the side of the second conductive layer facing away from the substrate 11. The first insulating layer 15 is provided with a first via hole 41 and a second via hole 42. The first compensation trace 171a passes through the first via hole. 41 and the second via hole 42 are exposed.

A common electrode layer 16 is formed on the side of the first insulating layer 15 facing away from the substrate 11 . The common electrode layer 16 is connected to the first compensation trace 171 a through the first via hole 41 and the second via hole 42 , as shown in FIG. 8 and FIG. 9 shown.

In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or more. Various, can be single layer, multi-layer or composite layer. The gate electrode, source electrode, drain electrode, gate line, data line, and electrode compensation layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). Any one or more, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, etc. The active layer can use amorphous indium gallium zinc oxide materials (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), Various materials such as hexathiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide Oxide technology, silicon technology, and organic technology. The pixel electrode and the common electrode layer can use transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Based on the inventive concepts of the foregoing embodiments, embodiments of the disclosure further provide a display device, which includes the display substrate in the embodiments of the disclosure. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame, a navigator, or any other product or component with a display function.

Exemplarily, the display device may be a liquid crystal display device. The display device may further include a color filter substrate, and a black matrix is provided on the color filter substrate. When the color filter substrate and the display substrate are paired, the second extension section, the third extension section or the fourth extension section in the first compensation line The orthographic projections of the extension sections on the substrate may all be located within the orthographic projection range of the black matrix on the substrate.

In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", ""Back","Left","Right","Vertical","Horizontal","Top","Bottom","Inside","Outside","Clockwise","Counterclockwise","Axis" , "radial", "circumferential" and other indicated directions or The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it is not to be construed as a limitation on the present disclosure.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present disclosure, "plurality" means two or more, unless otherwise expressly limited.

In this disclosure, unless otherwise explicitly stated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, or an internal connection between two elements or an interaction between two elements . For those of ordinary skill in the art, the meanings of the above terms in this disclosure can be understood according to the circumstances.

In this disclosure, unless otherwise expressly stated and limited, a first feature "on" or "below" a second feature may include the first and second features in direct contact, or may include the first and second features. Not in direct contact but through additional characteristic contact between them. Furthermore, the terms "above", "above" and "above" a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature. “Below”, “below” and “beneath” the first feature of the second feature includes the first feature being directly above and diagonally above the second feature, or simply means that the first feature has a smaller horizontal height than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. To simplify the present disclosure, the components and arrangements of specific examples are described above. Of course, they are merely examples and are not intended to limit the disclosure. Furthermore, this disclosure may repeat reference numbers and/or reference letters in different examples, such repetition being for purposes of simplicity and clarity and does not by itself indicate a relationship between the various embodiments and/or arrangements discussed.

The above are only exemplary embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of various changes or replacements within the technical scope of the present disclosure. , these should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

A display substrate includes a substrate and a plurality of sub-pixels located on one side of the substrate and arranged in M rows and N groups. Each group of sub-pixels includes two columns of sub-pixels. The display substrate also includes M pairs of gate lines, M A pair of gate lines corresponds one to one to M rows of sub-pixels. A pair of gate lines includes a first gate line and a second gate line extending along a first direction. The first gate line and the second gate line are respectively arranged at corresponding Opposite sides of the row of sub-pixels and located between two adjacent rows of sub-pixels, and the first direction is the direction of the row;

The display substrate also includes N data lines. Each data line corresponds to two adjacent groups of sub-pixels. The adjacent two groups of sub-pixels corresponding to the same data line are respectively a first group of sub-pixels and a second group of sub-pixels. sub-pixels, the pixel electrodes of the odd-numbered rows of sub-pixels in the first group of sub-pixels are connected to the corresponding data lines, and the pixel electrodes of the even-numbered rows of sub-pixels in the second group of sub-pixels are connected to the corresponding data lines. line connection;

The display substrate also includes an electrode compensation layer and a common electrode layer disposed on one side of the substrate. A first insulating layer is disposed between the electrode compensation layer and the common electrode layer. The electrode compensation layer includes a plurality of A plurality of first compensation lines corresponds to a row of sub-pixels, and the first compensation lines are located between two adjacent data lines and between two adjacent sub-pixels in the corresponding row. Between columns of sub-pixels, the first compensation line is connected to the common electrode layer through a first via hole penetrating the first insulation layer.
The display substrate according to claim 1, wherein a plurality of the first compensation traces are not connected to each other in the electrode compensation layer.
The display substrate according to claim 2, wherein the first via hole is located at one end of the first compensation trace, and the orthographic projection of the first via hole on the substrate is located in two adjacent rows. Between the orthographic projections of two adjacent gate lines of a pixel on the substrate, the first compensation line includes a first extension section and a second extension section, and the first extension section is located at two adjacent sub-pixels. The second extension section connects the first extension section and the first via hole, and there is no overlapping area between the first via hole and the extension line of the first extension section.
The display substrate according to claim 3, further comprising a second via hole penetrating the first insulating layer, and the other end of the first compensation line is connected to the common electrode layer through the second via hole, The orthographic projection of the second via hole on the substrate is located between the orthographic projections of two adjacent gate lines of two adjacent rows of sub-pixels on the substrate, and the first compensation trace also includes The third extension section, the third The extension section connects the first extension section and the second via hole, and there is no overlapping area between the second via hole and the extension line of the first extension section.
The display substrate according to claim 3, further comprising a preset light-shielding area, and the second extension section is located in the preset light-shielding area.
The display substrate according to claim 1, wherein the first compensation trace includes a first extension section, the first extension section is located between two adjacent sub-pixels and extends along the second direction, and the first extension section The orthographic projection of the via hole on the substrate is located between two adjacent rows of sub-pixels, and the orthographic projection of the first via hole on the substrate is consistent with the orthographic projection of the first extension section on the substrate. Orthographic projections at least partially overlap.
The display substrate according to claim 6, wherein the first compensation trace further includes a fourth extension section, the fourth extension section is located between two adjacent rows of sub-pixels, the fourth extension section is connected to the The first extension section is not parallel, and the orthographic projection of the first via hole on the substrate at least partially overlaps the orthographic projection of the fourth extension section on the substrate.
The display substrate according to claim 6, further comprising a third via hole penetrating the first insulating layer, the third via hole being located at an end of the first extension section away from the first via hole, so The orthographic projection of the third via hole on the substrate is located between two adjacent sub-pixels and between the orthographic projections of the two gate lines of the corresponding row of sub-pixels on the substrate.
The display substrate according to any one of claims 1 to 8, wherein the electrode compensation layer and the data line are located on the same layer.
The display substrate according to claim 2, further comprising a first conductive layer, a second insulating layer, a second conductive layer, the first insulating layer and the common electrode layer arranged in sequence on one side of the substrate , the electrode compensation layer and the gate line are located on the first conductive layer, the data line is located on the second conductive layer, the first compensation line includes a first extension section, the first extension section The first extension section is located between two adjacent sub-pixels and extends along the second direction. The first extension section is located between two gate lines corresponding to the row of sub-pixels. The orthographic projection of the first via hole on the substrate is located at Between two adjacent sub-pixels and between the orthographic projections of the two gate lines of the corresponding row of sub-pixels on the substrate, the number of the first via holes is at least one, and the first via holes penetrate all The second insulating layer and the first insulating layer are connected to the common electrode layer through the at least one first via hole.
The display substrate according to claim 1, wherein the data line includes a first portion of wiring corresponding to odd-numbered rows of sub-pixels and a second portion of wiring corresponding to even-numbered rows, and the A part of the wiring is located between two adjacent columns of sub-pixels in the corresponding first group of sub-pixels, the second part of the wiring is located between two adjacent columns of sub-pixels in the corresponding second group of sub-pixels, and the data line is also It includes a third part of wiring, the third part of wiring is located between two adjacent gate lines of two adjacent rows of sub-pixels, the first part of wiring corresponding to the two adjacent rows of sub-pixels and the The second part of the traces is connected through the third part of the traces.
The display substrate according to claim 1, wherein the data line is located between two adjacent groups of sub-pixels, the data line extends along a second direction, and the second direction is the direction of the column.
The display substrate according to claim 1, wherein each row of sub-pixels is configured as a plurality of pixel units, and the pixel units include sequentially adjacent first color sub-pixels, second color sub-pixels and third color sub-pixels, The pixel electrodes of the first color subpixels in the same row of subpixels are all connected to the same gate line, the pixel electrodes of the second color subpixels in the same row of subpixels are all connected to another gate line, and the pixel electrodes of the second color subpixels in the same row of subpixels are all connected to the same gate line. The pixel electrodes of the third color sub-pixels in two adjacent pixel units are respectively connected to different gate lines.
A display device comprising the display substrate according to any one of claims 1-13.