WO2023217255A1

WO2023217255A1 - Data processing method and device, processor and computer system

Info

Publication number: WO2023217255A1
Application number: PCT/CN2023/093749
Authority: WO
Inventors: 王官皓; 杨瑞
Original assignee: 华为技术有限公司
Priority date: 2022-05-12
Filing date: 2023-05-12
Publication date: 2023-11-16
Also published as: CN117093132A

Abstract

The present invention relates to the field of computers. Disclosed are a data processing method and device, a processor and a computer system. The method comprises: a first processor core obtains a first memory access request, the first memory access request being used for instructing the first processor core to perform data processing on data stored in a first memory space; when the first memory space is a memory space of a memory associated with a first attraction zone of the first processor core, the first processor core determines an address of the first memory space and performs data processing of the first memory access request according to the address of the first memory space. Therefore, access conflicts generated when a plurality of processor cores perform memory access in parallel are avoided, the overall duration of memory access is reduced, and the memory access efficiency is improved.

Description

Data processing methods, devices, processors and computer systems

This application claims the priority of the Chinese patent application submitted to the China Patent Office on May 12, 2022, with the application number 202210514855.0 and the invention name "data processing method, device, processor and computer system". All the patent applications The contents are incorporated into this application by reference.

Technical field

The present application relates to the field of computers, and in particular, to a data processing method, device, processor and computer system.

Background technique

At present, computer systems include traditional memory (such as dynamic random-access memory (DRAM)) and extended memory (such as storage-class-memory (SCM), solid-state disk (Solid State Disk) , SSD)), using both traditional memory and extended memory as the main memory of the computing system to expand the storage capacity of traditional memory. Furthermore, the processor (Central Processing Unit, CPU) in the computer system uses virtual memory technology to access the memory, that is, the processor accesses the memory according to the physical address (Physical Address) corresponding to the virtual address (Virtual Memory Address). The same CPU can include multiple processor cores (cores), which are used to process different memory access requests. When the processor core performs the data processing of the access request on the address of the memory space according to the memory access request, it will describe the data in the memory. Operate on the metadata of the properties of the data in memory. Multiple processor cores can access the memory storage space indicated by the physical address associated with the same virtual address and operate on the same metadata. Therefore, metadata is globally shared in memory, and multiple processor cores cannot operate on metadata at the same time to avoid multiple processor cores operating on metadata at the same time, resulting in inconsistent memory accessed by multiple processor cores. question.

When the first processor core among the multiple processor cores performs the data processing of the access request on the address of the memory space according to the memory access request, the processor cores other than the first processor core need to wait for the first processor core to complete. For memory access, only the first processor core can perform the data processing of the access request. Therefore, the operation of the above-mentioned access request will cause an access conflict, resulting in a longer memory access time, and ultimately leading to a decrease in the processing performance of the processor. Therefore, how to provide a more efficient memory access method has become an urgent technical issue to be solved.

Contents of the invention

The present application provides a data processing method, device, processor and computer system, thereby improving the memory access efficiency of the processor.

In a first aspect, a data processing method is provided, which is suitable for a computer system including a processor and a memory, and is executed by a first processor core of the processor. The above data processing method includes: the first processor core obtains a first memory access request. The first memory access request is used to instruct the first processor core to perform data processing on the data stored in the first memory space. When the first memory space is the first When the first attraction zone (Attraction Zone) of the processor core is associated with the storage space of the memory, the first processor core determines the address of the first memory space and performs the data processing of the first memory access request according to the address of the first memory space.

Therefore, when the first memory space that needs to be accessed indicated by the first memory access request is the storage space of the memory associated with the first attraction domain of the first processor core, the first processor core checks the address of the first memory space Perform data processing of the first memory access request, and associate the first processor core with the first memory space through the attraction domain, so that processor cores other than the first processor core cannot perform data processing on the address of the first memory space. Therefore, different processor cores perform data processing on addresses in different memory spaces, and different processor cores operate on different metadata when performing data processing. The operations of metadata between multiple processor cores do not affect each other, which is equivalent to the metadata in the memory being divided into multiple parts that are isolated from each other. Multiple processor cores can simultaneously operate metadata in their respective attraction domains. When the first processor core performs the data processing of the access request on the address of the memory space according to the memory access request, processors other than the first processor core The core does not need to wait for the first processor core to complete memory access and metadata operations, and can also operate on metadata outside the first attraction domain to complete memory access. This avoids access conflicts when multiple processor cores perform memory access in parallel, reduces the overall duration of memory access, and improves the efficiency of memory access.

In a possible implementation, the first attraction domain includes an association relationship between a memory space address and an attraction domain identifier. The attraction domain identifier is used to indicate the attraction domain to which the association relationship belongs. The memory space address is associated with the attraction domain to which the association relationship belongs. The address of the memory space.

In the above implementation, the processor core determines whether the memory space is the storage space of the memory associated with the attraction domain of the processor core based on the attraction domain identifier and the memory space address contained in the association relationship, ensuring that the processor checks the memory space and the attraction domain. Relevance judgment efficiency.

For example, the association is a page table entry, and the attraction domain identifier is set in a reserved bit of the page table entry. Using the existing reserved bits in the page table entry to record the attraction domain identifier, the processor can identify the attraction domain identifier without modifying the microarchitecture.

For another example, the attraction domain identifier includes a processor core identifier. The processor core identifier in the association relationship can indicate that the association relationship belongs to the attraction domain of the processor core represented by the processor core identifier.

In a possible implementation, the first memory access request may be generated by the first processor core when a thread executed by the first processor core needs to read and write data in the first memory space.

In another possible implementation, the first memory access request may be made by a thread outside the first processor core when a thread executed by a processor core outside the first processor core needs to read and write data in the first memory space. The processor core generates and sends it to the first processor core. After the first processor core performs the data processing of the first memory access request according to the address of the first memory space, the obtained data is sent to the processor core that sent the first memory access request, thereby avoiding the processor core not being reconciled with the processor. The memory space associated with the core's own attraction domain is used for data processing, which improves the isolation strength of the memory space associated with different attraction domains.

The processor core can also dynamically adjust the associations contained in the attraction domain. For example, the first processor core adds an association relationship that does not belong to any attraction domain to the first attraction domain.

The step for the first processor core to add an association relationship that does not belong to any attraction domain to the first attraction domain may be as follows: the first processor core may obtain a second memory access request, and the second memory access request is used to instruct the first processor Check the data stored in the second memory space and perform data processing. When the second memory space is not associated with any attraction domain and the cumulative number of second memory access requests is greater than the preset threshold, the first processor checks the data stored in the second memory space and performs data processing. The association relationship of the address of the second memory space is added to the first attraction domain.

Optionally, the first processor core adding the association relationship of the address of the second memory space to the first attraction domain may include: setting the attraction domain identifier containing the association relationship of the address of the second memory space as the first attraction domain. The attractor domain ID of the domain.

For another example, the first processor core migrates the association relationship belonging to the first attraction domain to an attraction domain outside the first attraction domain.

The steps for the first processor core to migrate the association relationship belonging to the first attraction domain to an attraction domain outside the first attraction domain may be as follows: the first processor core obtains a third memory access request, and the third memory access request is used to indicate the third memory access request. One processor core performs data processing on the data stored in the third memory space, and the third memory access request is generated by a processor core other than the first processor core and sent to the first processor core. The first processor core adds an association including the address of the third memory space to the attraction domain of the processor core that sends the third memory access request the most times.

Optionally, the first processor core adds an association including the address of the third memory space to the attraction domain of the processor core that sends the third memory access request the most, including: adding the association including the address of the third memory space. The attraction domain identifier of the association relationship is set to the attraction domain identifier of the attraction domain of the processor core that sends the third memory access request the most.

As a result, the processor core realizes the expansion and reduction of the attraction domain, so that according to the frequency of the processor core accessing different memory spaces, the memory space that is more likely to be accessed by the processor core is associated with the attraction domain, so as to reduce the The obtained memory access request indicates the probability of the processor core accessing the memory space associated with the attraction domain that does not belong to itself, thereby improving the utilization of the processing resources of the processor core.

As an optional implementation manner, the association relationship of the first attraction domain may be stored in a storage unit connected to the first processor core, and the storage unit is used to store and query the association relationship contained in the first attraction domain. The first memory access request includes the virtual address of the first memory space, and the associated memory space includes the physical address of the first memory space. Then the step for the first processor core to determine the address of the first memory space may be as follows: first The processor core queries the storage unit for an association relationship according to the virtual address of the first memory space, obtains the first association relationship, and determines the physical address of the first memory space based on the first association relationship.

Alternatively, the storage unit may be an address translation unit.

In addition, the first processor core may also delete associations in the storage unit that do not belong to the first attraction domain every other preset period.

This reduces the probability that the association relationship queried by the processor core in the connected storage unit does not exist or is invalid, and reduces the probability that the processor core obtains the association relationship from the memory when the association relationship is not queried in the connected storage unit. processing overhead, thus improving the performance of memory accesses.

It should be noted that when the first processor core determines the physical address of the memory space based on the association relationship, if the association relationship does not belong to any attraction domain, belongs to the first attraction domain, or belongs to an attraction domain outside the first attraction domain, all processor cores will There is no need to stop the thread to update the storage unit, thus improving the performance of memory access.

A second aspect provides a data processing device, which includes various modules for executing the data processing method in the first aspect or any possible implementation of the first aspect.

In a third aspect, a processor is provided. The processor core is configured to execute the operation steps of the data processing method in the first aspect or any possible implementation of the first aspect.

In a fourth aspect, a computer system is provided. The computer system includes a memory and a processor in the third aspect. The processor is configured to execute the operating steps of the data processing method in the first aspect or any possible implementation of the first aspect, The data processing of the memory access request is performed at the address of the memory storage space.

In a fifth aspect, a computer-readable storage medium is provided, including: computer software instructions; when the computer software instructions are run in a computing device, the computing device is caused to execute as in the first aspect or any possible implementation of the first aspect. The steps of the method.

In a sixth aspect, a computer program product is provided. When the computer program product is run on a computer system, it causes the computing device to perform the operation steps of the method described in the first aspect or any possible implementation of the first aspect.

Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods.

Description of the drawings

Figure 1 is a schematic diagram of a multi-layer storage system provided by an embodiment of the present application;

Figure 2 is an architectural schematic diagram of a computer system provided by an embodiment of the present application;

Figure 3 is a schematic flow chart of a data processing method provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of a page table entry provided by an embodiment of the present application;

Figure 5 is a schematic flowchart of data processing steps provided by an embodiment of the present application;

Figure 6 is a schematic flowchart of another data processing step provided by the embodiment of the present application;

Figure 7 is a schematic structural diagram of an attraction domain provided by an embodiment of the present application;

Figure 8 is a schematic flowchart of an attraction domain expansion step provided by an embodiment of the present application;

Figure 9 is a schematic flowchart of steps for reducing an attraction domain provided by an embodiment of the present application;

Figure 10 is a schematic structural diagram of a data processing device provided by an embodiment of the present application.

Detailed ways

In order to facilitate understanding, the relevant terms and related concepts such as virtual memory involved in the embodiments of this application are first introduced below.

(1) Hierarchical storage

Throughout the computer system, different types of storage media such as cache, main memory, and hard disks can be configured. During the data processing process, due to factors such as the communication protocol, access path, and bandwidth between the CPU and the storage medium, there are often differences in the access speed of the CPU to the storage medium. Data is usually stored and accessed in a hierarchical storage manner.

According to the speed at which the CPU accesses data, the processor's cache can be divided into Level 1 cache, Level 2 cache, and Level 3 cache. The computer system can also be configured with main memory (or memory), for example, using random access memory (Random Access Memory, RAM), dynamic random access memory (Dynamic Random Access Memory, DRAM), solid state drive , Mechanical hard disk (hard disk driver, HDD) serves as the main memory of the computer system.

There are many types of hard drives, and each type of hard drive has different performance. For example, the data storage speed of SSD is higher than that of mechanical hard disk. If data that is accessed frequently and has high performance requirements is placed on a hard disk with high read and write performance, and data that is not frequently accessed or has low performance requirements and is originally stored in a high-performance hard disk is moved to a low-performance hard disk, performance of the hard drive.

For example, FIG. 1 is a schematic diagram of a multi-layer storage system provided by the present application. From the first layer to the third layer, the storage capacity increases step by step, the access speed decreases step by step, and the cost decreases step by step. As shown in FIG. 1 , the first level includes a register 111 , a first-level cache 112 , a second-level cache 113 and a third-level cache 114 located in the processor 210 . The memory contained in the second level can be used as the main memory of the computer system, that is, memory. For example, dynamic random access memory 121, double data rate synchronous dynamic random access memory (double data date SDRAM, DDR SDRAM) 122, storage-class-memory (SCM) 123. Main memory can be simply referred to as main memory or internal memory, which is the memory that exchanges information with the CPU. The memory contained in the third level can be used as auxiliary memory of the computer system, that is, external memory. For example, network storage 131, solid state drive (Solid State Disk, SSD) 132, hard disk drive 133. The auxiliary storage may be referred to as auxiliary storage or external storage, that is, the hard disk in this embodiment. Compared with main memory, hard disks have large storage capacity and slow access speeds. It can be seen that the closer the memory is to the CPU, the smaller the capacity, the faster the access speed, the greater the bandwidth, and the lower the latency. Therefore, the memory contained in the third level stores data that is not frequently accessed by the CPU, improving data reliability. The memory contained in the second level can be used as a cache device to store data frequently accessed by the CPU, significantly improving the access performance of the system.

(2)Virtual memory

All programs running in the computer system require memory as storage space. If the executed program takes up a lot of memory resources, the memory will be exhausted. To solve this problem, the operating system of the computer system uses virtual memory technology, which uses part of the hard disk space as memory storage space. The operating system provides users with a virtual memory (Virtual Memory) through virtual memory technology. When starting a program, the operating system stores part of the program data in the memory, while leaving the remaining data on the hard disk, and then the program can be started. During program execution, when the data to be accessed by the program is not in the memory, the operating system swaps the required part of the data into the memory, and then continues to execute the program. On the other hand, the operating system swaps out the data in the memory that is not temporarily accessed by the program to the hard disk, thereby freeing up space to store the data that will be transferred into the memory. In this way, the system uses virtual memory technology to provide a memory much larger than the physical memory, that is, virtual memory, which logically implements memory expansion. From a technical perspective, the operating system uses virtual memory technology to set up a " Continuous "virtual storage space" divides the virtual storage space into multiple pages (Page) with continuous address ranges, and maps these pages to physical memory. During the running of the program, the pages of the virtual storage space are moved to Physical memory. When a program needs to access an address space in physical memory, the hardware performs mapping of virtual addresses and physical addresses; when a program references an address space that is not in physical memory, the operating system is responsible for converting the missing part Store into physical memory and re-execute the failed instruction.

(3)Page table entry

Data is stored in units of bytes in memory (for example, memory, hard disk). In order to correctly store or obtain data, each byte unit is given a unique memory address, called a physical address. In virtual memory technology, physical Address is the address used for data access. Logical Address (Logical Address) In a computer system with address conversion function, the address given by the memory access instruction (also called the internal access instruction) is called the logical address, also called the relative address. That is, in machine language instructions, it is used to specify an operand or the address of an instruction. The logical address can be composed of a segment selector plus an offset address relative to the specified segment. The logical address needs to be calculated or transformed by the addressing mode to obtain the actual effective address in the internal memory, that is, the physical address. Linear Address is the middle layer between logical address to physical address conversion. The program code will generate a logical address, or an offset address in the segment, which is added to the base address of the corresponding segment to generate a linear address. The virtual address is the intra-segment offset address in the logical address.

The virtual address space is divided into several units called pages according to a fixed size. Pages correspond to page frames in physical memory. Page frames are blocks into which physical memory is divided. Pages and page frames are generally the same size, such as 4KB, 8KB, 16KB or even larger. In fact, computer systems generally range from 512 bytes to 1GB. This is the paging technology in virtual memory technology.

The page table is a one-to-one relationship table between pages and page frames, and plays an indexing role when querying the page frame corresponding to a page. The corresponding relationship between a page table and a page frame in the page table is called a page table entry. The page table consists of multiple page table entries. The structure of the page table entries depends on the machine architecture, but they are basically the same. For example, the page table entry contains identification and data auxiliary information. The identification is the virtual address and the data is the physical address mapped by the virtual address. The auxiliary information includes valid bits, modification bits, access bits and reserved bits. The valid bit indicates whether the page currently exists in memory. When a thread executed by the processor or processor core attempts to access a page that does not exist in memory, a page fault interrupt will be caused. The protection bit indicates the type of access allowed to the page, such as read-write or read-only. The modification bit and access bit are introduced to record page usage and are used in page replacement. For example, when a memory page is modified by the program, the hardware will automatically set the modification bit. If the program encounters a page fault next time and needs to run the page replacement algorithm to call out the page to make room for the page to be called in, it will It will first access the modification bit to know that the page has been modified, that is, a dirty page. Then the latest page content needs to be written back to the hard disk for storage. Otherwise, it means that the copy content in the memory and the hard disk is synchronized. There is no need to write back to the hard disk; the access bit is also automatically set by the system when the program accesses the page. It is also a value used by the page replacement algorithm. The operating system will determine whether to eliminate this based on whether the page is being accessed. Pages, generally speaking, pages that are no longer used are more suitable for elimination. The reserved bits are used to store other auxiliary information, such as the attraction domain identification in this embodiment.

Embodiments of the present application provide a data processing method. The first processor core obtains a first memory access request. The first memory access request is used to instruct the first processor core to perform data processing on the data stored in the first memory space. If The first memory space is the storage space of the memory associated with the first attraction domain of the first processor core. After the first processor core determines the address of the first memory space, it executes the first memory space according to the address of the first memory space. Data processing of access requests. The processor cores are associated with the memory space associated with the attraction domain through the attraction domain, and then the attraction domain is associated with the metadata used to describe the attributes of the data stored in the memory space associated with the attraction domain, so that multiple processor cores can operate in parallel. When performing memory access, the metadata associated with the respective attraction domains and the data in the memory space can be processed. This avoids access conflicts when multiple processor cores perform memory access in parallel, reduces the overall duration of memory access, and improves memory access. s efficiency.

It should be noted that, in addition to being executed by the first processor core, the data processing method in the embodiment of the present application may also be executed by a processor. If the data processing method is executed by the processor, the difference from the method executed by the first processor core is that the first memory space is the storage space of the memory associated with the first attraction domain of the processor.

The implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Figure 2 is a schematic architectural diagram of a computer system provided by an embodiment of the present application. As shown in FIG. 2 , computer system 200 includes processor 210 , memory 220 and bus 230 .

The processor 210 can be a graphics processing unit (GPU), a central processing unit (CPU), other general-purpose processors, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (application-specific integrated circuit) specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor, etc.

Processor 210 includes at least one processor core. The processor core, also known as the core, is the most important component of the processor. Various processor cores have fixed logical structures, such as first-level cache, second-level cache, execution unit, instruction level unit, bus interface and other logical units. Each processor core of the processor 210 has a unique processor core identifier (identifier, id) in the operating system.

For example, as shown in FIG. 2 , the processor 210 includes a processor core 211 , a memory management unit (Memory Management Unit, MMU) 212 and a processor core 215 . The memory management unit 212 is connected to the memory 220 and the hard disk through the bus 230. The hard disk in this embodiment can also be called external memory relative to the memory 120 .

The memory management unit 212 is a hardware unit in the processor or processor core. The memory management unit 212 includes an address translation unit 213 and a page table walk unit (Table Walk Unit, TWU) 214. The memory management unit 212 is mainly used to manage the control lines of virtual memory and physical memory, and map virtual addresses to physical addresses. Typically there is one memory management unit per processor core. In this embodiment, the processor core 211 may be connected to one or more storage units. For example, the first storage unit is the address translation unit 213, and the second storage unit is the memory 220. In some possible embodiments, the memory management unit 212 may be provided within the processor core 211 . Optionally, the address translation unit 213 in this embodiment may also be called an address translation cache (Translation Lookaside Buffer, TLB).

The address translation unit 213 is used to store the correspondence between the virtual address and the physical address, that is, the page table entry. If the virtual address requested by the CPU exists in the corresponding relationship between the virtual address and the physical address of the address translation unit 213, the address translation unit 213 will quickly match a page table entry containing the virtual address of the access request, and will confirm the page table entry. It is sent to the CPU, and the CPU accesses the memory 220 according to the physical address contained in the obtained page table entry. In this way, compared to when the processor core 211 does not use the memory management unit 212 to perform memory access, it needs to obtain the page table entry from the memory 220 and then obtain the physical address from the page table entry. The memory management unit 212 can use the address translation unit. 213 obtains the physical address without accessing the memory 220 to realize the translation from the virtual address to the physical address, improving the translation speed from the virtual address to the physical address.

For example, the process of the address translation unit 213 matching the page table entry of the virtual address includes: the memory management unit 212 extracts the virtual address from the access request, and sends the virtual address to the address translation unit 213, where the address translation unit 213 can access and store the page. Query whether there is a page table entry that is the same as the virtual address in the storage space of the table entry; if so, it means that the address translation unit hits (TLB hit); if not, it means that the address translation unit misses (TLB miss). Optionally, the page table entry queried by the memory management unit 212 in the address translation unit 213 is invalid. For example, the valid bit of the page table entry indicates that the page table entry is invalid, or may also indicate that the address translation unit misses.

In this embodiment, if the virtual address requested by the CPU does not exist in the corresponding relationship between the virtual address and the physical address of the address translation unit 213, the page table traversal unit 214 queries and obtains the page table entry in the memory 220. The process in which the page table traversal unit 214 queries and obtains page table entries in the memory 220 includes: the page table traversal unit 214 performs a page table traversal. (Translation Table Walk) step: access the memory 120 multiple times according to multi-level page tables such as the first-level page table and the second-level page table to obtain the address of the page table entry, and then obtain the page table entry in the memory 220 according to the address of the page table entry.

Optionally, the memory management unit 212 of the processor 210 may be an integrated memory controller (IMC).

In this embodiment of the present application, the processor core 211 can obtain the first memory access request when the program needs to access the first data. The first memory access request is used to instruct the processor core 211 to perform data processing on the data stored in the first memory space. , after determining the address of the first memory space, the processor core 211 executes the data processing of the first memory access request according to the address of the first memory space.

Optionally, the above-mentioned first memory access request may be generated by the processor core 211 when a thread executed by the processor core 211 needs to access the first data. The first memory access request may be a data access instruction. The data access instruction is a Load/Store instruction. The Load/Store instruction is used to instruct data transfer between the register and the memory. The Load/Store instruction includes the information that the processor core 211 wants to access. The virtual address of the data.

In addition, the above-mentioned first memory access request may also be generated by a processor core other than the processor core 211 when a thread executed by a processor core other than the processor core 211 (for example, the processor core 215) needs to access the first data. The processor core of the first memory access request is sent to the processor core 211 . The first memory access request may be a proxy instruction, used to instruct the processor core 211 to perform data processing on the data stored in the first memory space, and send the obtained data to the processor core that generated the first memory access request.

The memory 220 and the hard disk are memories connected to the processor 210 . Memory is a memory device used to store programs and various data. The larger the memory capacity, the slower the access speed. On the contrary, the smaller the memory capacity, the faster the access speed. Access speed refers to the data transfer speed when writing data or reading data to the memory. Access speed can also be called read and write speed. Memory can be divided into different levels based on storage capacity and access speed.

In this embodiment, the memory 220 can store multi-level page tables. For example, the first-level page table is used to store the first-level page table index, the second-level page table is used to store the second-level page table index, and the third-level page table is used to store the first-level page table index. The three-level page table index and the fourth-level page table are used to store page table entries. Optionally, as shown in the dotted box in FIG. 2 , the dotted line between the dotted box and the memory 220 indicates that level one to level four page tables are stored in the memory 220 . The first-level page table can be Page Map Level 4 (PML4), the second-level page table can be Page Directory Pointer Table (PDPT), and the third-level page table can be Page Directory table (Page Directory). , PD), the fourth-level page table can be a page table (Page Table, PT), and the page table stores one or more page table entries. When the processor core 211 queries the page table entries in the multi-level page table according to the virtual address, the processor core 211 sequentially queries the first-level page table, the second-level page table and the second-level page table index according to the first-level page table index, the second-level page table index and the third-level page table index. The page table, the third-level page table and the fourth-level page table obtain the address of the page table entry in the memory 220, and obtain the page table entry in the memory 220 according to the address.

The memory 220 may also store metadata, which is information used to describe the data attributes (properties) of the physical pages of the memory space in the memory 220 . For example, active list, free list, LRU list, etc. The active list is used to maintain active physical pages, and the free list is used to maintain idle physical pages. The LRU list is used to maintain the proximity of active physical pages. The least recently used strategy (Least Recently Used, LRU) is a commonly used page replacement algorithm, which selects the most recently unused pages for elimination. LRU will use a linked list to maintain the access status of each data in the cache, and adjust the position of the data in the linked list based on the real-time access of the data. Then, the position of the data in the linked list will indicate whether the data has been accessed recently or is already there. Haven't visited in a while.

Please continue to refer to Figure 2. The bus 230 can be different types of buses for different connection objects. For example, the bus 230 between the processor 210 and the memory 220 may be a DDR3 interface standard bus, and the bus 230 between the processor 210 and the external memory may be a Peripheral Component Interconnect Express (PCIe) interface standard. bus. With the PCIe interface standard bus, the external memory can be PCIe SSD, PCIe SSD (PCIe solid state drive) (driver) is a high-speed expansion card that connects computer system 200 to its peripheral devices. In other words, PCIe SSD takes the form of a plug-in card built into the computer. Compared with interfaces such as SATA/SAS, PCIe uses a multi-queue method in data transmission, which can achieve the purpose of concurrent data transmission on a single disk and improve the efficiency of the data interface.

Combined with the computer system 200, the data processing method provided in this embodiment can be applied in memory expansion scenarios, such as memory expansion scenarios implemented through virtual memory technology. Specifically, the data processing method in the embodiment of the present application can be applied in scenarios such as memory expansion of data center servers and memory expansion of cloud computing servers.

In the application scenarios of memory expansion of data center servers and memory expansion of cloud computing servers, the server's operating system will process the thread of the user terminal's request based on the request generated by the user terminal (such as mobile phone, computer, tablet computer) or itself. Assigned to the processor core 211, the processor core 211 generates a first memory access request according to the thread. The first memory access request is used to instruct the processor core 211 to perform data processing on the data stored in the first memory space. The first memory space is the processing The storage space of the memory associated with the first attraction domain of the processor core 211, wherein each processor core is associated with at least one attraction domain, and the same attraction domain is only associated with one processor core. The processor core 211 determines the address of the first storage space according to the first memory access request, and then performs the data processing of the first memory access request according to the address of the first memory space. Through the attraction domain, the processor core is associated with the memory space associated with the attraction domain, and then the attraction domain is associated with metadata, so that multiple processor cores of the server can access the metadata associated with their respective attraction domains when performing memory access in parallel. The data and data in the memory space are processed, which avoids the access conflict of parallel memory access by multiple processor cores and reduces the overall duration of memory access. Therefore, the data processing method provided by this embodiment is applied in the application scenarios of memory expansion of data center servers and cloud computing servers with large concurrent accesses, which greatly improves the concurrent access efficiency of memory access and reduces concurrency. The overall access latency of the access.

FIG. 2 is only a schematic diagram of a system architecture provided by an embodiment of the present application. The positional relationship between the devices, devices, modules, etc. shown in FIG. 2 does not constitute any limitation.

Next, please refer to Figure 3 for a detailed explanation of the data processing method. In this embodiment, the first processor core is the processor core 211 in FIG. 2 and the processor core 211 accesses the first data as an example for explanation.

Step 310: The processor core 211 obtains the first memory access request.

As shown in the implementation of step S310 in Figure 3 and the dotted line, the first memory access request may be that the processor core 211 or a processor core outside the processor core 211 needs to read/write the first memory in the memory 220 during the execution of the thread. The first memory access request includes the virtual address of the first storage space. The first memory access request is used to instruct the processor core 211 to perform data processing on the data stored in the first memory space. The first memory space is the storage space of the memory 220 associated with the first attraction domain of the processor core 211 .

As a possible implementation, the first attraction domain includes an association relationship between a memory space address associated with the processor core 211 and an attraction domain identifier. The attraction domain identifier of the association relationship in the first attraction domain is used to globally uniquely indicate the location to which the association relationship belongs. The first attraction domain, the memory space address is the address of the memory space associated with the first attraction domain to which the association relationship belongs. After step 330, taking the first attraction domain as an example, the structure of the attraction domain will be described in detail with reference to Figure 7, which will not be described again.

In virtual memory technology, the processor core usually uses page table entries to convert virtual addresses and physical addresses. Therefore, this embodiment can use page table entries as an association relationship. The memory space address (virtual address) contained in a page table entry and physical address) is associated with the attraction domain represented by the attraction domain identifier.

For example, as shown in FIG. 4 , this embodiment can also set the attraction domain identifier in the reserved bit of the page table entry, so that the page table entry can carry the attraction domain identifier without modifying the microarchitecture of the processor. The attraction domain identifier in the page table entry may be the processor core identifier. For example, the attraction domain identifier of the first attraction domain is the processor core identifier of the processor core 211, so that the page table entry represents the memory space, the attraction domain and the processor. nuclear correlation.

Step 320: The processor core 211 determines the address of the first memory space.

The above-mentioned address of the first memory space refers to the physical address of the first memory space. Taking the association relationship as a page table entry as an example, first, the processor core 211 queries the address translation unit 213 according to the virtual address of the first memory space whether there is a first page table entry with the same identifier as the virtual address. If so, it indicates that the address If the translation unit hits (TLB hit), perform step 330; if not, it means that the address translation unit misses (TLB miss), and the processor core 211 uses the page table traversal unit 214 to obtain the first page table entry from the memory 220. Then, the processor core 211 determines the physical address of the first memory space according to the corresponding relationship between the virtual address and the physical address in the first page table entry.

Optionally, when the first memory space is the storage space of the memory 220 associated with the first attraction domain of the processor core 211, the memory management unit 212 determines that the first page table entry belongs to the first attraction domain of the processor core 211. After entering the domain, the address translation unit loading (Install) step is performed, that is, the first page table entry is copied, and the copied first page table entry is stored in the address translation unit 213 of the processor core 211 . After the processor core 211 stores the first page table entry to the address translation unit 213, if the processor core 211 needs to perform memory access based on the first page table entry again, it can directly hit the first page table entry in the address translation unit 213. Avoiding performing the page table entry traversal operation again to obtain the first page table entry from the memory 220 reduces the computational memory overhead and time overhead caused by the page table entry traversal operation, thereby improving memory access efficiency.

Step 330: The processor core 211 executes the data processing of the first memory access request according to the address of the first memory space.

The processor core 211 uses the memory management unit 212 to perform data processing of the first memory access request according to the physical address of the first memory space.

According to the first memory access request generated by the processor core 211 or a processor core other than the processor core 211, the memory management unit 212 performs the steps of data processing of the first memory access request on the physical address of the first memory space as follows:

Scenario 1: The first memory access request is generated by the processor core 211.

As shown in FIG. 5 , the memory management unit 212 sends the physical address of the first memory space to the memory 220 , receives the first data of the storage space of the physical address of the first memory space returned by the memory 220 , and sends the physical address of the first memory space to the processor core 211 . Register 111 sends the first data.

Case 2: The first memory access request is generated by the processor core 215 .

As shown in Figure 6, numbers 1-4 in Figure 6 represent the data transmission sequence. The memory management unit 212 sends the physical address of the first memory space to the memory 220, and receives the storage of the physical address of the first memory space returned by the memory 220. first data in the space, and sends the first data to the register of the processor core 215.

Therefore, the processor core and the memory space are associated through the attraction domain, and the processor core is used to perform data processing on the memory space associated with its own attraction domain, allowing different processor cores to perform data processing on the addresses of different memory spaces. , and then when different processor cores perform data processing, they operate on the metadata used to describe the data in the memory space to which their respective attraction domains belong. For example, the processor core 211 is configured to determine the address of the memory space according to the page table entry belonging to the first attraction domain, and perform data processing on the address of the memory space. Assume that the first metadata is part of the metadata in the memory 220 used to describe the data of the address of the memory space associated with the first attraction domain, because the processor core 211 only performs data on the data of the address of the memory space associated with the first attraction domain. Processing, the processor core 211 only needs to operate on the first metadata, thereby associating the processor core 211, the first attraction domain and the first metadata. Therefore, different processor cores operate on different portions of the metadata in memory 220, and different processor cores do not operate on the same portion of metadata. When one of the multiple processor cores is performing data processing in the memory space, the other processor cores do not need to wait for the processor core that is performing data processing to complete the data processing and metadata operations before executing the new memory space. data processing. Furthermore, multiple processor cores can process data concurrently, which avoids access conflicts when multiple processor cores perform memory access in parallel, reduces the overall duration of memory access, and improves the efficiency of memory access.

The attraction domain of the present application will be introduced in detail below with reference to Figures 7-9. For convenience of description, the first attraction domain associated with the processor core 211 will be taken as an example.

First, the structure of the first attraction domain is described. Please refer to FIG. 7 . FIG. 7 is a schematic structural diagram of an attraction domain provided by an embodiment of the present application.

The first attraction domain 700 includes one or more page table entries, and the attraction domain identifier in the one or more page table entries is the processor core identifier of the processor core 211 .

Since the metadata in the memory is divided into multiple isolated parts by the attraction domain, the processor core 211 is only associated with the first attraction domain 700 when performing data processing of the first memory access request according to the physical address of the first memory space. The first metadata of the data in the memory space is operated. Therefore, the first metadata may be used as data included in the first attraction domain 700 .

Optionally, the first metadata may include active list, free list, etc.

As a possible implementation manner, the page table entries included in the first attraction domain 700 may be page table entries stored in the address translation unit 213 , or may be page table entries stored in the memory 220 .

It should be noted that the page table entries included in the first attraction domain 700 can be dynamically adjusted. For example, the processor core 211 implements page table entry entry according to the access frequency to the memory space, that is, adds the page table entry to the first attraction domain 700 . an attraction domain 700, thereby realizing the expansion of the first attraction domain 700.

Next, taking the first attraction domain 700 as an example, the expansion steps of the attraction domain will be described in detail with reference to FIG. 8 .

Step 810: The processor core 211 queries the second page table entry in the address translation unit 213 according to the second memory access request, and a TLB miss occurs.

The second memory access request is used to instruct the processor core 211 to perform data processing on the second data stored in the second memory space corresponding to the virtual address of the second page table entry.

Step 820: The processor core 211 obtains the second page table entry from the memory 220.

The processor core 211 uses the page table traversal unit 214 to perform the page table traversal step to obtain the second page table entry from the memory 220. The attraction field identifier in the second page table entry is an initial value, indicating that the second memory space is not associated with any attraction. Domain association.

Step 830: When the cumulative number of times of obtaining the second page table entry is greater than the preset threshold, the processor core 211 performs data processing on the second memory access request according to the address of the second page table entry in the second memory space, and processes the second memory access request. The second page table entry is added to the first attraction field.

Each time the processor core 211 receives the second memory access request, it uses the page table traversal unit 214 to obtain the second page table entry from the multi-level page table of the memory 220. PML4E, PDPTE, PDE and PTE in Figure 8 represent respectively The second memory access requests the data queried in PML4, PDPT, PD and PT. The processor core 211 may use the first counter to record the cumulative number of times the page table traversal unit 214 obtains the second page table entry from the memory 220 . For example, when the page table traversal unit 214 obtains the second page table entry from the memory 220 for the first time, the register is used as the first counter, and the value of the first counter is incremented by one each time the second page table entry is obtained from the memory 220 . Optionally, the first threshold may be 5 times, 8 times, 15 times, etc.

Optionally, adding the second page table entry to the first attraction domain 700 by the processor core 211 also includes: the processor core 211 uses the page table traversal unit 214 to copy the second page table entry and stores the copied second page table entry. Enter the address translation unit 213.

In addition, the processor core 211 can also add the virtual page corresponding to the second page table entry to the activity table of the first attraction domain 700, that is, the processor core 211 adds the virtual page corresponding to the second page table entry in the processor core footprints (footprints). The virtual pages are added to the active table, and the processor core footprint sequence records which addresses corresponding to the virtual pages the processor checks to perform data processing.

The processor core 211 adds the second page entry to the first attraction domain, which may be by modifying the attraction domain identifier of the second page entry to the attraction domain identifier of the first attraction domain. After the processor core 211 stores the second page table entry to the address translation unit 213, if the processor core 211 needs to perform memory access based on the second page table entry again, the second page table entry can be directly queried in the address translation unit 213. , avoid performing the page table entry traversal operation again to obtain the second page table entry from the memory 220, reducing the computational memory overhead and time overhead caused by the page table entry traversal operation, thereby improving the memory access efficiency and improving the address translation unit 213 storage resource utilization.

In addition to the expansion of the first attraction domain 700 , the dynamic adjustment of the page table entries contained in the first attraction domain 700 by the processor core 211 may also include the reduction of the first attraction domain 700 . The steps for reducing the first attraction domain 700 will be described in detail below with reference to Figure 9 . ①-⑥ in Figure 9 represent the execution order of the steps.

Step 910: The processor core 211 queries the third page table entry in the address translation unit 213 according to the third memory access request, and a TLB miss occurs.

The third memory access request is a proxy instruction sent by a processor core other than the processor core 211 to instruct the processor core 211 to perform data processing on the third data stored in the third memory space corresponding to the virtual address of the third page table entry. .

Taking the processor core that sends proxy instructions to the processor core 211 as the processor core 215 as an example, the processor core 215 obtains a memory access request, and the virtual address contained in the memory access request is not found in the address translation unit of the processor core 215 If a TLB miss occurs in the third page table entry, the processor core 215 uses its own page table traversal unit to obtain the third page table entry in the memory 220. When the attraction domain identifier of the third page table entry is the attraction domain identifier of the first attraction domain 700, a proxy instruction is sent to the processor core 215 to the processor core 211, where the proxy instruction includes the virtual address of the third memory space.

Step 920: The processor core 211 obtains the third page table entry from the memory 220.

The processor core 211 uses the page table traversal unit 214 to perform the page table traversal step to obtain the third page table entry from the multi-level page table in the memory 220. PML4E, PDPTE, PDE and PTE in Figure 9 respectively represent the third memory access request. Data queried in PML4, PDPT, PD and PT. The attraction domain identifier in the third page entry is the attraction domain identifier of the processor core 211 .

Step 930: The processor core 211 migrates the third page table entry to the attraction domain of the processor core that has sent the third memory access request the most.

Assume that the processor core 215 is the processor core that sends the third memory access request to the processor core 211 the most. The processor core 211 migrates the third page table entry to the attraction domain of the processor core 215, which may be the third memory access request. The attraction domain identification of the three-page table entry is modified to the attraction domain identification of the attraction domain of the processor core 215 .

Each time the processor core 211 receives the proxy instruction, it uses the page table traversal unit 214 to obtain the third page table entry from the memory 220 . For each processor core that sends a proxy instruction to the processor core 211, the processor core 211 may use a counter to record the third data that the processor core other than the processor core 211 instructs the processor core 211 to store in the third memory space. The number of times data processing is performed.

The processor core 211 may record the number of times the proxy instruction sent by the processor core 215 is received through a second counter. For example, when the processor core 211 receives the proxy instruction sent by the processor core 215 for the first time, the register is used as the second counter, and each time the processor core 215 receives the proxy instruction sent by the processor core 215, the value of the second counter is incremented by one. Optionally, the second threshold may be 5 times, 8 times, 15 times, etc.

Optionally, the processor core 211 migrates the third page table entry to the attraction domain of the processor core 215, which also includes: the processor core 211 uses the page table traversal unit 214 to copy the third page table entry and copies the third page table entry. The page table entry is stored in the address translation unit 213.

In addition, the processor core 211 can also add the virtual page corresponding to the third page table entry to the activity table of the attraction domain of the processor core 215, that is, the processor core 215 adds the virtual page corresponding to the third page table entry in the processor core footprint. Page is added to the activity table.

As a result, the processor core 211 realizes the migration of the third page table entry between different attraction domains. When the processor core 215 performs data processing in the third memory space again, it does not need to send a proxy instruction to the processor core 211. Instead, The processor core 215 performs data processing in the third memory space according to the third page table entry in the address translation unit connected to itself, which improves the efficiency of memory access and reduces the overhead of communication resources between processor cores. On the other hand, the combination of migration and domain entry realizes the dynamic adjustment of the attraction domain, so that the page table entries in the attraction domain are page table entries with higher access frequency by the processor core, thereby improving the utilization of the storage resources of the address translation unit. .

In addition to more page table entries occupying the storage resource utilization of the address translation unit, swapping/ After swapping out the data, all processor cores update the page table entries of the connected address translation units, triggering TLB shootdown to suspend the threads being executed by all processor cores. There is a problem of low utilization of the computing resources of the processor cores. . In order to improve the utilization of the computing resources of the processor core, in this embodiment, the processor core periodically updates its own address translation unit.

Taking the processor core 211 as an example, the processor core 211 uses the page table traversal unit 214 to periodically update the address translation unit 213 . The page table traversal unit 214 determines the attraction domain identifiers of all page table entries in the address translation unit 213 , retains the page table entries in the address translation unit 213 whose attraction domain identifier is the attraction domain identifier of the first attraction domain 700 , and deletes the page table entries in the address translation unit 213 The attraction domain identifier is not a page table entry of the attraction domain identifier of the first attraction domain 700 .

Each two adjacent cycles of the above-mentioned update address translation unit 213 may be equal or unequal. The length of the period can be 10 seconds, 20 seconds, 30 seconds, or any other length.

Therefore, the processor core 211 uses the page table traversal unit 214 to complete the refresh of the page table entries, thereby avoiding the address translation unit 213 from querying the page table entries that do not belong to the first attraction domain, reducing the number of TLB shootdown triggers, thereby improving the processor The utilization of computing resources of the core improves the memory access performance of the processor 210 .

It should be noted that in this embodiment, when the processor core 211 or the processor core 215 queries the page table entry in the address translation unit and a TLB miss occurs, neither the processor core 211 nor the processor core 215 initiates a TLB shootdown, thereby further improving the efficiency of memory access.

The data processing method provided according to this embodiment is described in detail above with reference to FIGS. 1 to 9 . The data processing device provided according to this embodiment will be described below with reference to FIG. 10 .

Figure 10 is a schematic structural diagram of a possible data processing device provided by this embodiment. These data processing devices can be used to implement the functions of the processor or processor core in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments.

As shown in Figure 10, the data processing device 1000 includes a transceiver module 1010 and a processing module 1020. The data processing device 800 is used to implement the functions of the processor core 211 in the above method embodiment shown in Figure 3, Figure 8 or Figure 9.

The transceiver module 1010 is used to obtain a first memory access request. The first memory access request is used to instruct the first processor core to perform data processing on the data stored in the first memory space. The first memory space is the first attraction of the first processor core. The memory storage space associated with the domain.

The processing module 1020 is configured to determine the address of the first memory space, and perform data processing of the first memory access request according to the address of the first memory space.

As a possible implementation, the first attraction domain includes an association relationship between a memory space address and an attraction domain identifier. The attraction domain identifier is used to indicate the attraction domain to which the association relationship belongs. The memory space address is the memory associated with the attraction domain to which the association relationship belongs. The address of the space.

For example, the association is a Page Table Entry (PTE), and the attraction field identifier is set in the reserved bit of the page table entry. Using the existing reserved bits in the page table entry to record the attraction domain identifier, the processor can identify the attraction domain identifier without modifying the microarchitecture.

In another possible implementation, the first memory access request may be made by a thread outside the first processor core when a thread executed by a processor core outside the first processor core needs to read and write data in the first memory space. The processor core generates and sends it to the first processor core.

The data processing device 1000 can also dynamically adjust the association relationships included in the attraction domain.

For example, the transceiver module 1010 is also used to obtain the second memory access request. The processing module 1020 is used to perform steps 810 to 830 in Figure 8 .

As another example, the transceiving module 1010 is also used to obtain the third memory access request, and the processing module 1020 is used to execute steps 910 to 930 in Figure 9 .

As a possible implementation manner, the association relationship of the first attraction domain may be stored in a storage unit connected to the first processor core, and the storage unit is used to store and query the association relationship contained in the first attraction domain. The first memory access request includes the virtual address of the first memory space, and the associated memory space includes the physical address of the first memory space. When determining the address of the first memory space, the processing module 1020 is specifically configured to: query the association relationship in the storage unit according to the virtual address of the first memory space, obtain the first association relationship, and determine the first memory space according to the first association relationship. physical address.

Alternatively, the storage unit may be an address translation unit.

In addition, the processing module 1020 is also configured to: delete associations in the storage unit that do not belong to the first attraction domain every preset period.

It should be understood that the data processing device 1000 in the embodiment of the present application can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The above PLD can be a complex program. Logic device (complex programmable logical device, CPLD), field-programmable gate array (field-programmable gate array, FPGA), general array logic (generic array logic, GAL) or any combination thereof.

The data processing device 1000 according to the embodiment of the present application may correspond to performing the method described in the embodiment of the present application, and the above and other operations and/or functions of the various units in the data processing device 1000 are in order to implement FIG. 3, FIG. 8 or FIG. The corresponding processes of each method in 9 will not be repeated here for the sake of brevity.

The method steps in this embodiment can be implemented by hardware or by a processor executing software instructions. Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (random access memory, RAM), flash memory, read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM) , PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or other well-known in the art any other form of storage media. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage media may be located in an ASIC. Additionally, the ASIC can be located in a computing device. Of course, the processor and storage medium may also exist as discrete components in a computing device.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer program or instructions may be transmitted from a website, computer, A server or data center transmits via wired or wireless means to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media, such as floppy disks, hard disks, and magnetic tapes; they may also be optical media, such as digital video discs (DVDs); they may also be semiconductor media, such as solid state drives (solid state drives). ,SSD). The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of various equivalent methods within the technical scope disclosed in the present application. Modification or replacement, these modifications or replacements shall be covered by the protection scope of this application. Therefore, this application The scope of protection shall be based on the scope of protection of the claims.

Claims

A data processing method, characterized in that the method is applicable to a computer system including a processor and a memory, and the method is executed by the first processor core of the processor, including:

Obtain a first memory access request. The first memory access request is used to instruct the first processor core to perform data processing on data stored in a first memory space. The first memory space is the first memory space of the first processor core. The storage space of the memory associated with the first attraction domain;

Determine the address of the first memory space;

Perform data processing of the first memory access request according to the address of the first memory space.
The method of claim 1, wherein the first attraction domain includes an association relationship between a memory space address and an attraction domain identifier, and the attraction domain identifier is used to indicate the attraction domain to which the association relationship belongs, and the memory space The address is the address of the memory space associated with the attraction domain to which the association relationship belongs.
The method of claim 2, further comprising:

Obtain a second memory access request, the second memory access request is used to instruct the first processor to perform data processing on the data stored in the second memory space, and the second memory space is not associated with any attraction domain;

If the cumulative number of times the first processing core obtains the second memory access request is greater than a preset threshold, the association of the address of the second memory space is added to the first attraction domain.
The method according to claim 2, characterized in that the first processor core is connected to a storage unit, the storage unit is used to store and query the association relationships contained in the first attraction domain, and the first memory The access request includes the virtual address of the first memory space, the associated memory space includes the physical address of the first memory space, and determining the address of the first memory space includes:

Query the association relationship in the storage unit according to the virtual address of the first memory space to obtain the first association relationship;

Determine the physical address of the first memory space according to the first association relationship.
The method of claim 4, further comprising:

Every preset period, associations in the storage unit that do not belong to the first attraction domain are deleted.
The method according to any one of claims 2 to 5, characterized in that the association relationship is a page table entry, and the attraction domain identifier is set in a reserved bit of the page table entry.
A data processing device, characterized in that it includes:

A transceiver module configured to obtain a first memory access request. The first memory access request is used to instruct the first processor to perform data processing on the data stored in the first memory space. The first memory space is the third memory space. The storage space of the memory associated with the first attraction domain of a processor core;

A processing module used to determine the address of the first memory space;

The processing module is also configured to perform data processing of the first memory access request according to the address of the first memory space.
The device according to claim 7, wherein the first attraction domain includes an association relationship between a memory space address and an attraction domain identifier, and the attraction domain identifier is used to indicate the attraction domain to which the association relationship belongs, and the memory space The address is the address of the memory space associated with the attraction domain to which the association relationship belongs.
The device according to claim 8, characterized in that the transceiver module is further used to obtain a second memory access request, and the second memory access request is used to instruct the first processor to check the information stored in the second memory space. The data performs data processing, and the second memory space is not associated with any attraction domain;

The processing module is also configured to add the association of the address of the second memory space to the first attraction when the cumulative number of times the first processing core obtains the second memory access request is greater than a preset threshold. area.
The device according to claim 8, characterized in that the first processor core is connected to a storage unit, the storage unit is used to store and query the association relationships contained in the first attraction domain, and the first memory The access request includes the virtual address of the first memory space, the associated memory space includes the physical address of the first memory space, and the processing module is also used to:

Query the association relationship in the storage unit according to the virtual address of the first memory space to obtain the first association relationship;

Determine the physical address of the first memory space according to the first association relationship.
The device according to claim 10, characterized in that the processing module is also used to:

Every preset period, associations in the storage unit that do not belong to the first attraction domain are deleted.
The device according to any one of claims 8-11, wherein the association relationship is a page table entry, and the attraction field identifier is set in a reserved bit of the page table entry.
A processor, characterized in that the processor includes a processor core, and the processor core is used to execute the operating steps of the method described in any one of claims 1-6.
A computing system, characterized in that the computer system includes a memory and a processor as claimed in claim 13, and the processor is configured to perform the operating steps of the method as claimed in any one of claims 1 to 6, The data processing of the memory access request is performed at the address of the memory storage space.