WO2023216853A1 - 控制器和车辆 - Google Patents

控制器和车辆 Download PDF

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Publication number
WO2023216853A1
WO2023216853A1 PCT/CN2023/090083 CN2023090083W WO2023216853A1 WO 2023216853 A1 WO2023216853 A1 WO 2023216853A1 CN 2023090083 W CN2023090083 W CN 2023090083W WO 2023216853 A1 WO2023216853 A1 WO 2023216853A1
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WO
WIPO (PCT)
Prior art keywords
wake
circuit
transceiver
control unit
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/090083
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English (en)
French (fr)
Inventor
何永斌
蒋锦
朱书阳
钟路平
余子皓
韩冰
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BYD Co Ltd
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BYD Co Ltd
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Publication of WO2023216853A1 publication Critical patent/WO2023216853A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • B60R16/023—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for transmission of signals between vehicle parts or subsystems
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

Definitions

  • the present disclosure relates to the field of electronic technology, and more specifically, to a controller and a vehicle.
  • An object of the present disclosure is to provide a new technical solution for a controller.
  • Another object of the present disclosure is to provide a new technical solution for a vehicle, which includes the controller, a CAN bus and a power supply.
  • a controller includes a power management circuit, a micro control unit, a first CAN transceiver, or a logic circuit and a wake-up trigger latch circuit; the power management circuit is used to control the power supply to power the micro control unit; the micro control The power hold signal port of the unit is connected to the first input end of the OR logic circuit, and the output end of the OR logic circuit is connected to the enable end of the power management circuit; the first control end of the micro control unit is respectively It is connected to the standby mode setting port of the first CAN transceiver and the latch control terminal of the wake-up trigger latch circuit; the first signal sending terminal of the first CAN transceiver is connected to the latch control terminal of the wake-up trigger latch circuit.
  • the trigger input terminal is connected, and the wake-up output terminal of the wake-up trigger latch circuit is connected with the second input terminal of the OR logic circuit; the OR logic circuit is used to maintain the power output of the signal port according to the power supply of the micro control unit.
  • the hold signal and the wake-up signal output by the wake-up output terminal of the wake-up trigger latch circuit control the power on or off of the micro control unit, wherein the wake-up trigger latch circuit is used to power off the micro control unit.
  • the wake-up signal is latched in the first level state.
  • the micro control unit is configured to control the first CAN transceiver to enter standby mode through the first control terminal and control the wake-up trigger latch circuit to enter pre-latching when sleep is required. state, and sets the power hold signal port to the second level state.
  • the first CAN transceiver is configured to monitor the CAN bus in the standby mode, and when a wake-up message is monitored, trigger the wake-up trigger through the first signal transmitter (RXD)
  • the latch circuit enters the latch state and outputs a first level wake-up signal.
  • the micro control unit is further configured to set the power hold signal port to the first A level state, and through the first control terminal, the first CAN transceiver is controlled to enter the normal operating mode and the wake-up trigger latch circuit is controlled to unlock.
  • the third input end of the OR logic circuit is used to access a hard-wired wake-up signal, and the hard-wired wake-up signal is used to control powering on of the micro control unit.
  • the wake-up trigger latch circuit is used for switching from the first level to the second level at the first signal transmitting end (RXD) after entering the pre-latch state. In this case, it enters the latch state and outputs a high-level wake-up signal.
  • the wake-up trigger latch circuit includes a falling edge triggered flip-flop.
  • the flip-flop is a D flip-flop (U2); the asynchronous reset terminal (1CLR-) of the first channel of the D flip-flop (U2) and the latch control terminal of the wake-up trigger latch circuit Connect; the clock terminal (1CLK-) of the first channel of the D flip-flop (U2) is connected to the trigger input terminal of the wake-up trigger latch circuit; the output terminal (1Q) of the first channel of the D flip-flop (U2) is connected to The wake-up output terminal of the wake-up trigger latch circuit is connected.
  • the wake-up trigger latch circuit further includes: a seventh capacitor (C7), a ninth capacitor (C9), and a tenth capacitor (C10);
  • the power terminal (VCC) of the D flip-flop (U2), the input terminal (1D) of the first channel of the D flip-flop (U2), and the asynchronous setting terminal (1PRE-) of the first channel of the D flip-flop (U2) are respectively connected with all The power supply terminal connection of the above-mentioned wake-up trigger latch circuit;
  • the asynchronous reset terminal (1CLR) of the first channel of the D flip-flop (U2) is connected to ground through the seventh capacitor (C7);
  • the asynchronous set terminal (1PRE-) of the first channel of the D flip-flop (U2) is connected to ground through the tenth capacitor (C10);
  • the power terminal (VCC) of the D flip-flop (U2) is connected to ground through the ninth capacitor (C9).
  • the wake-up trigger latch circuit includes a first switch control unit and a second switch control unit;
  • the first switch control unit is connected to the first signal sending end (RXD) of the first CAN transceiver, and the second control unit is connected to the first control end of the micro control unit; wherein, the third When a switch control unit is turned on, it will trigger the second switch control unit to turn on. After the second switch control unit is turned on, the conduction state of the first switch control unit is maintained, so that the first switch control unit The unit latches the wake-up signal in a first level state.
  • the first switch control unit includes a fourth transistor (Q4), a fourth diode (D4), an eighth resistor (R8), and an eleventh resistor (R11).
  • the second switch control unit includes a fifth transistor (Q5), a sixth transistor (Q6), a tenth resistor (R10), and a thirteenth resistor (R13), wherein the fourth transistor (Q4) is PNP type transistor, the fifth transistor (Q5) and the sixth transistor (Q6) are NPN type transistors.
  • the base of the fourth transistor (Q4) is connected to the anode of the fourth diode (D4), and the cathode of the fourth diode (D4) is connected to the trigger input end of the wake-up trigger latch circuit;
  • the emitter of the fourth transistor (Q4) is connected to the power end of the wake-up trigger latch circuit, and the collector of the fourth transistor (Q4) is connected to the first end of the eleventh resistor (R11).
  • the second end of the eleventh resistor (R11) is connected to the first end of the thirteenth resistor (R13), and the second end of the thirteenth resistor (R13) is connected to ground;
  • the base of the fifth transistor (Q5) is connected to the second end of the eleventh resistor (R11), and the collector of the fifth transistor (Q5) is connected to the fourth diode (R10) through the tenth resistor (R10).
  • the anode of D4) is connected, and the emitter of the fifth transistor (Q5) is connected to the collector of the sixth transistor (Q6);
  • the base of the sixth transistor (Q6) is connected to the latch control terminal of the wake-up trigger latch circuit, and the emitter of the sixth transistor (Q6) is connected to ground;
  • the eighth resistor (R8) is connected in series between the emitter of the fourth transistor (Q4) and the anode of the fourth diode (D4);
  • the collector of the fourth transistor (Q4) is connected to the wake-up output terminal of the wake-up trigger latch circuit.
  • the wake-up trigger latch circuit further includes a ninth resistor (R9) and a twelfth resistor (R12); ninth The resistor (R9) is connected in series between the cathode of the fourth diode (D4) and the trigger input end of the wake-up trigger latch circuit; the twelfth resistor (R12) is connected in series between the base of the sixth transistor (Q6) pole and the latch control terminal of the wake-up trigger latch circuit.
  • the controller further includes a standby mode setting circuit
  • the first control terminal of the micro control unit is respectively connected to the standby mode setting port (STB) of the first CAN transceiver and the latch control terminal of the wake-up trigger latch circuit through the standby mode setting circuit, wherein , the first control end of the micro control unit is connected to the input end of the standby mode setting circuit, and the output end of the standby mode setting circuit is respectively connected to the standby mode setting port (STB) and the first CAN transceiver.
  • the latch control terminal of the wake-up trigger latch circuit is connected;
  • the standby mode setting circuit is used to perform level conversion on the control signal (MCU-STB) output by the first control terminal and then output it to the standby mode setting port (STB) of the first CAN transceiver and the Wake up the latch control terminal of the trigger latch circuit.
  • the standby mode setting circuit includes a first resistor (R1), an eighteenth resistor (R18), and a first transistor (Q1), wherein the first transistor (Q1) is NPN type triode;
  • the base of the first transistor (Q1) is connected to the input terminal of the standby mode setting circuit, and the collector of the first transistor (Q1) is connected to the power supply of the standby mode setting circuit through the first resistor (R1). terminal is connected, and the emitter of the first transistor (Q1) is connected to ground;
  • the collector of the first transistor (Q1) is connected to the output end of the standby mode conversion circuit
  • the input terminal of the standby mode setting circuit is connected to ground through the eighteenth resistor (R18).
  • the standby mode setting circuit further includes a third resistor (R3); the third resistor (R3) is connected in series between the base of the first transistor (Q1) and the standby mode Set between the input terminals of the circuit.
  • the power terminal of the first CAN transceiver, the power terminal of the wake-up trigger latch circuit, and the power terminal of the standby mode setting circuit are respectively connected to a normal power supply.
  • the controller further includes a voltage drop circuit for converting a high-voltage normal power supply into a low-voltage normal power supply and then providing the power supply to the first CAN transceiver respectively. terminal, the power terminal of the wake-up trigger latch circuit, and the power terminal of the standby mode setting circuit.
  • the controller further includes an anti-backflow circuit
  • the anti-backflow circuit is connected between the first signal sending end (RXD) of the first CAN transceiver and the bus signal receiving end of the micro control unit;
  • the anti-backflow circuit is used to prevent the first CAN transceiver from flowing back current to the micro-control unit in standby mode.
  • the anti-backflow circuit includes a fifteenth resistor (R15) and a third diode (D3);
  • the anode of the third diode (D3) is connected to the bus signal receiving end of the micro control unit, and the cathode of the third diode (D3) is connected to the first signal transmitting end (RXD) of the first CAN transceiver. connect;
  • One end of the fifteenth resistor (R15) is connected to the external power supply port of the power management circuit, and the other end is connected to the anode of the third diode D3.
  • a vehicle having the controller, a CAN bus, and a power supply according to any one of the first aspects of the present disclosure.
  • the controller and the vehicle in the embodiment of the present disclosure can realize the power control function through the first CAN transceiver, that is, realize the sleep wake-up of the controller through the first CAN transceiver.
  • the first CAN transceiver can use CAN transceiver chips of model 1042 and model 1044, breaking through the original application limitations of these two types of CAN transceiver chips.
  • Figure 1 shows a system block diagram of a controller based on CAN transceiver 1043
  • Figure 2 shows the pinout of the CAN transceiver 1043
  • FIG. 3 shows peripheral circuitry suitable for the CAN transceiver 1043
  • Figure 4(a) shows a system block diagram of the controller of the first embodiment of the present disclosure
  • Figure 4(b) shows a system block diagram of the controller of the second embodiment of the present disclosure
  • Figure 4(c) shows a system block diagram of the controller of the third embodiment of the present disclosure
  • Figure 5 shows the pinout of the CAN transceiver 1042/1044
  • FIG. 6 shows peripheral circuitry suitable for the CAN transceiver 1042/1044
  • Figure 7 shows a standby mode setting circuit of an embodiment of the present disclosure
  • Figure 8(a) shows a wake-up trigger latch circuit according to an embodiment of the present disclosure
  • Figure 8(b) shows a wake-up trigger latch circuit according to another embodiment of the present disclosure
  • Figure 9 shows an anti-backflow circuit according to an embodiment of the present disclosure
  • FIGS. 10(a)-10(b) illustrate a design layout of a controller compatible with the CAN transceiver 1042/1044 and the CAN transceiver 1043 according to an embodiment of the present disclosure.
  • CAN Controller Area Network, controller area network.
  • CAN is an internationally standardized serial communication protocol.
  • the CAN bus protocol has become the standard bus protocol for automotive computer control systems and embedded industrial control LANs.
  • MCU Microcontroller Unit, micro control unit.
  • PMIC Power Management IC, power management integrated circuit.
  • LDO low dropout regulator, low dropout linear voltage regulator circuit.
  • a first embodiment of the present disclosure provides a controller, which includes a power management circuit, a microcontrol unit, a first CAN transceiver, or a logic circuit and a wake-up trigger latch circuit. .
  • the power management circuit is used to control the power supply to the micro control unit.
  • the power hold signal port of the micro control unit is connected to the first input terminal of the OR logic circuit, and the output terminal of the OR logic circuit is connected to the enable terminal EN' of the power management circuit.
  • the first control terminal of the micro control unit is respectively connected to the standby mode setting port STB of the first CAN transceiver and the latch control terminal of the wake-up trigger latch circuit.
  • the first signal sending terminal RXD of the first CAN transceiver is connected to the trigger input terminal of the wake-up trigger latch circuit, and the wake-up output terminal of the wake-up trigger latch circuit is connected to the second input terminal of the OR logic circuit.
  • the logic circuit is used to control the power on or off of the micro control unit according to the power hold signal output by the power hold signal port of the micro control unit and the wake up signal output by the wake up output terminal of the wake up trigger latch circuit, wherein the wake up trigger latch
  • the circuit is configured to latch the wake-up signal in the first level state in response to the wake-up message received by the first CAN transceiver after the micro control unit is powered off.
  • the micro control unit is used to control the first CAN transceiver to enter the standby mode through the first control terminal when sleep is required, control the wake-up trigger latch circuit to enter the pre-latched state, and set the power hold signal port to Second level state.
  • the first CAN transceiver is used to monitor the CAN bus in the standby mode, and when monitoring the wake-up message, trigger the wake-up trigger latch circuit through the first signal sending terminal RXD to enter the latch state and output the first power A flat wake-up signal.
  • the micro control unit is also used to set the power hold signal port to a first level state after power-on, and control the first CAN transceiver to enter the normal operating mode through the first control terminal and control the wake-up trigger.
  • the latch circuit is unlocked.
  • the controller in the embodiment of the present disclosure can complete the sleep wake-up function of the controller through the first CAN transceiver.
  • the micro control unit may be an MCU.
  • the power management circuit can be a PMIC.
  • the main feature of PMIC is high integration, which encapsulates traditional multi-output power supplies in one chip, making multi-power application scenarios more efficient and smaller.
  • the first CAN transceiver may use a CAN transceiver chip of model 1042 or 1044, which is hereinafter referred to as CAN transceiver 1042/1044.
  • the first level may be a high level
  • the second level may be a low level
  • the first level state is a high level state
  • the second level state is a low level state. That is to say, the micro control unit is used to control the first CAN transceiver to enter the standby mode through the first control terminal when sleep is required, control the wake-up trigger latch circuit to enter the pre-latched state, and set the power hold signal port to low level status.
  • the microcontrol unit is also used to set the power hold signal port to a high level state after power-on, and control the first CAN transceiver to enter the normal operating mode through the first control terminal and control the wake-up trigger latch circuit to unlock.
  • the first CAN transceiver is used to monitor the CAN bus in standby mode, and when monitoring the wake-up message, trigger the wake-up trigger latch circuit through the first signal sending terminal RXD to enter the latch state and output a high-level wake-up signal.
  • the wake-up trigger latch circuit is used to enter the latch state and output when the first signal sending terminal RXD of the first CAN transceiver switches from high level to low level after entering the pre-latch state. High level wake-up signal.
  • the power supply terminals of the first CAN transceiver and the wake-up trigger latch circuit are respectively connected to normal power supplies to ensure that the controller can be woken up by the wake-up message of the CAN bus after the controller is powered off.
  • a second embodiment of the present disclosure provides a controller.
  • One difference from the first embodiment is that a hard wire wake-up method is added.
  • the third input terminal of the OR logic circuit is used to receive a hard-wired wake-up signal, and the hard-wired wake-up signal can be used to control the micro control unit to power on.
  • the power management circuit can also be enabled through a hard-wired wake-up signal, thereby waking up the controller. That is to say, the controller of the embodiment of the present disclosure has two wake-up modes, the first is a hard wire wake-up mode, and the second is a CAN bus wake-up mode.
  • the power hold signal port of the micro control unit is used to output the power hold signal to prevent the CAN signal and hardwire wake-up signal from being accidentally disconnected and causing the controller to suddenly lose power. Under normal working conditions of the micro control unit, the power hold signal port continuously outputs a high-level power hold signal.
  • the power management circuit under the action of the OR logic circuit, as long as any one of the three signals of the power hold signal, the hard wire wake-up signal, and the wake-up signal is high level, the power management circuit will be enabled. After the power management circuit is enabled, normal power supply is restored and the micro control unit is powered on.
  • the power supply terminals of the first CAN transceiver and the wake-up trigger latch circuit are respectively connected to normal power supplies to ensure that the controller can be woken up by the wake-up message of the CAN bus after the controller is powered off.
  • the controller may further include a voltage drop circuit.
  • the voltage drop circuit is used to convert the high-voltage normal power supply into a low-voltage normal power supply and then provide it to the first CAN transceiver and the wake-up trigger latch circuit respectively.
  • the voltage drop circuit is always in a normal working state regardless of whether the controller is sleeping or waking up, and it always provides a low-voltage constant power supply to the first CAN transceiver and the wake-up trigger latch circuit.
  • the voltage drop circuit can be an LDO. The LDO is always in normal working condition regardless of whether the controller is sleeping or waking up.
  • the controller further includes an anti-backflow circuit.
  • the anti-backflow circuit is connected between the first signal sending end RXD of the first CAN transceiver and the bus signal receiving end of the micro control unit.
  • the anti-backflow circuit is used to prevent the first CAN transceiver from flowing current back to the micro-control unit in standby mode, which can reduce the static power consumption of the controller in the sleep state and protect the port of the micro-control unit.
  • Step S11 After the micro control unit is powered on, it pulls the power hold signal high, pulls down the standby mode setting port STB of the CAN transceiver 1042/1044 through the first control terminal and controls the wake-up trigger latch circuit to unlock, and the CAN transceiver 1042/1044 Enter "normal working mode” and the controller enters normal working status.
  • the CAN transceiver 1042/1044 Based on the working mechanism of the CAN transceiver 1042/1044 itself, when the standby mode setting port STB of the CAN transceiver 1042/1044 is pulled low, the CAN transceiver 1042/1044 enters the "normal operating mode", and the CAN transceiver 1042/1044 is in Regular message information transmission is performed between the micro control unit and the CAN bus. Specifically, the bus signal receiving end of the micro control unit is connected to the first signal transmitting end RXD of the CAN transceiver 1042/1044, and the bus signal transmitting end of the micro control unit is connected to the first signal receiving end TXD of the CAN transceiver 1042/1044. Connection, the micro control unit communicates with other controllers on the CAN bus via CAN transceiver 1042/1044.
  • Step S12 When the micro control unit wants to sleep, it pulls up the standby mode setting port STB of the CAN transceiver 1042/1044 through the first control terminal and controls the wake-up trigger latch circuit to enter the pre-latched state, and then the micro control unit turns the power on Keep the signal pulled low.
  • the CAN transceiver 1042/1044 Based on the working mechanism of the CAN transceiver 1042/1044 itself, when the standby mode setting port STB of the CAN transceiver 1042/1044 is pulled high, the CAN transceiver 1042/1044 enters "standby mode". In "standby mode", the CAN transceiver 1042/1044 can monitor the wake-up message on the CAN bus and maintain its static power consumption at about 15 ⁇ A.
  • the first signal sending terminal RXD of the CAN transceiver 1042/1044 When entering the "standby mode", the first signal sending terminal RXD of the CAN transceiver 1042/1044 is in a silent state and is at a high level. When the first signal sending terminal RXD of the CAN transceiver 1042/1044 is high level, the wake-up output terminal of the wake-up trigger latch circuit is low level. Because the wake-up output terminal of the wake-up trigger latch circuit is low level and the power hold signal is also low level, or the output terminal of the logic circuit is low level and cannot enable the power management circuit, powering off the micro control unit causes the controller to completely Entering the sleep state, the static power consumption of the controller is maintained at the lowest state.
  • Step S13 The CAN transceiver 1042/1044 monitors the CAN bus in "standby mode".
  • the first signal sending end RXD of the CAN transceiver 1042/1044 will follow the wake-up message and have corresponding high and low power levels. flat change.
  • the first signal sending terminal RXD of the CAN transceiver 1042/1044 is connected to the trigger input terminal of the wake-up trigger latch circuit, and the first signal sending terminal RXD of the CAN transceiver 1042/1044 switches from high level to low level.
  • the wake-up trigger latch circuit is triggered to enter the latch state and output a high-level wake-up signal to the OR logic circuit.
  • the wake-up trigger latch circuit Since the wake-up trigger latch circuit has entered the pre-latched state before, as long as the first signal sending terminal RXD of the CAN transceiver 1042/1044 switches from high level to low level, the wake-up trigger latch circuit will Enters the latch state and outputs a high-level wake-up signal. Afterwards, no matter how the level state of the first signal sending terminal RXD changes with the external message, the wake-up trigger latch circuit will keep outputting a stable high-level wake-up signal.
  • This The disclosed embodiment utilizes the latch function of the wake-up trigger latch circuit to improve the stability and reliability of the CAN bus wake-up function of the controller.
  • Step S14 or the logic circuit receives a high-level wake-up signal output from the wake-up trigger latch circuit, and enables the power management circuit to power on the micro-control unit.
  • the micro control unit After the micro control unit is powered on, it first pulls the power hold signal high, and then pulls down the standby mode setting port STB of the CAN transceiver 1042/1044 through the first control terminal and controls the wake-up trigger latch circuit to unlock, and the CAN transceiver 1042/1044 enters "Normal working mode" and the controller enters the normal working state, that is, it returns to step S11.
  • the controller's wake-up and sleep function is implemented based on the CAN transceiver 1042/1044.
  • the wake-up trigger latch circuit can make the wake-up trigger more stable. After the wake-up trigger latch circuit enters the pre-latched state, the first signal sending end RXD of the CAN transceiver 1042/1044 only needs to occur once. The event of switching from high level to low level can trigger the wake-up trigger latch circuit to stably output a high-level wake-up signal to the OR logic circuit, thereby ensuring that the controller can be woken up stably.
  • the controller can be implemented using a CAN transceiver chip model 1043 (hereinafter referred to as CAN transceiver 1043).
  • the power control port INH of the CAN transceiver 1043 is connected to the enable terminal EN' of the power management circuit.
  • the micro control unit sets the standby mode setting port STB of the CAN transceiver 1043 low when it needs to sleep.
  • the CAN transceiver 1043 will switch to "enter sleep mode” and pass the CAN transceiver 1043
  • the CAN transceiver 1043 will enter the "sleep mode", and its power control port INH will change from high level to low level.
  • the power management circuit is not enabled, and the controller will completely enter the sleep state after power off. .
  • the controller When the controller is in sleep state, the CAN transceiver 1043 switches to "standby mode" after listening to the wake-up message on the CAN bus.
  • its power control port INH will change from low level to high level, and the power management circuit will be Enable the controller to enter normal operating mode.
  • the micro control unit After the micro control unit is powered on, it will set the standby mode setting port STB of the CAN transceiver 1043 and the enable pin EN of the CAN transceiver 1043 to high, and the CAN transceiver 1043 will enter the "normal operating mode" at this time.
  • Figure 2 shows the pin settings of the CAN transceiver 1043
  • Figure 5 shows the pin settings of the CAN transceiver 1042/1044. It can be seen that some packages of the CAN transceiver 1043 and the CAN transceiver 1042/1044 are compatible. Yes, the PIN pins of the upper part of the CAN transceiver 1043 are mostly the same as those of the CAN transceiver 1042/1044. The difference is that pin 5 of the CAN transceiver 1042/1044 is the VIO power supply pin, while the CAN transceiver 1043 Pin 11 at the same position is an open pin.
  • Figure 3 shows part of the peripheral circuits of the CAN transceiver 1043
  • Figure 6 shows part of the peripheral circuits of the CAN transceiver 1042/1044. It can be seen that part of the peripheral circuits of the CAN transceiver 1043 and the CAN transceiver 1042/1044 are The same, that is, the two can share part of the same peripheral circuits.
  • the embodiment of the present disclosure provides a hardware solution to replace the CAN transceiver 1043 in the controller shown in Figure 1 with the CAN transceiver 1042/1044 without changing the original code logic of the micro control unit. , so that the CAN transceiver 1042/1044 can replace the CAN transceiver 1043, and the micro control unit still wakes up and sleep according to the original code logic.
  • the third embodiment of the present disclosure provides a controller that can use CAN transceiver 1042/1044 to replace CAN transceiver 1043 without changing the original code logic of the micro control unit.
  • a standby mode setting circuit is added to the embodiment shown in Fig. 4(c).
  • the first control terminal of the micro control unit is respectively connected to the standby mode setting port STB of the first CAN transceiver and the latch control terminal of the wake-up trigger latch circuit through the standby mode setting circuit, wherein the first control terminal of the micro control unit is connected to the standby mode setting port STB of the first CAN transceiver.
  • the input terminal of the standby mode setting circuit is connected, and the output terminal of the standby mode setting circuit is respectively connected with the standby mode setting port STB of the first CAN transceiver and the latch control terminal of the wake-up trigger latch circuit.
  • the standby mode setting circuit is used to perform level conversion on the control signal MCU-STB output by the first control terminal and then output it to the standby mode setting port STB of the first CAN transceiver and the latch control terminal of the wake-up trigger latch circuit respectively.
  • its standby mode setting port STB is set high corresponding to "normal operating mode” and set low corresponding to "standby mode”.
  • its standby mode setting port STB is set low corresponding to "normal operating mode” and set high corresponding to "standby mode”. That is to say, the mechanism of the standby mode setting port STB of the CAN transceiver 1043 and the CAN transceiver 1042/1044 is opposite.
  • the standby mode setting circuit electrically controls the control signal output by the first control terminal of the micro control unit. After flat conversion, they are output to the standby mode setting port STB of the CAN transceiver and the latch control end of the wake-up trigger latch circuit.
  • the standby mode setting circuit can also prevent current from flowing back to the first control port of the microcontroller, playing a certain protective role.
  • the third input terminal of the OR logic circuit is used to access the hard-wired wake-up signal.
  • the power management circuit can also be enabled through a hard-wired wake-up signal, thereby waking up the controller.
  • the power management circuit under the action of the OR logic circuit, as long as any one of the three signals of the power hold signal, the hard wire wake-up signal, and the wake-up signal is high level, the power management circuit will be enabled.
  • the power terminals of the first CAN transceiver, the wake-up trigger latch circuit and the standby mode setting circuit are respectively Connect to a normal power supply to ensure that the controller can be woken up by the CAN bus wake-up message after powering off.
  • the controller may further include a voltage drop circuit. The voltage drop circuit is used to convert the high-voltage normal power supply into a low-voltage normal power supply and then provide it to the first CAN transceiver, the wake-up trigger latch circuit and the standby mode setting circuit respectively.
  • the voltage drop circuit is always in a normal working state regardless of whether the controller is sleeping or waking up, and therefore always provides low-voltage constant power to the first CAN transceiver, the wake-up trigger latch circuit and the standby mode setting circuit.
  • the voltage drop circuit can be an LDO.
  • the LDO is always in normal working condition regardless of whether the controller is sleeping or waking up.
  • Step S21 After the micro control unit is powered on, the power hold signal is pulled high to control the first control terminal to output a high level control signal MCU-STB.
  • the standby mode setting circuit performs level conversion on the control signal MCU-STB and then outputs a low level. flat CAN-STB signal.
  • the low-level CAN-STB signal pulls down the standby mode setting port STB of the CAN transceiver 1042/1044 and controls the wake-up trigger latch circuit to unlock.
  • the CAN transceiver 1042/1044 enters the "normal operating mode" and the controller enters the normal operating state. .
  • the CAN transceiver 1042/1044 Based on the working mechanism of the CAN transceiver 1042/1044 itself, when the standby mode setting port STB of the CAN transceiver 1042/1044 is pulled low, the CAN transceiver 1042/1044 enters the "normal operating mode", and the CAN transceiver 1042/1044 is in Regular message information transmission is performed between the micro control unit and the CAN bus. Specifically, the bus signal receiving end of the micro control unit is connected to the first signal transmitting end RXD of the CAN transceiver 1042/1044, and the bus signal transmitting end of the micro control unit is connected to the first signal receiving end TXD of the CAN transceiver 1042/1044. Connection, the microcontrol unit communicates with the CAN bus via CAN transceiver 1042/1044.
  • Step S22 When the micro control unit wants to sleep, it outputs a low-level control signal MCU-STB through the first control terminal.
  • the standby mode setting circuit performs level conversion on the control signal MCU-STB and then outputs a high-level CAN-STB. Signal.
  • the high-level CAN-STB signal pulls up the standby mode setting port STB of the CAN transceiver 1042/1044 and controls the wake-up trigger latch circuit to enter the pre-latched state, and then the micro-control unit pulls the power hold signal low.
  • the CAN transceiver 1042/1044 Based on the working mechanism of the CAN transceiver 1042/1044 itself, when the standby mode setting port STB of the CAN transceiver 1042/1044 is pulled high, the CAN transceiver 1042/1044 enters "standby mode". In "standby mode", the CAN transceiver 1042/1044 can monitor the wake-up message on the CAN bus and maintain its static power consumption at about 15 ⁇ A.
  • the first signal sending terminal RXD of the CAN transceiver 1042/1044 When entering the "standby mode", the first signal sending terminal RXD of the CAN transceiver 1042/1044 is in a silent state and is at a high level. When the first signal sending terminal RXD of the CAN transceiver 1042/1044 is high level, the wake-up output terminal of the wake-up trigger latch circuit is low level. Because the wake-up output terminal of the wake-up trigger latch circuit is low level and the power hold signal is also low level, or the output terminal of the logic circuit is low level and cannot enable the power management circuit, powering off the micro control unit causes the controller to completely Entering the sleep state, the static power consumption of the controller is maintained at the lowest state.
  • Step S23 The CAN transceiver 1042/1044 monitors the CAN bus in "standby mode".
  • the first signal sending end RXD of the CAN transceiver 1042/1044 will follow the wake-up message and have corresponding high and low power levels. flat change.
  • the first signal sending terminal RXD of the CAN transceiver 1042/1044 is connected to the trigger wake-up port of the wake-up trigger latch circuit, and the first signal sending terminal RXD of the CAN transceiver 1042/1044 switches from high level to low level.
  • the wake-up trigger latch circuit is triggered to enter the latch state and output a high-level wake-up signal to the OR logic circuit.
  • the wake-up trigger latch circuit Since the wake-up trigger latch circuit has entered the pre-latched state before, as long as the first signal sending terminal RXD of the CAN transceiver 1042/1044 switches from high level to low level, the wake-up trigger latch circuit will Enters the latch state and outputs a high-level wake-up signal. Afterwards, no matter how the level state of the first signal sending terminal RXD changes with the external message, the wake-up trigger latch circuit will keep outputting a stable high-level wake-up signal.
  • This The disclosed embodiment utilizes the latch function of the wake-up trigger latch circuit to improve the stability and reliability of the CAN bus wake-up function of the controller.
  • Step S24 or the logic circuit receives a high-level wake-up signal output by the wake-up trigger latch circuit, and enables the power management circuit to power on the micro control unit.
  • the micro control unit After the micro control unit is powered on, it first pulls the power hold signal high, and then controls the first control terminal to output a high level control signal MCU-STB.
  • the standby mode setting circuit performs level conversion on the control signal MCU-STB and then outputs a low level.
  • CAN-STB signal The low-level CAN-STB signal pulls down the standby mode setting port STB of the CAN transceiver 1042/1044 and controls the wake-up trigger latch circuit to unlock.
  • the CAN transceiver 1042/1044 enters the "normal operating mode" and the controller enters the normal operating state. , that is, return to step S21.
  • the power terminals of the first CAN transceiver, the wake-up trigger latch circuit, and the standby mode setting circuit are respectively connected to the normal power supply to ensure that when the power management circuit is in sleep state, the CAN transceiver, the wake-up trigger latch circuit, The standby mode setting circuit has wake-up capability.
  • the controller also includes a voltage drop circuit. The voltage drop circuit is used to convert a high-voltage normal power supply into a low-voltage normal power supply and then provide the CAN transceiver, wake-up trigger latch circuit, and standby mode setting circuit respectively.
  • the voltage drop circuit is always in a normal working state regardless of whether the controller is sleeping or waking up, and it always provides low-voltage constant power to the CAN transceiver, wake-up trigger latch circuit, and standby mode setting circuit.
  • the voltage drop circuit can be an LDO.
  • the LDO is always in normal working condition regardless of whether the controller is sleeping or waking up.
  • the standby mode setting circuit can be implemented with a simple semiconductor (transistor, MOS tube) switching circuit
  • the anti-backflow circuit can be implemented with an anti-reverse diode
  • the wake-up trigger latch circuit can be implemented using a discrete circuit or a pass-through circuit.
  • Flip-flop chip implementation The controller of the embodiment of the present disclosure is illustrated below with an example.
  • the controller includes a microcontrol unit, power management circuit, or logic circuit, voltage drop circuit, CAN transceiver 1042/1044, wake-up trigger latch circuit, standby mode setting circuit, and anti-backflow circuit.
  • the power management circuit and voltage drop circuit are connected to 12V normal power respectively.
  • the voltage drop circuit converts the external 12V normal power supply into a 5V normal power supply and provides it to the power terminals of the wake-up trigger latch circuit, CAN transceiver 1042/1044, and standby mode setting circuit respectively.
  • the voltage drop circuit is always in a normal working mode to ensure the CAN bus wake-up function of the controller.
  • the +5V power supply is provided by the voltage drop circuit that supplies normal power
  • the +5VIO power supply is provided by the power management circuit after being awakened.
  • the power management circuit requires a high-level signal input or logic circuit to be enabled to wake up and work normally.
  • the three input signals of the OR logic come from the wake-up signal of the wake-up trigger latch circuit, the external hard-wired wake-up signal, and the power hold signal provided by the micro-control unit after power-on.
  • the micro control unit can be powered on normally only after the power management circuit wakes up.
  • the standby mode setting circuit and the wake-up trigger latch circuit When the controller is in the sleep state, the standby mode setting circuit and the wake-up trigger latch circuit have almost no current; when the controller is in normal working state, the standby mode setting circuit and the wake-up trigger latch circuit have relatively large current flow.
  • control signal output by the first control terminal of the micro control unit is recorded as "MCU-STB”
  • control signal output by the output terminal of the standby mode setting circuit is recorded as "CAN-STB”
  • CAN transceiver is The signal output by the first signal sending port RXD of the device 1042/1044 is recorded as "CANRX”
  • the wake-up signal output by the wake-up output terminal of the wake-up trigger latch circuit is recorded as "CAN-WAKE”
  • bus signal received by the micro-control unit is The terminal is marked as "MCU-RX”.
  • the standby mode setting circuit includes a first resistor R1 , an eighteenth resistor R18 and a first transistor Q1 .
  • the first transistor Q1 is an NPN transistor.
  • the base of the first transistor Q1 is connected to the input end of the standby mode setting circuit to receive the control signal MCU-STB output from the first control port of the micro control unit.
  • the collector of the first transistor Q1 is connected to the power terminal of the standby mode setting circuit through the first resistor R1, that is, connected to the 5V normal power supply provided by the voltage drop circuit.
  • the collector of the first transistor Q1 is connected to the output terminal of the standby mode conversion circuit to respectively provide the control signal CAN- to the standby mode setting port STB of the CAN transceiver 1042/1044 and the latch control terminal of the wake-up trigger latch circuit.
  • STB, the control signal CAN-STB and the control signal MCU-STB have opposite level states.
  • the emitter of the first transistor Q1 is grounded.
  • the function of the first resistor R1 is to set the initial voltage of the collector when the first transistor Q1 is turned on. The flat state is high level.
  • the input terminal of the standby mode setting circuit is connected to ground through the eighteenth resistor R18.
  • the eighteenth resistor R18 is a pull-down resistor, and its function is to set the initial state of the first transistor Q1 to a closed state.
  • the standby mode setting circuit may also include a third resistor R3.
  • the third resistor R3 is connected in series between the base of the first transistor Q1 and the input terminal of the standby mode setting circuit to play a current limiting role.
  • the wake-up trigger latch circuit can be implemented by a flip-flop chip.
  • the flip-flop chip is a falling edge triggered flip-flop. That is to say, after the flip-flop enters the pre-latched state, the first signal sending end RXD of the CAN transceiver 1042/1044 switches from high level to low level. In the event of a flat event, the flip-flop enters the latched state and outputs a high level wake-up signal.
  • the first example of the wake-up trigger latch circuit according to the embodiment of the present disclosure is introduced, which is implemented by using D flip-flop U2.
  • D flip-flop U2 has dual channels, channel 1 and channel 2 respectively.
  • a wake-up trigger latch circuit is implemented based on the first channel of the D flip-flop U2.
  • the first channel may be any one of channel 1 and channel 2 of the D flip-flop U2.
  • the asynchronous reset terminal 1CLR- of the first channel of the D flip-flop U2 is connected to the latch control terminal of the wake-up trigger latch circuit.
  • the clock terminal 1CLK- of the first channel of the D flip-flop U2 is connected to the trigger input terminal of the wake-up trigger latch circuit.
  • the output terminal 1Q of the first channel of the D flip-flop U2 is connected to the wake-up output terminal of the wake-up trigger latch circuit.
  • the power terminal VCC of the D flip-flop U2, the input terminal 1D of the first channel of the D flip-flop U2, and the asynchronous set terminal 1PRE- of the first channel of the D flip-flop U2 are respectively connected to the power terminal of the wake-up trigger latch circuit. That is, they are respectively connected to the 5V normal power supply provided by the voltage drop circuit.
  • the wake-up trigger latch circuit may further include a seventh capacitor C7, a ninth capacitor C9, and a tenth capacitor C10.
  • the asynchronous reset terminal 1CLR of the first channel of the D flip-flop U2 is connected to the ground through the seventh capacitor C7.
  • the asynchronous setting terminal 1PRE- of the first channel of the D flip-flop U2 is connected to the ground through the tenth capacitor C10.
  • the power terminal VCC of the D flip-flop U2 is connected to the ground through the ninth capacitor C9.
  • the functions of the seventh capacitor C7, the ninth capacitor C9 and the tenth capacitor C10 are filtering.
  • the anti-backflow circuit includes a fifteenth resistor R15 and a third diode D3.
  • the anode of the third diode D3 is connected to the bus signal receiving end MCU-RX of the micro control unit, and the cathode of the third diode D3 is connected to the first signal transmitting end RXD of the CAN transceiver.
  • One end of the fifteenth resistor R15 is connected to the external power supply port of the power management circuit. That is to say, the +5VIO voltage of the anti-backflow circuit is provided by the power management circuit after waking up.
  • the other end of the fifteenth resistor R15 is connected to the third diode. Connect the positive terminal of tube D3.
  • the function of the third diode D3 is to prevent the current of the first signal sending terminal RXD of the CAN transceiver from flowing back into the micro control unit, thereby solving the problem of excessive static power consumption during sleep, and in addition to protecting the micro control The port of the unit.
  • the first control terminal of the micro control unit When the controller needs to power off and sleep under normal working conditions, the first control terminal of the micro control unit outputs a low-level control signal MCU-STB, causing the first transistor Q1 of the standby mode setting circuit to be non-conductive and output a high level.
  • the high-level control signal "CAN-STB” will pull up the level of the standby mode port STB of the CAN transceiver 1042/1044 to 5V, causing the CAN transceiver 1042/1044 to enter the "standby mode".
  • the signal CANRX output by the first signal sending terminal RXD of the CAN transceiver 1042/1044 When entering the "standby mode", the signal CANRX output by the first signal sending terminal RXD of the CAN transceiver 1042/1044 is high level.
  • the D flip-flop circuit Under the action of the high-level control signal CAN-STB and the high-level signal CANRX, the D flip-flop circuit
  • the CAN transceiver 1042/1044 can monitor the wake-up message on the CAN bus and maintain its static power consumption at about 15 ⁇ A.
  • the static power consumption of the controller depends on the power consumption of the voltage drop circuit, CAN transceiver 1042/1044, D flip-flop circuit, as well as the leakage current of the standby mode setting circuit and the anti-backflow circuit.
  • the first signal sending end RXD of the CAN transceiver 1042/1044 will have corresponding level changes following the external wake-up message.
  • the D flip-flop circuit is triggered to enter the latch state and outputs the high level wake-up signal CAN-WAKE.
  • the power management circuit is enabled to wake up, and the micro control unit Power-on.
  • the micro control unit After the micro control unit is powered on, it first sets the power hold signal high, and then outputs a high level control signal MCU-STB through the first control terminal, causing the first transistor Q1 of the standby mode setting circuit to conduct and output a low level.
  • the low-level control signal "CAN-STB” will pull the level of the standby mode setting port STB of the CAN transceiver 1042/1044 to ground, causing the CAN transceiver 1042/1044 to enter the "normal operating mode” and the controller enters to normal working condition.
  • the low-level control signal "CAN-STB” will unlock the D flip-flop circuit, that is, clear the latch, and the wake-up signal CAN-WAKE will always be in a low-level state.
  • the micro control unit After the micro control unit is powered on, it first sets the power hold signal high to ensure that the micro control unit does not lose power, and then sets the CAN transceiver 1042/1044 to enter the "normal operating mode". After the power hold signal is set high, the microcontrol unit maintains the enable state of the power management circuit through the power hold signal. After the controller enters the normal working state, the microcontrol unit continues to maintain the enable state of the power management circuit through the power hold signal.
  • the difference from the previous example is that the wake-up trigger latch circuit is implemented by a discrete circuit.
  • the wake-up trigger latch circuit includes a first switch control unit and a second switch control unit.
  • the first switch control unit of the second switch control unit is connected to the first signal sending end RXD of the CAN transceiver 1042/1044, and the second control unit of the second switch control unit is connected to the first control end of the micro control unit of the second switch control unit. .
  • the first switch control unit of the second switch control unit When the first switch control unit of the second switch control unit is turned on, it will trigger the second switch control unit to turn on. After the second switch control unit of the second switch control unit is turned on, it will maintain the first switch of the second switch control unit.
  • the conduction state of the control unit is such that the first switch control unit of the second switch control unit latches the wake-up signal of the second switch control unit in the first level state.
  • the first signal sending end RXD of the CAN transceiver 1042/1044 will have corresponding level changes following the external wake-up message.
  • the signal CANRX switches from high level to low level, it will trigger the first switch control unit to turn on first, and the first switch control unit to turn on will trigger the second switch control unit to turn on, and the second switch control unit to turn on.
  • the first switch control unit will in turn be maintained in the conductive state.
  • no matter how the level state of the first signal transmitting terminal RXD of the CAN transceiver 1042/1044 changes the first switch control unit is maintained in the conductive state.
  • the wake-up latch circuit enters the latch state and outputs a high-level wake-up signal CAN-WAKE, thereby enabling the power management circuit to wake up and the micro-control unit is powered on.
  • the first switch control unit includes a fourth transistor Q4, a fourth diode D4, an eighth resistor R8, and an eleventh resistor R11.
  • the second switch control unit It includes a fifth transistor Q5, a sixth transistor Q6, a tenth resistor R10 and a thirteenth resistor R13.
  • the fourth transistor Q4 is a PNP transistor Q4, and the fifth transistor Q5 and the sixth transistor Q6 are NPN type transistors.
  • the base of the fourth transistor Q4 is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to the trigger input end of the wake-up trigger latch circuit, and the emitter of the fourth transistor Q4 is connected to the anode of the fourth diode D4.
  • the power supply terminal of the wake-up trigger latch circuit is connected, that is, the 5V normal power supply provided by the voltage drop circuit is connected.
  • the collector of the fourth transistor Q4 is connected to the first terminal of the eleventh resistor R11, the second terminal of the eleventh resistor R11 is connected to the first terminal of the thirteenth resistor R13, and the second terminal of the thirteenth resistor R13 end grounded.
  • the base of the fifth transistor Q5 is connected to the second end of the eleventh resistor R11, and the collector of the fifth transistor Q5 is connected to the anode of the fourth diode D4 through the tenth resistor R10.
  • the emitter of tube Q5 is connected to the collector of sixth transistor Q6.
  • the base of the sixth transistor Q6 is connected to the latch control terminal of the wake-up trigger latch circuit, and the emitter of the sixth transistor Q6 is connected to the ground.
  • the eighth resistor R8 is connected in series between the emitter of the fourth transistor Q4 and the anode of the fourth diode D4.
  • the collector of the fourth transistor Q4 is connected to the wake-up output terminal of the wake-up trigger latch circuit.
  • the function of the fourth diode D4 is to divide the voltage to a certain extent to prevent the fourth transistor Q4 from being accidentally triggered.
  • the eighth resistor R8, the tenth resistor R10, the eleventh resistor R11, the thirteenth resistor R13, the fourth transistor Q4, and the fifth transistor Q5 are the latch part.
  • the sixth transistor Q6 plays the role of unlocking, that is, it is responsible for clearing the latch.
  • the eighth resistor R8 is a pull-up resistor and is used to set the fourth transistor Q4 to an initial off state.
  • the tenth resistor R10 serves as the base resistor of the fourth transistor Q4 and is used to set the base current when the fourth diode Q4 is in the conductive state.
  • the eighth resistor R8 and the tenth resistor R10 play a voltage dividing role before the fourth transistor Q4 is turned on, providing a suitable turn-on voltage for the fourth transistor Q4.
  • the thirteenth resistor R13 is a pull-down resistor and is used to set the fifth transistor Q5 to an initial off state.
  • the eleventh resistor R11 is used as the base resistor of the fifth transistor Q5 and is used to set the fifth transistor Q5. The base current in the on state.
  • the eleventh resistor R11 and the thirteenth resistor R13 play a voltage dividing role before the fifth transistor Q5 is turned on, providing a suitable turn-on voltage for the fifth transistor Q5.
  • the wake-up trigger latch circuit may further include a ninth resistor R9 and a twelfth resistor R12.
  • the ninth resistor R9 is connected in series between the cathode of the fourth diode D4 and the trigger input terminal of the wake-up trigger latch circuit.
  • the twelfth resistor R12 is connected in series between the base of the sixth transistor Q6 and the latch control terminal of the wake-up trigger latch circuit.
  • the ninth resistor R9 and the twelfth resistor R12 play the role of current limiting.
  • the first control terminal of the micro control unit When the controller needs to power off and sleep under normal working conditions, the first control terminal of the micro control unit outputs a low-level control signal MCU-STB, causing the first transistor Q1 of the standby mode setting circuit to be non-conductive and output a high level.
  • the high-level control signal "CAN-STB” will pull up the level of the standby mode port STB of the CAN transceiver 1042/1044 to 5V, causing the CAN transceiver 1042/1044 to enter the "standby mode".
  • the signal CANRX output by the first signal sending terminal RXD of the CAN transceiver 1042/1044 When entering the "standby mode", the signal CANRX output by the first signal sending terminal RXD of the CAN transceiver 1042/1044 is high level.
  • the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 of the wake-up trigger latch circuit will not is turned on, the wake-up trigger latch circuit enters the pre-latched state. Then the micro control unit sets the power hold signal low and the controller enters sleep state completely.
  • the CAN transceiver 1042/1044 can monitor the wake-up message on the CAN bus and maintain its static power consumption at about 15 ⁇ A.
  • the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 will not be turned on.
  • the static power consumption of the controller depends on the power consumption of the voltage drop circuit, CAN transceiver 1042/1044, wake-up trigger latch circuit, and the leakage current of the standby mode setting circuit and the anti-backflow circuit.
  • the first signal sending end RXD of the CAN transceiver 1042/1044 will have corresponding level changes following the external wake-up message.
  • the signal CANRX switches from high level to low level, it will trigger the fourth transistor Q4 to be turned on first, and then the fifth transistor Q5 will be turned on. Only when the fifth transistor Q5 is turned on can the sixth transistor be turned on. Transistor Q6 is turned on.
  • the fourth triode The base of transistor Q4 will remain in the low state, and the fourth transistor Q4 will always be turned on, that is, the wake-up latch circuit enters the latch state and outputs a high-level wake-up signal.
  • CAN-WAKE whereby the power management circuit is enabled to wake up and the micro control unit is powered on.
  • the micro control unit After the micro control unit is powered on, it first sets the power hold signal high, and then outputs a high level control signal MCU-STB through the first control terminal, causing the first transistor Q1 of the standby mode setting circuit to conduct and output a low level.
  • the low-level control signal "CAN-STB” will pull the level of the standby mode setting port STB of the CAN transceiver 1042/1044 to ground, causing the CAN transceiver 1042/1044 to enter the "normal operating mode” and the controller enters to normal working condition.
  • the low-level control signal "CAN-STB” will cause the sixth transistor Q6 to be disconnected.
  • the disconnection of the sixth transistor Q6 can release the latches of the fourth transistor Q4 and the fifth transistor Q5. state, at this time, the fifth transistor Q5 and the sixth transistor Q6 are not conducting, and there are only the eighth resistor R8, the ninth resistor R9, the fourth transistor Q4, and the fourth diode in the wake-up trigger latch circuit.
  • the tube D4 the eleventh resistor R11, and the thirteenth resistor R13 work, the level state of the wake-up signal CAN-WAKE will change following the signal CANRX output by the first signal sending terminal RXD of the CAN transceiver 1042/1044.
  • the micro control unit After the micro control unit is powered on, it first sets the power hold signal high to ensure that the micro control unit does not lose power, and then sets the CAN transceiver 1042/1044 to enter the "normal operating mode". After the power hold signal is set high, the microcontrol unit maintains the enable state of the power management circuit through the power hold signal. After the controller enters the normal working state, the microcontrol unit continues to maintain the enable state of the power management circuit through the power hold signal.
  • embodiments of the present disclosure provide a controller compatible with the CAN transceiver 1043 and the CAN transceiver 1042/1044 circuit board design layout.
  • chip U1 can select CAN transceiver 1043 or CAN transceiver 1042/1044 according to the actual situation.
  • the CAN transceiver 1043 illustrated in Figures 10(a) and 10(b) is just one case.
  • circuit modules A01-A05 are unique peripheral circuits that need to be set for the CAN transceiver 1043 when the controller selects the CAN transceiver 1043.
  • Circuit modules B01-B02 are unique peripheral circuits that need to be set for the CAN transceiver 1042/1044 when the controller selects the CAN transceiver 1042/1044.
  • the standby mode setting circuit, the wake-up trigger latch circuit and the anti-backflow circuit are the circuits that need to be set to realize the controller CAN bus sleep wake-up function when the controller selects the CAN transceiver 1042/1044.
  • a voltage drop circuit can also be attached.
  • the remaining circuit parts not circled in Figure 10(a) and Figure 10(b) belong to peripheral circuits that can be shared by the CAN transceiver 1043 and the CAN transceiver 1042/1044, and are hereinafter referred to as "common circuits". In this way, the device can be selected based on the availability of CAN transceiver 1042/1044 and CAN transceiver 1043.
  • the circuit module A01 includes resistors R62, R63, R64, R65, R66, capacitors C63 and C67.
  • Circuit module A02 includes resistor R61.
  • Circuit module A03 includes resistor R68.
  • Circuit module A04 includes resistor R67.
  • Circuit module A05 includes resistor R69.
  • Circuit module B01 includes a resistor R74 and a capacitor C74.
  • Circuit module B02 includes resistor R79.
  • the common circuit includes common cathode diode D51, common cathode diode D52, resistor R52, resistor R54, capacitor C51, capacitor C53, inductor L51, capacitor C55 and capacitor C56.
  • CAN transceiver 1043 When the CAN transceiver 1043 is in sufficient supply, you can choose to combine the circuit modules B01-B02 and the standby mode setting circuit, wake-up trigger latch circuit, anti-backflow circuit, voltage Leave all the circuits blank, that is, do not set them up; then paste all the CAN transceiver 1043, circuit modules A01-A05, and public circuits.
  • the embodiment of the present disclosure can realize circuit compatibility of CAN transceiver 1042/1044 and CAN transceiver 1043 on the same circuit board design layout, and both can realize the CAN bus wake-up and sleep function of the controller without modification. Code logic of the microcontrol unit.
  • the micro control unit includes a memory and a processor, and computer programs/instructions are stored in the memory. Under the action of the computer program/instructions, the micro control unit can implement the control logic in the wake-up/sleep mechanism.
  • the first CAN transceiver includes a memory and a processor, and a computer program/instruction is stored in the memory. Under the action of the computer program/instruction, the first CAN transceiver can support the wake-up/instruction function of the embodiment of the present disclosure. Hibernation mechanism.
  • the power management unit includes a memory and a processor, and computer programs/instructions are stored in the memory. Under the action of the computer program/instructions, the power management unit can support the wake-up/sleep mechanism of the embodiment of the present disclosure.
  • the trigger includes a memory and a processor, and a computer program/instruction is stored in the memory. Under the action of the computer program/instruction, the trigger can support the wake-up/sleep mechanism of the embodiment of the present disclosure.
  • the controller in the embodiment of the present disclosure may be a vehicle-mounted controller used in a vehicle.
  • An embodiment of the present disclosure provides a vehicle, including the controller, CAN bus and power supply of any of the foregoing embodiments.
  • Embodiments of the present specification may relate to methods and/or computer program products.
  • a computer program product may include a computer-readable storage medium having computer instructions thereon for causing a processor to implement various aspects of the embodiments of this specification.

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Abstract

一种控制器和车辆。该控制器包括电源管理电路、微控制单元、第一CAN收发器、或逻辑电路以及唤醒触发锁存电路。电源管理电路用于控制电源为微控制单元供电。微控制单元的电源保持信号端口与或逻辑电路的第一输入端连接。或逻辑电路的输出端与电源管理电路的使能端连接。微控制单元的第一控制端分别与第一CAN收发器的待机模式设置端口和唤醒触发锁存电路的锁存控制端连接。第一CAN收发器的第一信号发送端与唤醒触发锁存电路的触发输入端连接。

Description

控制器和车辆
本公开要求于2022年05月12日提交中国专利局的申请号为202210533293.4、申请名称为“控制器和车辆”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及电子技术领域，更具体地，涉及一种控制器和车辆。
背景技术
目前，型号为1042以及型号为1044的CAN收发芯片的设计、制造工艺已经非常成熟。但是，这两种型号的CAN收发芯片本身不具有电源控制功能，其应用场景被限制在单纯的CAN信号收发功能，不利于其自身的推广应用。因此，有必要设计一种新的电源管理方案，可以适用于这两种型号的CAN收发芯片实现电源控制功能。
发明内容
本公开的一个目的是提供一种控制器的新技术方案。
本公开的又一个目的是提供一种车辆的新技术方案，该车辆包括该控制器、CAN总线以及电源。
根据本公开的第一方面，提供了控制器。所述控制器包括电源管理电路、微控制单元、第一CAN收发器、或逻辑电路以及唤醒触发锁存电路；所述电源管理电路用于控制电源为所述微控制单元供电；所述微控制单元的电源保持信号端口与所述或逻辑电路的第一输入端连接，所述或逻辑电路的输出端与所述电源管理电路的使能端连接；所述微控制单元的第一控制端分别与所述第一CAN收发器的待机模式设置端口和所述唤醒触发锁存电路的锁存控制端连接；所述第一CAN收发器的第一信号发送端与所述唤醒触发锁存电路的触发输入端连接，所述唤醒触发锁存电路的唤醒输出端与所述或逻辑电路的第二输入端连接；所述或逻辑电路用于根据所述微控制单元的电源保持信号端口输出的电源保持信号和所述唤醒触发锁存电路的唤醒输出端输出的唤醒信号控制所述微控制单元的上电或下电，其中，所述唤醒触发锁存电路用于在所述微控制单元下电后，响应于所述第一CAN收发器接收到的唤醒报文将所述唤醒信号锁存在第一电平状态。
根据本公开的实施例，所述微控制单元用于在需要休眠时，通过所述第一控制端控制所述第一CAN收发器进入待机模式并控制所述唤醒触发锁存电路进入预锁存状态，并且将所述电源保持信号端口设置为第二电平状态。
根据本公开的实施例，所述第一CAN收发器用于在所述待机模式下监听CAN总线，以及在监听到唤醒报文时，通过所述第一信号发送端(RXD)触发所述唤醒触发锁存电路进入锁存状态并输出第一电平的唤醒信号。
根据本公开的实施例，所述微控制单元还用于在上电后，将所述电源保持信号端口设置为第 一电平的状态，并且通过所述第一控制端控制所述第一CAN收发器进入正常工作模式并控制所述唤醒触发锁存电路解锁。
根据本公开的实施例，所述或逻辑电路的第三输入端用于接入硬线唤醒信号，所述硬线唤醒信号用于控制所述微控制单元上电。
根据本公开的实施例，所述唤醒触发锁存电路用于在进入预锁存状态后，在所述第一信号发送端(RXD)发生从第一电平切换至第二电平的事件的情况下，进入锁存状态并输出高电平的唤醒信号。
根据本公开的实施例所述唤醒触发锁存电路包括下降沿触发的触发器。
根据本公开的实施例，所述触发器为D触发器(U2)；D触发器(U2)的第一通道的异步复位端(1CLR-)与所述唤醒触发锁存电路的锁存控制端连接；D触发器(U2)的第一通道的时钟端(1CLK-)与所述唤醒触发锁存电路的触发输入端连接；D触发器(U2)的第一通道的输出端(1Q)与所述唤醒触发锁存电路的唤醒输出端连接。
根据本公开的实施例，所述唤醒触发锁存电路还包括：第七电容(C7)、第九电容(C9)以及第十电容(C10)；
D触发器(U2)的电源端(VCC)、D触发器(U2)的第一通道的输入端(1D)以及D触发器的第一通道的异步置位端(1PRE-)，分别与所述唤醒触发锁存电路的电源端连接；
D触发器(U2)的第一通道的异步复位端(1CLR)通过第七电容(C7)接地；
D触发器(U2)的第一通道的异步置位端(1PRE-)通过第十电容(C10)接地；
D触发器(U2)的电源端(VCC)通过第九电容(C9)接地。
根据本公开的实施例，所述唤醒触发锁存电路包括第一开关控制单元和第二开关控制单元；
所述第一开关控制单元和所述第一CAN收发器的第一信号发送端(RXD)连接，所述第二控制单元和所述微控制单元的第一控制端连接；其中，所述第一开关控制单元导通时会触发所述第二开关控制单元导通，所述第二开关控制单元导通后维持所述第一开关控制单元的导通状态，以使得所述第一开关控制单元将所述唤醒信号锁存在第一电平状态。
根据本公开的实施例，所述第一开关控制单元包括第四三极管(Q4)、第四二极管(D4)、第八电阻(R8)以及第十一电阻(R11)，所述第二开关控制单元包括第五三极管(Q5)、第六三极管(Q6)、第十电阻(R10)以及第十三电阻(R13)，其中，第四三极管(Q4)为PNP型三极管，第五三极管(Q5)和第六三极管(Q6)为NPN型三极管。
第四三极管(Q4)的基极与第四二极管(D4)的正极连接，第四二极管(D4)的负极与所述唤醒触发锁存电路的触发输入端连接；
第四三极管(Q4)的发射极与所述唤醒触发锁存电路的电源端连接，第四三极管(Q4)的集电极与第十一电阻(R11)的第一端连接，第十一电阻(R11)的第二端与第十三电阻(R13)的第一端连接，第十三电阻(R13)的第二端接地；
第五三极管(Q5)的基极与第十一电阻(R11)的第二端连接，第五三极管(Q5)的集电极通过第十电阻(R10)与第四二极管(D4)的正极连接，第五三极管(Q5)的发射极与第六三极管(Q6)的集电极连接；
第六三极管(Q6)的基极与所述唤醒触发锁存电路的锁存控制端连接，第六三极管(Q6)的发射极接地；
第八电阻(R8)串联在第四三极管(Q4)的发射极和第四二极管(D4)的正极之间；
第四三极管(Q4)的集电极与所述唤醒触发锁存电路的唤醒输出端连接。
根据本公开的实施例，所述唤醒触发锁存电路还包括第九电阻(R9)和第十二电阻(R12)；第九 电阻(R9)串联在第四二极管(D4)的负极和所述唤醒触发锁存电路的触发输入端之间；第十二电阻(R12)串联在第六三极管(Q6)的基极和所述唤醒触发锁存电路的锁存控制端之间。
根据本公开的实施例，所述控制器还包括待机模式设置电路；
所述微控制单元的第一控制端通过所述待机模式设置电路分别与所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端连接，其中，所述微控制单元的第一控制端与所述待机模式设置电路的输入端连接，所述待机模式设置电路的输出端分别与所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端连接；
所述待机模式设置电路用于对所述第一控制端输出的控制信号(MCU-STB)进行电平转换后分别输出至所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端。
根据本公开的实施例，所述待机模式设置电路包括第一电阻(R1)、第十八电阻(R18)以及第一三极管(Q1)，其中，第一三极管(Q1)为NPN型三极管；
第一三极管(Q1)的基极与所述待机模式设置电路的输入端连接，第一三极管(Q1)的集电极通过第一电阻(R1)与所述待机模式设置电路的电源端连接，第一三极管(Q1)的发射极接地；
第一三极管(Q1)的集电极与所述待机模式转换电路的输出端连接；
所述待机模式设置电路的输入端通过第十八电阻(R18)接地。
根据本公开的实施例，所述待机模式设置电路还包括第三电阻(R3)；所述第三电阻(R3)串联在所述第一三极管(Q1)的基极和所述待机模式设置电路的输入端之间。
根据本公开的实施例，所述第一CAN收发器的电源端、所述唤醒触发锁存电路的电源端、所述待机模式设置电路的电源端分别接常电源。
根据本公开的实施例，所述控制器还包括压降电路，所述压降电路用于将高电压的常电源转成低电压的常电源后分别提供至所述第一CAN收发器的电源端、所述唤醒触发锁存电路的电源端、所述待机模式设置电路的电源端。
根据本公开的实施例，所述控制器还包括防倒灌电路；
所述防倒灌电路连接在所述第一CAN收发器的第一信号发送端(RXD)和所述微控制单元的总线信号接收端之间；
所述防倒灌电路用于防止所述第一CAN收发器在待机模式下将电流倒灌至所述微控制单元。
根据本公开的实施例，所述防倒灌电路包括第十五电阻(R15)和第三二极管(D3)；
第三二极管(D3)的正极与所述微控制单元的总线信号接收端连接，第三二极管(D3)的负极与所述第一CAN收发器的第一信号发送端(RXD)连接；
所述第十五电阻(R15)的一端与电源管理电路的对外供电端口连接，另一端与第三二极管D3的正极连接。
根据本公开的第二方面，提供了车辆，所述车辆具有本公开第一方面任一项所述的控制器、CAN总线以及电源。
本公开实施例的控制器和车辆，可以通过第一CAN收发器实现电源控制功能，也就是通过第一CAN收发器实现控制器的休眠唤醒。在本公开实施例的控制器和车辆中，第一CAN收发器可以采用型号为1042以及型号为1044的CAN收发芯片，突破了这两种型号的CAN收发芯片原本的应用限制。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
被结合在说明书中并构成说明书的一部分的附图示出了本公开的实施例，并且连同其说明一起用于解释本公开的原理。
图1示出了基于CAN收发器1043的控制器的系统框图；
图2示出了CAN收发器1043的引脚设置；
图3示出了适用于CAN收发器1043的外围电路；
图4(a)示出了本公开第一个实施例的控制器的系统框图；
图4(b)示出了本公开第二个实施例的控制器的系统框图；
图4(c)示出了本公开第三个实施例的控制器的系统框图；
图5示出了CAN收发器1042/1044的引脚设置；
图6示出了适用于CAN收发器1042/1044的外围电路；
图7示出了本公开实施例的待机模式设置电路；
图8(a)示出了本公开一个实施例的唤醒触发锁存电路；
图8(b)示出了本公开另一个实施例的唤醒触发锁存电路；
图9示出了本公开实施例的防倒灌电路；
图10(a)-10(b)示出了本公开实施例的兼容CAN收发器1042/1044和CAN收发器1043的控制器的设计版图。
具体实施方式
现在将参照附图来详细描述本说明书的各种示例性实施例。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本说明书实施例及其应用或使用的任何限制。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
本公开实施例中涉及的英文简称的释义：
CAN：Controller Area Network，控制器局域网络。CAN是国际标准化的串行通信协议，CAN总线协议已经成为汽车计算机控制系统和嵌入式工业控制局域网的标准总线协议。
MCU：Microcontroller Unit，微控制单元。
PMIC：Power Management IC，电源管理集成电路。
LDO：low dropout regulator，低压差线性稳压电路。
参见图4(a)所示，本公开的第一实施例提供了一种控制器，该控制器包括电源管理电路、微控制单元、第一CAN收发器、或逻辑电路以及唤醒触发锁存电路。
电源管理电路用于控制电源为微控制单元供电。微控制单元的电源保持信号端口与或逻辑电路的第一输入端连接，或逻辑电路的输出端与电源管理电路的使能端EN’连接。微控制单元的第一控制端分别与第一CAN收发器的待机模式设置端口STB和唤醒触发锁存电路的锁存控制端连接。第一CAN收发器的第一信号发送端RXD与唤醒触发锁存电路的触发输入端连接，唤醒触发锁存电路的唤醒输出端与或逻辑电路的第二输入端连接。
或逻辑电路用于根据微控制单元的电源保持信号端口输出的电源保持信号和唤醒触发锁存电路的唤醒输出端输出的唤醒信号控制微控制单元的上电或下电，其中，唤醒触发锁存电路用于在微控制单元下电后，响应于第一CAN收发器接收到的唤醒报文将唤醒信号锁存在第一电平状态。
在一个例子中，微控制单元用于在需要休眠时，通过第一控制端控制第一CAN收发器进入待机模式并控制唤醒触发锁存电路进入预锁存状态，并且将电源保持信号端口设置为第二电平状态。
在一个例子中，第一CAN收发器用于在待机模式下监听CAN总线，以及在监听到唤醒报文时，通过第一信号发送端RXD触发唤醒触发锁存电路进入锁存状态并输出第一电平的唤醒信号。
在一个例子中，微控制单元还用于在上电后，将电源保持信号端口设置为第一电平的状态，并且通过第一控制端控制第一CAN收发器进入正常工作模式并控制唤醒触发锁存电路解锁。
本公开实施例的控制器，可以通过第一CAN收发器完成控制器的休眠唤醒功能。
本公开实施例中，微控制端单元可以是MCU。电源管理电路可以是PMIC。PMIC的主要特点是高集成度，将传统的多路输出电源封装在一颗芯片内，使得多电源应用场景高效率更高，体积更小。第一CAN收发器可以使用型号为1042或者型号为1044的CAN收发芯片，下文称之为CAN收发器1042/1044。
在本公开实施例中，第一电平可以为高电平，第二电平可以为低电平，第一电平状态为高电平状态，第二电平状态为低电平状态。也就是说，微控制单元用于在需要休眠时，通过第一控制端控制第一CAN收发器进入待机模式并控制唤醒触发锁存电路进入预锁存状态，并且将电源保持信号端口设置为低电平状态。微控制单元还用于在上电后，将电源保持信号端口设置为高电平状态，并且通过第一控制端控制第一CAN收发器进入正常工作模式并控制唤醒触发锁存电路解锁。第一CAN收发器用于在待机模式下监听CAN总线，以及在监听到唤醒报文时，通过第一信号发送端RXD触发唤醒触发锁存电路进入锁存状态并输出高电平的唤醒信号。唤醒触发锁存电路用于在进入预锁存状态后，在第一CAN收发器的第一信号发送端RXD发生从高电平切换至低电平的事件的情况下，进入锁存状态并输出高电平的唤醒信号。
本公开实施例中，第一CAN收发器、唤醒触发锁存电路的电源端分别接常电源，以保证控制器下电后能被CAN总线的唤醒报文唤醒。
参见图4(b)所示，本公开的第二实施例提供了一种控制器。和第一实施例的一个不同之处在于，增加了硬线唤醒方式。
或逻辑电路的第三输入端用于接入硬线唤醒信号，该硬线唤醒信号可以用于控制微控制单元上电。也就是说，通过硬线唤醒信号也可以使能电源管理电路，进而唤醒控制器。也就是说，本公开实施例的控制器具有两种唤醒方式，第一种是硬线唤醒方式，第二种是CAN总线唤醒方式。
微控制单元的电源保持信号端口用于输出电源保持信号，防止CAN信号及硬线唤醒信号意外断开导致控制器突然掉电。微控制单元在正常工作状态下，电源保持信号端口持续输出高电平的电源保持信号。在本公开实施例中，在或逻辑电路的作用下，电源保持信号、硬线唤醒信号、唤醒信号三个信号中只要有任一个为高电平，电源管理电路都会被使能。电源管理电路被使能后恢复正常供电，微控制单元上电。
本公开实施例中，第一CAN收发器、唤醒触发锁存电路的电源端分别接常电源，以保证控制器下电后能被CAN总线的唤醒报文唤醒。本公开实施例中，控制器还可以包括压降电路。压降电路用于将高电压的常电源转成低电压的常电源后分别提供给第一CAN收发器、唤醒触发锁存电路。压降电路无论控制器休眠或唤醒一直都处于正常工作状态、也就一直向第一CAN收发器、唤醒触发锁存电路提供低电压的常电源。该压降电路可以为LDO，LDO无论控制器休眠或唤醒一直都处于正常工作状态。
本公开实施例中，控制器中还包括防倒灌电路。防倒灌电路连接在第一CAN收发器的第一信号发送端RXD和微控制单元的总线信号接收端之间。防倒灌电路用于防止第一CAN收发器在待机模式下将电流倒灌至微控制单元，可以降低控制器在休眠状态下的静态功耗，以及保护微控制单元的端口。
假设硬线唤醒信号一直为低电平，即在硬线唤醒信号无效的情况下，图4(b)所示的实施例的 控制器的休眠唤醒过程为：
步骤S11、微控制单元上电后将电源保持信号拉高，通过第一控制端拉低CAN收发器1042/1044的待机模式设置端口STB并且控制唤醒触发锁存电路解锁，CAN收发器1042/1044进入“正常工作模式”，控制器进入正常工作状态。
基于CAN收发器1042/1044自身的工作机制，在CAN收发器1042/1044的待机模式设置端口STB被拉低时，CAN收发器1042/1044进入“正常工作模式”，CAN收发器1042/1044在微控制单元和CAN总线之间进行常规的报文信息传输工作。具体来说，微控制单元的总线信号接收端与CAN收发器1042/1044的第一信号发送端RXD连接，微控制单元的总线信号发送端与CAN收发器1042/1044的第一信号接收端TXD连接，微控制单元通过CAN收发器1042/1044与CAN总线上的其他控制器进行通信。
步骤S12、微控制单元想要休眠时，通过第一控制端拉高CAN收发器1042/1044的待机模式设置端口STB同时控制控制唤醒触发锁存电路进入预锁存状态，然后微控制单元将电源保持信号拉低。
基于CAN收发器1042/1044自身的工作机制，在CAN收发器1042/1044的待机模式设置端口STB被拉高时，CAN收发器1042/1044进入“待机模式”。在“待机模式”下,CAN收发器1042/1044可以监听CAN总线上的唤醒报文，并将自己的静态功耗维持在15μA左右。
在进入“待机模式”时，CAN收发器1042/1044的第一信号发送端RXD处于静默状态为高电平。CAN收发器1042/1044的第一信号发送端RXD为高电平时，唤醒触发锁存电路的唤醒输出端为低电平。由于唤醒触发锁存电路的唤醒输出端为低电平并且电源保持信号也为低电平，或逻辑电路的输出端为低电平无法使能电源管理电路，微控制单元下电使得控制器彻底进入休眠状态，控制器的静态功耗维持在最低状态。
步骤S13、CAN收发器1042/1044在“待机模式”下监听CAN总线，在监听到唤醒报文时，CAN收发器1042/1044的第一信号发送端RXD会跟随唤醒报文有相应的高低电平变化。CAN收发器1042/1044的第一信号发送端RXD与唤醒触发锁存电路的触发输入端连接，CAN收发器1042/1044的第一信号发送端RXD发生从高电平切换至低电平的事件时，会触发唤醒触发锁存电路进入锁存状态并输出高电平的唤醒信号至或逻辑电路。
由于唤醒触发锁存电路在之前已经进入预锁存状态，只要CAN收发器1042/1044的第一信号发送端RXD发生一次从高电平切换至低电平的事件，唤醒触发锁存电路就会进入锁存状态并输出高电平的唤醒信号，之后无论第一信号发送端RXD的电平状态如何跟随外界报文变化，唤醒触发锁存电路都会保持输出稳定的高电平的唤醒信号，本公开实施例利用唤醒触发锁存电路的锁存功能提升了控制器的CAN总线唤醒功能的稳定可靠性。
步骤S14、或逻辑电路接收到唤醒触发锁存电路输出的高电平的唤醒信号，使能电源管理电路使得微控制单元上电。
微控制单元上电后先将电源保持信号拉高，然后通过第一控制端拉低CAN收发器1042/1044的待机模式设置端口STB并控制唤醒触发锁存电路解锁，CAN收发器1042/1044进入“正常工作模式”并且控制器进入正常工作状态，也就是回到了步骤S11。
本公开实施例中，基于CAN收发器1042/1044实现了控制器的唤醒休眠功能。本公开实施例中，唤醒触发锁存电路可使得唤醒触发更为稳定，在醒触发锁存电路进入预锁存状态后，CAN收发器1042/1044的第一信号发送端RXD只需要发生一次从高电平切换至低电平的事件，就可以触发唤醒触发锁存电路稳定地输出高电平的唤醒信号至或逻辑电路，从而保证控制器可以被稳定唤醒。
参见图1所示，控制器可以采用型号为1043的CAN收发芯片(下文简称为CAN收发器1043)实现，CAN收发器1043的电源控制端口INH与电源管理电路的使能端EN’连接。基于CAN收发器1043的工作特性，微控制单元在需要休眠时将CAN收发器1043的待机模式设置端口STB置低，此时CAN收发器1043会切换到“进入休眠模式”，经过CAN收发器1043默认的既定时间后CAN收发器1043会进入“休眠模式”，其电源控制端口INH由高电平变成低电平，此时电源管理电路不被使能，控制器掉电后彻底进入休眠状态。控制器处于休眠状态时，CAN收发器1043监听到CAN总线上的唤醒报文后切换到“待机模式”，此时其电源控制端口INH会由低电平变换成高电平，电源管理电路被使能控制器进入正常工作模式。微控制单元上电后会将CAN收发器1043的待机模式设置端口STB及CAN收发器1043的使能引脚EN置高，此时CAN收发器1043此时会进入“正常工作模式”。图2示出了CAN收发器1043的引脚设置，图5示出了CAN收发器1042/1044的引脚设置，可以看出，CAN收发器1043和CAN收发器1042/1044的部分封装是兼容的，CAN收发器1043的上半部分的PIN脚与CAN收发器1042/1044的PIN脚大部分相同，区别在于CAN收发器1042/1044的5号脚是VIO供电引脚，而CAN收发器1043同样位置的11号引脚是空接引脚。图3示出了CAN收发器1043的部分外围电路，图6示出了CAN收发器1042/1044的部分外围电路，可以看出，CAN收发器1043和CAN收发器1042/1044的部分外围电路是相同的，即两者可以共用一部分相同的外围电路。
基于此，本公开实施例提供了一种硬件方案，在不改变微控制单元原有代码逻辑的情况下，将图1所示的控制器中的CAN收发器1043替换为CAN收发器1042/1044，使得CAN收发器1042/1044可以代替CAN收发器1043，微控制单元依然按照原有的代码逻辑进行唤醒休眠。
参见图4(c)所示，本公开第三实施例提供了一种控制器，可以在不改变微控制单元原有代码逻辑的情况下，使用CAN收发器1042/1044代替CAN收发器1043。
图4(c)所示的实施例和图4(b)所示的实施例的不同之处在于，图4(c)所示的实施例中增加了待机模式设置电路。微控制单元的第一控制端通过待机模式设置电路分别与第一CAN收发器的待机模式设置端口STB和唤醒触发锁存电路的锁存控制端连接，其中，微控制单元的第一控制端与待机模式设置电路的输入端连接，待机模式设置电路的输出端分别与第一CAN收发器的待机模式设置端口STB和唤醒触发锁存电路的锁存控制端连接。待机模式设置电路用于对第一控制端输出的控制信号MCU-STB进行电平转换后分别输出至第一CAN收发器的待机模式设置端口STB和唤醒触发锁存电路的锁存控制端。
对于CAN收发器1043，其待机模式设置端口STB被置高对应于“正常工作模式”，被置低对应于“待机模式”。对于CAN收发器1042/1044，其待机模式设置端口STB被置低对应于“正常工作模式”，被置高对应于“待机模式”。也就是说，CAN收发器1043和CAN收发器1042/1044的待机模式设置端口STB的机制是相反的。为了能够让CAN收发器1042/1044代替CAN收发器1043，并且保证微控制单元依然按照原有的代码逻辑进行唤醒休眠，待机模式设置电路对微控制单元的第一控制端输出的控制信号进行电平转换后分别输出至CAN收发器的待机模式设置端口STB和唤醒触发锁存电路的锁存控制端。此外，待机模式设置电路还能够防止电流倒灌至微控制器的第一控制端口，起到一定的保护作用。
在一个例子中，参见图4(c))所示，或逻辑电路的第三输入端用于接入硬线唤醒信号。也就是说，通过硬线唤醒信号也可以使能电源管理电路，进而唤醒控制器。在本公开实施例中，在或逻辑电路的作用下，电源保持信号、硬线唤醒信号、唤醒信号三个信号中只要有任一个为高电平，电源管理电路都会被使能。
本公开实施例中，第一CAN收发器、唤醒触发锁存电路以及待机模式设置电路的电源端分别 接常电源，以保证控制器下电后能被CAN总线的唤醒报文唤醒。本公开实施例中，控制器还可以包括压降电路。压降电路用于将高电压的常电源转成低电压的常电源后分别提供给第一CAN收发器、唤醒触发锁存电路以及待机模式设置电路。压降电路无论控制器休眠或唤醒一直都处于正常工作状态、也就一直向第一CAN收发器、唤醒触发锁存电路以及待机模式设置电路提供低电压的常电源。该压降电路可以为LDO，LDO无论控制器休眠或唤醒一直都处于正常工作状态。
假设硬线唤醒信号一直为低电平，即在硬线唤醒信号无效的情况下，图4(c)所示的实施例的控制器的休眠唤醒过程为：
步骤S21、微控制单元上电后将电源保持信号拉高，控制第一控制端输出高电平的控制信号MCU-STB，待机模式设置电路对控制信号MCU-STB进行电平转换后输出低电平的CAN-STB信号。低电平的CAN-STB信号拉低CAN收发器1042/1044的待机模式设置端口STB并且控制唤醒触发锁存电路解锁，CAN收发器1042/1044进入“正常工作模式”，控制器进入正常工作状态。
基于CAN收发器1042/1044自身的工作机制，在CAN收发器1042/1044的待机模式设置端口STB被拉低时，CAN收发器1042/1044进入“正常工作模式”，CAN收发器1042/1044在微控制单元和CAN总线之间进行常规的报文信息传输工作。具体来说，微控制单元的总线信号接收端与CAN收发器1042/1044的第一信号发送端RXD连接，微控制单元的总线信号发送端与CAN收发器1042/1044的第一信号接收端TXD连接，微控制单元通过CAN收发器1042/1044与CAN总线进行通信。
步骤S22、微控制单元想要休眠时，通过第一控制端输出低电平的控制信号MCU-STB，待机模式设置电路对控制信号MCU-STB进行电平转换后输出高电平的CAN-STB信号。高电平的CAN-STB信号拉高CAN收发器1042/1044的待机模式设置端口STB同时控制唤醒触发锁存电路进入预锁存状态，然后微控制单元将电源保持信号拉低。
基于CAN收发器1042/1044自身的工作机制，在CAN收发器1042/1044的待机模式设置端口STB被拉高时，CAN收发器1042/1044进入“待机模式”。在“待机模式”下,CAN收发器1042/1044可以监听CAN总线上的唤醒报文，并将自己的静态功耗维持在15μA左右。
在进入“待机模式”时，CAN收发器1042/1044的第一信号发送端RXD处于静默状态为高电平。CAN收发器1042/1044的第一信号发送端RXD为高电平时，唤醒触发锁存电路的唤醒输出端为低电平。由于唤醒触发锁存电路的唤醒输出端为低电平并且电源保持信号也为低电平，或逻辑电路的输出端为低电平无法使能电源管理电路，微控制单元下电使得控制器彻底进入休眠状态，控制器的静态功耗维持在最低状态。
步骤S23、CAN收发器1042/1044在“待机模式”下监听CAN总线，在监听到唤醒报文时，CAN收发器1042/1044的第一信号发送端RXD会跟随唤醒报文有相应的高低电平变化。CAN收发器1042/1044的第一信号发送端RXD与唤醒触发锁存电路的触发唤醒端口连接，CAN收发器1042/1044的第一信号发送端RXD发生从高电平切换至低电平的事件时，会触发唤醒触发锁存电路进入锁存状态并输出高电平的唤醒信号至或逻辑电路。
由于唤醒触发锁存电路在之前已经进入预锁存状态，只要CAN收发器1042/1044的第一信号发送端RXD发生一次从高电平切换至低电平的事件，唤醒触发锁存电路就会进入锁存状态并输出高电平的唤醒信号，之后无论第一信号发送端RXD的电平状态如何跟随外界报文变化，唤醒触发锁存电路都会保持输出稳定的高电平的唤醒信号，本公开实施例利用唤醒触发锁存电路的锁存功能提升了控制器的CAN总线唤醒功能的稳定可靠性。
步骤S24、或逻辑电路接收到触发唤醒触发锁存电路输出的高电平的唤醒信号，使能电源管理电路使得微控制单元上电。
微控制单元上电后先将电源保持信号拉高，然后控制第一控制端输出高电平的控制信号MCU-STB，待机模式设置电路对控制信号MCU-STB进行电平转换后输出低电平的CAN-STB信号。低电平的CAN-STB信号拉低CAN收发器1042/1044的待机模式设置端口STB并且控制唤醒触发锁存电路解锁，CAN收发器1042/1044进入“正常工作模式”，控制器进入正常工作状态，也就是回到了步骤S21。
在一个例子中，第一CAN收发器、唤醒触发锁存电路、待机模式设置电路的电源端分别接常电源，以保证在电源管理电路休眠的情况下，CAN收发器、唤醒触发锁存电路、待机模式设置电路具有唤醒能力。例如，控制器还包括压降电路，压降电路用于将高电压的常电源转成低电压的常电源后分别提供CAN收发器、唤醒触发锁存电路、待机模式设置电路。压降电路无论控制器休眠或唤醒一直都处于正常工作状态，也就一直向CAN收发器、唤醒触发锁存电路、待机模式设置电路提供低电压的常电源。该压降电路可以为LDO，LDO无论控制器休眠或唤醒一直都处于正常工作状态。
本公开实施例中，待机模式设置电路可用简单的半导体(三极管、MOS管)开关电路实现，防倒灌电路可以用防反二极管实现，唤醒触发锁存电路既可以采用分立电路实现，也可以采用通过触发器芯片实现。下面对本公开实施例的控制器进行举例说明。
<例子1>
下面参见图4(c)-图7、图8(a)以及图9说明本公开实施例提供的控制器。
控制器包括微控制单元、电源管理电路、或逻辑电路、压降电路、CAN收发器1042/1044、唤醒触发锁存电路、待机模式设置电路以及防倒灌电路。
电源管理电路和压降电路分别接12V常电。压降电路将外部的12V常电源转化成5V常电源后分别提供给唤醒触发锁存电路、CAN收发器1042/1044、待机模式设置电路的电源端。本公开实施例中，无论控制器处于休眠状态还是正常工作状态，压降电路一直处于正常工作模式，以保证控制器的CAN总线唤醒功能。控制器电路中，+5V供电都由供常电的压降电路提供，+5VIO供电都由被唤醒后的电源管理电路提供。
电源管理电路需要或逻辑电路有一个高电平信号输入才能被使能唤醒正常工作。或逻辑的三路输入信号来自于唤醒触发锁存电路的唤醒信号、外部硬线唤醒信号及微控制单元上电后提供的电源保持信号。电源管理电路唤醒后才能让微控制单元正常上电。
控制器处于休眠状态时，待机模式设置电路和唤醒触发锁存电路几乎无电流；控制器正常工作状态时，待机模式设置电路和唤醒触发锁存电路才有较大电流通过。
本公开实施例中，将微控制单元的第一控制端输出的控制信号记为“MCU-STB”，将待机模式设置电路的输出端输出的控制信号记为“CAN-STB”，将CAN收发器1042/1044的第一信号发送端口RXD输出的信号记为“CANRX”，将唤醒触发锁存电路的唤醒输出端输出的唤醒信号记为“CAN-WAKE”,将微控制单元的总线信号接收端记为“MCU-RX”。
参见图7所示，待机模式设置电路包括第一电阻R1、第十八电阻R18以及第一三极管Q1。其中，第一三极管Q1为NPN型三极管。
第一三极管Q1的基极与待机模式设置电路的输入端连接，以接入微控制单元的第一控制端口输出的控制信号MCU-STB。第一三极管Q1的集电极通过第一电阻R1与待机模式设置电路的电源端连接，也就是接入压降电路提供的5V常电源。第一三极管Q1的集电极与待机模式转换电路的输出端连接，以分别向CAN收发器1042/1044的待机模式设置端口STB和唤醒触发锁存电路的锁存控制端提供控制信号CAN-STB，控制信号CAN-STB与控制信号MCU-STB的电平状态相反。第一三极管Q1的发射极接地。第一电阻R1的作用是设定第一三极管Q1导通时集电极的初始电 平状态为高电平。
待机模式设置电路的输入端通过第十八电阻R18接地。第十八电阻R18为下拉电阻，作用是设定第一三极管Q1的初始状态为关闭状态。
待机模式设置电路还可以包括第三电阻R3。第三电阻R3串联在第一三极管Q1的基极与待机模式设置电路的输入端之间，起到限流作用。
本公开实施例中，唤醒触发锁存电路可以通过触发器芯片实现。该触发器芯片为下降沿触发的触发器，也就是说，该触发器在进入预锁存状态后，在CAN收发器1042/1044的第一信号发送端RXD发生从高电平切换至低电平的事件的情况下，触发器进入锁存状态并输出高电平的唤醒信号。
参见图8(a)所示，介绍本公开实施例的唤醒触发锁存电路的第一个例子，采用D触发器U2实现。
D触发器U2具有双通道，分别为通道1和通道2。本公开实施例中，基于D触发器U2的第一通道实现唤醒触发锁存电路，第一通道可以是D触发器U2的通道1和通道2中的任意一个通道。
下面第一通道是通道1为例，说明本公开实施例的基于D触发器U2的唤醒锁存电路：
D触发器U2的第一通道的异步复位端1CLR-与唤醒触发锁存电路的锁存控制端连接。D触发器U2的第一通道的时钟端1CLK-与唤醒触发锁存电路的触发输入端连接。D触发器U2的第一通道的输出端1Q与唤醒触发锁存电路的唤醒输出端连接。
D触发器U2的电源端VCC、D触发器U2的第一通道的输入端1D以及D触发器U2的第一通道的异步置位端1PRE-，分别与唤醒触发锁存电路的电源端连接，也就是分别接入压降电路提供的5V常电源。
唤醒触发锁存电路还可以包括第七电容C7、第九电容C9以及第十电容C10。D触发器U2的第一通道的异步复位端1CLR通过第七电容C7接地。D触发器U2的第一通道的异步置位端1PRE-通过第十电容C10接地。D触发器U2的电源端VCC通过第九电容C9接地。第七电容C7、第九电容C9以及第十电容C10的作用是滤波。
参见图9所示，介绍本公开实施例的防倒灌电路。防倒灌电路包括第十五电阻R15和第三二极管D3。第三二极管D3的正极与微控制单元的总线信号接收端MCU-RX连接，第三二极管D3的负极与CAN收发器的第一信号发送端RXD连接。第十五电阻R15的一端与电源管理电路的对外供电端口连接，也就是说防倒灌电路的+5VIO电压由被唤醒后的电源管理电路提供，第十五电阻R15的另一端与第三二极管D3的正极连接。
第三二极管D3起到的作用是防止CAN收发器的第一信号发送端RXD的电流倒灌到微控制单元内部，以此解决休眠时静态功耗过大的问题，此外还可以保护微控制单元的端口。
下面说明例子1的控制器的唤醒休眠机制：
假设硬线唤醒信号一直为低电平，即在硬线唤醒信号无效的情况下，例子1的控制器的休眠唤醒过程为：
控制器在正常工作状态下需要下电休眠时，微控制单元的第一控制端输出低电平的控制信号MCU-STB，使得待机模式设置电路的第一三极管Q1不导通从而输出高电平的控制信号“CAN-STB”。高电平的控制信号“CAN-STB”会将CAN收发器1042/1044的待机模式端口STB的电平上拉到5V，使得CAN收发器1042/1044进入到“待机模式”。在进入“待机模式”时，CAN收发器1042/1044的第一信号发送端RXD输出的信号CANRX为高电平。在高电平的控制信号CAN-STB和高电平的信号CANRX的作用下，D触发器电路进入预锁存状态。然后微控制单元 将电源保持信号置低，控制器彻底进入休眠状态。
在“待机模式”下，CAN收发器1042/1044可以监听CAN总线上的唤醒报文，并将自己的静态功耗维持在15μA左右。当控制器处于休眠状态时，控制器的静态功耗取决于压降电路、CAN收发器1042/1044、D触发器电路的功耗，以及待机模式设置电路、防倒灌电路的漏电流。
当CAN收发器1042/1044接收到总线上任意唤醒报文后，CAN收发器1042/1044的第一信号发送端RXD会跟随外界唤醒报文有相应电平变化。信号CANRX发生从高电平切换至低电平的事件时，触发D触发器电路进入锁存状态并输出高电平的唤醒信号CAN-WAKE，由此电源管理电路被使能唤醒，微控制单元上电。
微控制单元上电后先将电源保持信号置高，再通过第一控制端输出高电平的控制信号MCU-STB，使得待机模式设置电路的第一三极管Q1导通从而输出低电平的控制信号“CAN-STB”。低电平的控制信号“CAN-STB”会将CAN收发器1042/1044的待机模式设置端口STB的电平拉低到地，使得CAN收发器1042/1044进入“正常工作模式”，控制器进入到正常工作状态。同时，低电平的控制信号“CAN-STB”会使得D触发器电路被解锁，也就是清除锁存，唤醒信号CAN-WAKE一直为低电平状态。
微控制单元在上电后先将电源保持信号置高，以保证微控制单元不会掉电，再去设置CAN收发器1042/1044进入“正常工作模式”。在电源保持信号置高后，微控制单元通过电源保持信号维持电源管理电路的使能状态。控制器进入到正常工作状态后，微控制单元继续通过电源保持信号维持电源管理电路的使能状态。
<例子2>
下面参见图4(c)-图7、图8(b)以及图9说明本公开实施例提供的控制器。
和前述例子的不同之处在于，唤醒触发锁存电路通过分立电路实现。唤醒触发锁存电路包括第一开关控制单元和第二开关控制单元。
第二开关控制单元第一开关控制单元和CAN收发器1042/1044的第一信号发送端RXD连接，第二开关控制单元第二控制单元和第二开关控制单元微控制单元的第一控制端连接。第二开关控制单元第一开关控制单元导通时会触发第二开关控制单元第二开关控制单元导通，第二开关控制单元第二开关控制单元导通后维持第二开关控制单元第一开关控制单元的导通状态，以使得第二开关控制单元第一开关控制单元将第二开关控制单元唤醒信号锁存在第一电平状态。具体来说，当CAN收发器1042/1044接收到总线上任意唤醒报文后，CAN收发器1042/1044的第一信号发送端RXD会跟随外界唤醒报文有相应电平变化。信号CANRX发生从高电平切换至低电平的事件，会触发第一开关控制单元首先导通，第一开关控制单元导通会触发第二开关控制单元导通，第二开关控制单元导通后会反过来维持第一开关控制单元的导通状态，之后无论CAN收发器1042/1044的第一信号发送端RXD的电平状态如何变化，第一开关控制单元都被维持在导通状态，使得唤醒锁存电路进入锁存状态并输出高电平的唤醒信号CAN-WAKE，由此电源管理电路被使能唤醒，微控制单元上电。
在一个例子中，参见图8(b)所示，第一开关控制单元包括第四三极管Q4、第四二极管D4、第八电阻R8以及第十一电阻R11，第二开关控制单元包括第五三极管Q5、第六三极管Q6、第十电阻R10以及第十三电阻R13。其中，第四三极管Q4为PNP型三极管Q4，第五三极管Q5和第六三极管Q6为NPN型三极管。
第四三极管Q4的基极与第四二极管D4的正极连接，第四二极管D4的负极与唤醒触发锁存电路的触发输入端连接，第四三极管Q4的发射极与唤醒触发锁存电路的电源端连接，也就是接入压降电路提供的5V常电源。
第四三极管Q4的集电极与第十一电阻R11的第一端连接，第十一电阻R11的第二端与第十三电阻R13的第一端连接，第十三电阻R13的第二端接地。第五三极管Q5的基极与第十一电阻R11的第二端连接，第五三极管Q5的集电极通过第十电阻R10与第四二极管D4的正极连接，第五三极管Q5的发射极与第六三极管Q6的集电极连接。第六三极管Q6的基极与唤醒触发锁存电路的锁存控制端连接，第六三极管Q6的发射极接地。第八电阻R8串联在第四三极管Q4的发射极和第四二极管D4的正极之间。第四三极管Q4的集电极与唤醒触发锁存电路的唤醒输出端连接。
第四二极管D4的作用是起到一定分压作用从而防止第四三极管Q4误触发。第八电阻R8、第十电阻R10、第十一电阻R11、第十三电阻R13、第四三极管Q4、第五三极管Q5为锁存部分。第六三极管Q6起解锁作用，也就是负责清除锁存。
第八电阻R8为上拉电阻，用于设定第四三极管Q4初始为关闭状态。第十电阻R10作为第四三极管Q4的基极电阻用于设定第四二极管Q4导通状态时候的基极电流。同时第八电阻R8、第十电阻R10在第四三极管Q4导通前起到分压作用，为第四三极管Q4提供合适开启电压。
第十三电阻R13为下拉电阻，用于设定第五三极管Q5初始为关闭状态，第十一电阻R11作为第五三极管Q5的基极电阻用于设定第五三极管Q5导通状态时候的基极电流。同时第十一电阻R11、第十三电阻R13在第五三极管Q5导通前起到分压作用，为第五三极管Q5提供合适开启电压。
唤醒触发锁存电路还可以包括第九电阻R9和第十二电阻R12。第九电阻R9串联在第四二极管D4的负极和唤醒触发锁存电路的触发输入端之间。第十二电阻R12串联在第六三极管Q6的基极和唤醒触发锁存电路的锁存控制端之间。第九电阻R9和第十二电阻R12起到限流的作用。
下面说明例子2的控制器的唤醒休眠机制：
假设硬线唤醒信号一直为低电平，即在硬线唤醒信号无效的情况下，例子1的控制器的休眠唤醒过程为：
控制器在正常工作状态下需要下电休眠时，微控制单元的第一控制端输出低电平的控制信号MCU-STB，使得待机模式设置电路的第一三极管Q1不导通从而输出高电平的控制信号“CAN-STB”。高电平的控制信号“CAN-STB”会将CAN收发器1042/1044的待机模式端口STB的电平上拉到5V，使得CAN收发器1042/1044进入到“待机模式”。在进入“待机模式”时，CAN收发器1042/1044的第一信号发送端RXD输出的信号CANRX为高电平。在高电平的控制信号CAN-STB和高电平的信号CANRX的作用下，唤醒触发锁存电路的第四三极管Q4、第五三极管Q5、第六三极管Q6均不会被导通，唤醒触发锁存电路进入预锁存状态。然后微控制单元将电源保持信号置低，控制器彻底进入休眠状态。
在“待机模式”下，CAN收发器1042/1044可以监听CAN总线上的唤醒报文，并将自己的静态功耗维持在15μA左右。当控制器处于休眠状态时(控制信号CAN-STB和信号CANRX一直为高电平时)，第四三极管Q4、第五三极管Q5、第六三极管Q6均不会被导通，此时控制器的静态功耗取决于压降电路、CAN收发器1042/1044、唤醒触发锁存电路的功耗，以及待机模式设置电路、防倒灌电路的漏电流。
当CAN收发器1042/1044接收到总线上任意唤醒报文后，CAN收发器1042/1044的第一信号发送端RXD会跟随外界唤醒报文有相应电平变化。信号CANRX发生从高电平切换至低电平的事件，会触发第四三极管Q4首先导通，接着第五三极管Q5被导通，第五三极管Q5导通才能导致第六三极管Q6导通，当第五三极管Q5及第六三极管Q6导通后，无论CAN收发器1042/1044的第一信号发送端RXD的电平状态如何变化，第四三极管Q4的基极都将保持为一直拉低的状态，第四三极管Q4会一直被导通，也就是唤醒锁存电路进入锁存状态并输出高电平的唤醒信号 CAN-WAKE，由此电源管理电路被使能唤醒，微控制单元上电。
微控制单元上电后先将电源保持信号置高，再通过第一控制端输出高电平的控制信号MCU-STB，使得待机模式设置电路的第一三极管Q1导通从而输出低电平的控制信号“CAN-STB”。低电平的控制信号“CAN-STB”会将CAN收发器1042/1044的待机模式设置端口STB的电平拉低到地，使得CAN收发器1042/1044进入“正常工作模式”，控制器进入到正常工作状态。同时，低电平的控制信号“CAN-STB”会使得第六三极管Q6断开，第六三极管Q6断开可解除第四三极管Q4、第五三极管Q5的锁存状态，此时第五三极管Q5、第六三极管Q6均不导通，唤醒触发锁存电路中只有第八电阻R8、第九电阻R9、第四三极管Q4、第四二极管D4、第十一电阻R11、第十三电阻R13工作，唤醒信号CAN-WAKE的电平状态会跟随CAN收发器1042/1044的第一信号发送端RXD输出的信号CANRX而变化。
微控制单元在上电后先将电源保持信号置高，以保证微控制单元不会掉电，再去设置CAN收发器1042/1044进入“正常工作模式”。在电源保持信号置高后，微控制单元通过电源保持信号维持电源管理电路的使能状态。控制器进入到正常工作状态后，微控制单元继续通过电源保持信号维持电源管理电路的使能状态。
参见图10(a)和图10(b)所示的电路图，以及结合图1-9示出的方案，本公开实施例提供了可兼容CAN收发器1043和CAN收发器1042/1044的控制器的电路板设计版图。
在图10(a)和图10(b)中，芯片U1可以根据实际情况选用CAN收发器1043或CAN收发器1042/1044。图10(a)和图10(b)中示意出的CAN收发器1043只是其中一种情况。在图10(a)和图10(b)中，电路模块A01-A05，是控制器选用CAN收发器1043时，需要为CAN收发器1043设置的独有外围电路。电路模块B01-B02，是控制器选用CAN收发器1042/1044时，需要为CAN收发器1042/1044设置的独有外围电路。待机模式设置电路、唤醒触发锁存电路以及防倒灌电路，是控制器选用CAN收发器1042/1044时，实现控制器CAN总线休眠唤醒功能需要设置的电路。此外，控制器选用CAN收发器1042/1044时，还可以贴上压降电路。图10(a)和图10(b)中剩余的没有被圈出的电路部分属于CAN收发器1043和CAN收发器1042/1044可以共用的外围电路，下文称之为“公共电路”。这样可以根据CAN收发器1042/1044及CAN收发器1043供货情况来选贴器件。
电路模块A01包括电阻R62、电阻R63、电阻R64、电阻R65、电阻R66、电容C63以及电容C67。电路模块A02包括电阻R61。电路模块A03包括电阻R68。电路模块A04包括电阻R67。电路模块A05包括电阻R69。电路模块B01包括电阻R74以及电容C74。电路模块B02包括电阻R79。公共电路包括共阴极二极管D51、共阴极二极管D52、电阻R52、电阻R54、电容C51、电容C53、电感L51、电容C55以及电容C56。
当CAN收发器1043供货充足时，可以根据图10(a)及图10(b)的方案，选择将电路模块B01-B02以及待机模式设置电路、唤醒触发锁存电路、防倒灌电路、压降电路全部空贴，也就是全部不设置；然后将CAN收发器1043、电路模块A01-A05、公共电路全部贴上。
当CAN收发器1043及触发器芯片供货困难时，可以根据图10(b)的方案，选择将电路模块A01-A05全部空贴，也就是全部不设置；然后将CAN收发器1042/1044、待机模式设置电路、基于分立电路的唤醒触发锁存电路、防倒灌电路、压降电路、电路模块B01-B02、公共电路全部贴上。
当仅有CAN收发器1043供货困难、触发器芯片供货不困难时，可以根据图10(a)或图10(a)的方案，选择将电路模块A01-A05全部空贴，也就是全部不设置；然后将CAN收发器1042/1044、待机模式设置电路、唤醒触发锁存电路(基于分立电路的唤醒触发锁存电路或者基于触发器芯片的唤醒触发锁存电路均可)、防倒灌电路、压降电路、电路模块B01-B02、公共电路全部贴上。
也就是说，本公开实施例可以在同一个电路板设计版图上实现CAN收发器1042/1044及CAN收发器1043的电路兼容，均可以实现控制器的CAN总线唤醒休眠功能，同时可以不需要修改微控制单元的代码逻辑。
本公开实施例中，微控制单元中包括存储器和处理器，存储器上存储有计算机程序/指令，在计算机程序/指令的作用下，微控制单元可以实现唤醒/休眠机制中的控制逻辑。
本公开实施例中，第一CAN收发器中包括存储器和处理器，存储器上存储有计算机程序/指令，在计算机程序/指令的作用下，第一CAN收发器可以支持本公开实施例的唤醒/休眠机制。
本公开实施例中，电源管理单元中包括存储器和处理器，存储器上存储有计算机程序/指令，在计算机程序/指令的作用下，电源管理单元可以支持本公开实施例的唤醒/休眠机制。
本公开实施例中，触发器中包括存储器和处理器，存储器上存储有计算机程序/指令，在计算机程序/指令的作用下，触发器可以支持本公开实施例的唤醒/休眠机制。
本公开实施例中的控制器可以是车载控制器，用于车辆中。本公开实施例提供了一种车辆，包括前述任一实施例的控制器、CAN总线以及电源。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。对于车辆实施例而言，其相关之处参见控制器实施例的部分说明即可。
本说明书的实施例可以涉及方法和/或计算机程序产品。计算机程序产品可以包括计算机可读存储介质，其上载有用于使处理器实现本说明书实施例的各个方面的计算机指令。
以上已经描述了本说明书的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (20)

  1. 一种控制器，其特征在于，所述控制器包括电源管理电路、微控制单元、第一CAN收发器、或逻辑电路以及唤醒触发锁存电路；
    所述电源管理电路用于控制电源为所述微控制单元供电；
    所述微控制单元的电源保持信号端口与所述或逻辑电路的第一输入端连接，所述或逻辑电路的输出端与所述电源管理电路的使能端(EN’)连接；
    所述微控制单元的第一控制端分别与所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端连接；
    所述第一CAN收发器的第一信号发送端(RXD)与所述唤醒触发锁存电路的触发输入端连接，所述唤醒触发锁存电路的唤醒输出端与所述或逻辑电路的第二输入端连接；
    所述或逻辑电路用于根据所述微控制单元的电源保持信号端口输出的电源保持信号和所述唤醒触发锁存电路的唤醒输出端输出的唤醒信号控制所述微控制单元的上电或下电，其中，所述唤醒触发锁存电路用于在所述微控制单元下电后，响应于所述第一CAN收发器接收到的唤醒报文将所述唤醒信号锁存在第一电平状态。
  2. 根据权利要求1所述的控制器，其特征在于，所述微控制单元用于在需要休眠时，通过所述第一控制端控制所述第一CAN收发器进入待机模式并控制所述唤醒触发锁存电路进入预锁存状态，并且将所述电源保持信号端口设置为第二电平状态。
  3. 根据权利要求2所述的控制器，其特征在于，所述第一CAN收发器用于在所述待机模式下监听CAN总线，以及在监听到唤醒报文时，通过所述第一信号发送端(RXD)触发所述唤醒触发锁存电路进入锁存状态并输出第一电平的唤醒信号。
  4. 根据权利要求1所述的控制器，其特征在于，所述微控制单元还用于在上电后，将所述电源保持信号端口设置为第一电平的状态，并且通过所述第一控制端控制所述第一CAN收发器进入正常工作模式并控制所述唤醒触发锁存电路解锁。
  5. 根据权利要求1所述的控制器，其特征在于，所述或逻辑电路的第三输入端用于接入硬线唤醒信号，所述硬线唤醒信号用于控制所述微控制单元上电。
  6. 根据权利要求1所述的控制器，其特征在于，所述唤醒触发锁存电路用于在进入预锁存状态后，在所述第一信号发送端(RXD)发生从第一电平切换至第二电平的事件的情况下，进入锁存状态并输出高电平的唤醒信号。
  7. 根据权利要求1-6任一项所述的控制器，其特征在于，所述唤醒触发锁存电路包括下降沿 触发的触发器。
  8. 根据权利要求7所述的控制器，其特征在于，所述触发器为D触发器(U2)；
    D触发器(U2)的第一通道的异步复位端(1CLR-)与所述唤醒触发锁存电路的锁存控制端连接；
    D触发器(U2)的第一通道的时钟端(1CLK-)与所述唤醒触发锁存电路的触发输入端连接；
    D触发器(U2)的第一通道的输出端(1Q)与所述唤醒触发锁存电路的唤醒输出端连接。
  9. 根据权利要求8所述的控制器，其特征在于，所述唤醒触发锁存电路还包括：第七电容(C7)、第九电容(C9)以及第十电容(C10)；
    D触发器(U2)的电源端(VCC)、D触发器(U2)的第一通道的输入端(1D)以及D触发器的第一通道的异步置位端(1PRE-)，分别与所述唤醒触发锁存电路的电源端连接；
    D触发器(U2)的第一通道的异步复位端(1CLR)通过第七电容(C7)接地；
    D触发器(U2)的第一通道的异步置位端(1PRE-)通过第十电容(C10)接地；
    D触发器(U2)的电源端(VCC)通过第九电容(C9)接地。
  10. 根据权利要求1-6任一项所述的控制器，其特征在于，所述唤醒触发锁存电路包括第一开关控制单元和第二开关控制单元；
    所述第一开关控制单元和所述第一CAN收发器的第一信号发送端(RXD)连接，所述第二控制单元和所述微控制单元的第一控制端连接；其中，所述第一开关控制单元导通时会触发所述第二开关控制单元导通，所述第二开关控制单元导通后维持所述第一开关控制单元的导通状态，以使得所述第一开关控制单元将所述唤醒信号锁存在第一电平状态。
  11. 根据权利要求10所述的控制器，其特征在于，
    所述第一开关控制单元包括第四三极管(Q4)、第四二极管(D4)、第八电阻(R8)以及第十一电阻(R11)，所述第二开关控制单元包括第五三极管(Q5)、第六三极管(Q6)、第十电阻(R10)以及第十三电阻(R13)，其中，第四三极管(Q4)为PNP型三极管，第五三极管(Q5)和第六三极管(Q6)为NPN型三极管；
    第四三极管(Q4)的基极与第四二极管(D4)的正极连接，第四二极管(D4)的负极与所述唤醒触发锁存电路的触发输入端连接；
    第四三极管(Q4)的发射极与所述唤醒触发锁存电路的电源端连接，第四三极管(Q4)的集电极与第十一电阻(R11)的第一端连接，第十一电阻(R11)的第二端与第十三电阻(R13)的第一端连接，第十三电阻(R13)的第二端接地；
    第五三极管(Q5)的基极与第十一电阻(R11)的第二端连接，第五三极管(Q5)的集电极通过第十 电阻(R10)与第四二极管(D4)的正极连接，第五三极管(Q5)的发射极与第六三极管(Q6)的集电极连接；
    第六三极管(Q6)的基极与所述唤醒触发锁存电路的锁存控制端连接，第六三极管(Q6)的发射极接地；
    第八电阻(R8)串联在第四三极管(Q4)的发射极和第四二极管(D4)的正极之间；
    第四三极管(Q4)的集电极与所述唤醒触发锁存电路的唤醒输出端连接。
  12. 根据权利要求11所述的控制器，其特征在于，所述唤醒触发锁存电路还包括第九电阻(R9)和第十二电阻(R12)；
    第九电阻(R9)串联在第四二极管(D4)的负极和所述唤醒触发锁存电路的触发输入端之间；
    第十二电阻(R12)串联在第六三极管(Q6)的基极和所述唤醒触发锁存电路的锁存控制端之间。
  13. 根据权利要求1-6任一项所述的控制器，其特征在于，所述控制器还包括待机模式设置电路；
    所述微控制单元的第一控制端通过所述待机模式设置电路分别与所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端连接，其中，所述微控制单元的第一控制端与所述待机模式设置电路的输入端连接，所述待机模式设置电路的输出端分别与所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端连接；
    所述待机模式设置电路用于对所述第一控制端输出的控制信号(MCU-STB)进行电平转换后分别输出至所述第一CAN收发器的待机模式设置端口(STB)和所述唤醒触发锁存电路的锁存控制端。
  14. 根据权利要求13所述的控制器，其特征在于，所述待机模式设置电路包括第一电阻(R1)、第十八电阻(R18)以及第一三极管(Q1)，其中，第一三极管(Q1)为NPN型三极管；
    第一三极管(Q1)的基极与所述待机模式设置电路的输入端连接，第一三极管(Q1)的集电极通过第一电阻(R1)与所述待机模式设置电路的电源端连接，第一三极管(Q1)的发射极接地；
    第一三极管(Q1)的集电极与所述待机模式转换电路的输出端连接；
    所述待机模式设置电路的输入端通过第十八电阻(R18)接地。
  15. 根据权利要求14所述的控制器，其特征在于，所述待机模式设置电路还包括第三电阻(R3)；
    所述第三电阻(R3)串联在所述第一三极管(Q1)的基极和所述待机模式设置电路的输入端之间。
  16. 根据权利要求13所述的控制器，其特征在于，所述第一CAN收发器的电源端、所述唤醒触发锁存电路的电源端、所述待机模式设置电路的电源端分别接常电源。
  17. 根据权利要求13所述的控制器，其特征在于，所述控制器还包括压降电路，所述压降电 路用于将高电压的常电源转成低电压的常电源后分别提供至所述第一CAN收发器的电源端、所述唤醒触发锁存电路的电源端、所述待机模式设置电路的电源端。
  18. 根据权利要求1-6任一项所述的控制器，其特征在于，所述控制器还包括防倒灌电路；
    所述防倒灌电路连接在所述第一CAN收发器的第一信号发送端(RXD)和所述微控制单元的总线信号接收端之间；
    所述防倒灌电路用于防止所述第一CAN收发器在待机模式下将电流倒灌至所述微控制单元。
  19. 根据权利要求18所述的控制器，其特征在于，所述防倒灌电路包括第十五电阻(R15)和第三二极管(D3)；
    第三二极管(D3)的正极与所述微控制单元的总线信号接收端连接，第三二极管(D3)的负极与所述第一CAN收发器的第一信号发送端(RXD)连接；
    所述第十五电阻(R15)的一端与电源管理电路的对外供电端口连接，另一端与第三二极管D3的正极连接。
  20. 一种车辆，其特征在于，所述车辆具有权利要求1-19任一项所述的控制器、CAN总线以及电源。
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