WO2023216817A1 - Processeur et procédé d'auto-détection et système associé, mémoire et unité d'éclairage intelligente - Google Patents

Processeur et procédé d'auto-détection et système associé, mémoire et unité d'éclairage intelligente Download PDF

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Publication number
WO2023216817A1
WO2023216817A1 PCT/CN2023/089020 CN2023089020W WO2023216817A1 WO 2023216817 A1 WO2023216817 A1 WO 2023216817A1 CN 2023089020 W CN2023089020 W CN 2023089020W WO 2023216817 A1 WO2023216817 A1 WO 2023216817A1
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WO
WIPO (PCT)
Prior art keywords
processor
storage space
abnormal
data storage
main timer
Prior art date
Application number
PCT/CN2023/089020
Other languages
English (en)
Chinese (zh)
Inventor
杨健荣
Original Assignee
厦门荣汇源科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 厦门荣汇源科技有限公司 filed Critical 厦门荣汇源科技有限公司
Publication of WO2023216817A1 publication Critical patent/WO2023216817A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L5/00—Local operating mechanisms for points or track-mounted scotch-blocks; Visible or audible signals; Local operating mechanisms for visible or audible signals
    • B61L5/12—Visible signals
    • B61L5/18—Light signals; Mechanisms associated therewith, e.g. blinders
    • B61L5/1809—Daylight signals
    • B61L5/1845—Optical systems, lenses
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L5/00—Local operating mechanisms for points or track-mounted scotch-blocks; Visible or audible signals; Local operating mechanisms for visible or audible signals
    • B61L5/12—Visible signals
    • B61L5/18—Light signals; Mechanisms associated therewith, e.g. blinders
    • B61L5/1809—Daylight signals
    • B61L5/1881—Wiring diagrams for power supply, control or testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Definitions

  • the invention relates to the field of software processing, and in particular to a processor and its self-test method, system, memory and intelligent lighting unit.
  • the processor (such as MCU) is the heart of many electronic devices and is indispensable. Moreover, its performance directly affects the performance of the electronic device. If there is a problem with the processor, the electronic device may lose control in some cases, or in serious cases it may fail. causing accidents.
  • the intelligent lighting unit under the control of its internal processor, can make the two LED lamp beads in the bulb automatically light alternately and cycle, and can also automatically detect faults and trigger alarms.
  • the processor since the working environment of the railway signal light system is easily affected by external electromagnetic interference or encounters other extreme conditions, there is a certain probability that the processor will make an error, causing the two LED beads in the bulb to fail to cycle normally or alarm normally, reducing the The reliability of the railway signal light system is affected, and safety accidents may even occur. .
  • the technical problem to be solved by the present invention is that there is a defect in the existing technology that the processor may make errors due to strong magnetism or other serious interference, causing loss of control or accidents in electronic equipment.
  • the technical solution adopted by the present invention to solve the technical problem is to construct a self-test method of the processor, which includes:
  • the program storage space of the processor is detected and judged whether the program storage space is abnormal. Moreover, when abnormal, the current status is recorded and the processor is restarted, and remains unchanged after the restart. the recorded status;
  • the step of regularly detecting the data storage space of the processor and determining whether the data storage space is abnormal includes:
  • the initial calculated value is obtained by performing verification calculations on all data in the data storage space of the processor in advance;
  • it also includes:
  • the periodic detection of the data storage space of the processor and determining whether the data storage space is abnormal include:
  • it also includes:
  • the method of detecting the program storage space of the processor in each execution cycle and determining whether the program storage space is abnormal includes:
  • the step of detecting the main timer of the processor and determining whether the main timer is abnormal includes:
  • the step of detecting the main timer of the processor and determining whether the main timer is abnormal includes:
  • the auxiliary timer and the main timer respectively determine whether their respective timing times have arrived, and when they arrive, clear the other party's count value to zero, wherein the timing time of the auxiliary timer and the main timer are the same;
  • the count value of the auxiliary timer is not greater than 1, it is determined that the main timer is normal.
  • the invention also constructs a processor self-test system, which includes:
  • the data detection module is used to regularly detect the data storage space of the processor according to the first preset period, and determine whether the data storage space is abnormal. Moreover, when abnormal, restart the processor and perform all the data storage operations on the processor. Initialize the above data storage space;
  • the program detection module is used to detect the program storage space of the processor in each program execution cycle, and determine whether the program storage space is abnormal. Moreover, when abnormal, record the current status and perform inspection on the processor. Restart, and maintain the recorded status after restarting;
  • the timer detection module is used to regularly detect the main timer of the processor according to the second preset period, and determine whether the main timer is abnormal, and, when abnormal, perform the hardware parameters of the main timer. Reconfigure so that the main timer runs again.
  • the present invention also constructs a processor that implements the steps of any of the above self-test methods when executing a stored computer program.
  • the present invention also constructs a memory that stores a computer program, and when the computer program is executed by the processor, the steps of the above self-test method are implemented.
  • the present invention also constructs an intelligent lighting unit, which is applied to the LED railway signal light system and includes the above-mentioned processor.
  • the technical solution provided by the present invention detects the data storage space, program storage space and main timer of the processor respectively, and when an abnormality is detected, the abnormality is eliminated in time to ensure the normal operation of the electronic equipment and avoid the occurrence of accidents.
  • Figure 1 is a flow chart of Embodiment 1 of the self-test method of the processor of the present invention
  • FIG. 2 is a logical structure diagram of Embodiment 1 of the LED railway signal light system of the present invention.
  • FIG. 3 is a logical structure diagram of Embodiment 1 of the self-test system of the processor of the present invention.
  • FIG. 1 is a flow chart of Embodiment 1 of a self-test method for a processor of the present invention.
  • the self-test method in this embodiment includes the following steps:
  • Step S10 Regularly detect the data storage space of the processor according to the first preset period, and determine whether the data storage space is abnormal. Moreover, when abnormal, restart the processor and perform the data storage operation on the processor. Space is initialized;
  • the data stored in the data storage space includes: the switching time of the two LED lamp bead circuits, the recorded fault information, etc.
  • Step S20 Detect the program storage space of the processor in each program execution cycle, and determine whether the program storage space is abnormal. Moreover, when abnormal, record the current status and restart the processor, and Maintain the recorded status after restarting;
  • the main program stored in its program storage space is implemented when executed: obtained from the fault detection modules 131, 132 Corresponding to the detection results of the LED lamp beads 210, 220 and their circuits, and based on the detection results of the two LED lamp beads 210, 220 and their circuits, when the first condition is met, the two constant current drive modules 121, 122 are used to control the two LED lamp beads 210, 220 and their circuits.
  • the LED lamp beads 210 and 220 are alternately in the lighting state; when the second condition is met, the normal LED lamp beads 210 or 220 are controlled to be in the lighting state through the corresponding constant current drive module 121 or 122, and the alarm module 140 alarm; when neither the first condition nor the second condition is satisfied, the power control module 160 controls the two constant current drive modules 121 and 122 to stop working to trigger the first alarm 300 to alarm. It needs to be explained here What is important is that the first alarm 300 is set at the front end (main control room), and its relay drive coil is connected in series with the primary side winding of the transformer of the power module.
  • the first alarm triggers an alarm because the current on its relay driving coil is much lower than the pickup current.
  • the first condition is: both LED lamp beads and their circuits are normal; the second condition is: one LED lamp bead and its circuit are normal, and the other LED lamp bead or its circuit has an open circuit failure or the other LED lamp bead A light failure failure occurred.
  • this step detects whether the program storage space of the processor is abnormal due to interference from extreme external conditions. If an abnormality occurs, the current working status is recorded and the processor chip is automatically restarted. After the restart, the working status before the restart is maintained.
  • Step S30 Detect the main timer of the processor regularly according to the second preset period, and determine whether the main timer is abnormal. Furthermore, when abnormal, reconfigure the hardware parameters of the main timer to Make the main timer run again.
  • a processor chip usually contains multiple timers, and the applied timer can be used as the main timer, that is, the timer to be tested, and other timers can be used as auxiliary timers.
  • This step detects the working status of the main timer. If the main timer stops working or changes the counting period due to severe electromagnetic interference from the outside or other extreme circumstances, the hardware parameters of the main timer are actively reconfigured to make the main timer run again.
  • the data storage space, program storage space and main timer of the processor are respectively detected, and when an abnormality is detected, the abnormality is eliminated in time to ensure the normal operation of the electronic equipment and avoid the occurrence of accidents. .
  • steps S10, S20, and S30 are timing
  • the timing cycles may be the same or different; step S20 is performed in each program execution cycle.
  • step S10 of an optional embodiment whether the data storage space of the processor is abnormal can be determined by the following method:
  • the initial calculated value is obtained by performing verification calculations on all data in the data storage space of the processor in advance;
  • data verification calculations can be performed on all data in the data storage space of the processor in advance (for example, when the data in the data storage space is updated) according to a preset algorithm to generate an initial calculation value, And the initial calculated value is stored in specific locations in the program storage space and data storage space.
  • the processor When the processor is running, it can regularly perform verification calculations on all the data in the data storage space according to the preset algorithm to generate the current calculation value, and then compare the current calculation value with the initial calculation value stored in the two places to see whether it is consistent. If there is any inconsistency, the data storage space is considered abnormal.
  • step S10 of an optional embodiment whether the data storage space of the processor is abnormal can be determined by the following method:
  • a set of specific data (first specific data) is randomly written in the data storage space, and then regularly checked whether the set of specific data changes. If it changes, the data stored in the entire data storage space is considered Unreliable.
  • step S20 of an optional embodiment whether the program storage space of the processor is abnormal can be determined by the following method:
  • a set of specific data (second specific data) is randomly written in the program storage space (ROM) of the processor.
  • ROM program storage space
  • multiple sets of specific data can also be written. The correctness of this specific data is checked at every program execution cycle. If an error occurs, the program storage space is considered unreliable.
  • step S30 of an optional embodiment whether the main timer of the processor is abnormal can be determined in the following manner:
  • a watchdog is set in the main loop, and the main timer performs the dog feeding action regularly.
  • the main timer stops working or slows down, an error occurs in the dog feeding cycle, and the main loop can determine that the dog feeding is abnormal.
  • step S30 of an optional embodiment whether the main timer of the processor is abnormal can be determined in the following manner:
  • the auxiliary timer and the main timer respectively determine whether their respective timing times have arrived, and when they arrive, clear the other party's count value to zero, wherein the timing time of the auxiliary timer and the main timer are the same;
  • the count value of the auxiliary timer is not greater than 1, it is determined that the main timer is normal.
  • a timer that is not used in the processor is used as an auxiliary timer, that is, a guard timer, and maintains the same timing period as the main timer. Moreover, the two perform count-clearing operations on each other when their respective timing times arrive. If the count value of one party is greater than 1, it is considered that the other party's timer is working abnormally.
  • Figure 3 is a logical structure diagram of the first embodiment of the self-test system of the processor of the present invention.
  • the self-test system of this embodiment includes: a data detection module 10, a program detection module 20, and a timer detection module 30.
  • the data detection module 10 Used to regularly detect the data storage space of the processor according to the first preset period, and determine whether the data storage space is abnormal, and, when abnormal, restart the processor, and check the data storage space Initialization is performed;
  • the program detection module 20 is used to detect the program storage space of the processor in each program execution cycle, and determine whether the program storage space is abnormal.
  • the timer detection module 30 is used to regularly detect the main timer of the processor according to the second preset period, and determine whether the main timer is abnormal, and, In the event of an exception, the hardware parameters of the main timer are reconfigured so that the main timer runs again.
  • the present invention also constructs a processor, which implements the steps of the above self-test method when executing a stored computer program.
  • the processor may be a central processing unit (CPU), or other general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), or an application specific integrated circuit (Application Specific Integrated Circuit). Specific Integrated Circuit (ASIC), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general processor can be a microprocessor or any conventional processor.
  • the processor can implement the steps of any self-test method provided by the embodiments of the present invention when executing the computer program, it is possible to realize the benefits that can be achieved by any self-test method provided by the embodiments of the present invention.
  • the processor can implement the steps of any self-test method provided by the embodiments of the present invention when executing the computer program, it is possible to realize the benefits that can be achieved by any self-test method provided by the embodiments of the present invention.
  • the present invention also constructs a memory that stores a computer program, and when the computer program is executed by the processor, the steps of the above self-test method are implemented.
  • the readable storage medium may include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), magnetic disk or optical disk, and other computer-readable storage media that can store program codes.
  • the computer program stored in the readable storage medium can implement the steps of any self-test method provided by the embodiment of the present invention when executed, any self-test method provided by the embodiment of the present invention can be implemented.
  • the beneficial effects that can be achieved by the self-test method are detailed in the previous embodiments and will not be described again here.
  • the present invention also constructs an intelligent lighting unit, which is applied to the LED railway signal light system.
  • the intelligent lighting unit includes the above-mentioned processor.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)

Abstract

La présente invention concerne un processeur et un procédé d'auto-détection et un système associé, une mémoire et une unité d'éclairage intelligente. Le procédé d'auto-détection consiste : à détecter périodiquement un espace de stockage de données du processeur selon une première période prédéfinie, et à déterminer si l'espace de stockage de données est anormal ; à redémarrer le processeur lorsque l'espace de stockage de données est anormal, et à initialiser l'espace de stockage de données ; à détecter un espace de stockage de programme du processeur dans chaque période d'exécution de programme, et à déterminer si l'espace de stockage de programme est anormal ; en outre, à enregistrer l'état actuel lorsque l'espace de stockage de programme est anormal, à redémarrer le processeur, et à maintenir l'état enregistré après redémarrage ; et à détecter périodiquement un temporisateur principal du processeur selon une seconde période prédéfinie, à déterminer si le temporisateur principal est anormal, et à reconfigurer des paramètres matériels du temporisateur principal lorsque le temporisateur principal est anormal.
PCT/CN2023/089020 2022-05-10 2023-04-18 Processeur et procédé d'auto-détection et système associé, mémoire et unité d'éclairage intelligente WO2023216817A1 (fr)

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Application Number Priority Date Filing Date Title
CN202210504021.1A CN114996061A (zh) 2022-05-10 2022-05-10 处理器及其自检方法、系统、存储器及智能点灯单元
CN202210504021.1 2022-05-10

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114996061A (zh) * 2022-05-10 2022-09-02 厦门荣汇源科技有限公司 处理器及其自检方法、系统、存储器及智能点灯单元

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170010933A1 (en) * 2015-07-08 2017-01-12 Microsoft Technology Licensing, Llc High availability and energy-efficient watchdog timer
CN107943603A (zh) * 2016-10-13 2018-04-20 迈普通信技术股份有限公司 一种运行状态检测方法、检测电路及电子设备
CN111008099A (zh) * 2018-10-08 2020-04-14 新唐科技股份有限公司 自我检测系统及其方法
CN114996061A (zh) * 2022-05-10 2022-09-02 厦门荣汇源科技有限公司 处理器及其自检方法、系统、存储器及智能点灯单元

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170010933A1 (en) * 2015-07-08 2017-01-12 Microsoft Technology Licensing, Llc High availability and energy-efficient watchdog timer
CN107943603A (zh) * 2016-10-13 2018-04-20 迈普通信技术股份有限公司 一种运行状态检测方法、检测电路及电子设备
CN111008099A (zh) * 2018-10-08 2020-04-14 新唐科技股份有限公司 自我检测系统及其方法
CN114996061A (zh) * 2022-05-10 2022-09-02 厦门荣汇源科技有限公司 处理器及其自检方法、系统、存储器及智能点灯单元

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