WO2023208320A1

WO2023208320A1 - Transceiver with antenna switch incorporating input impedance matching for receiver amplifier

Info

Publication number: WO2023208320A1
Application number: PCT/EP2022/060984
Authority: WO
Inventors: Mustafa ÖZEN; Anders Nejdel
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2023-11-02

Abstract

A transceiver (200) comprising a receiver comprising a receiver amplifier (LNA 210), a transmitter comprising a power amplifier (PA 220), an antenna switch (230) having a first port (A), a second port (Rx) and a third port (Tx). The transceiver (200) further comprises a direct current (DC) blocking capacitor (CDC). The first port (A) of the antenna switch (230) is to be connected to an antenna. The second port (Rx) of the antenna switch (230) is directly connected to a first terminal (211) of the DC blocking capacitor (CDC). An input terminal (212) of a transistor (Q3) comprised in the receiver amplifier (LNA 210) is directly connected to a second terminal (213) of the DC blocking capacitor (CDC). The third port (Tx) of the antenna switch (230) is connected to an output (PAout) of the power amplifier (PA 220) via an impedance matching network (PA MN 240).

Description

TRANSCEIVER WITH ANTENNA SWITCH INCORPORATING INPUT IMPEDANCE

MATCHING FOR RECEIVER AMPLIFIER

TECHNICAL FIELD

Embodiments herein relate to a transceiver. In particular, they relate to a transceiver with an improved antenna switch and an electronic device comprising the transceiver.

BACKGROUND

A wireless communication device or equipment usually comprises an antenna, a transceiver comprising a transmitter (Tx) and a receiver (Rx), and a baseband processing unit. The transmitter typically up-converts baseband signals to Radio Frequency (RF) signals for transmission, and the receiver down-converts received RF signals to baseband signals for further processing in the baseband processing unit.

In RF transceivers, typically the same antenna is used for both transmitting and receiving. In most implementations, in transmitting mode (Tx mode), the receiver port is isolated from the transmitter port to protect a low-noise-amplifier (LNA) in the receiver. Similarly, in receiving mode (Rx mode), the receiver port is isolated from the transmitter port to avoid loading of the transmitter. Low loss transmitter-receiver (TRx) switches with high isolation are key components for realization of high performance, Time Division Duplexing (TDD) RF transceivers for 5^th generation (5G) wireless communication systems. TRx switches may also be refereed as antenna switches.

A conventional TRx switch 100 suitable for Complementary Metal Oxide Semiconductor (CMOS) technology implementations is shown in Figure 1 , where Rx branch 110 with an example LNA core circuitry is also shown. The TRx switch 100 has a receiver Rx port, a transmitter Tx port and an antenna A port. For typical frequencies used for a wireless communication system, e.g. 300 MHz to 300 GHz, matching networks 120, 130 are used to transform impedances at Rx and Tx ports to optimal impedances needed for LNA 110 and power amplifier (PA) 140, respectively.

In CMOS realizations, it is preferred that the transistors Q1 , Q2 of the TRx switch 100 are turned-on or switched-on in the Tx mode from reliability point of view. The transistors Q1 , Q2 might otherwise have large swings when the PA 140 generates high power signals. As seen from the schematic, Q2 is used as a series switch and switched-off to isolate Tx branch (not shown) from the Rx branch in Rx mode. An inductor L2 may be used to resonate out an output capacitance of Q2 when it is switched-off to further reduce the loading of the transmitter branch in Rx mode. Q1 is used as a shunt switch and switched-on to protect the Rx branch in Tx mode. A quarter wave transmission line TL is used to transform switch on resistance of the transistor Q1 , which is typically nearly a short circuit, to a high impedance to avoid loading of the Tx branch. The matching network 120, 130 are also needed after the TRx switch 100 to transform antenna impedance to optimal impedances desired by LNA and PA.

In conventional transceiver realizations, the TRx switch presents ideally the antenna impedance at the Tx and Rx ports. As mentioned, additional matching networks 120, 130 are required after the TRx switch 100 for impedance matching. Due to conductive substrate of semiconductor technology, inductors used for impedance matching have high losses in CMOS technologies. This causes high losses from PA output PAout and LNA input LNAin to the antenna port A, which directly effects noise figure of the LNA and efficiency of the PA.

SUMMARY

It is therefore an object of embodiments herein to provide a transceiver with an improved antenna switch to increase performance of the transceiver.

According to one aspect of embodiments herein, the object is achieved by a transceiver comprising a receiver comprising a receiver amplifier, a transmitter comprising a power amplifier and an antenna switch having a first port, a second port and a third port. The antenna switch comprises a first inductor coupled between the first port and the second port, a first switching transistor coupled between the first port and a signal ground, a second inductor coupled between the first port and the third port, a second switching transistor coupled between the first port and the third port and a first capacitor coupled between the first port and the signal ground.

The transceiver further comprises a direct current (DC) blocking capacitor. The first port of the antenna switch is connected to an antenna. The second port of the antenna switch is directly connected to a first terminal of the DC blocking capacitor. An input terminal of a transistor comprised in the receiver amplifier is directly connected to a second terminal of the DC blocking capacitor. The third port of the antenna switch is connected to an output of the power amplifier via an impedance matching network.

According to some embodiments herein, an input impedance of the antenna switch at the second port may be designed based on a desired source admittance for the receiver amplifier such that impedance matching network for the receiver amplifier is incorporated into the antenna switch. The desired source admittance for the receiver amplifier may be determined based on noise or power performance of the receiver amplifier or based on a trade-off between noise and power performance of the receiver amplifier. In other words, embodiments herein provide a TRx switch solution, where the matching network for the receiver amplifier e.g. an LNA, is incorporated into the TRx switch. The component values of the TRx switch can be derived in terms of the optimal impedance for the LNA, i.e. the desired source admittance for the receiver amplifier. The optimal impedance for the LNA may be determined based on noise or power performance of the LNA or based on a trade-off between noise and power performance. That is, with the optimal impedance, the LNA has the lowest noise figure or maximum power or has an improved performance on both noise and power.

Integrating or incorporating the LNA input impedance matching into the TRx switch enables a lower noise-figure, lower losses and a reduced area for a transceiver. Only a single inductor, i.e. the first inductor, is needed for both LNA matching and isolation of the Rx from the Tx. Further, the design approach is fully analytical.

Therefore, embodiments herein provide a transceiver with an improved antenna switch to increase performance of the transceiver with respect to noise figure, losses, and area.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments herein are described in more detail with reference to attached drawings in which:

Figure 1 is a schematic block view of a conventional TRx switch;

Figure 2 is a schematic block view of a transceiver according to embodiments herein;

Figure 3 is a schematic block view of a transceiver in Tx mode according to embodiments herein;

Figure 4 is a schematic block view of a transceiver in Rx mode according to embodiments herein;

Figure 5 is a schematic block view of a conventional transceiver;

Figure 6 shows simulation results of LNA noise figure for the conventional and the proposed transceiver;

Figure 7 shows simulation results of losses from Tx port to antenna port in the Tx mode for the conventional and the proposed transceiver;

Figure 8 shows simulation results of reflection coefficient seen from the Tx port for the conventional and the proposed transceiver; and

Figure 9 is a block diagram illustrating a wireless communication device in which a transceiver according to embodiments herein may be implemented. DETAILED DESCRIPTION

Figure 2(a) shows a schematic view of a transceiver 200 according to embodiments herein. The transceiver 200 comprises a receiver comprising a receiver amplifier LNA 210, a transmitter comprising a power amplifier PA 220 and an antenna switch 230 having a first port, an antenna port A, a second port, a receiver port Rx and a third port, a transmitter port Tx.

The antenna switch 230 comprises a first inductor L1 coupled between the first port A and the second port Rx, a first switching transistor Q1 coupled between the first port A and a signal ground gnd, a second inductor L2 coupled between the first port A and the third port Tx, a second switching transistor Q2 coupled between the first port A and the third port Tx, and a first capacitor C1 coupled between the first port A and the signal ground gnd.

The transceiver 200 further comprises a direct current (DC) blocking capacitor CDC-

The first port A of the antenna switch 230 is to be connected to an antenna (not shown), the second port Rx of the antenna switch 230 is directly connected to a first terminal 211 of the DC blocking capacitor CDC, an input terminal 212 of a transistor Q3 comprised in the receiver amplifier LNA 210 is directly connected to a second terminal 213 of the DC blocking capacitor CDC-

The third port Tx of the antenna switch 230 is connected to an output PAout of the power amplifier PA 220 via an impedance matching network PA MN 240.

The receiver amplifier LNA 210 shown in Figure 2(a) is just one example design. The proposed antenna switch 230 will work with any other LNA configuration.

According to some embodiment herein, the receiver amplifier LNA 210 may be a common source or emitter amplifier, as shown in Figure 2(a), the input terminal of the transistor comprised in the receiver amplifier LNA 210 is a gate or base terminal of the transistor, e.g. the gate terminal 212 of the transistor Q3.

According to some embodiment herein, the receiver amplifier LNA 210 may be a common gate or base amplifier, as shown in Figure 2(b), and the input terminal of the transistor comprised in the receiver amplifier LNA 210 is a source or emitter terminal of the transistor, e.g. the source terminal 212 of the transistor Q3.

As shown in Figure 2(a) and (b), the Rx port of the antenna switch 230 is directly connected to the input LNAin of the receiver amplifier LNA 210 without a matching network in between. Only a DC-bias network, i.e. the DC blocking capacitor CDC, is needed between the antenna switch 230 and the gate terminal 212 of transistor Q3 in the receiver amplifier LNA 210. In this way, the total loss from the input LNAin of the receiver amplifier LNA 210 to the antenna port A maybe reduced. It also helps for reducing the size of the transceiver 200. Moreover, the proposed antenna switch 230 does not require a quarter wave transmission line impedance transformer, which will reduce the losses and size of the transceiver 200 even further.

Although the transistors Q1 , Q2, Q3, Q4 shown in Figures 2(a) and (b) are implemented using N-type metal-oxide-semiconductor (NMOS) transistors, P-type Metal Oxide Semiconductor (PMOS) transistors, Complementary Metal Oxide Semiconductor (CMOS) transistors, Silicon on Insulator (SOI) CMOS transistors, or other types of fieldeffect transistors (FETs) and Bi-polar transistors implementation are also possible.

An input impedance of the antenna switch 230 at the second port Rx is designed based on a desired source admittance, Y_opt = G_opt + jB_opt, for the receiver amplifier LNA 210 such that impedance matching network for the receiver amplifier LNA 210 is incorporated into the antenna switch 230. That is the input impedance of the antenna switch 230 at the second port Rx is designed in terms of an optimal admittance Y_opt or impedance Z_opt = 1/Y_opt for the receiver amplifier LNA 210. The optimal admittance Y_opt or impedance Z_opt for the receiver amplifier LNA 210 is the source admittance/impedance needed or desired by the receiver amplifier LNA 210 for either an optimal noise performance or an optimal power performance, or a trade-off between optimal noise and power performance. That is, with the optimal admittance/impedance, the receiver amplifier LNA 210 may have the lowest or minimum noise figure or maximum power or have an improved performance on both noise and power.

Therefore, according to some embodiments herein, the desired source admittance/ impedance for the receiver amplifier LNA 210 may be determined based on noise performance, i.e. for optimizing noise performance, or based on power performance, i.e. for optimizing power performance, or based on a trade-off between noise and power performance, i.e. for optimizing performance on both noise and power, of the receiver amplifier LNA 210.

The input admittance/impedance of the antenna switch 230 at the second port Rx is the admittance/impedance seen by the receiver amplifier LNA 210 from the Rx port towards the antenna switch 230, which is related to the first inductor L1 , the first capacitor C1 and the first switching transistor Q1 . Therefore, the component values of the first inductor L1 and the first capacitor C1 and a size of the first switching transistor Q1 in the antenna switch 230 are derived based on the desired source admittance/ impedance for the receiver amplifier LNA 210 with a constraint that the first inductor L1 and the first capacitor C1 form a parallel resonance circuit resonating at a transmitting signal frequency when the transceiver 200 is in transmitting (TX) mode.

Figure 3 shows an equivalent circuit representation for the transceiver 200 in Tx mode, where the first and second switching transistors Q1 , Q2 are switched on and represented by switch on resistance R_oni, R_On2 respectively. The first inductor L1 together with the series on-resistance R_oni of the first switching transistors Q1 will form a parallel resonance circuit with the first capacitor C1 . The parallel resonance circuit resonates at a transmitting signal frequency and provides a high impedance at the antenna port A when the transceiver 200 is in TX mode to avoid loading of the transmitter.

In the following, the component values for the first inductor L1 , the first capacitor C1 and an output capacitance C_outl of the first switching transistor Q1 will be derived analytically. The output capacitance C_outl of the first switching transistor Q1 is related to the size of the first switching transistor Q1 .

The input impedance of the antenna switch 230 seen from the Rx port should be equal to the optimal source impedance needed for the receiver amplifier LNA 210, i.e. Z_opt = 1/Y_opt, i-^e-> the desired source impedance for the LNA 210 to achieve optimal performance.

In the analysis, it is assumed that L1 and C1 are in resonance and form a parallel resonance circuit in transmitting (Tx) mode. This ensures that there is no loading on the transmitter from the receiver.

The analysis is based on an equivalent circuit of the transceiver 200 shown in Figure 4, where the antenna switch 230 is represented by an equivalent circuit when the transceiver 200 is in receiving (Rx) mode, the first and second switching transistors Q1 , Q2 are switched off and represented by output capacitances C_outi and C_out2, respectively. The input admittance seen from the LNAin node, i.e. the Rx port, Y_LNAin = Y_opt, can be written as:

Y_opt = G_opt + jB_opt = BLI/G_L + j (B_Coutl + B_L1) (2) where B_L1, B_Coutl are susceptance’s of L1 and C_outl. G_L is a load conductance of the antenna, which is typically 1/50 fl^-1. Note that, as L1 and C1 are in resonance, B_L1 = -B_C1.

From the equations above, B_L1, B_Coutl are derived as following:

Ecouti ^— B_opt + G L G _Op_t (4)

The component values are derived as following:

Where, G_opt is a conductance of the desired source admittance for the receiver amplifier LNA 210, G_L is antenna load conductance, co_o is an angular frequency in radians per second of a transmitting or receiving signal. For the antenna switch 230 working in a TDD system, the transmitting and receiving signals have the same frequency.

According to some embodiments herein, a size of the second switching transistor Q2 may be derived such that a level of losses when the transceiver 200 is in transmitting (TX) mode is below a threshold and the second inductor L2 may be chosen to resonate out an output capacitance C_out2 of the second switching transistor Q2 when the transceiver 200 is in receiving (RX) mode and the second switching transistor Q2 is switched off.

Based on the analysis above, a design procedure can be defined as:

• Performing simulations to find the required or desired source impedance for the receiver amplifier LNA 210 to achieve the minimum NF or the maximum power or an optimal performance for both noise and power;

• Calculating the components values according to equations (5)-(7);

• Choosing a size of the first transistor Q1 to achieve an output capacitance of Couti ! • Choosing a size of the second transistor Q2 to have an output capacitance C_out2 and choosing the inductor value of the second inductor L2 to achieve a good balance between the losses in the Tx mode and loading in the Rx mode.

To demonstrate the performance and advantages of the transceiver 200 with the antenna switch 230 according to embodiments herein, the performance of the proposed antenna switch 230 is simulated and compared with a conventional antenna switch. A cascode LNA 210 is used for the simulations, as shown in Figures 1-4. An antenna impedance of 50 fl is assumed. The proposed antenna switch 230 implementation has the same schematic shown in Figures 2 and 4 except that no PA matching network PA MN 240 is implemented. In the conventional design, a series inductance L_in is used for input impedance matching of the LNA 210 as shown in Figure 5, where a conventional antenna switch 530 is shown. Note that in the proposed solution as shown in Figures 1-4, this inductor is not needed as the LNA 210 input impedance matching is integrated into the antenna switch 230. The resulting component values are summarized in Table 1 for both cases.

Table 1 : Summary of components values for the antenna (TRx) switches

The NF simulation results are shown in Figure 6, where the proposed antenna switch 230 provides 0.7 dB NF improvement at the center frequency. Losses in the Tx mode is plotted in Figure 7. The Tx loss is around 0.7-0.9 dB across a designed band of 24.25-29.5 GHz for both solutions, and the Tx loss for the proposed antenna switch 230 is 0.03 dB lower than the conventional antenna switch. The reflection coefficient S_X1 seen from the Tx port is shown in Figure 8. Both solutions provide an S_X1 of better than -19 dB across the band of 24.25-29.5 GHz, and the S_X1 of the proposed antenna switch 230 is 1 .2 dB lower than that of the conventional antenna switch.

The transceiver 200 according to the embodiments herein may be employed in various electronic circuits or devices. Figure 9 shows a block diagram for an electronic device 900. The electronic device 900 comprises a transceiver 200 according to the embodiments herein. The electronic device 900 may comprise other units, where a memory 920, a processing unit 930 are shown. The electronic device 900 may be a user equipment or a mobile device, a wireless communication device, a radio base station, an access point, a relay or a repeater for a cellular communication system.

To summarize, the transceiver 200 according to the embodiments herein incorporating the input impedance matching network for the receiver amplifier LNA 210 into the antenna switch 230. The component values of the antenna switch 230 are derived in terms of the optimal impedance needed or desired for the receiver amplifier LNA 210. At the optimal impedance, the receiver amplifier LNA 210 has the optimal performance either on noise or on power or has the optimal performance on both noise and power. Thanks to the integrating or incorporating of the receiver amplifier LNA input impedance matching into the antenna switch 210, only a single inductor L1 is needed for both the receiver amplifier LNA 210 input matching and isolation of the receiver from the transmitter, thus a lower noise figure, lower losses and a reduced area for a transceiver are achieved compared to the conventional antenna switch. Further, embodiments herein have derived and provided design equations for the antenna switch 230 and the design approach can thus be fully analytical. However, the design can also be performed using simulations. The analytical expressions above can then, for instance, be used as suitable starting values for the simulations. It should also be noted that, depending on application, it is not required to use optimal component values, but component values that give good enough performance, e.g. good enough impedance matching, for a given application can suffice. What is considered “good enough” can, of course, differ between different applications.

The transceiver 200 according to the embodiments herein has an improved antenna switch 210 and thus the performance of the transceiver 200 with respect to noise figure, power and losses have been improved and the area of the transceiver 200 has been reduced compared to a transceiver with the conventional antenna switch. Those skilled in the art will understand that the transceiver 200 according to embodiments herein may be implemented by any semiconductor technology, e.g. Bi-polar, NMOS, PMOS, CMOS, FET or Micro-Electro-Mechanical Systems (MEMS) technology etc. The word "comprise" or “comprising”, when used herein, shall be interpreted as nonlimiting, i.e. meaning "consist at least of".

The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1 . A transceiver (200) comprising: a receiver comprising a receiver amplifier (LNA 210); a transmitter comprising a power amplifier (PA 220); and an antenna switch (230) having a first port (A), a second port (Rx) and a third port (Tx), wherein the antenna switch (230) comprises: a first inductor (L1 ) coupled between the first port (A) and the second port

(Rx), a first switching transistor (Q1 ) coupled between the first port (A) and a signal ground (gnd), a second inductor (L2) coupled between the first port (A) and the third port (Tx), a second switching transistor (Q2) coupled between the first port (A) and the third port (Tx), and a first capacitor (C1) coupled between the first port (A) and the signal ground (gnd); and wherein the transceiver (200) further comprises a direct current, DC, blocking capacitor (CDC); the first port (A) of the antenna switch (230) is to be connected to an antenna; the second port (Rx) of the antenna switch (230) is directly connected to a first terminal (211 ) of the DC blocking capacitor (CDC); an input terminal (212) of a transistor (Q3) comprised in the receiver amplifier (LNA 210) is directly connected to a second terminal (213) of the DC blocking capacitor (CDC); and the third port (Tx) of the antenna switch (230) is connected to an output (PAout) of the power amplifier (PA 220) via an impedance matching network (PA MN 240).

2. The transceiver (200) according to claim 1 , wherein the input terminal (212) of the transistor (Q3) comprised in the receiver amplifier (LNA 210) is a gate or base terminal of the transistor.

3. The transceiver (200) according to claim 1 , wherein the input terminal of the transistor comprised in the receiver amplifier (LNA 210) is a source or emitter terminal of the transistor.

4. The transceiver (200) according to any one of claims 1 -3, wherein an input impedance of the antenna switch (230) at the second port (Rx) is designed based on a desired source admittance, Y_opt = G_opt + jB_opt, for the receiver amplifier (LNA 210) such that impedance matching network for the receiver amplifier (LNA 210) is incorporated into the antenna switch (230).

5. The transceiver (200) according to claim 4, wherein component values of the first inductor (L1 ) and the first capacitor (C1 ) and a size of the first switching transistor (Q1 ) are derived based on the desired source admittance for the receiver amplifier (LNA 210) with a constraint that the first inductor (L1 ) and the first capacitor (C1 ) form a parallel resonance circuit resonating at a transmitting signal frequency when the transceiver is in transmitting mode.

6. The transceiver (200) according to claim 5, wherein an inductor value for the first inductor (L1 ) is calculated by equation:

and a capacitance value for the first capacitor (C1 ) is calculated by equation:

Wherein, G_opt is a conductance of the desired source admittance for the receiver amplifier (LNA 210), G_L is antenna load conductance, co_o is an angular frequency in radians per second of a transmitting or receiving signal.

7. The transceiver (200) according to any one of claims 4-6, wherein the size of the first switching transistor (Q1 ) is designed to achieve an output capacitance by equation:

Wherein B_opt is a susceptance of the desired source admittance for the receiver amplifier (LNA 210), G_opt is a conductance of the desired source admittance for the receiver amplifier (LNA 210), G_L is antenna load conductance, co_o is an angular frequency in radians per second of a transmitting or receiving signal.

8. The transceiver (200) according to any one of claims 4-7, wherein a size of the second switching transistor (Q2) is derived such that a level of losses when the transceiver (200) is in transmitting mode is below a threshold and the second inductor (L2) is chosen to resonate out an output capacitance (C_out2) of the second switching transistor (Q2) when the transceiver is in receiving mode.

9. The transceiver (200) according to any one of claims 4-8, wherein the desired source admittance, Y_opt = G_opt + jB_opt, for the receiver amplifier (LNA 210) is determined based on noise or power performance of the receiver amplifier (LNA 210) or based on a trade-off between noise and power performance of the receiver amplifier (LNA 210).

10. An electronic device (900) comprising a transceiver (200) according to any one of claims 1-9.

11 . The electronic device (900) according to claim 10 is any one of a base station, a wireless communication device, a user equipment, an access point, a relay or a repeater for a communication system.