WO2014020297A1

WO2014020297A1 - Radio frequency transceivers

Info

Publication number: WO2014020297A1
Application number: PCT/GB2013/051139
Authority: WO
Inventors: Franco Lauria
Original assignee: Toumaz Microsystems Limited
Priority date: 2012-07-30
Filing date: 2013-05-02
Publication date: 2014-02-06
Also published as: GB201213513D0; GB2504488A

Abstract

A radio frequency transceiver comprising: a transmitter comprising a power amplifier forming the output stage of a transmitter chain; a receiver comprising a low noise amplifier forming the input stage of a receiver chain; an impedance matching circuit; a branching radio frequency path connecting said power amplifier and low noise amplifier to said matching circuit, and a further radio frequency path connecting said matching circuit to an antenna; wherein said low noise amplifier comprises a receiver amplifying device, and a single series switch is placed in the radio frequency path between said receiver amplifying device and said antenna to achieve switching of said transceiver between receive and transmit modes; and wherein said power amplifier comprises a transmitter amplifying transistor which operates as an amplifier in said transmit mode and which operates as an isolation device in said receive mode, said isolation device isolating said power amplifier from said branching radio frequency path in said receive mode.

Description

Radio frequency transceivers

FIELD OF THE INVENTION

The invention relates to radio frequency transceivers, and to an area and power efficient on-chip switch for switching between transmit and receive modes.

BACKGROUND OF THE INVENTION

In wireless communication systems it is known to use an antenna to both transmit (TX) and receive (RX) in a time division duplex manner. As shown in Figure 1 , a time division duplex transceiver (8, 10) may employ a single antenna 4 for transmission and reception with a TX RX switch and interface circuit (6), containing matching networks 1 1 , connecting the antenna 4 to a receive Low Noise Amplifier (LNA) 8 and transmit Power Amplifier (PA) 10.

To maximize power efficiency, typically the transmit (TX) and receive (RX) circuits are integrated on a chip and operate at large on chip impedance while being interfaced with a lower impedance antenna (typically about 50 Ohm). Switches 6 are used to connect the antenna 4 to the Power Amplifier 10 in TX mode, and to connect the antenna 4 to the Low Noise Amplifier 8 in RX mode, while matching networks 1 1 provide impedance matching between the antenna 4 and the Low Noise Amplifier 8 and Power Amplifier 10. Also, conflicting matching requirements are needed for TX and RX functions. The result is a complex circuit that consumes a large die area if integrated on chip or requires costly off chip components if implemented on a printed circuit board (PCB). Also as the TX/RX switch 6 is in cascade to the Transceiver (8, 10) the switch insertion loss degrades TX and RX performances. SUMMARY OF THE INVENTION

The invention provides a radio frequency transceiver as set out in the accompanying claims. BRIEF DESCRIPTION OF THE FIGURES

Figure 1 shows a known arrangement in which an antenna is connected to a transmitter and receiver operating in a time division duplex manner;

Figure 2 shows a first embodiment of the invention; and

Figure 3 shows a second embodiment of the invention. DESCRIPTION OF PREFERRED EMBODIMENTS

The embodiments described integrate a switch and impedance matching into a simple single RF (radio frequency) interface and modify the Low Noise Amplifier and Power Amplifier designs in order to keep the bulk of the design away from the signal path, thus minimizing the RF losses and implementation size. The implementation size is reduced due to the fact that (1 ) a common and simpler matching network common to both TX and RX is employed and (2) a single series switch is used in RX mode only, whilst in TX mode there is no series switch in the RF path. Figure 2 shows a simplified diagram outlining an embodiment of the invention. A Low Noise Amplifier 12 forms the input stage of a receiver chain (not shown), and a Power Amplifier 14 forms the output stage of a transmitter chain (not shown). An inductor 16 (labelled Lmatch in Figure 2) and a capacitor 18 (labelled Cmatch in Figure 2) form a matching network 20. The matching network 20 matches the impedance of an antenna 22 (about 50 Ohm) with the higher impedances (800-1200 Ohm), of the Low Noise Amplifier 12 and Power Amplifier 14 which high impedances are required for Low Noise Amplifier noise and power matching and to maximize Power Amplifier efficiency and transmit power. The matching network 20 serves two purposes: (a) to maximize power transfer from the antenna 22 to the LNA 12 and (b) to minimize LNA noise.

Two transistors T5 and T6 are used as switches to select TX or RX bias voltages. To implement the RX or TX function, the Low Noise Amplifier input 24 and Power Amplifier output 26 are connected together to the single RF port 28. Transistors T5 and T6 are used to implement a SPDT (single pole double throw) switch, that connects the appropriate bias voltage (labelled VDD PA and Bias LNA in Figure 2) to the AC ground terminal 30 of the Matching inductor 16.

In TX mode, T5 turns on, T6 turns off and the DC bias voltage for the Power Amplifier 14 (Vbias PA) is connected to the inductor 16. In RX mode, T5 turns off, T6 turns on and the DC bias voltage for the Low Noise Amplifier 12 (VBias LNA) is connected to the inductor 16.

Nine transistors, labelled T1 to T9 in Figure 2, are used to implement the switching arrangement. Table 1 below gives a summary of the states of each of the transistors T1 to T9 in receive (RX) mode and transmit (TX) mode.

Table 1

Low Noise Amplifier Block

T1 is the input transistor of the Low Noise Amplifier 12. T2 is a series switch closed (ie ON) in RX mode and open (ie OFF) in TX mode so that the Low Noise Amplifier input is connected to the RF port 28 in RX mode, while it is disconnected in TX mode. T2 is a high voltage device, as in TX mode there are large voltage swings across its terminals.

Power Amplifier block

T3 and T4 form the last stage of the Power Amplifier 14, and together form a cascode amplifier. T3 is a low voltage device designed to provide large transconductance gain, while T4 is a cascode device chosen to cope with the large TX output voltage swings. In TX mode the gate of T4 is connected to VDD, making it operate as a cascode. In this mode the Power Amplifier 14 operates as in a standard Power Amplifier (ie a power amplifier without a TX RX switch). In RX mode the gate of T4 is connected to ground disconnecting the Power Amplifier 14 from the antenna 22. Simulations show that the Power Amplifier performance is largely unaffected, with similar power and efficiency to the standard Power Amplifier. The Power Amplifier output will see an additional capacitance due to T2 drain but this can be tuned out adjusting the matching network.

When the Transceiver is in RX mode, the Power Amplifier 14 is disconnected from the RF port 28 by turning off T4, T7 is open (ie OFF) and T8 is closed (ie ON) to guarantee that T4 is off. T8 ensures that the gate of T4 is at zero potential, by shorting any accumulated charge to ground.

Matching Network

The matching network in its simplest form comprises the inductor 16 (L match), which acts as a shunt inductor, as shown in Figure 2.

The shunt inductor 16 is needed to provide a DC bias voltage to the RF port 28. If required, alternative matching networks can be used as long as a DC bias voltage path exists from Vbias to the RF port 28.

Figure 3 below shows the TXRX switch with a matching network 31 which uses two inductors 32 and 34. The other components of Figure 3 are the same as those of Figure 2. It should be noted that in the embodiments of Figures 2 and 3 only a single matching network (20, 31 ) is required, and the matching network (20, 31 ) provides the required impedance matching in both transmit and receive modes. A single RF port 28 forms part of a branching radio frequency path 36 which connects the matching network (20, 31 ) to each of the Low Noise Amplifier 12 and the Power Amplifier 14. The branching radio frequency path 36 comprises a branching point 38 (ie at the RF port 28) at which radio frequency paths from the matching network 20, Low Noise Amplifier 12 and Power Amplifier 14 meet each other. No passive components (inductors or capacitors) are required between the branching point 38 and the Low Noise Amplifier 12, or between the branching point 38 and the Power Amplifier 14.

It will be seen that the embodiments provide a transmit / receive switch requiring no additional passive RF components, and using a single FET switch, T2, in the RF path. In Figure 2 the RF path starts at the antenna 22 and for the receiver ends at the drain of T1 (labelled To receive chain in Figure 2), and for the transmitter starts at the gate of T3 (labelled From transmit chain in Figure 2) and ends at the antenna 22.

The embodiments provide the following advantages: No insertion loss in TX mode - No series switch is provided between the Power Amplifier output device T4 and RF port 28. Note that in TX mode, T4 is not a series switch which causes insertion loss, but is instead a common gate amplifier, an integral part of the Power Amplifier design and is required even if TX/RX switching functionality is not required. T4 need not necessarily be a FET, and could instead be a bipolar transistor arranged as a common base amplifier.

The output stage of the Power Amplifier 14 is composed of T3, configured as a common source amplifier and T4 a common gate amplifier. This is part of the Power Amplifier design and would be there even if a RX function is not necessary.

By setting the gate of T4 to zero in RX mode, T4 can be switched off, disconnecting the TX circuit from the RF port 28. The fact that T4 is a common gate amplifier makes T4 the best candidate to be switched off in RX mode. This is because in normal operation, a common gate amplifier has no voltage swing at its gate (the gate is at zero potential), so the addition of T7 and T8 does not compromise performance and their size can be small. Therefore T4 is a transistor which operates as an amplifier in transmit mode, and in receive mode T4 operates as an isolation device which isolates the Power Amplifier 14 from the RF port 28 and the rest of the radio frequency path between the antenna 22, Low Noise Amplifier 12 and Power Amplifier 14.

Small Insertion loss in RX mode - As the series switch, T2, is placed after the impedance matching network 20, its resistance causes negligible power loss.

Low chip area/Low cost - A single, simple matching network for TX and RX requiring no additional costly external components, such as the components in block 6 in Figure 1 .

Claims

CLAIMS:

1 . A radio frequency transceiver comprising :

a transmitter comprising a power amplifier forming the output stage of a transmitter chain;

a receiver comprising a low noise amplifier forming the input stage of a receiver chain;

an impedance matching circuit;

a branching radio frequency path connecting said power amplifier and low noise amplifier to said matching circuit,

and a further radio frequency path connecting said matching circuit to an antenna;

wherein said low noise amplifier comprises a receiver amplifying device, and a single series switch is placed in the radio frequency path between said receiver amplifying device and said antenna to achieve switching of said transceiver between receive and transmit modes;

and wherein said power amplifier comprises a transmitter amplifying transistor which operates as an amplifier in said transmit mode and which operates as an isolation device in said receive mode, said isolation device isolating said power amplifier from said branching radio frequency path in said receive mode.

2. A transceiver as claimed in claim 1 , wherein said transmitter amplifying transistor is a FET arranged as a common gate amplifier or a bipolar transistor arranged as a common base amplifier.

3. A transceiver as claimed in claim 1 or 2, wherein said transmitter amplifying transistor is part of a cascode which forms part of said power amplifier.

4. A transceiver as claimed in any preceding claim, wherein said branching radio frequency path comprises a branching point at which radio frequency paths from said matching circuit, said power amplifier and said low noise amplifier meet each other, and wherein no inductor or capacitor is positioned between said branching point and said single series switch.

5. A transceiver as claimed in any preceding claim, wherein said branching radio frequency path comprises a branching point at which radio frequency paths from said matching circuit, said power amplifier and said low noise amplifier meet each other, and wherein no inductor or capacitor is positioned between said branching point and said transmitter amplifying transistor.

6. A transceiver as claimed in any preceding claim, wherein said impedance matching network performs impedance matching in both said transmit mode and said receive mode.

7. A transceiver as claimed in claim 6, wherein said impedance matching network is the only impedance matching network in the radio frequency paths connecting said antenna to said power amplifier and said low noise amplifier.

8. A transceiver as claimed in any preceding claim, wherein said receiver amplifying device is a FET.

9. A transceiver as claimed in any preceding claim, wherein said receiver amplifying device is the first amplifying device of said low noise amplifier when following the radio frequency path from the antenna to the low noise amplifier.

10. A transceiver as claimed in any preceding claim, wherein said single switch is a FET having a source and drain which are connected in series with the radio frequency path between said low noise amplifier and said antenna.

1 1 . A transceiver as claimed in any preceding claim, wherein no additional series switch is provided in the radio frequency path between said transmitter amplifying transistor and said antenna.

12. A transceiver as claimed in any preceding claim, wherein said transmitter amplifying transistor is the final amplifying device of said power amplifier when following the radio frequency path from said power amplifier to said antenna.

13. A transceiver as claimed in any preceding claim, wherein said impedance matching circuit comprises a single inductor.

14. A transceiver as claimed in any preceding claim, wherein at least one DC bias voltage is provided to the transmitter or receiver through said matching circuit.

15. A transceiver as claimed in any preceding claim, wherein said impedance matching circuit is positioned between said antenna and said single series switch.

16. A transceiver as claimed in any preceding claim, wherein said single series switch is an on-chip switch.