WO2023208178A1

WO2023208178A1 - Information processing method and unit, chip, device, medium, and product

Info

Publication number: WO2023208178A1
Application number: PCT/CN2023/091515
Authority: WO
Inventors: 吴臻志; 何伟; 祝夭龙
Original assignee: 北京灵汐科技有限公司
Priority date: 2022-04-29
Filing date: 2023-04-28
Publication date: 2023-11-02

Abstract

The present invention relates to an information processing method and unit, a chip, a device, a medium, and a product. The information processing method comprises: on the basis of difference information between information to be processed of a neuron and target information, executing a processing operation of the information to be processed, wherein the information to be processed comprises a weight value of the neuron, target information corresponding to the weight value comprises a weight value interval, the processing operation comprises storage processing that the storage accuracy of the weight value is adjusted or storage processing that the storage accuracy is not adjusted, and/or the information to be processed comprises a membrane potential of the neuron, target information corresponding to the membrane potential comprises a resting potential, and the processing operation comprises storage processing or discard processing on the membrane potential.

Description

Information processing methods and processing units, chips, equipment, media, and products

Technical field

Embodiments of the present disclosure relate to the field of computer technology, and in particular, to an information processing method and a processing unit, a chip, an electronic device, a computer-readable storage medium, and a computer program product.

Background technique

The neural network may include multiple neurons, at least some of the multiple neurons may communicate with each other through synapses, and corresponding weight values may be set between at least some of the synapses. Normally, the weight values are stored with a unified storage precision, and the storage precision is generally high. In addition, the neuron information of the neurons can also be stored so that the neurons can perform processing actions based on the neuron information.

Contents of the invention

Embodiments of the present disclosure provide an information processing method and a processing unit, a chip, an electronic device, a computer-readable storage medium, and a computer program product.

In a first aspect, embodiments of the present disclosure provide an information processing method, including: performing a processing operation on the information to be processed based on the difference information between the information to be processed and the target information of the neuron; wherein the information to be processed is Including the weight value of the neuron, the target information corresponding to the weight value includes a weight value interval, the processing operation includes a storage process of adjusting the storage accuracy of the weight value or a storage process of not adjusting the storage accuracy, and/or, the The information to be processed includes the membrane potential of the neuron, the target information corresponding to the membrane potential includes the resting potential, and the processing operation includes storage processing or discarding processing of the membrane potential.

In some embodiments, the information processing method can be applied to weight storage, and the information processing method includes: dividing all weight values between neurons of the current processing core and neurons of the target processing core into multiple target weights. Reorganization, the target weight group includes multiple target weight values; for each target weight group, determine whether each target weight value in the target weight group is located within the target weight value range; if it is determined that each target weight If the values are all within the target weight value range, then each target weight value is stored according to the target storage precision, and the target storage precision is lower than the current storage precision of the target weight value.

In some embodiments, the information processing method may be applied to a chip that simulates at least one neuron through at least one computing core it includes; the information processing method may include: obtaining each of the at least one neuron. a current membrane potential of the neuron; in response to the current membrane potential being different from the resting potential of the neuron, associated storage of the current membrane potential and the neuron information of the neuron; in response to the current The membrane potential is the same as the resting potential, and the current membrane potential is discarded.

In a second aspect, embodiments of the present disclosure provide an information processing unit, including: a processing subunit configured to perform a processing operation on the information to be processed based on the difference information between the information to be processed and the target information of the neuron; Wherein, the information to be processed includes the weight value of the neuron, the target information corresponding to the weight value includes the weight value interval, and the processing operation includes storage processing of adjusting the storage accuracy of the weight value or storage without adjusting the storage accuracy. processing, and/or, the information to be processed includes the membrane potential of the neuron, the target information corresponding to the membrane potential includes the resting potential, and the processing operation includes storage processing or discarding processing of the membrane potential.

In some embodiments, the processing subunit may include a weight storage device, and the weight storage device may include: a dividing module configured to divide all weight values between neurons of the current processing core and neurons of the target processing core into Multiple target weight groups, the target weight group includes multiple target weight values; the judgment module is configured to determine for each target weight group whether each of the target weight values in the target weight group is located in the target weight value range within; a storage module configured to store each target weight value according to the target storage accuracy when the judgment module determines that each target weight value is located within the target weight value interval, and the target storage The accuracy is lower than the currently stored accuracy of the target weight value.

In some embodiments, the processing subunit may include a neuron information processing device, which may be applied to a chip that simulates at least one neuron through at least one computing core it includes; the neuron information processing device The device may include: an acquisition module configured to acquire a current membrane potential of each of the at least one neuron; a storage module configured to respond to the current membrane potential and the resting state of the neuron. If the potentials are different, the current membrane potential and the neuron information of the neuron are stored in association; in response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded.

In a third aspect, embodiments of the present disclosure provide a chip that simulates at least one neuron through at least one computing core it includes; wherein the computing core is configured to be based on the to-be-processed information and target information of the neuron. difference information between them, and perform the processing operation of the information to be processed; wherein the information to be processed includes the weight value of the neuron, the target information corresponding to the weight value includes the weight value interval, and the processing operation includes The storage processing in which the weight value adjusts the storage accuracy or the storage processing in which the storage accuracy is not adjusted, and/or the information to be processed includes the membrane potential of the neuron, and the target information corresponding to the membrane potential includes static information potential, and the processing operation includes storage processing or discarding processing of the membrane potential.

In some embodiments, the chip simulates at least one neuron through at least one computing core it includes; wherein the computing core is configured to obtain the current membrane of each of the at least one neuron. potential; in response to the current membrane potential being different from the resting potential of the neuron, correlating and storing the current membrane potential and the neuron information of the neuron; in response to the current membrane potential being different from the resting potential Same, discard the current membrane potential.

In a fourth aspect, embodiments of the present disclosure provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the embodiments of the present disclosure are implemented. Any information processing method.

In a fifth aspect, embodiments of the present disclosure provide a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, any information processing method of the embodiments of the disclosure is implemented.

In a sixth aspect, embodiments of the present disclosure provide a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is in a processor of an electronic device When running, the processor in the electronic device executes the information processing method described in any one of the embodiments of the present disclosure.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of the drawings

Figure 1 is a flow chart of an information processing method provided by an embodiment of the present disclosure.

FIG. 2 is a schematic flowchart of an information processing method provided by an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a method of dividing target weight groups provided by an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a method of dividing target weight groups provided by an embodiment of the present disclosure.

FIG. 5 is a schematic diagram of a method of dividing target weight groups provided by an embodiment of the present disclosure.

Figure 6 is a flow chart of an information processing method provided by an embodiment of the present disclosure.

Figure 7 is a flow chart of an information processing method provided by an embodiment of the present disclosure.

FIG. 8 is a schematic flowchart of an information processing method provided by an embodiment of the present disclosure.

Figure 9 is a schematic diagram of a method for obtaining resting potential according to an embodiment of the present disclosure.

Figure 10 is a schematic flowchart of a method for obtaining current membrane potential according to an embodiment of the present disclosure.

Figure 11 is a schematic flowchart of a method for obtaining current membrane potential according to an embodiment of the present disclosure.

Figure 12 is a block diagram of an information processing unit provided by an embodiment of the present disclosure.

Figure 13 is a block diagram of a weight storage device provided by an embodiment of the present disclosure.

Figure 14 is a block diagram of a weight storage device provided by an embodiment of the present disclosure.

Figure 15 is a block diagram of a neuron information processing device provided by an embodiment of the present disclosure.

Figure 16 is a block diagram of a chip provided by an embodiment of the present disclosure.

Figure 17 is a block diagram of an electronic device provided by an embodiment of the present disclosure.

Figure 18 is a block diagram of an electronic device provided by an embodiment of the present disclosure.

Figure 19 is a block diagram of a computer-readable storage medium provided by an embodiment of the present disclosure.

Detailed ways

The present disclosure will be further described in detail below in conjunction with the accompanying drawings and examples. It can be understood that the specific embodiments described here are only used to explain the present disclosure, but not to limit the present disclosure. It should also be noted that, for convenience of description, only some but not all structures related to the present disclosure are shown in the drawings.

In the related art, a chip can be used to construct a neural network (for example, a neuromorphic chip). At least some of the multiple neurons in the neural network can communicate with each other through synapses, and at least some of the synapses can be provided with corresponding weight value.

In this type of chip, its computing core can be used to simulate at least one neuron in the neural network. Therefore, neuron information of the neurons is usually stored in this type of chip, thereby facilitating the neurons to perform processing actions based on the neuron information. The currently commonly used method is to store the neuron information of each neuron, so that each neuron can process accordingly based on its respective neuron information. This method of processing neuron information may cause neuron information to occupy too much storage space on the chip.

In addition, the weight values of neurons usually need to be stored, and the weight values of neurons are usually stored with a unified storage precision, and the storage precision is generally high to meet the storage of maximum and minimum values. When only some neurons have small weight values, in order to meet the storage requirements of these small weight values, it may result in all weight values being stored with a higher storage precision, or when all weight values of the neurons are equal In smaller cases, etc., it may lead to excessive and invalid use of storage space, thus It may put higher demands on chips (for example, storage requirements), which is not conducive to the production and expanded application of chips.

In view of this, embodiments of the present disclosure provide an information processing method and a processing unit, a chip, an electronic device, a computer-readable storage medium, and a computer program product.

The information processing method of the embodiment of the present disclosure performs the processing operation of the information to be processed based on the difference information between the information to be processed and the target information of the neuron; wherein the information to be processed includes the weight value of the neuron and the target corresponding to the weight value. The information includes a weight value interval, and the processing operation includes a storage process that adjusts the storage accuracy of the weight value or a storage process that does not adjust the storage accuracy, and/or the information to be processed includes the membrane potential of the neuron, and the target information corresponding to the membrane potential includes Resting potential, the processing operation includes storage processing or discarding processing of the membrane potential. It can be seen from this that in the embodiment of the present disclosure, on the one hand, when the information to be processed includes a weight value, it can be determined whether to adjust the storage accuracy of the weight value through the difference information between the weight value and the weight value interval, and The corresponding storage operation is performed based on the determined storage accuracy. Compared with the method of storing weight values according to a unified high storage accuracy, the processing method of the embodiment of the present disclosure can adjust the storage accuracy of the weight value if necessary, so that it is possible Reducing the ineffective occupation of storage space is equivalent to improving the utilization of storage resources; on the other hand, when the information to be processed includes membrane potential, it can be determined through the difference information between the membrane potential and the resting potential. Whether to store the membrane potential or discard the membrane potential, compared to storing all membrane potentials of neurons, the processing method of the embodiment of the present disclosure can only store the membrane potential of neurons in the working state, without storing the membrane potential in the non-working state. The membrane potential of the neuron can effectively save storage space; similarly, when the information to be processed includes both, similar processing operations can be performed on the weight value and membrane potential respectively.

The information processing method of the embodiment of the present disclosure can be executed by electronic equipment such as a terminal device or a server. The terminal device can be a vehicle-mounted device, user equipment (User Equipment, UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal Digital assistants (Personal Digital Assistant, PDA), handheld devices, computing devices, wearable devices, etc., the information processing method can be implemented by the processor calling computer-readable program instructions stored in the memory. Alternatively, the information processing method of the embodiment of the present disclosure may be executed through a server, where the server may be an independent physical server, a server cluster composed of multiple servers, or a cloud server capable of cloud computing.

In a first aspect, embodiments of the present disclosure provide an information processing method.

Figure 1 is a flow chart of an information processing method provided by an embodiment of the present disclosure. Referring to Figure 1, the information processing method includes:

In step S1, based on the difference information between the neuron's information to be processed and the target information, a processing operation of the information to be processed is performed;

Wherein, the information to be processed includes the weight value of the neuron, the target information corresponding to the weight value includes the weight value interval, and the processing operation includes storage processing of adjusting the storage accuracy of the weight value or storage processing without adjusting the storage accuracy, and/or, The information to be processed includes the membrane potential of the neuron, the target information corresponding to the membrane potential includes the resting potential, and the processing operation includes storing or discarding the membrane potential.

In some embodiments, the information processing method of the embodiment of the present disclosure may be applied to processing weight values.

In some embodiments, the information to be processed may include the weight value of the neuron, and the corresponding target information may include a weight value interval. The weight value interval may be a predetermined value range used to characterize the weight value. By comparing the weight value and the weight value interval, the difference information about the two can be obtained. This difference information can reflect the value relationship between the weight value and the weight value interval. For example, the difference information indicates that the weight value is located in the weight value interval. within, or the difference information indicates that the weight value is outside the weight value range. Correspondingly, according to the content represented by the difference information, it can be determined whether the storage accuracy of the weight value needs to be adjusted, and after the storage accuracy is determined, the storage processing of the weight value can be performed based on the determined storage accuracy. The determined storage precision may be the current storage precision of the weight value, or it may be a new storage precision after adjusting the current storage precision.

In some embodiments, multiple weight values can be grouped in advance to obtain at least one weight group (a weight group can include one or more weight values), and corresponding processing operations can be performed in units of weight groups.

Exemplarily, the information to be processed includes multiple target weight values of at least one target weight group, the target information includes a target weight value interval, and the difference information is used to characterize the range relationship between the multiple target weight values of the target weight group and the target weight value interval. , the processing operation includes performing storage processing of multiple target weight values with adjusted storage accuracy in target weight group units, or performing storage processing of multiple target weight values without adjusting storage accuracy in target weight group units.

In other words, the information to be processed may correspond to one or more target weight groups, and each target weight group includes at least one target weight value. For each target weight group, by comparing multiple target weight values and target weight value intervals in the target weight group, the relationship between the value ranges of the two can be clarified, thereby obtaining the corresponding difference information, and based on the difference information, the target can be targeted Multiple target weight values in the weight group determine whether the storage accuracy needs to be adjusted. When it is determined that the storage accuracy needs to be adjusted, multiple target weight values in the target weight group are stored with the adjusted storage accuracy. When it is determined that no adjustment is required In the case of storage precision, multiple target weight values within the target weight group are stored based on the current storage precision.

It should be noted that in related technologies, when storing the weight values of neurons, they are usually stored directly based on unified storage accuracy. It only needs to be stored, and the adjustment of the storage accuracy of the weight value is not considered. In the embodiment of the present disclosure, through the relationship between the weight value and the weight value interval, it can be determined whether the storage accuracy of the weight value needs to be adjusted, so that the invalid occupation of storage space can be minimized while meeting the usage requirements. Improved storage space utilization.

In some embodiments, the information processing methods of embodiments of the present disclosure may be applied to processing membrane potential.

In some embodiments, the information to be processed includes the current membrane potential of the neuron, the target information includes the resting potential of the neuron, and the difference information is used to characterize whether the current membrane potential of the neuron is the same as the resting potential of the neuron. The processing operation Including the storage operation of the current membrane potential, or the discarding operation of the current membrane potential.

In other words, when the current membrane potential is obtained, the current membrane potential is not stored directly, but by comparing whether the current membrane potential is the same as the resting potential, and based on the comparison result, it is determined whether to store the current membrane potential or discard the current membrane potential. .

It should be noted that in related technologies, after obtaining the membrane potential of a neuron, the membrane potential is usually directly stored for later use. This processing method does not take into account the working status of the neuron, but directly stores the membrane potential, so it may require more storage space. In the embodiment of the present disclosure, considering that the current working state of the neuron can be clarified through the current membrane potential and resting potential of the neuron, and based on this, it is determined whether the current membrane potential needs to be stored or whether the current membrane potential needs to be discarded, so it can be Reduce the amount of data that needs to be stored to a certain extent and reduce the amount of storage space occupied.

To sum up, the information processing method of the embodiment of the present disclosure can be applied to at least the following processing processes:

First, it can be applied to the storage process of the weight value of the neuron, that is, before storing the weight value of the neuron, first determine whether the storage accuracy of the neuron can be adjusted, and perform the weight value based on the adjusted storage accuracy. Adjustment.

Second, it can be applied to the storage process of the membrane potential of the neuron, that is, for the obtained membrane potential of the neuron, first compare the membrane potential with the resting potential of the neuron, and determine whether to store or discard it based on the comparison result. the membrane potential.

The information processing method according to the embodiment of the present disclosure will be described below with reference to FIGS. 2 to 11 .

Figure 2 is a schematic flowchart of an information processing method provided by an embodiment of the present disclosure, which can be applied to weight storage.

Referring to Figure 2, an embodiment of the present disclosure provides an information processing method, and the corresponding weight storage process may include:

Step S201: Divide multiple weight values between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups, and the target weight group includes multiple target weight values.

Many-core systems based on neuromorphic chips usually include multiple processing cores, and neurons can be loaded in at least some of the processing cores, and one or more neurons can be loaded in each processing core. Weight data (for example, weight values) corresponding to the connection relationship between each neuron of the current processing core and other neurons of other processing cores is usually stored in advance. When a neuron fires a pulse, the predecessor neuron or successor neuron obtains the weight data and performs related calculations based on the weight data.

In some embodiments, when the weight value is stored, it is stored in the form of a target weight group. The target weight group is formed by dividing the current processing core (the current processing core can be any processing core loaded with neurons in the many-core system). ) and the neurons of the target processing core are divided according to the target weight division method. The target weight group may include at least one target weight value, or may include multiple target weight values. Among them, the target weight group can be divided based on a variety of target weight division methods, and the embodiment of the present disclosure does not limit this.

In some embodiments, dividing the multiple weight values between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups includes: obtaining the multiple neurons of the current processing core and the target processing core. The weight value between multiple neurons; the weight value corresponding to at least one neuron in the current processing core is used as a target weight group. In other words, for each neuron in the current processing core, the weight value of the neuron and each neuron in the target processing core can be obtained, and the weight value corresponding to a neuron in the current processing core can be used as a Target weight grouping.

For example, all weight values between the neurons of the current processing core and the neurons of the target processing core can be divided according to the target weight division method, thereby obtaining one or more target weight groups.

For example, at least part of the weight values between the neurons of the current processing core and the neurons of the target processing core can be divided according to the target weight division method, thereby obtaining one or more target weight groups.

FIG. 3 is a schematic diagram of a division method of a target weight group provided by an embodiment of the present disclosure. FIG. 3 exemplarily shows a division method of weight values stored between the current processing core and the target processing core. As shown in Figure 3, the target weight group is divided as follows: for each neuron in the current processing core, obtain the weight value of the neuron and each neuron in the target processing core, and combine one neuron in the current processing core The weight value corresponding to the neuron is used as a target weight group, that is, using a neuron in the current processing core as an index, all weight values connected to the neuron in the target processing core are used as a target weight group. For example, as shown in Figure 3, neuron A1 in the current processing core can be used as an index to divide the weight values of all neurons connected to neuron A1 in the target processing core into a target weight group to divide the target weight group into The storage precision of the weight value is stored with precision 1. Alternatively, neuron A2 in the current processing core can also be used as an index to divide the weight values of all neurons connected to neuron A2 in the target processing core into a target weight group to store the weight values of the target weight group. The precision is stored as precision 2.

In some embodiments, the weight values corresponding to multiple neurons in the current processing core can also be used as a target weight group. For example, as shown in Figure 3, you can use neurons A3, A4, and A5 in the current processing core as indexes to divide the weight values of all neurons connected to neurons A3 to A5 in the target processing core into a target weight group. The storage precision of the weight value of the target weight group is stored as precision 3.

FIG. 4 is a schematic diagram of a division method of a target weight group provided by an embodiment of the present disclosure. FIG. 4 exemplarily shows a division method of weight values stored between the current processing core and the target processing core. As shown in Figure 4, the target weight group is divided as follows: obtain the weight value between each neuron in the current processing core and at least one neuron in the target processing core, and combine each neuron in the current processing core with the target processing core. The weight value between one neuron of the core is used as a target weight group, that is, using a neuron in the target processing core as an index, the weight value of each neuron in the current processing core connected to a neuron in the target processing core is The weight value serves as a target weight group. For example, as shown in Figure 4, neuron B1 in the target processing core can be used as an index to divide the weight values of all neurons connected to neuron B1 in the current processing core into a target weight group, so as to divide the target weight group into The storage precision of the weight value is stored with precision 1. Alternatively, neuron B3 in the target processing core can also be used as an index to divide the weight values of all neurons connected to neuron B3 in the current processing core into a target weight group to store the weight values of the target weight group. The precision is stored as precision 2.

In some embodiments, the weight values corresponding to multiple neurons in the target processing core can also be used as a target weight group. As shown in Figure 4, neurons B5, B6, and B7 in the target processing core can be used as indexes to divide the weight values of all neurons connected to neurons B5 to B7 in the current processing core into a target weight group. The storage precision of the weight value of the target weight group is stored as precision 3.

To sum up, in Figure 3, the source neuron (the neuron in the current processing core) is used as the index to determine the target weight group, and in Figure 4, the target neuron (the neuron in the target processing core) is used as the index to determine the target weight group. , both are two different weighted division forms based on the same division principle. In addition, it should be noted that in the target weight grouping method shown in Figures 3 and 4, the target processing core can be the successor core of the current processing core, or the target processing core can be the successor processing core of the current processing core. The embodiments of the present disclosure do not limit this.

FIG. 5 is a schematic diagram of a division method of a target weight group provided by an embodiment of the present disclosure. FIG. 5 exemplarily shows a division method of weight values stored between the current processing core and the target processing core. As shown in Figure 5, the target weight group can use the weight value between some neurons in the current processing core and some neurons in the target processing core as a target weight group. As shown in Figure 5, the weight values between the neurons A1 to A3 in the current processing core and the neurons B1 to B3 in the target processing core can be divided into a target weight group to store the weight of the target weight group. The accuracy is stored as accuracy 1. In the same way, the weight values between the neurons A1 to A3 in the current processing core and the neurons B4 to B7 in the target processing core can also be divided into a target weight group to divide the target weight. The reorganized weight storage precision is stored as precision 2. It should be noted that in this embodiment, the intersection between any two target weight groups among multiple target weight groups is an empty set (it can also be referred to as no intersection between any two target weight groups among multiple target weight groups). ).

In some embodiments, in step S201, the neuron of the current processing core and the target neuron of the target processing core can be obtained by querying the pre-stored corresponding weight value between the current neuron of the current processing core and the target neuron of the target processing core. Multiple weight values between neurons of the target processing core. For example, these weight values can be obtained by querying the synaptic array used to store the weight values corresponding to the neurons in the current processing core.

Step S202: For each target weight group, determine whether multiple target weight values in the target weight group are within the target weight value range.

In some embodiments, for each target weight group, it can be determined whether each target weight value is within the target weight value range. For example, for each target weight group, determine whether all target weight values in the target weight group are within the target weight value range.

In some embodiments, the target weight value interval is a preset value interval used to determine the storage accuracy of the target weight value. The determination condition of the target weight value interval may be: having at least a preset proportion of weights in the many-core system The value belongs to the target weight value range. For example, the preset ratio is 90%.

In addition, it should be noted that in some embodiments, based on the distribution characteristics of weight values in many-core systems in this field, the determined target weight value range is usually smaller than the value range to which all weight values in the many-core system belong. For example, the numerical range to which all weight values in the many-core system belong is [-50, 50], and the target weight value range can be [-10, 10], where the target weight value range represents the large number of weights in the many-core system. Some (for example, 90%) of the weight values belong to the numerical interval [-10,10].

In some embodiments, the target weight value interval can be determined based on experience by those skilled in the art.

In some embodiments, the target weight value range may be determined based on statistical calculations of all weight values included in the many-core system.

It should be noted that the above method of determining the target weight value interval is only an example, and the embodiment of the present disclosure does not limit this.

In step S202, for each target weight group, if it is determined that multiple target weight values of the target weight group are located within the target weight numerical interval, it means that each target weight value in the target weight group belongs to a smaller numerical interval. Therefore, there may be no need to use a higher storage precision for storage. Therefore, step S203 can be performed to store multiple target weight values of the target weight group with a storage precision lower than the current storage precision, thereby reducing the occupation of storage space; When it is determined that at least one target weight value among the multiple target weight values in the target weight group is outside the target weight value range, it means that there may be a maximum value or a minimum value among the multiple target weight values in the target weight group. , therefore, it is still necessary to use a higher storage precision for storage to completely store all the target weight values of the target weight group. At this time, the current storage accuracy of each target weight value of the target weight group remains unchanged, that is, Each target weight value of the target weight group continues to be stored with the current storage precision.

Step S203: When the multiple target weight values of the target weight group are within the target weight value range, store the multiple target weight values according to the target storage precision, which is lower than the current storage precision of the target weight value.

Step S204: If at least one target weight value among the multiple target weight values in the target weight group is outside the target weight value range, keep the current storage accuracy of the multiple target weight values in the target weight group unchanged.

In some embodiments, the target storage accuracy can be determined based on the target weight value interval, and the target storage accuracy should at least meet the storage byte requirements for the values included in the target weight value interval. For example, when the maximum value contained in the target weight value interval does not exceed 127 and the minimum value is not less than -128, the target storage precision can be set to an 8-bit integer (int8).

In addition, it should be noted that in the embodiment of the present disclosure, the target storage accuracy is lower than the current storage accuracy of the target weight value. This is because the target weight value range is compared with the values to which all weight values in the many-core system belong. The interval has been reduced, so the target storage accuracy must be lower than the current storage accuracy of the target weight value.

In some embodiments, in order to minimize the impact of storage precision on the weight value during subsequent changes, the type of the target storage precision can be kept the same as the type of the current storage precision. For example, if the current storage precision is floating point, the type of the target storage precision can still be floating point. Among them, the current storage precision can be floating point storage precision or integer storage precision.

In the embodiment of the present disclosure, when storing the weight values corresponding to the neurons, the weight values between the neurons are divided into target weight groups, and for each target weight group, it is determined whether the weight values are all within the preset category. Within a smaller range of target weight value range, if so, the weight value will be stored with a storage precision lower than the current storage, thereby reducing the storage space occupied by the weight storage of the neuron, thereby reducing the storage of the neuromorphic chip. The ineffective occupation of space reduces the storage requirements of neuromorphic chips, which is conducive to the expanded application of neuromorphic chips.

In some embodiments, the target weight value may be stored based on the form of a data packet.

In some embodiments, the target weight set may be stored in the form of data packets.

In some embodiments, the format of the data packet is as follows:

Among them, cid represents the identification information of the target processing core; startaddr represents the address of the starting target neuron in the target processing core that is connected to a neuron in the current processing core; len represents the starting target of self-connection in the target processing core. The address of the neuron starts from the number of continuously connected target neurons; acc represents the target storage accuracy; weight represents the weight value of each target, and each target weight value corresponds to the target neuron determined based on the fields startaddr and len.

It should be noted that in some embodiments, when the addresses of the target neurons in the target processing core are discontinuous, the weight values of the neurons spaced between each target neuron can be set to zero, and the corresponding Stored in parameter weight.

In some embodiments, if a neuron in the current processing core is only connected to one target neuron in the target processing core, the format of the data packet may be:

Among them, cid represents the identification information of the target processing core; addr represents the address of the target neuron, acc represents the target storage accuracy; weight represents the target weight value.

In some embodiments, one neuron corresponds to at least one data packet, each data packet corresponds to a target processing core connected to the neuron, and each data packet can have its own storage precision.

In some embodiments, in order to further reduce the occupation of storage space (for example, to reduce the occupation of storage space of a neuromorphic chip), multiple data packets corresponding to one neuron in the current processing core can be stored according to the target accuracy. Classify storage instead of marking the storage accuracy in each data packet. That is, data packets with the same target storage accuracy are stored as one large data packet, as shown below. The format of the large data packet can be:

Among them, acc represents the target storage accuracy, and each set of addr and weight represents the data packet corresponding to a target processing core connected to a neuron in the current processing core as mentioned above. Among them, addr represents the address of the target neuron, and weight represents Target weight value.

For example, if all data packets corresponding to a neuron include 1000 32-bit floating point (fp32) data packets and 10 16-bit floating point (fp16) data packets, then 1000 32-bit floating point type (fp16) data packets can be The data packets are stored together, and the storage precision is uniformly marked as fp32. The 10 16-bit floating point data packets are stored together, and the storage precision is uniformly marked as fp16. This storage method can further reduce the storage space occupied by neuromorphic chips because it shares storage accuracy related fields.

It should be noted that in the embodiment of the present disclosure, if the target weight group is divided using the target neuron in the target processing core as an index, then the information related to the target processing core address in the above data packet can be expressed as the target neuron in the current processing core. Corresponding address related information. For example, cid represents the identification information of the current processing core, addr represents the address of the neuron in the current processing core, startaddr represents the address of the starting neuron in the current processing core that is connected to a neuron in the target processing core, and so on.

In the embodiment of the present disclosure, in addition to the above-mentioned storage of the target weight value in the form of data packets, the target weight value can also be stored in the form of an array, which is not limited in the embodiment of the present disclosure.

Figure 6 is a flow chart of an information processing method provided by an embodiment of the present disclosure, which can be applied to weight storage.

Referring to Figure 6, before step S201, the information processing method may also include:

Step S200: Determine the target weight value interval.

In the embodiment of the present disclosure, the target weight value range can be determined based on different methods.

In some embodiments, the target weight value range can be determined based on experience by those skilled in the art.

In some embodiments, the target weight value range may be determined by performing statistical calculations on all weight values included in the many-core system.

Regarding steps S201 to S204, please refer to the relevant content of the embodiments of the present disclosure, and the description will not be further elaborated here.

In some embodiments, determining the target weight value range may include: obtaining multiple weight values included in the many-core system (for example, the multiple weight values may be all weight values included in the many-core system, or may be is at least part of the weight values); perform normal distribution statistics on the multiple weight values obtained, and determine the normal distribution rules of multiple weight values; calculate the weights whose distribution probability in the normal distribution rule satisfies the preset probability value The range is determined as the target weight value range.

Figure 7 is a flow chart of an information processing method provided by an embodiment of the present disclosure, which is used to describe some steps in the weight storage process.

Referring to Figure 7, in the weight storage process of the embodiment of the present disclosure, step S200, the step of determining the target weight value interval, may include:

Step S2001: Obtain all weight values included in the many-core system.

Step S2002: Perform normal distribution statistics on all obtained weight values to determine the normal distribution rule of the weight values.

Step S2003: Determine the weight range in which the distribution probability in the normal distribution law satisfies the preset probability value as the target weight range.

In some embodiments, the distribution of all weight values in the many-core system satisfies the normal distribution law. Therefore, the normal distribution statistics of all weight values included in the many-core system can be used to determine the normal distribution of all weight values in the many-core system. According to the normal distribution law, the target weight value range is determined based on the obtained normal distribution law.

Illustratively, in step S2002, normal distribution statistics are performed on all weight values obtained in the many-core system to obtain a normal distribution rule of the weight values. The normal distribution rule includes the expected value and standard deviation of the normal distribution. ; In step S2003, based on the determined expected value and standard deviation, it is determined by querying the standard normal distribution table that the distribution probability of the weight value satisfies the weight range corresponding to the preset probability value, and the weight range is determined as the target weight value interval, Among them, the distribution probability of the weight value satisfies the weight range corresponding to the preset probability value, which means that each weight value will be located in the weight range with a probability of not less than the preset probability value.

For example, by counting all the weight values in the many-core system, it can be calculated and determined that the expected value in the normal distribution law that satisfies the normal distribution is μ = 12, the standard deviation is σ = 2, and the preset probability value is set to 90 %, by querying the standard normal distribution table, it is determined that when the distribution probability of the weight value satisfies 90%, the corresponding weight range is (μ-2σ, μ+2σ). From this, it can be determined that the target weight value range is (8 ,16).

Figure 8 is a schematic flowchart of an information processing method provided by an embodiment of the present disclosure, which can be applied to membrane potential storage.

Referring to Figure 8, an embodiment of the present disclosure provides an information processing method, and the corresponding membrane potential storage process may include:

Step S802: Obtain the current membrane potential of at least one neuron.

In some embodiments, obtaining the current membrane potential of at least one neuron may be obtaining the current membrane potential of one neuron, or obtaining the current membrane potential of multiple neurons, which is not limited in the embodiments of the present disclosure.

In some embodiments, the membrane potential storage process can be applied to a chip, which can calculate The core simulates at least one neuron. Correspondingly, obtaining the current membrane potential of at least one neuron may be to obtain the current membrane potential of each neuron in the at least one neuron for the above calculation core. Alternatively, the current membrane potential of at least one neuron may be obtained, or the current membrane potential of multiple neurons corresponding to multiple computing cores may be obtained. The embodiments of the present disclosure are not limited to this.

In some embodiments, the current membrane potential may refer to the voltage value generated by a neuron being stimulated by other neurons. The neurons may be neurons in an artificial neural network or a spiking neural network.

In some embodiments, the current membrane potential may refer to the current membrane potential of the neuron calculated based on stimulation signals emitted by other neurons connected to the neuron.

In some embodiments, the process of obtaining the current membrane potential may include: obtaining multiple stimulation signals received by the neuron at the current moment, and weighting the multiple stimulation signals according to the weight corresponding to each stimulation signal to obtain the input potential. Based on the input potential, the current membrane potential of the neuron is obtained by combining the leakage voltage of the neuron and the membrane potential at the previous moment.

For example, neuron A is connected to neurons B, C, and D through synapses 1, 2, and 3 respectively. When obtaining the membrane potential corresponding to neuron A, the stimulation signals currently sent by neurons B, C, and D to neuron A can be calculated based on the weights set for synapses 1, 2, and 3 (it can also be performed on the stimulation signals). The processed signals) are weighted and summed to obtain the input potential of neuron A. Then the input potential is summed with the membrane potential of neuron A at the previous moment, and the difference is calculated with the leakage potential of neuron A to obtain the membrane potential corresponding to neuron A.

Step S804: In response to the current membrane potential being different from the resting potential of the neuron, associate and store the current membrane potential and the neuron information of the neuron.

In some embodiments, the resting potential refers to the potential of a neuron when it is not stimulated by other neurons. If the membrane potential of a neuron is equal to the resting potential, it means that the neuron has not been stimulated, that is, it is in a non-working state; if the membrane potential of the neuron is not equal to the resting potential, it means that the neuron has been stimulated, that is, it is in a non-working state. working status.

In some embodiments, the chip may pre-allocate a storage space for storing neuron information of multiple neurons included in the chip (for example, for storing neuron information of all neurons included in the chip). Among them, the neuron information can include the resting potential of the neuron, release threshold information, etc.

In some embodiments, the process of obtaining the resting potential may include: obtaining neuron information corresponding to the neuron from the pre-allocated storage space, and obtaining the resting potential of the neuron therefrom.

In some embodiments, the neuron information includes at least one of the following: release threshold, leakage value, resting potential. The above examples of neuron information are only examples, and the embodiments of the present disclosure do not limit this.

In some embodiments, the neuron information can be pre-stored in the chip. Correspondingly, in step S804, associated storage can be achieved by co-storing the identifier indicating the neuron information and the obtained current membrane potential.

For example, the identifier can be a storage address indicating neuron information, and associative storage can be achieved by storing the storage address together with the obtained current membrane potential.

For example, the identifier could be a neuron type number. Neurons corresponding to this type number have the same neuron information. Associative storage can also be achieved by storing the neuron type number together with the obtained current membrane potential. Among them, neurons can be divided into corresponding neuron types based on the resting potential, firing threshold and other information of the neuron, and each neuron type can be identified using the neuron type number.

In some embodiments, the neurons simulated by the chip can be numbered in advance. Correspondingly, in step S804, the current membrane potential and the neuron information of the neuron can be sequentially stored in association based on the preset neuron number identifier.

For example, the chip can simulate 100 neurons numbered from 1 to 100, and can store the current membrane potential and the neuron information of each neuron in sequence in order from small to large.

Step S806, in response to the current membrane potential being the same as the resting potential, discard the current membrane potential.

In some embodiments, after obtaining the current membrane potential and the resting potential of the neuron, the two sizes can be compared. If the two are different, it can mean that the neuron is stimulated by other neurons and the neuron is in a working state. The membrane potential can be stored in association. If the two are the same, it means that the neuron is not stimulated by other neurons and the neuron is in a non-working state, and the membrane potential can be discarded.

For example, in a sparse network, most of the neurons are usually in a non-working state. These neurons are not stimulated by other neurons, and only a small number of neurons are in a working state. Through the information processing method of the embodiment of the present disclosure, After performing relevant processing, only the membrane potential of a small number of neurons (that is, the membrane potential of neurons in working state) will be recorded, and the membrane potential of most neurons will be discarded, thus saving a lot of storage space.

In summary, since the membrane potential of a neuron is equal to its resting potential, it can mean that the neuron is in a non-working state. The membrane potential is not equal to the resting potential, which can mean that the neuron is in a working state. Therefore, in the embodiment of the present disclosure, By responding to the current membrane potential being different from the resting potential of the neuron, the neuronal information of the current membrane potential and the neuron is stored in association, and in response to the current membrane potential being different from the resting potential of the neuron, If the current membrane potential is discarded, only the membrane potential of the neuron in the working state can be stored, and there is no need to store the membrane potential of the neuron in the non-working state, thus saving storage space.

In some embodiments, neurons of the same type have at least part of the same neuron information. The chip can only store one copy of the same neuron information for neurons of the same type, and there is no need to store the same neuron information for each neuron. Neuronal information (e.g., the same resting potential), thereby further saving storage space. It should be noted that the above-mentioned storage of only one copy of neuron information usually does not change depending on whether the neuron is subject to external stimulation. This ensures that any neuron that shares this copy of neuron information will not be affected by any external stimulus. Stimulation causes changes in the shared neuron information or the neuron is unable to use the shared neuron information. For example, this type of neuron information may include any one or more of resting potential, release threshold, leakage value, etc.

In some embodiments, neuron information of at least one neuron can be pre-stored in the chip according to neuron type.

Figure 9 is a schematic diagram of a method for obtaining resting potential according to an embodiment of the present disclosure. As shown in Figure 9, the process of obtaining the resting potential can include:

Step S902: Obtain the neuron type identifier of the neuron.

In some embodiments, a chip may include multiple types of neurons. The neuron type identifier may be a type identifier maintained in advance for each neuron of the chip.

In some embodiments, a storage space can be pre-allocated for each neuron type in the chip, and neuron information of the corresponding neuron type can be stored in the storage space.

Step S904: Obtain the resting potential included in the neuron information corresponding to the neuron type identifier.

In some embodiments, after obtaining the neuron type of the neuron based on step S902, the storage space corresponding to the neuron type can be found, and then the neuron information of the neuron of this type is read from the storage space, and from Resting potential is obtained from neuronal information.

For example, neuron types may include two types, A and B. The resting potential of neurons in type A is -70mv (millivolts) and the release threshold is 0.7V (volts). The resting potential of neurons in type B is -70mv and the release threshold is 0.9V. Storage spaces can be maintained separately for types A and B in the chip. Each storage space can store neuron information of the corresponding neuron type (which may include resting potential and release threshold). For any neuron, if it is determined to be a neuron of type B, the resting potential can be obtained from the storage space corresponding to type B, thereby clarifying that the resting potential of the neuron is -70mv.

As a result, only one copy of the same neuron information for the same type of neuron can be stored, and there is no need to store neuron information for each neuron, which can further save storage space.

In some embodiments, neuron information of at least one neuron may be pre-stored in the chip according to neuron type. Correspondingly, in step S804, in response to the current membrane potential being different from the resting potential of the neuron, the neuron type identifier corresponding to the current membrane potential and the neuron can be stored in association; in step S806, in response to the current membrane potential being different from the resting potential of the neuron, The resting potential is the same, the current membrane potential is discarded, and the neuron type identifier corresponding to the neuron is stored.

Thus, neuron information can be associated with the current membrane potential through the neuron type to achieve associative storage. In addition to only recording the membrane potential of the neuron in the working state, the neuron type identification of the neuron can also be associated with the membrane potential. The potential correlation is stored in the same storage space, which makes it easy to query other neuron information of the neuron when updating the membrane potential of the neuron. While improving storage efficiency and storage space utilization, it can also improve the neuron information query experience.

In some embodiments, different methods may be used to obtain the current membrane potential of the target neuron depending on whether the membrane potential of the target neuron is stored.

Figure 10 is a schematic flowchart of a method for obtaining current membrane potential according to an embodiment of the present disclosure. As shown in Figure 10, the process of obtaining the current membrane potential may include:

Step S1002, in response to storing the membrane potential of the target neuron, determine the stored membrane potential of the target neuron as the current membrane potential of the target neuron.

The target neuron can be any neuron among at least one neuron simulated by the chip. In some embodiments, each neuron included in the chip can be sequentially determined as a target neuron according to the neuron number.

In some embodiments, if the membrane potential of the target neuron is stored, it means that the target neuron is in a working state and may have received external stimulation. Therefore, the stored membrane potential of the target neuron can be used as the current membrane potential of the target neuron.

Step S1004, in response to the fact that the membrane potential of the target neuron is not stored, determine the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.

In some embodiments, if the membrane potential of the target neuron is not stored, it means that the target neuron is in a non-working state and may not be stimulated by the outside world. Therefore, the resting potential of the target neuron can be used as the current membrane potential of the target neuron. .

In some embodiments, neuron information of at least one neuron can be pre-stored in the chip according to neuron type. Correspondingly, in step S1004, the neuron type of the target neuron can be obtained, and then based on the neuron type, the neuron information of the target neuron can be queried, and the resting potential included in the neuron information of the target neuron can be used as The current membrane electricity of the target neuron Bit.

It can be seen from steps S1002 and S1004 that when only the membrane potential of neurons in the working state is recorded, the current membrane potential of the target neuron can still be accurately determined regardless of the working state of the target neuron.

In some embodiments, after determining the current membrane potential of the target neuron, the current membrane potential may also be compared with the release threshold of the target neuron. If the current membrane potential reaches the release threshold, the target neuron can be caused to send a pulse signal to the neuron to which it is connected.

In some embodiments, the neuron type identifier can be stored only once for the same type of neuron, thereby further reducing storage space.

For example, the neuron information of at least one neuron can be pre-stored in the chip according to the neuron type; the neuron type identifier of at least one neuron is stored in the chip. Correspondingly, in step S804, in response to the current membrane potential being different from the resting potential of the neuron, the number identification and the current membrane potential of the neuron can be stored, and the stored number identification and the current membrane potential can be compared with the neuron's neuron potential. Metatype identifier associated.

In some embodiments, the number identification may be a number ID assigned in advance to each neuron included in the chip.

In some embodiments, each numbered identifier may indicate a unique neuron.

In some embodiments, a mapping relationship between numbered identifiers and neuron types may be maintained. Through this mapping relationship and the number of the neuron, the neuron type of the neuron can be known. For example, the chip can maintain numbering identifiers 1-100 mapped to type A, and numbering identifiers 101-200 mapped to type B. If the neuron number is 50, it can be determined that the neuron type is A.

In some embodiments, the number identifier may also reflect the neuron type of the neuron. In other words, the neuron type of a neuron can be known by its number identification. For example, if the number of the neuron is B1, it can indicate that the neuron is a type B neuron and the number is 1. For example, if the number of the neuron is A10, it can indicate that the neuron is a type A neuron and the number is 10.

Correspondingly, in step S804, in response to the current membrane potential being different from the resting potential of the neuron, it may be determined whether the type identifier of the neuron is stored in the chip. If the chip stores the type identification of the neuron, the number identification of the neuron and the obtained current membrane potential can be stored in association with the type identification.

If the chip does not store the type identifier of the neuron, it can first store the type identifier of the neuron, and then store the neuron number identifier and the obtained current membrane potential in association with the type identifier.

For example, a section of storage space can be allocated for each type of neuron. Correspondingly, after obtaining the type of neuron in step S804, it can be determined whether there is a storage space allocated for this type in the chip. If so, associate the number identification of the neuron with the obtained current membrane potential and store it in the storage space corresponding to the type. If not, you can first allocate a storage space for this type of neuron, and then associate the number identification of the neuron with the obtained current membrane potential and store it in the storage space corresponding to this type. In this way, the current membrane potential of neurons of the same type can be stored in the storage space corresponding to the type, so that there is no need to store a neuron type identifier for each neuron, which can further save storage space.

In some embodiments, the method shown in Figure 11 can be used to obtain the current membrane potential of the target neuron.

Figure 11 is a schematic flowchart of a method for obtaining current membrane potential according to an embodiment of the present disclosure. As shown in Figure 11, the process of obtaining the current membrane potential may include:

S1102. In response to storing the number identification of the target neuron, determine the membrane potential stored in association with the number of the target neuron as the current membrane potential of the target neuron.

In some embodiments, the target neuron may be any neuron in at least one neuron simulated by the chip.

In some embodiments, each neuron included in the chip can be determined as a target neuron in sequence according to the neuron number.

In some embodiments, if the number identification of the target neuron is stored, it means that the target neuron is in a working state and may have received external stimulation. Therefore, the membrane potential stored in association with the number of the target neuron can be used as the current membrane potential.

S1104. In response to the number identification of the target neuron not being stored, determine the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.

In some embodiments, if the number identification of the target neuron is not stored, it means that the target neuron is in a non-working state, that is, it does not receive external stimulation or the stimulation is small. Therefore, the resting potential of the target neuron can be used as the current membrane potential.

In some embodiments, neuron information of at least one neuron can be pre-stored in the chip according to neuron type. Correspondingly, in step S1104, the neuron type of the target neuron can be obtained, and then based on the neuron type, the neuron information of the target neuron can be queried, and the resting potential included in the neuron information of the target neuron can be used as the target. The current membrane potential of the neuron.

It can be seen that the current membrane potential of the target neuron can be accurately determined while only storing the type identifier once for the same type of neuron.

In some embodiments, after determining the current membrane potential of the target neuron, the current membrane potential can also be compared with the current membrane potential of the target neuron. Release threshold is compared. If the current membrane potential reaches the release threshold, the target neuron can be caused to send a pulse signal to the neuron to which it is connected.

In some embodiments, in order to facilitate the management of the membrane potential of neurons (for example, management may include updating and reading), the storage space may be divided according to the neural network layer of the neuron, and the neuron information of the neuron may be stored in In the storage space corresponding to the network layer to which the neuron belongs. This facilitates management of the membrane potential of neurons layer by layer.

The following is an exemplary description based on the scenario of managing neuron information in a brain chip.

In some embodiments, a brain-based chip may include one or more computing cores. Each computing core can simulate one or more neurons, or multiple computing cores can simulate one neuron. This is not limited in the embodiments of the present disclosure. The neuron may be a neuron in a spiking neural network. Each neuron can be numbered and the neuron type determined in advance, and the mapping relationship between neuron numbers and neuron types can be stored in the chip. Each neuron type can correspond to some static neuron information (i.e., information that does not change whether the neuron is stimulated or not, which can include resting potential). The chip can store static neuron information by neuron type. The chip can also allocate storage space for storing current membrane potentials by neuron type.

In some embodiments, step S802 may be performed first. That is, in step S802, the current membrane potential of the neuron can be determined based on the neuron's stimulation information, and its neuron type can be determined based on the neuron number and the aforementioned mapping relationship, and its resting potential can be obtained.

In step S804, if the membrane potential is different from the resting potential, it means that the neuron is stimulated. It can be determined whether the chip allocates storage space for this type of neuron. If so, the number of the neuron and the membrane potential are associated and stored in allocated storage space. If not, you can first allocate storage space for this type of neuron, and then associate the number of the neuron with the membrane potential and store it in the allocated storage space.

In step S806, if the membrane potential is the same as the resting potential, it means that the neuron is in a non-working state, and the membrane potential can be discarded without storage.

Through the aforementioned steps, in the brain-type chip, on the one hand, a storage space can be allocated for the same type of neurons, that is, the neurons in the same storage space have the same neuron type, so there is no need to record the neuron model for each neuron. information, which can further save storage space. On the other hand, the same storage space only records the number identification and membrane potential of the neurons in the working state. There is no need to record the relevant information of the neurons in the non-working state, so there is no need to allocate storage space for the neurons in the non-working state. , which can further save storage space. On the other hand, allocating neuron information of the same type of neurons in the same storage space makes it easier to query the membrane potential of neurons.

When querying the current membrane potential of a brain chip neuron, the target neuron can be determined sequentially according to the neuron number from small to large, and S1102 and S1104 can be executed, so that the current membrane potential of the target neuron can be accurately determined.

In a second aspect, embodiments of the present disclosure provide an information processing unit.

Figure 12 is a block diagram of an information processing unit provided by an embodiment of the present disclosure. Referring to Figure 12, the information processing unit 1200 includes:

The processing subunit 1201 is configured to perform processing operations on the information to be processed based on the difference information between the information to be processed and the target information of the neuron;

In some embodiments, the information processing device of the embodiment of the present disclosure may be applied to the storage of weight values.

In some embodiments, the processing subunit may include a weight storage device, and the weight storage device may include:

a dividing module configured to divide multiple weight values between neurons of the current processing core and neurons of the target processing core into multiple target weight groups, where the target weight group includes multiple target weight values;

The judgment module is configured to judge whether multiple target weight values in the target weight group are within the target weight value range for each target weight group;

The storage module is configured to store the multiple target weight values according to the target storage accuracy when the multiple target weight values of the target weight group are within the target weight value range, and the target storage accuracy is lower than the current storage of the target weight value. Accuracy.

Figure 13 is a block diagram of a weight storage device provided by an embodiment of the present disclosure, which can be applied to the storage of weight values.

Referring to Figure 13, the weight storage device 1300 may include:

The dividing module 1310 is configured to divide all connection weights between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups, where the target weight group includes multiple target weight values;

The judgment module 1320 is configured to, for each target weight group, judge whether each target weight value in the target weight group is within the target weight value range;

The storage module 1330 is configured to store each target weight value according to the target storage accuracy when the judgment module 1320 determines that each target weight value is within the target weight value interval, and the target storage accuracy is lower than the current target weight value. Storage accuracy.

Figure 14 is a block diagram of a weight storage device provided by an embodiment of the present disclosure, which can be applied to the storage of weight values.

Referring to FIG. 14 , the weight storage device 1400 may include: a determination module 1440 , a dividing module 1410 , a judgment module 1420 and a storage module 1430 .

The determination module 1440 is configured to determine the preset weight value interval before the dividing module 1410 divides all weight values between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups. For the division module 1410, the judgment module 1420 and the storage module 1430, please refer to the relevant content of the embodiments of the present disclosure, and the description will not be further elaborated here.

In the embodiments of the present disclosure, the target weight value interval can be determined based on different methods. In some embodiments, the target weight value interval is determined by those skilled in the art based on experience; in some embodiments, the target weight value interval can be determined by analyzing the many-core system. All included weight values are statistically calculated to determine the target weight range.

In some embodiments, referring to FIG. 14 , the determination module 1440 may include: an acquisition sub-module 1441 , a statistics sub-module 1442 and a determination sub-module 1443 .

Among them, the acquisition sub-module 1441 is configured to acquire all weight values contained in the many-core system; the statistics sub-module 1442 is configured to perform normal distribution statistics on all acquired weight values to determine the normality of multiple weight values. Distribution rule; the determination sub-module 1443 is configured to determine the weight range in which the distribution probability satisfies the preset probability value in the normal distribution rule as the target weight value range.

In the embodiment of the present disclosure, the weight storage device can be used to implement weight storage. For the functional modules of the weight storage device and the interaction process between the functional modules, please refer to the relevant information about weight storage in the information processing method of the embodiment of the present disclosure. The content will not be repeated here.

It can be seen from this that the weight storage device provided by the embodiment of the present disclosure, when storing the weight values corresponding to the neurons, divides the weight values between neurons into target weight groups, and determines for each target weight group whether it contains Whether the weight values are all within the preset target weight value range belonging to a smaller range, if so, the weight values contained in the target weight group are stored with a target storage precision lower than the current storage precision, thereby reducing the neural network The memory space occupied by the weight storage of the element is reduced, thereby reducing the ineffective occupation of the storage space of the neuromorphic chip and reducing the storage requirements of the neuromorphic chip, thereby conducive to the expanded application of neuromorphic chips.

In some embodiments, the information processing device of the embodiment of the present disclosure may be applied to the storage of membrane potential.

In some embodiments, the information processing unit can be applied to a chip, wherein the chip simulates at least one neuron through at least one computing core it includes, and accordingly, the information processing unit includes a neuron information processing device;

In some embodiments, the neuron information processing device may include:

an acquisition module configured to acquire the current membrane potential of at least one neuron;

a storage module configured to, in response to the current membrane potential being different from the resting potential of the neuron, associate and store the current membrane potential with the neuron information of the neuron; and, in response to the current membrane potential being the same as the resting potential, discard the current membrane potential .

Figure 15 is a block diagram of a neuron information processing device provided by an embodiment of the present disclosure, which can be applied to the storage of membrane potential.

Referring to Figure 15, the neuron information processing device 1500 may include:

The acquisition module 1510 is configured to acquire the current membrane potential of at least one neuron;

The storage module 1520 is configured to, in response to the current membrane potential being different from the resting potential of the neuron, associate and store the current membrane potential with the neuron information of the neuron; and, in response to the current membrane potential being the same as the resting potential, discard the current membrane potential. Potential.

It can be seen from this that the neuron information processing device provided by the embodiment of the present disclosure determines the working state of the neuron by comparing the current membrane potential and the resting potential of the neuron when storing the membrane potential of the neuron, thereby based on the working state of the neuron. The state determines whether to store the current membrane potential. Based on this, the storage pressure caused by storing the membrane potential of neurons in a non-working state can be reduced and the occupation of storage resources can be reduced. In other words, when the membrane potential of a neuron is equal to its resting potential, it can be said that the neuron is in a non-working state. When the membrane potential is not equal to its resting potential, it can be said that the neuron is in a working state. Therefore, by In response to the current membrane potential being different from the resting potential of the neuron, the current membrane potential and the neuron information of the neuron can be stored in association to ensure that the membrane potential information of the working neuron is stored, and in response to the current membrane potential being different from the resting potential, The current membrane potential is the same, and the current membrane potential is discarded to reduce the amount of information storage of neurons in the non-working state, so that only the membrane potential of the neurons in the working state can be stored, without the need to store the membrane potential of the neurons in the non-working state. , thus effectively saving storage space.

It should be noted that in some embodiments of the present disclosure, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to perform the method described in the above method embodiments, and its optional implementation methods and technical effects Reference may be made to the description of the method embodiments above. For the sake of brevity, details will not be described again here.

In a third aspect, embodiments of the disclosure provide a chip that can be used to perform information processing in any of the embodiments of the disclosure. management method.

FIG. 16 is a block diagram of a chip provided by an embodiment of the present disclosure, which can be applied to perform any information processing method according to the embodiment of the present disclosure.

Referring to Figure 16, the chip 1600 may include at least one computing core, and the computing core may simulate at least one neuron, where:

The computing core 1601 is configured to perform processing operations on the information to be processed based on the difference information between the information to be processed and the target information of the neuron;

In some embodiments, the computing core (which can also be regarded as a processing core) in the chip can be configured to divide multiple weight values between the neurons of the current processing core and the neurons of the target processing core into multiple targets. Weight group, the target weight group includes multiple target weight values; for each target weight group, determine whether the multiple target weight values in the target weight group are within the target weight value range; the multiple target weight values in the target weight group are within the target weight value In the case of within the numerical range, multiple target weight values are stored according to the target storage precision, and the target storage precision is lower than the current storage precision of the target weight value.

In some embodiments, the computing core in the chip may be configured to obtain the current membrane potential of at least one neuron; in response to the current membrane potential being different from the resting potential of the neuron, associate and store the current membrane potential with the neuron's neuron. Metainformation; in response to the current membrane potential being the same as the resting potential, discard the current membrane potential.

In a fourth aspect, embodiments of the present disclosure provide an electronic device.

Referring to Figure 17, an embodiment of the present disclosure provides an electronic device. The electronic device includes multiple processing cores 1701 and an on-chip network 1702. The multiple processing cores 1701 are connected to the on-chip network 1702, and the on-chip network 1702 is configured to interact Data between multiple processing cores and external data.

One or more instructions are stored in one or more processing cores 1701, and the one or more instructions are executed by one or more processing cores 1701, so that the one or more processing cores 1701 can execute the above information processing method.

In some embodiments, the electronic device may be a brain-like chip, because the brain-like chip can adopt a vectorized calculation method and needs to be loaded into the neural network through an external memory such as a double data rate (Double Data Rate, DDR) synchronous dynamic random access memory. Model weight information and other parameters. Therefore, the operation efficiency of batch processing in the embodiments of the present disclosure is relatively high.

Referring to Figure 18, an embodiment of the present disclosure provides an electronic device, which includes: at least one processor 1801; at least one memory 1802, and one or more I/O interfaces 1803, connected between the processor 1801 and the memory 1802 among them, the memory 1802 stores one or more computer programs that can be executed by at least one processor 1801, and the one or more computer programs are executed by at least one processor 1801, so that at least one processor 1801 can execute the above-mentioned Information processing methods.

Embodiments of the present disclosure also provide a computer-readable storage medium with a computer program stored thereon.

Figure 19 is a block diagram of a computer-readable medium provided by an embodiment of the present disclosure. Wherein, the computer program implements the above data processing method when executed by the processor/processing core. Computer-readable storage media may be volatile or non-volatile computer-readable storage media.

Embodiments of the present disclosure also provide a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code is stored in a processor of an electronic device When running, the processor in the electronic device executes the above information processing method.

Those of ordinary skill in the art can understand that all or some steps, systems, and functional modules/units in the devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may consist of several physical components. Components execute cooperatively. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit . Such software may be distributed on computer-readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).

As is known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. lossless, removable and non-removable media. Computer storage media includes, but is not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, Portable Compact Disk Read Only Memory (CD-ROM), Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or can be used to store desired information and can be accessed by a computer any other media. Additionally, it is known to those of ordinary skill in the art that communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery medium.

Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to various computing/processing devices, or to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium in the respective computing/processing device .

Computer program instructions for performing operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or instructions in one or more programming languages. Source code or object code written in any combination of programming languages including object-oriented programming languages - such as Smalltalk, C++, etc., and conventional procedural programming languages - such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server implement. In situations involving remote computers, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as an Internet service provider through the Internet). connect). In some embodiments, by utilizing state information of computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can Computer readable program instructions are executed to implement various aspects of the disclosure.

The computer program products described herein may be implemented in hardware, software, or a combination thereof. In an optional embodiment, the computer program product can be embodied as a computer storage medium. In an optional embodiment, the computer program product can be embodied as a software product, such as a software development kit (Software Development Kit, SDK) and so on.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, thereby producing a machine that, when executed by the processor of the computer or other programmable data processing apparatus, , resulting in an apparatus that implements the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium. These instructions cause the computer, programmable data processing device and/or other equipment to work in a specific manner. Therefore, the computer-readable medium storing the instructions includes An article of manufacture that includes instructions that implement aspects of the functions/acts specified in one or more blocks of the flowcharts and/or block diagrams.

Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other equipment, causing a series of operating steps to be performed on the computer, other programmable data processing apparatus, or other equipment to produce a computer-implemented process , thereby causing instructions executed on a computer, other programmable data processing apparatus, or other equipment to implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions that contains one or more operable elements for implementing the specified logical function(s). Execute instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two consecutive blocks may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts. , or can be implemented using a combination of specialized hardware and computer instructions.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a general illustrative sense only and not for purpose of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be used in conjunction with other embodiments, unless expressly stated otherwise. Features and/or components used in combination. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

An information processing method, including:

Based on the difference information between the information to be processed and the target information of the neuron, perform the processing operation of the information to be processed;

Wherein, the information to be processed includes the weight value of the neuron, the target information corresponding to the weight value includes the weight value interval, and the processing operation includes storage processing of adjusting the storage accuracy of the weight value or storage without adjusting the storage accuracy. processing, and/or,

The information to be processed includes the membrane potential of the neuron, the target information corresponding to the membrane potential includes the resting potential, and the processing operation includes storage processing or discarding processing of the membrane potential.
The information processing method according to claim 1, wherein the information to be processed includes a plurality of target weight values of at least one target weight group, the target information includes a target weight value interval, and the difference information is used to characterize the The range relationship between the multiple target weight values of the target weight group and the target weight value interval, the processing operation includes performing storage processing of adjusting the storage accuracy of the multiple target weight values in units of the target weight group, or, in The target weight group performs storage processing of multiple target weight values without adjusting the storage accuracy in units.
The information processing method according to claim 2, applied to weight storage, wherein the information processing method includes:

Divide multiple weight values between neurons of the current processing core and neurons of the target processing core into multiple target weight groups, where the target weight groups include multiple target weight values;

For each target weight group, determine whether multiple target weight values in the target weight group are within the target weight value range;

When multiple target weight values of the target weight group are located within the target weight numerical interval, multiple target weight values are stored according to the target storage accuracy, and the target storage accuracy is lower than the target weight. The current storage precision of the value.
The information processing method according to claim 3, wherein storing the plurality of target weight values according to target storage accuracy includes:

A plurality of the target weight values are stored in the form of a data packet, and the data packet includes the target weight value and the target storage accuracy.
The information processing method according to claim 3, wherein when at least one of the plurality of target weight values in the target weight group is located outside the target weight value interval, the method is maintained. The current storage accuracy of multiple target weight values in the target weight group remains unchanged.
The information processing method according to claim 3, wherein the current storage precision is a floating-point storage precision or an integer storage precision, and the type of the target storage precision is the same as the type of the current storage precision.
The information processing method according to claim 3, wherein before the step of dividing the plurality of weight values between the neurons of the current processing core and the neurons of the target processing core into a plurality of target weight groups, the Information processing methods also include:

Determine the target weight range.
The information processing method according to claim 7, wherein determining the target weight value interval includes:

Obtain multiple weight values contained in the many-core system;

Perform normal distribution statistics on the multiple obtained weight values, and determine the normal distribution rules of the multiple weight values;

The weight range in which the distribution probability in the normal distribution law satisfies the preset probability value is determined as the target weight value range.
The information processing method according to claim 3, wherein dividing the multiple weight values between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups includes:

Obtain weight values between multiple neurons of the current processing core and multiple neurons of the target processing core;

The weight value corresponding to at least one neuron in the current processing core is used as one of the target weight groups.
The information processing method according to claim 3, wherein dividing the multiple weight values between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups includes:

Obtain weight values between multiple neurons in the current processing core and at least one neuron in the target processing core;

The weight values between multiple neurons in the current processing core and at least one neuron in the target processing core are used as one of the target weight groups.
The information processing method according to claim 3, wherein the intersection between any two target weight groups among the plurality of target weight groups is an empty set.
The information processing method according to claim 1, wherein the information to be processed includes the current membrane potential of the neuron, the target information includes the resting potential of the neuron, and the difference information is used to characterize the neuron. Whether the current membrane potential of the neuron is the same as the resting potential of the neuron, the processing operation includes a storage operation on the current membrane potential, or a discarding operation on the current membrane potential.
The information processing method according to claim 12, applied to a chip, wherein the chip includes at least one Each computing core simulates at least one neuron; the information processing method includes:

obtaining the current membrane potential of at least one of said neurons;

In response to the current membrane potential being different from the resting potential of the neuron, storing the neuron information of the current membrane potential and the neuron in association;

In response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded.
The information processing method according to claim 13, wherein the neuron information includes at least one of the following: release threshold, leakage value, resting potential.
The information processing method according to claim 13, wherein the neuron information of the at least one neuron is pre-stored in the chip according to neuron type;

In response to the current membrane potential being different from the resting potential of the neuron, storing the neuron information of the current membrane potential and the neuron in association includes:

In response to the current membrane potential being different from the resting potential of the neuron, storing the neuron type identifier corresponding to the current membrane potential and the neuron in association;

The step of discarding the current membrane potential in response to the current membrane potential being the same as the resting potential includes:

In response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded and the neuron type identifier corresponding to the neuron is stored.
The information processing method according to claim 13, wherein the information processing method further includes:

responsive to storing the membrane potential of the target neuron, determining the stored membrane potential of the target neuron as the current membrane potential of the target neuron;

In response to the membrane potential of the target neuron not being stored, the resting potential corresponding to the target neuron is determined as the current membrane potential of the target neuron.
The information processing method according to claim 13, wherein the neuron information of the at least one neuron is pre-stored in the chip according to the neuron type; the neuron of the at least one neuron is stored in the chip. type identifier;

In response to the current membrane potential being different from the resting potential of the neuron, storing the neuron information of the current membrane potential and the neuron in association includes:

In response to the current membrane potential being different from the resting potential of the neuron, storing the number identification of the neuron and the current membrane potential, and comparing the stored number identification and the current membrane potential with the associated with the neuron type identifier of the neuron in question.
The information processing method according to claim 17, wherein the information processing method further includes:

In response to storing the number identification of the target neuron, determining the membrane potential stored in association with the number identification of the target neuron as the current membrane potential of the target neuron;

In response to the number identification of the target neuron not being stored, the resting potential corresponding to the target neuron is determined as the current membrane potential of the target neuron.
The information processing method according to any one of claims 13-18, wherein the associated storage of the current membrane potential and the neuron information of the neuron includes:

Based on the preset neuron number identification, the current membrane potential and the neuron information of the neuron are sequentially stored in association.
The information processing method according to claim 13, wherein the chip includes a many-core chip; the neurons include neurons in a spiking neural network.
An information processing unit, which includes:

A processing subunit configured to perform a processing operation on the information to be processed based on the difference information between the information to be processed and the target information of the neuron;

Wherein, the information to be processed includes the weight value of the neuron, the target information corresponding to the weight value includes the weight value interval, and the processing operation includes storage processing of adjusting the storage accuracy of the weight value or storage without adjusting the storage accuracy. processing, and/or, the information to be processed includes the membrane potential of the neuron, the target information corresponding to the membrane potential includes the resting potential, and the processing operation includes storage processing or discarding processing of the membrane potential.
The information processing unit according to claim 21, wherein the processing subunit includes a weight storage device, and the weight storage device includes:

a dividing module configured to divide multiple weight values between neurons of the current processing core and neurons of the target processing core into multiple target weight groups, where the target weight group includes multiple target weight values;

A judgment module configured to, for each target weight group, judge whether a plurality of the target weight values in the target weight group are located within the target weight value range;

A storage module configured to operate when multiple target weight values of the target weight group are located within the target weight value interval. , multiple target weight values are stored according to a target storage accuracy, and the target storage accuracy is lower than the current storage accuracy of the target weight value.
The information processing unit according to claim 22, wherein the weight storage device further includes:

The determining module is configured to determine the preset weight value interval before the dividing module divides the multiple weight values between the neurons of the current processing core and the neurons of the target processing core into multiple target weight groups.
The information processing unit according to claim 23, wherein the determining module includes:

The acquisition sub-module is configured to obtain multiple weight values contained in the many-core system;

The statistics submodule is configured to perform normal distribution statistics on the multiple weight values obtained, and determine the normal distribution law of the multiple weight values;

The determination sub-module is configured to determine the weight range in which the distribution probability in the normal distribution law satisfies the preset probability value as the target weight value range.
The information processing unit according to claim 21, applied to a chip, wherein the chip simulates at least one neuron through at least one computing core it includes, the information processing unit includes a neuron information processing device; the neuron Information processing devices include:

an acquisition module configured to acquire the current membrane potential of at least one of the neurons;

a storage module configured to associate and store the current membrane potential with the neuron information of the neuron in response to the current membrane potential being different from the resting potential of the neuron; and, in response to the current membrane potential Identical to the resting potential, the current membrane potential is discarded.
A chip, wherein the chip simulates at least one neuron through at least one computing core it includes; wherein,

The computing core is configured to perform a processing operation on the information to be processed based on the difference information between the information to be processed and the target information of the neuron;

Wherein, the information to be processed includes the weight value of the neuron, the target information corresponding to the weight value includes the weight value interval, and the processing operation includes storage processing of adjusting the storage accuracy of the weight value or storage without adjusting the storage accuracy. processing, and/or,

The information to be processed includes the membrane potential of the neuron, the target information corresponding to the membrane potential includes the resting potential, and the processing operation includes storage processing or discarding processing of the membrane potential.
The chip according to claim 26, wherein the computing core is configured to obtain the current membrane potential of at least one of the neurons; in response to the current membrane potential being different from the resting potential of the neuron, associate The current membrane potential and neuronal information of the neuron are stored; in response to the current membrane potential being the same as the resting potential, the current membrane potential is discarded.
An electronic device, including a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that when the processor executes the computer program, any one of claims 1 to 20 is implemented The information processing method described.
A computer-readable storage medium with a computer program stored thereon, characterized in that when the computer program is executed by a processor, the information processing method as claimed in any one of claims 1 to 20 is implemented.
A computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, wherein when the computer readable code is executed in a processor of an electronic device, the The processor in the electronic device executes the information processing method according to any one of claims 1 to 20.