CN114742213A - Neuron information processing method, device, chip and storage medium - Google Patents
Neuron information processing method, device, chip and storage medium Download PDFInfo
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Abstract
The application provides a neuron information processing method, a neuron information processing device, a chip and a storage medium. The method is applied to a chip. The chip simulates at least one neuron by at least one computational core comprised by the chip. The method may include: obtaining a current membrane potential for each of the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, associatively storing neuron information of the current membrane potential and the neuron; in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a chip, and a storage medium for processing neuron information.
Background
Some chips (e.g., neuromorphic chips) may be used to construct neural networks. A plurality of neurons may be included in the neural network. The computational core in the chip can be used for simulating the neurons in the neural network. At least some of the neurons may be in synaptic communication with each other.
In this type of chip, it is necessary to store neuron information of neurons, and the neurons can perform processing actions according to the neuron information. At present, the commonly adopted mode is to store the neuron information of each neuron, so that each neuron can conveniently perform corresponding processing according to the neuron information. But this may take up too much memory space of the chip.
Disclosure of Invention
In view of this, the present application discloses a method for processing neuron information. The method is applied to a chip. The chip simulates at least one neuron by at least one computational core comprised by the chip. The method may include: obtaining a current membrane potential of each of the at least one neuron; in response to the current membrane potential differing from a resting potential of the neuron, associatively storing neuron information for the current membrane potential and the neuron; discarding the current membrane potential in response to the current membrane potential being the same as the resting potential.
In some embodiments, the neuron information comprises at least one of: release threshold, leakage value, resting potential.
In some embodiments, neuron information of the at least one neuron is pre-stored within the chip by neuron type; said associating storing neuron information for the current membrane potential and the neuron in response to the current membrane potential being different from a resting potential of the neuron, comprising: in response to the current membrane potential being different from a resting potential of the neuron, associatively storing a neuron type identifier corresponding to the current membrane potential and the neuron; in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential, the method comprising: in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential and storing a neuron type identifier corresponding to the neuron.
In some embodiments, the method further comprises: in response to storing a membrane potential of a target neuron, determining the stored membrane potential of the target neuron as a current membrane potential of the target neuron; in response to not storing a membrane potential of a target neuron, determining a resting potential corresponding to the target neuron as a current membrane potential of the target neuron.
In some embodiments, neuron information of the at least one neuron is pre-stored within the chip by neuron type; the chip stores a neuron type identifier of the at least one neuron; said associating storing neuron information for the current membrane potential and the neuron in response to the current membrane potential being different from a resting potential of the neuron, comprising: in response to the current membrane potential being different from a resting potential of the neuron, storing a numbered identification of the neuron and the current membrane potential, and associating the stored numbered identification and the current membrane potential with a neuron type identification of the neuron.
In some embodiments, the method further comprises: in response to storing a number identification of a target neuron, determining a stored membrane potential associated with a number of the target neuron as a current membrane potential of the target neuron; in response to not storing the number identification of the target neuron, determining a resting potential corresponding to the target neuron as a current membrane potential of the target neuron.
In some embodiments, the associating stores the current membrane potential with neuron information for the neuron, including: and sequentially associating and storing the current membrane potential and the neuron information of the neuron based on preset neuron number identification.
In some embodiments, the chip comprises a many-core chip; the neurons comprise neurons in a spiking neural network.
The application also provides a neuron information processing device. The device is applied to a chip. The chip simulates at least one neuron through at least one computational core included by the chip; the device comprises: an obtaining module, configured to obtain a current membrane potential of each of the at least one neuron; a storage module, configured to, in response to the current membrane potential being different from a resting potential of the neuron, store neuron information of the neuron in association with the current membrane potential; discarding the current membrane potential in response to the current membrane potential being the same as the resting potential.
The present application also proposes a chip that simulates, by means of at least one computational core it comprises, at least one neuron; wherein, the computation core is used for obtaining the current membrane potential of each neuron in the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, associatively storing neuron information of the current membrane potential and the neuron; in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.
The present application also proposes a storage medium storing a program for causing a chip computation core to execute the neuron information processing method as shown in any one of the foregoing embodiments.
In the solution described in any of the foregoing embodiments, by associating and storing the neuron information of the current membrane potential and the neuron in response to that the current membrane potential is different from the resting potential of the neuron, and discarding the current membrane potential in response to that the current membrane potential is the same as the resting potential, only the membrane potential of the neuron in an operating state can be stored, and the membrane potential of the neuron in a non-operating state does not need to be stored, thereby saving the storage space of a chip.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
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In order to more clearly illustrate one or more embodiments of the present application or technical solutions in the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in one or more embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive exercise.
Fig. 1 is a flowchart illustrating a method of processing neuron information according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a method for obtaining a rest potential according to an embodiment of the present disclosure;
FIG. 3 is a schematic flow chart of a method for obtaining a current membrane potential according to an embodiment of the present disclosure;
FIG. 4 is a schematic flow chart illustrating a method for obtaining a current membrane potential according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a neuron information processing device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It should also be understood that the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination," depending on the context.
The application provides a neuron information processing method. The method can only store the membrane potential of the neuron under the working state, and does not need to store the membrane potential of the neuron under the non-working state, thereby saving the storage space. The method can be applied to a chip. The chip may simulate at least one neuron by at least one computational core it comprises.
In some embodiments, the chip may be an AI chip. The AI chip may be a neuromorphic chip (brain-like chip). Such chips may be many-core chips. Each compute core in a many-core chip may emulate one or more neurons.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for processing neuron information according to an embodiment of the present disclosure. As shown in fig. 1, the method may include S102-S106.
And S102, acquiring the current membrane potential of each neuron in the at least one neuron.
The current membrane potential refers to a voltage value generated by the stimulation of the neuron by other neurons. Wherein the neuron can be a neuron in an artificial neural network or a spiking neural network.
In some embodiments, the current membrane potential is calculated from stimulation signals emitted by other neurons connected to the neuron.
In some embodiments, obtaining the current membrane potential may comprise: obtaining multiple paths of stimulation signals received by the neuron at the current moment, then carrying out weighting processing on the multiple paths of stimulation signals according to the weight corresponding to each path of stimulation signal to obtain an input potential, and then obtaining the membrane potential together with the leakage voltage of the neuron and the membrane potential at the previous moment.
For example, neuron a is connected to neuron B, C, D through synapses 1, 2, 3. When the membrane potential corresponding to the neuron a is obtained, the stimulation signals currently sent by the neuron B, C, D (or the signals after the stimulation signals are processed) may be weighted and summed according to the weights set for the synapses 1, 2, and 3, so as to obtain the input potential. And then summing the input voltage with the membrane potential of the neuron A at the previous moment, and then differencing with the leakage potential of the neuron A to obtain the membrane potential corresponding to the neuron A.
S104, responding to the difference between the current membrane potential and the resting potential of the neuron, and associating and storing the neuron information of the current membrane potential and the neuron.
The resting potential refers to the potential of the neuron when not stimulated by other neurons. If the membrane potential of the neuron is equal to the rest potential, the neuron is not stimulated, namely is in a non-working state; if the membrane potential of a neuron is not equal to the resting potential, it can be said that the neuron is stimulated, i.e., in an operational state.
In some embodiments, the chip may pre-allocate a block of memory space for storing neuron information for each neuron included in the chip. The neuron information may include resting potential of neurons, release threshold information, and the like.
Acquiring the resting potential may include acquiring neuron information corresponding to the neuron from the pre-allocated storage space, and acquiring the resting potential of the neuron therefrom.
The neuron information comprises at least one of: release threshold, leakage value, resting potential.
In some embodiments, the neuron information may be pre-stored in the chip, and the associative storage may be implemented by storing an identifier indicating the neuron information together with the acquired current membrane potential in S104.
For example, the identification may be a memory address indicating the neuron information, and storing the memory address together with the acquired current membrane potential may implement the associative storage. As another example, the identification may be a neuron type number. The neurons corresponding to the type number have the same neuron information. Storing this neuron type number together with the acquired current membrane potential may also enable the associative storage.
In some embodiments, the neurons simulated on the chip may be numbered in advance. In S104, the current membrane potential and the neuron information of the neuron may be sequentially stored in association based on a preset neuron number identification.
For example, a chip may simulate 100 neurons numbered 1 to 100. The current membrane potential and neuron information can be stored sequentially for each neuron association in a mode of numbering from small to large.
S106, in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.
In some embodiments, after obtaining the current membrane potential and the resting potential of the neuron, the magnitudes of the two potentials may be compared, if the two potentials are different, the neuron may be stimulated by other neurons and in an operating state, the membrane potential may be stored in an associated manner, and if the two potentials are the same, the neuron may be not stimulated by other neurons and in a non-operating state, the membrane potential may be discarded.
For example, in a sparse network, most of the neurons will not work, i.e., will not be stimulated by other neurons, only a few of the neurons will work, and only the membrane potentials of a few of the neurons will be recorded through the steps of S102-S106, so that a lot of storage space can be saved.
Through the technical solutions recorded in S102-S106, since the membrane potential of a neuron is equal to its resting potential, it can be said that the neuron is in a non-operating state, and the membrane potential is not equal to the resting potential, it can be said that the neuron is in an operating state, therefore, in the method, in response to that the current membrane potential is different from the resting potential of the neuron, the neuron information of the current membrane potential and the neuron is stored in association, and in response to that the current membrane potential is the same as the resting potential, the current membrane potential is discarded, so that only the membrane potential of the neuron in the operating state can be stored, and the membrane potential of the neuron in the non-operating state does not need to be stored, thereby saving storage space.
In some embodiments, the same neuron information of the same type is at least partially the same, and the same neuron information of the chip for the same type of neuron can be stored only in one copy without storing the same neuron information (e.g., the same resting potential) for each neuron, thereby further saving storage space. It is understood that the neuron information of this example is not changed by whether the neuron receives an external stimulus. For example, the neuron-like information may include resting potential, release threshold, leakage value, and the like.
In some embodiments, neuron information of the at least one neuron may be pre-stored within the chip by neuron type.
Please refer to fig. 2, fig. 2 is a schematic diagram illustrating a method for obtaining a resting potential according to an embodiment of the present application. Fig. 2 is a detailed illustration of the method of obtaining resting potential. As shown in fig. 2, the method may include S202-S204.
And S202, acquiring a neuron type identifier of the neuron.
The chip shown may include various types of neurons. The neuron type identifier may be a type identifier maintained in advance for each neuron of the chip. In some embodiments, a section of storage space may be allocated in advance for each neuron type in the chip, and the neuron information corresponding to each neuron type may be stored in the storage space.
S204, obtaining resting potential included in the neuron information corresponding to the neuron type identifier.
S202 obtains the neuron type of the neuron, finds a storage space corresponding to the neuron type, reads neuron information of the neuron type from the storage space, and obtains a resting potential.
For example, the neuron types may include A, B two types, where the A resting potential is-70 mv and the release threshold is 0.7V. The resting potential of B is-70 mv, and the release threshold value is 0.9V. Memory space may be maintained in the chip for types a and B, respectively. Each memory space may store corresponding neuron information (including resting potential and release threshold). Assuming that the neuron is known to be a neuron of type B in S202, a resting potential can be obtained from the memory space corresponding to type B through S204, i.e., the resting potential of the neuron is-70 mv.
Therefore, only one piece of same neuron information is stored for the same type of neurons, and the neuron information does not need to be stored for each neuron, so that the storage space is further saved.
In some embodiments, neuron information of the at least one neuron may be pre-stored within the chip by neuron type. For example, a segment of storage space may be allocated in advance for each neuron type in the chip, and the neuron information corresponding to each neuron type may be stored in the storage space.
In S104, a neuron type identifier corresponding to the current membrane potential and the neuron may be stored in association in response to the current membrane potential being different from a resting potential of the neuron.
In S106, in response to the current membrane potential being the same as the resting potential, the current membrane potential may be discarded, and the neuron type identifier corresponding to the neuron may be stored.
Therefore, the association between the neuron information and the current membrane potential can be established through the neuron type, and the association storage is realized, so that the neuron type identification of the neuron and the membrane potential can be stored in the same storage space in association besides only recording the membrane potential of the neuron in a working state, the information of other neurons of the neuron can be conveniently inquired when the membrane potential of the neuron is updated, and the storage efficiency and the storage space utilization rate are improved.
In some embodiments, the current membrane potential of a target neuron may be obtained in different ways depending on whether the membrane potential of the target neuron is stored.
Referring to fig. 3, fig. 3 is a schematic flow chart illustrating a method for obtaining a current membrane potential according to an embodiment of the present disclosure. As shown in fig. 3, the method may include S302-S304.
S302, in response to storing a membrane potential of a target neuron, determining the stored membrane potential of the target neuron as a current membrane potential of the target neuron.
The target neuron is any neuron in at least one neuron simulated by the chip. In some embodiments, the neurons included in the chip may be sequentially determined as the target neuron according to the neuron number.
If the membrane potential of the target neuron is stored, the target neuron is in a working state and is subjected to external stimulation, and the stored membrane potential of the target neuron can be used as the current membrane potential of the target neuron.
S304, in response to the membrane potential of the target neuron not being stored, determining a rest potential corresponding to the target neuron as a current membrane potential of the target neuron.
If the membrane potential of the target neuron is not stored, the target neuron is in a non-working state, namely is not stimulated by the outside world, and the resting potential of the target neuron can be used as the current membrane potential.
In some embodiments, neuron information of the at least one neuron may be pre-stored in the chip by neuron type. In S304, the neuron type of the target neuron may be acquired, and then, based on the neuron type, the neuron information of the target neuron may be queried. The resting potential included in the neuron information of the target neuron may then be taken as the current membrane potential of the target neuron.
Through the steps of S302-S304, the current membrane potential of the target neuron can be accurately determined under the condition that only the membrane potential of the neuron in the working state is recorded.
In some embodiments, after determining the current membrane potential of a target neuron, the current membrane potential may also be compared to a release threshold of the target neuron. The target neuron may be caused to send a pulse signal to its connected neuron if the current membrane potential reaches the release threshold.
In some embodiments, the neuron type identification may be stored only once for neurons of the same class, thereby further reducing storage space.
In this example, the neuron information of the at least one neuron may be stored in advance in the chip according to the neuron type; the chip stores a neuron type identifier of the at least one neuron.
In S104, a numbered identification of the neuron and the current membrane potential may be stored in response to the current membrane potential being different from a resting potential of the neuron, and the stored numbered identification and the current membrane potential may be associated with a neuron type identification of the neuron.
The number identifier may be a number ID assigned to each neuron included in the chip in advance. In some embodiments, each numbered identification may indicate a unique neuron. In some embodiments, a mapping relationship between number identifications and neuron types may be maintained. The neuron type of the neuron can be obtained through the mapping relation and the number of the neuron. For example, the chip may maintain the mapping of numbers 1-100 to type A and 101-200 to type B. If the neuron number is 50, it can be determined that the neuron type is A.
The number identifies the type of neuron that may also embody the neuron. The neuron type of the neuron can be known through the number identification of the neuron. For example, a neuron with number B1 may indicate that the neuron is a type B neuron, number 1. As another example, a neuron of number a10 may indicate that the neuron is a type a neuron, number 10.
In S104, in response to the current membrane potential being different from the resting potential of the neuron, it may be determined whether a type identifier of the neuron is stored in the chip. If the chip stores the type identification of the neuron, the number identification of the neuron, the acquired current membrane potential and the type identification can be stored in an associated mode.
If the chip does not store the type identifier of the neuron, the type identifier of the neuron can be stored first, then the number identifier of the neuron is identified, and the obtained current membrane potential is stored in association with the type identifier.
For example, a segment of memory space may be allocated for each class of neurons. After obtaining the type of the neuron in S104, it may be determined whether a segment of memory space is allocated in the chip for the type. If so, storing the number identification of the neuron and the acquired current membrane potential association into a storage space corresponding to the type. If not, a section of storage space can be allocated to the neuron, and then the serial number identification of the neuron and the acquired current membrane potential are stored in the storage space corresponding to the type in an associated mode.
Therefore, the current membrane potential of the neurons of the same type is stored in the storage space corresponding to the type, so that the neuron type identification does not need to be stored for each neuron, and the storage space is further saved.
In some embodiments, the following method may be employed for the above associative storage method to obtain the current membrane potential of the target neuron.
Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a method for obtaining a current membrane potential according to an embodiment of the present disclosure. As shown in fig. 4, the method may include S402-S404.
S402, in response to storing the number identification of the target neuron, determining the stored membrane potential associated with the number of the target neuron as the current membrane potential of the target neuron.
The target neuron is any neuron in at least one neuron simulated by the chip. In some embodiments, the neurons included in the chip may be sequentially determined as the target neuron according to the neuron number.
If the number identification of the target neuron is stored, the target neuron is in a working state and is stimulated by the outside, and the membrane potential stored in association with the number of the target neuron can be used as the current membrane potential.
S404, in response to the fact that the number identification of the target neuron is not stored, the resting potential corresponding to the target neuron is determined as the current membrane potential of the target neuron.
If the number identification of the target neuron is not stored, the target neuron is in a non-working state, namely is not stimulated by the outside, and the resting potential of the target neuron can be used as the current membrane potential.
In some embodiments, neuron information of the at least one neuron may be pre-stored in the chip by neuron type. In S404, a neuron type of the target neuron may be obtained, and then neuron information of the target neuron may be queried based on the neuron type. The resting potential included in the neuron information of the target neuron may then be taken as the current membrane potential of the target neuron.
The current membrane potential of the target neuron can be accurately determined by the steps of S402-S404 in the case where the type identifier is stored only once for the same type of neuron.
In some embodiments, after determining the current membrane potential of a target neuron, the current membrane potential may also be compared to a release threshold of the target neuron. The target neuron may be caused to send a pulse signal to its connected neuron if the current membrane potential reaches the release threshold.
In some embodiments, to facilitate management (including updating and reading) of the membrane potential of the neuron, the storage space may be divided according to the neural network layer of the neuron, and the neuron information of the neuron may be stored in the storage space corresponding to the network layer to which the neuron belongs. Thereby facilitating layer-by-layer management of the membrane potential of neurons.
The following description is given by way of example in conjunction with a scenario for managing brain chip neuron information.
The brain chip may include one or more compute cores. Where each compute kernel may simulate one or more neurons, or multiple compute kernels may simulate one neuron, embodiments of the present disclosure are not limited. The neuron may be a neuron in a spiking neural network. Each neuron may be numbered and a neuron type may be determined in advance, and then a mapping relationship of the neuron number and the neuron type may be stored in the chip. Each neuron type corresponds to some static neuron information (i.e., information that does not change whether the neuron is stimulated or not, which may include resting potentials). The chip may store static neuron information by neuron type. The chip may also allocate a storage space for storing the current membrane potential according to the neuron type.
Wherein S102 may be performed first. In S102, the current membrane potential of the neuron may be determined according to the stimulated information of the neuron, and the neuron type may be determined according to the number of the neuron and the mapping relationship, and the resting potential may be obtained.
In S104, if the membrane potential is different from the resting potential, it indicates that the neuron is stimulated, and it may be determined whether to allocate a storage space for the neuron, and if so, the number of the neuron and the membrane potential are stored in the allocated storage space in an associated manner. If not, storage space may be allocated for the class of neurons first, and then the number of the neuron and the membrane potential association are stored in the allocated storage space.
In S106, if the membrane potential is the same as the resting potential, it indicates that the neuron is in a non-operating state, and the membrane potential can be discarded without being stored.
In the brain type chip, on one hand, a block of storage space is allocated to the same type of neurons, that is, the neurons in the same block of storage space have the same neuron type, so that the information of the neuron type number of each neuron does not need to be recorded, and the storage space is further saved. On the other hand, only the number identification and the membrane potential of the neuron under the working state are recorded in the same storage space, and the related information of the neuron under the non-working state does not need to be recorded, so that the storage space does not need to be allocated to the neuron under the non-working state, and the storage space is further saved. In another aspect, the neuron information of the same type of neurons is distributed in the same block of storage space, so that the membrane potential of the neurons can be conveniently inquired.
When the current membrane potential of the brain chip neuron is inquired, the target neuron can be determined in sequence from small to large according to the neuron number, and S402-S404 is executed, so that the current membrane potential of the target neuron can be accurately determined.
In accordance with the foregoing embodiment, the present application proposes a neuron information processing device. The device may be applied to a chip that simulates at least one neuron by means of at least one computational core comprised therein.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a neuron information processing device according to an embodiment of the present application.
As shown in fig. 5, the apparatus 500 may include:
an obtaining module 510, configured to obtain a current membrane potential of each of the at least one neuron;
a storage module 520, configured to store neuron information of the neuron in association with the current membrane potential in response to the current membrane potential being different from a resting potential of the neuron;
in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.
In some embodiments, the neuron information comprises at least one of: release threshold, leakage value, resting potential.
In some embodiments, neuron information of the at least one neuron is pre-stored within the chip by neuron type; the storage module 520 is specifically configured to:
in response to the current membrane potential being different from a resting potential of the neuron, associatively storing a neuron type identifier corresponding to the current membrane potential and the neuron;
in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential, the method comprising:
in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential and storing a neuron type identifier corresponding to the neuron.
In some embodiments, the apparatus 500 further comprises:
a first determining module for, in response to storing a membrane potential of a target neuron, determining the stored membrane potential of the target neuron as a current membrane potential of the target neuron;
the second determination module is used for responding to the membrane potential of the target neuron which is not stored, and determining the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.
In some embodiments, neuron information of the at least one neuron is pre-stored within the chip by neuron type; the chip stores a neuron type identifier of the at least one neuron;
the storage module 520 is specifically configured to:
in response to the current membrane potential being different from a resting potential of the neuron, storing a numbered identification of the neuron and the current membrane potential, and associating the stored numbered identification and the current membrane potential with a neuron type identification of the neuron.
In some embodiments, the method further comprises:
a third determination module to determine, in response to storing a number identification of a target neuron, a stored membrane potential associated with a number of the target neuron as a current membrane potential of the target neuron;
and the fourth determination module is used for responding to the condition that the number identification of the target neuron is not stored, and determining the resting potential corresponding to the target neuron as the current membrane potential of the target neuron.
In some embodiments, the storage module 520 is specifically configured to:
and sequentially associating and storing the current membrane potential and the neuron information of the neuron based on preset neuron number identification.
In some embodiments, the chip comprises a many-core chip; the neurons comprise neurons in a spiking neural network.
The application also provides a chip. The chip simulates at least one neuron through at least one computational core included by the chip; wherein, the computation core is used for obtaining the current membrane potential of each neuron in the at least one neuron;
in response to the current membrane potential being different from a resting potential of the neuron, associatively storing neuron information of the current membrane potential and the neuron;
discarding the current membrane potential in response to the current membrane potential being the same as the resting potential.
In the foregoing solution, in response to that the current membrane potential is different from the resting potential of the neuron, the neuron information of the current membrane potential and the neuron is stored in an associated manner, and in response to that the current membrane potential is the same as the resting potential, the current membrane potential is discarded, so that only the membrane potential of the neuron in the working state can be stored, and the membrane potential of the neuron in the non-working state does not need to be stored, thereby saving the storage space of the chip.
The computation core may also execute the neuron information processing method shown in any one of the foregoing embodiments, which is not described in detail herein.
The application also discloses an electronic device. The electronic device includes a chip. Wherein the chip simulates at least one neuron by at least one computational core comprised by the chip; the computation core is used for obtaining the current membrane potential of each neuron in the at least one neuron; in response to the current membrane potential being different from a resting potential of the neuron, associatively storing neuron information of the current membrane potential and the neuron; discarding the current membrane potential in response to the current membrane potential being the same as the resting potential.
The present application proposes a computer-readable storage medium storing a computer program that can be used to cause a processor to execute the neuron information processing method shown in any one of the foregoing embodiments.
One skilled in the art will recognize that one or more embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
"and/or" as recited herein means having at least one of two, for example, "a and/or B" includes three scenarios: A. b, and "A and B".
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the data processing apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to part of the description of the method embodiment.
Specific embodiments of the present application have been described. Other embodiments are within the scope of the following claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Embodiments of the subject matter and functional operations described in this application may be implemented in the following: digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this application and their structural equivalents, or a combination of one or more of them. Embodiments of the subject matter described in this application can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode and transmit information to suitable receiver apparatus for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.
The processes and logic flows described in this application can be performed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).
Computers suitable for executing computer programs include, for example, general and/or special purpose microprocessors, or any other type of central processing system. Generally, a central processing system will receive instructions and data from a read-only memory and/or a random access memory. The essential components of a computer include a central processing system for implementing or executing instructions, and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer does not necessarily have such a device. Moreover, a computer may be embedded in another device, e.g., a mobile telephone, a Personal Digital Assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device such as a Universal Serial Bus (USB) flash drive, to name a few.
Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., an internal hard disk or a removable disk), magneto-optical disks, and 0xCD _00ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
Although this application contains many specific implementation details, these should not be construed as limiting the scope of any disclosure or of what may be claimed, but rather as merely describing features of particular disclosed embodiments. Certain features that are described in this application in the context of separate embodiments can also be implemented in combination in a single embodiment. In other instances, features described in connection with one embodiment may be implemented as discrete components or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the described embodiments is not to be understood as requiring such separation in all embodiments, and it is to be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Further, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.
The above description is only for the purpose of illustrating the preferred embodiments of the present application and is not intended to limit the present application to the particular embodiments of the present application, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present application and are intended to be included within the scope of the present application.
Claims (11)
1. A neuron information processing method is applied to a chip and is characterized in that the chip simulates at least one neuron through at least one computational core included in the chip; the method comprises the following steps:
obtaining a current membrane potential of each of the at least one neuron;
in response to the current membrane potential being different from a resting potential of the neuron, associatively storing neuron information of the current membrane potential and the neuron;
discarding the current membrane potential in response to the current membrane potential being the same as the resting potential.
2. The method of claim 1, wherein the neuron information comprises at least one of: release threshold, leakage value, resting potential.
3. The method according to claim 1, wherein neuron information of the at least one neuron is stored in advance in the chip by neuron type;
said associating storing neuron information for the current membrane potential and the neuron in response to the current membrane potential being different from a resting potential of the neuron, comprising:
in response to the current membrane potential being different from a resting potential of the neuron, associatively storing a neuron type identifier corresponding to the current membrane potential and the neuron;
in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential, the method comprising:
in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential and storing a neuron type identifier corresponding to the neuron.
4. The method of claim 1, further comprising:
in response to storing a membrane potential of a target neuron, determining the stored membrane potential of the target neuron as a current membrane potential of the target neuron;
in response to not storing a membrane potential of a target neuron, determining a resting potential corresponding to the target neuron as a current membrane potential of the target neuron.
5. The method of claim 1, wherein neuron information of the at least one neuron is pre-stored in the chip by neuron type; the chip stores a neuron type identifier of the at least one neuron;
said associating storing neuron information for the current membrane potential and the neuron in response to the current membrane potential being different from a resting potential of the neuron, comprising:
in response to the current membrane potential being different from a resting potential of the neuron, storing a numbered identification of the neuron and the current membrane potential, and associating the stored numbered identification and the current membrane potential with a neuron type identification of the neuron.
6. The method of claim 5, further comprising:
in response to storing a number identification of a target neuron, determining a stored membrane potential associated with a number of the target neuron as a current membrane potential of the target neuron;
in response to not storing the number identification of the target neuron, determining a resting potential corresponding to the target neuron as a current membrane potential of the target neuron.
7. The method of any one of claims 1-6, wherein said correlating stores said current membrane potential with neuron information for said neuron, comprising:
and sequentially associating and storing the current membrane potential and the neuron information of the neuron based on preset neuron number identification.
8. The method of claim 1, wherein the chip comprises a many-core chip; the neurons comprise neurons in a spiking neural network.
9. A neuron information processing device is applied to a chip, and is characterized in that the chip simulates at least one neuron through at least one computing core contained in the chip; the device comprises:
an obtaining module, configured to obtain a current membrane potential of each of the at least one neuron;
a storage module for storing neuron information of the neuron in association with the current membrane potential in response to the current membrane potential being different from a resting potential of the neuron;
in response to the current membrane potential being the same as the resting potential, discarding the current membrane potential.
10. A chip, characterized in that it simulates at least one neuron by means of at least one computational core it comprises; wherein the content of the first and second substances,
the computation core is used for obtaining the current membrane potential of each neuron in the at least one neuron;
in response to the current membrane potential being different from a resting potential of the neuron, associatively storing neuron information of the current membrane potential and the neuron;
discarding the current membrane potential in response to the current membrane potential being the same as the resting potential.
11. A storage medium characterized by storing a program for causing a chip computation core to execute the neuron information processing method according to any one of claims 1 to 8.
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| CN202210473210.7A CN114742213A (en) | 2022-04-29 | 2022-04-29 | Neuron information processing method, device, chip and storage medium |
| PCT/CN2023/091515 WO2023208178A1 (en) | 2022-04-29 | 2023-04-28 | Information processing method and unit, chip, device, medium, and product |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023208178A1 (en) * | 2022-04-29 | 2023-11-02 | 北京灵汐科技有限公司 | Information processing method and unit, chip, device, medium, and product |
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| WO2023208178A1 (en) * | 2022-04-29 | 2023-11-02 | 北京灵汐科技有限公司 | Information processing method and unit, chip, device, medium, and product |
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