WO2023207972A1

WO2023207972A1 - Package structure, electronic device, and packaging method

Info

Publication number: WO2023207972A1
Application number: PCT/CN2023/090576
Authority: WO
Inventors: 杨望来
Original assignee: 维沃移动通信有限公司
Priority date: 2022-04-28
Filing date: 2023-04-25
Publication date: 2023-11-02
Also published as: CN114843238A

Abstract

The present application discloses a package structure, an electronic device, and a packaging method. The package structure comprises: a carrier plate; multiple package bodies, the multiple package bodies being successively stacked on a first surface of the carrier plate; wires, each of the package bodies being electrically connected to the first surface of the carrier plate by means of the wire; and a first package layer, the first package layer covering the carrier plate and the multiple package bodies.

Description

Packaging structure, electronic equipment and packaging method

Cross-references to related applications

This application claims priority to the Chinese patent application with application number 202210471504.6 and the invention title "Packaging Structure, Electronic Device and Packaging Method" submitted on April 28, 2022, which is fully incorporated into this application by reference.

Technical field

The present application belongs to the technical field of electronic equipment, and specifically relates to a packaging structure, electronic equipment and packaging method.

Background technique

With the development of mobile terminals and wearable electronic products, more and more challenges have been brought to the motherboard layout of electronic products. In order to solve this problem, the application of integrating various different chips into a package template is becoming more and more widespread. Existing packaging structures mostly use multiple chips to be packaged on a substrate to form a package. Since the number of chips in the package is limited, the function is relatively single.

Contents of the invention

This application aims to provide a packaging structure, electronic equipment and packaging method, which at least solves the problem of limited number of chips and single function in the package.

In order to solve the above technical problems, this application is implemented as follows:

In a first aspect, an embodiment of the present application proposes a packaging structure, including: a carrier board; a plurality of packages, each of which is stacked in sequence on the first surface of the carrier board; a wire, each of the packages The packages are all electrically connected to the first surface of the carrier board through the wires; a first encapsulation layer covers the carrier board and the plurality of packages.

In the second aspect, embodiments of the present application provide an electronic device, including: a housing; a packaging structure The packaging structure is the packaging structure as described above, and the packaging structure is arranged in the housing.

In a third aspect, an embodiment of the present application proposes a packaging method, which includes: stacking multiple packages on the first surface of the carrier board; electrically connecting each of the packages to the first surface of the carrier board through wires ; Package the carrier board, the package body and the wires into a whole.

The packaging structure of this application realizes the integration of multiple packages into a whole by stacking multiple packages in sequence, using wires to electrically connect each package with the carrier board, and then packaging them into a whole, so that the packaging structure can be integrated Multiple chips have multiple functions, such as data storage and calculation, as well as video transcoding, audio transcoding, etc.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

Figure 1 is one of the schematic diagrams of the fan-out packaging structure provided by this application;

Figure 2 is the second schematic diagram of the fan-out packaging structure provided by this application;

Figure 3 is one of the structural schematic diagrams of the package shown in Figure 1;

Figure 4 is the second structural schematic diagram of the package shown in Figure 1;

Figure 5 is a third structural schematic diagram of the package shown in Figure 1;

Figure 6 is the fourth structural schematic diagram of the package shown in Figure 1;

Reference signs:

100: Carrier board; 200: Package; 201: Substrate; 202: Chip; 203: Second packaging layer; 204: Conductor; 205: Insulating layer; 206: Rewiring layer; 210: First slot; 220: Second through groove; 300: wire; 400: first packaging layer; 2041: first bonding wire; 2042: second bonding wire; 2043: metal bump.

Detailed ways

Embodiments of the present application will be described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and cannot be understood as limiting the present application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first" and "second" features in the description and claims of this application may include one or more of these features, either explicitly or implicitly. In the description of this application, unless otherwise stated, "plurality" means two or more. In addition, "and/or" in the description and claims indicates at least one of the connected objects, and the character "/" generally indicates that the related objects are in an "or" relationship.

The following describes the packaging structure, electronic device and packaging method of the embodiment of the present application with reference to Figures 1-6.

As shown in FIG. 1 , in the embodiment of the present application, the packaging structure includes: a carrier board 100 , a plurality of packaging bodies 200 , wires 300 and a first packaging layer 400 . A plurality of packages 200 are stacked on the first surface of the carrier board 100. Each package 200 is electrically connected to the first surface of the carrier board 100 through wires 300. The first package layer 400 covers the carrier board 100 and a plurality of Package 200.

Specifically, the carrier board 100 is a conductor. The first package body 200 is first placed on the carrier board 100, and then the second package body 200 is stacked on the package body 200. The second package body 200 can be connected with the first package body 200. The packages 200 are arranged in alignment or offset. Each package 200 is electrically connected to the first surface of the carrier board 100 through wires 300 . According to this arrangement method, multiple packages 200 can be stacked in sequence. After each package body 200 is electrically connected to the first surface of the carrier board 100, the carrier board 100, the plurality of packages 200 and the wires 300 can be packaged into a whole through the first packaging layer 400, and the package body 200 can be and wires 300 are located within the first packaging layer 400 .

Further, in this embodiment, each package is a small package structure, which has a substrate 201. Multiple grooves are opened on the substrate 201, and multiple chips are stacked in each groove. 202. A conductor 204 is provided on each chip 202, and the packaging material is filled in the groove to form a second packaging layer 203. An insulating layer 205 is provided on the second packaging layer 203, and a rewiring layer 206 is provided in the insulating layer 205. The chip 202 is electrically connected to the rewiring layer 206 through the conductor 204 to form a small package structure. Furthermore, in this embodiment, in order to reduce the thickness of the package 200, the bottom of the groove is ground away after the package 200 is formed, so that the groove becomes the first through groove 210.

Optionally, the first encapsulation layer 400 may be glue or plastic sealing material.

Further, in one embodiment of the present invention, multiple packages 200 are stacked and offset in sequence. Specifically, the second package 200 can be offset relative to the first package 200 along the length direction or width direction of the first package 200, so that part of the surface of the first package 200 is exposed. The exposed surface is used for disposing wires 300 , and each package 200 is electrically connected to the first surface of the carrier board 100 through the wires 300 .

Optionally, as shown in FIG. 1 , the number of wires 300 is multiple, and the first surface of the carrier board 100 and the multiple packages 200 are connected in series through the multiple wires 300 .

Optionally, as shown in FIG. 2 , the first ends of the plurality of wires 300 are electrically connected to the first surface of the carrier board 100 , and the second ends of the plurality of wires 300 are electrically connected to the plurality of packages 200 one-to-one. connect.

As shown in FIG. 2 , the fan-out package structure also includes a plurality of solder pads 501 and a plurality of solder balls 502 . The second surface of the carrier board 100 is provided with a plurality of solder pads 501, and each solder pad 501 is provided with a solder ball 502, wherein the second surface is opposite to the first surface.

As shown in FIG. 3 , each package 200 includes: a substrate 201 , a chip 202 , a second packaging layer 203 , a conductor, an insulating layer 205 and a rewiring layer 206 . The substrate 201 is provided with at least one first through groove 210, and at least one chip 202 is disposed in the at least one first through groove 210. The conductor is electrically connected to the chip 202 . The second packaging layer 203 covers the conductor and at least one chip 202, The insulating layer 205 is provided on the second packaging layer 203. A plurality of second through-slots are provided on the insulating layer 205. A rewiring layer 206 is provided in each second through-slot, wherein the rewiring layer 206 is electrically connected to the conductor 300. connect.

Specifically, the packaging process of each package 200 includes the following steps:

Step 101: Create multiple grooves on the silicon substrate, place the non-functional surface of the chip 202 toward the bottom of the grooves, and use adhesive glue to fix the non-functional surface of the chip 202 to the bottom of the grooves.

Step 102: A second chip 202 is stacked on the chip 202. The second chip 202 and the first chip 202 form a certain offset in the length direction or width direction, and the non-functional surface of the second chip 202 faces The first chip 202 is installed, and the two chips 202 are fixed with adhesive glue. In this way, multiple chips 202 can be stacked.

Step 103: Set a conductor 204 on each chip 202 and lead out the input/output interface of each chip 202.

Step 104: Fill the grooves of the silicon substrate with glue or plastic sealing material to form the second encapsulation layer 203. After solidification, grind the thickness of the silicon substrate to expose the conductor.

Step 105: Set an insulating layer 205 on the surface of the second encapsulation layer 203, open a plurality of second through-slots 220 on the insulating layer 205, set a rewiring layer 206 in each second through-slot 220, and conduct the conductor 204 and The rewiring layer 206 is connected to realize the electrical connection and relocation of each input/output interface.

Step 106: Process the bottom of the groove of the silicon substrate to make the groove become the first through groove 210, thereby reducing the thickness of the package 200. Further, the wire 300 is electrically connected to a rewiring layer 206 .

In this application, a groove is created inside the silicon substrate, and after the chip and conductor are packaged, the bottom of the groove of the silicon substrate is processed away, thereby thinning the thickness of the entire package and effectively reducing the package thickness. Using a silicon substrate can enhance the strength of the package, and the thermal expansion coefficients of the silicon substrate and the internal chip are similar, which can further reduce warpage during packaging.

In one embodiment of the present application, there are multiple chips 202 , and the multiple chips 202 are sequentially offset and stacked in at least one first through groove 210 . The conductor 204 includes a plurality of conductive elements, a plurality of One end of the conductive member is connected to the plurality of chips 202 in a one-to-one correspondence, and the other end of the plurality of conductive members is connected to the rewiring layer 206 .

Optionally, as shown in FIGS. 3 and 4 , the plurality of conductive members include at least one of a first bonding wire 2041 and a metal bump 2043 . Specifically, multiple first bonding wires 2041 can be provided on the uppermost chip 202, and one first bonding wire 2041 can be provided on the exposed surfaces of the other layers of chips 202. Each first bonding wire 2041 The first end is electrically connected to the chip 202, and the second end is electrically connected to a rewiring layer 206. Optionally, metal bumps 2043 may also be provided on the chip 202 adjacent to the insulating layer 205. The metal bumps 2043 may be provided separately or may be integrally formed with the chip 202. In this embodiment, to facilitate installation, the chip 202 and the metal bumps 2043 are integrally formed. Further, in this embodiment, the first bonding wire 2041 is a vertical bonding wire.

In this application, by arranging the first bonding wire or metal bump, the wire arc length is shortened, the electrical connection path is relatively short, and the thickness of the package can be further reduced. At the same time, the electrical connection path of the first bonding wire or metal bump is shorter, which can improve product performance.

As shown in FIG. 5 , in another embodiment of the present application, the number of chips 202 is multiple. The multiple chips 202 are sequentially offset and stacked in at least one first through slot 210 . The conductor 204 includes a first conductor. and a second conductive member, multiple chips 202 are connected in series through the first conductive member, and a chip 202 close to the rewiring layer 206 is electrically connected to the rewiring layer 206 through the second conductive member. In this embodiment, the first conductive component is the second bonding wire 2042, and the second conductive component is the first bonding wire 2041 or the metal bump 2043.

Specifically, in this embodiment, the chip 202 adjacent to the insulating layer 205 is electrically connected to the rewiring layer 206 through the first bonding wire 2041 or the metal bump 2043, and the chip 202 far away from the insulating layer 205 is electrically connected to the rewiring layer 206 through the second bonding wire 2041 or the metal bump 2043. The wire 2042 is electrically connected to the upper chip 202. In this embodiment, the second bonding wire 2042 is a curved bonding wire.

In this application, first bonding wires or metal bumps are provided on the chip adjacent to the insulating layer, and the chip far away from the insulating layer is connected to the chip located on it through the second bonding wire. This shortens the arc length and the electrical connection path is relatively opposite. Shorter, the thickness of the package can be further reduced. At the same time, the electrical connection path of the first bonding wire or metal bump is shorter, which can improve product performance.

As shown in FIG. 6 , in another embodiment of the present application, a plurality of first through grooves 210 can be opened on the silicon substrate, and the rewiring layer 206 corresponding to each first through groove 210 is integrally provided.

Specifically, in this embodiment, the arrangement of the conductors in each first through slot 210 may be the same or different. For example, the conductors 204 in each first through groove 210 are first bonding wires 2041; or the conductors 204 in one first through groove 210 are first bonding wires 2041, and the conductors 204 in another first through groove 210 are first bonding wires 2041. The conductor 204 is a metal bump 2043 and a first bonding wire 2041; or as shown in FIG. 6, the conductor 204 in one first through groove 210 is a metal bump 2043 and the first bonding wire 2041, and the other conductor 204 is a metal bump 2043 and a first bonding wire 2041. The conductor 204 in a through groove 210 is a first bonding wire 2041 and a second bonding wire 2042.

After the second encapsulation layer 203 is formed in each first through groove 210, an insulating layer 205 can be provided on all the second encapsulation layers 203. A second through groove 220 is opened in the insulating layer 205, and the rewiring layer 206 is disposed in the second through groove 220 , and the conductor 204 in each first through groove 210 is electrically connected to the rewiring layer 206 to reduce the manufacturing process of the package 200 .

It should be noted that in the above-mentioned embodiments, only the two chips 202 or the two first through slots 210 shown in the drawings are used as examples for explanation. In actual use, each chip can be used according to the specific situation. A plurality of chips 202 are disposed in the first through groove 210, and a plurality of first through grooves 210 are opened on the silicon substrate.

Furthermore, in the above-described embodiment, the functional surface of each chip 202 is away from the bottom of the first through groove 210 .

This application also provides an electronic device, including a casing and a packaging structure, and the packaging structure is arranged in the casing.

Specifically, in this embodiment, the electronic device may be a mobile phone, a tablet, a computer, etc.

The electronic equipment provided by this application effectively reduces the packaging thickness of the packaging structure, reserves more space for the electronic equipment to install other components, and improves the functionality of the electronic equipment.

This application also provides a packaging method, which specifically includes the following steps:

Step 201: Stack a plurality of packages 200 on the first surface of the carrier 100;

Step 202: electrically connect each package 200 to the first surface of the carrier board 11 through the wire 300 connect;

Step 203: Package the carrier board 100, the package body 200 and the wires 300 into a whole.

Specifically, the first package 200 is first placed on the carrier 100, and then the second package 200 is stacked on the package 200. The second package 200 can be aligned with the first package 200. , can also be set as an offset. Each package 200 is electrically connected to the first surface of the carrier board 100 through wires 300 . According to this arrangement method, multiple packages 200 can be stacked in sequence. After each package body 200 is electrically connected to the first surface of the carrier board 100, the carrier board 100, the plurality of packages 200 and the wires 300 can be packaged into a whole through the first packaging layer 400, and the package body 200 can be and wires 300 are located within the first packaging layer 400 .

The packaging method of this application realizes the integration of multiple packages into a whole by stacking multiple packages in sequence, using wires to electrically connect each package with the carrier board, and then packaging them into a whole, so that the packaging structure can be integrated Multiple chips have multiple functions, such as data storage and calculation, as well as video transcoding, audio transcoding, etc.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" or the like is intended to be incorporated into the description of the implementation. An example or example describes a specific feature, structure, material, or characteristic that is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present application have been shown and described, those of ordinary skill in the art will understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the application is defined by the claims and their equivalents.

Claims

A packaging structure including:

carrier board;

A plurality of packages, a plurality of packages stacked on the first surface of the carrier board;

Wires, each of the packages is electrically connected to the first surface of the carrier board through the wires;

A first packaging layer covers the carrier board and the plurality of packages.
The packaging structure of claim 1, wherein there are a plurality of conductors, first ends of the plurality of conductors are electrically connected to the first surface of the carrier board, and second ends of the plurality of conductors are electrically connected to the first surface of the carrier board. The terminals are electrically connected to a plurality of the packages in a one-to-one correspondence.
The packaging structure according to claim 1, wherein there are a plurality of wires, and the first surface of the carrier board and the plurality of packages are electrically connected through a plurality of the wires.
The packaging structure according to claim 1, wherein a plurality of the packages are sequentially offset and stacked on the first surface of the carrier board.
The packaging structure according to claim 1, wherein the packaging structure further includes a plurality of solder balls, the carrier board has a second surface opposite to the first surface, and the second surface is provided with a plurality of solder balls. A plurality of solder balls are connected to a plurality of solder pads in a one-to-one correspondence.
The packaging structure according to any one of claims 1 to 5, wherein at least one of the packaging bodies includes:

A substrate, at least one first through-slot is provided on the substrate, and at least one chip is disposed in the at least one first through-slot;

A conductor, the at least one chip is electrically connected to the conductor;

a second encapsulation layer, the second encapsulation layer covering the conductor and the at least one chip;

An insulating layer, the insulating layer is provided on the second packaging layer;

A rewiring layer, a second through slot is provided on the insulating layer, the rewiring layer is disposed in the second through slot, and the rewiring layer is electrically connected to the conductor.
The packaging structure according to claim 6, wherein there are a plurality of said chips, and a plurality of said chips are sequentially offset and stacked in the at least one first through groove;

The conductor includes a plurality of conductive elements, one end of the plurality of conductive elements is connected to a plurality of the chips in a one-to-one correspondence, and the other ends of the plurality of conductive elements are connected to the rewiring layer.
The package structure of claim 7, wherein the plurality of conductive members includes at least one of a first bonding wire and a metal bump.
The packaging structure according to claim 8, wherein a plurality of the conductive members include metal bumps, and the chip is integrally connected to the metal bumps.
The packaging structure according to claim 6, wherein there are a plurality of said chips, and a plurality of said chips are sequentially offset and stacked in the at least one first through groove;

The conductor includes a first conductive member and a second conductive member. A plurality of the chips are connected in series through the first conductive member. One of the chips close to the rewiring layer is connected to the second conductive member through the second conductive member. Reroute layer connections.
The packaging structure according to claim 10, wherein the first conductive member is a second bonding wire, and the second conductive member is a first bonding wire or a metal bump.
An electronic device including:

case;

A packaging structure, the packaging structure is the packaging structure according to any one of claims 1 to 11, and the packaging structure is arranged in the housing.
A packaging method including:

Multiple packages are stacked on the first surface of the carrier board;

electrically connecting each of the packages to the first surface of the carrier board through wires;

The carrier board, the package body and the wires are packaged as a whole.