WO2023207847A1

WO2023207847A1 - Flat panel detector and driving method therefor, and x-ray detection device

Info

Publication number: WO2023207847A1
Application number: PCT/CN2023/090070
Authority: WO
Inventors: 吴俊宇; 徐帅
Original assignee: 京东方科技集团股份有限公司; 北京京东方光电科技有限公司
Priority date: 2022-04-27
Filing date: 2023-04-23
Publication date: 2023-11-02
Also published as: CN117007617A

Abstract

A flat panel detector and a driving method therefor, and an X-ray detection device. The flat panel detector comprises a base substrate (10), a plurality of data lines (D) located on the base substrate (10), a multi-path selection circuit (20) respectively coupled to one end of each data line (D), and a plurality of holding capacitors (30) respectively coupled to the other end of each data line (D) in an one-to-one correspondence manner, wherein each holding capacitor (30) is used for maintaining the potential of the other data lines (D) to a fixed potential when a detection signal of the coupled data line (D) is read by means of the multi-path selection circuit (20). Noise interference in the data reading process of the flat panel detector is avoided, and the image quality of the flat panel detector is improved.

Description

Flat panel detector, its driving method and X-ray detection device

Cross-references to related applications

This disclosure requires the priority of the Chinese patent application submitted to the China Patent Office on April 27, 2022, with the application number 202210458777.7 and the application title "A flat-panel detector, its driving method and an X-ray detection device", and its entire content incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of detection technology, and in particular to a flat panel detector, its driving method and an X-ray detection device.

Background technique

X-rays have high penetrating power and can penetrate many materials that are opaque to visible light, such as ink, paper, wood, etc. Because the X-Ray detector (FPXD) can sense the intensity distribution of X-rays transmitted through the object, it can display the internal structure image of the object in the display interface, and has a wide range of applications in medicine, science and industry.

Existing X-ray detection devices usually use flat panel detectors (Flat Panel Detector, FPD) to convert X-ray information into digital image information. Generally, a flat panel detector includes a plurality of gate lines and a plurality of data lines arranged in a crosswise manner, as well as photosensitive pixels defined by the gate lines and data lines. Each photosensitive pixel may include a photodiode and a thin film transistor (Thin Film) coupled to the photodiode. Transistor, TFT). Moreover, the TFT is also connected to gate lines and data lines. When working, the scintillator located on the surface of the flat-panel detector converts the attenuated X-rays after passing through the human body into visible light. The photodiode converts the visible light into an electrical signal, and forms a stored charge on the capacitance of the photodiode itself, which is transmitted through the grid line. The gate scanning signal drives each photosensitive pixel to turn on, so as to read out the stored charge of each photosensitive pixel through the data line connected to the photosensitive pixel, thereby forming an X-ray digital image based on the stored charge. As the refresh frequency of flat-panel detectors becomes higher and higher, the turn-on time of transistors becomes shorter and shorter, and the delay in transmitting electrical signals is greater, reducing the accuracy of X-ray digital images.

Contents of the invention

The present disclosure provides a flat-panel detector, its driving method and an X-ray detection device, which are used to avoid noise interference during the data reading process of the flat-panel detector and improve the image quality of the flat-panel detector.

In a first aspect, an embodiment of the present disclosure provides a flat panel detector, including:

A base substrate, a plurality of data lines located on the base substrate, a multiplex selection circuit respectively coupled to one end of each of the data lines, and a one-to-one correspondence to the other end of each of the data lines. A plurality of coupled holding capacitors, wherein each of the holding capacitors is used to maintain the potential of the other data lines at a fixed potential when the detection signal of the coupled data line is read through the multiplexing circuit. .

In a possible implementation, each holding capacitor includes a first plate and a second plate facing away from the substrate substrate in sequence, and the second plate is coupled to the other end of the corresponding data line. The first electrode plates are connected to each other and the electric potential is the fixed electric potential.

In a possible implementation, the flat panel detector further includes a reading circuit coupled to the multiplexing circuit. When the reading circuit reads the detection signal through the multiplexing circuit, , the reference potential of the reading circuit is the fixed potential.

In a possible implementation, the capacitance values of each of the holding capacitors are the same.

In a possible implementation, the substrate includes a detection area and a peripheral area surrounding the detection area, and each of the data lines extends in a direction from the detection area to the peripheral area, and each of the data lines extends in a direction from the detection area to the peripheral area. The holding capacitor is disposed on a side close to the other end of the corresponding data line.

In a possible implementation, the plurality of holding capacitors are located in the detection area or the peripheral area.

In a possible implementation, the detection area includes a gate layer, a gate insulating layer, a semiconductor layer, a first conductive layer, an interlayer insulating layer, a second conductive layer, and a photoelectric induction layer in order facing away from the substrate. layer, a transparent wiring layer and a bias electrode layer; each of the first electrode plates and the first conductive layer are made in the same layer, and each of the second electrode plates and the bias electrode layer are made in the same layer.

In a possible implementation, the detection area further includes a first passivation layer, a flat layer and a first passivation layer located between the transparent wiring layer and the bias electrode layer and facing away from the base substrate in sequence. second passivation layer, the intermediate dielectric layer between each of the first electrode plate and the second electrode plate, and the interlayer insulating layer, the first passivation layer and the second passivation layer. At least one film layer should be made on the same layer.

In a possible implementation, the flat panel detector further includes a plurality of binding electrodes located in the peripheral area, and each of the first electrode plates passes through the first passivation layer, the flat layer and The via hole of the second passivation layer is coupled to the transparent electrode layer and coupled to the plurality of bonding electrodes.

In a possible implementation, the flat panel detector further includes a system mainboard located in the peripheral area and a gate drive circuit coupled to the system mainboard, and the plurality of binding electrodes are located on the gate on the drive circuit.

In a possible implementation, the flat panel detector further includes a system motherboard located in the peripheral area and coupled to the reading circuit, and the plurality of binding electrodes are located on the reading circuit.

In a possible implementation, the flat panel detector further includes a plurality of detection units arranged in an array, each of the detection units includes a switch control unit, and the multiplex selection circuit includes a plurality of switch selection units, wherein , each of the switch selection units is coupled to one end of the corresponding data line, the active layer of the transistor included in each of the switch selection units, and the active layer of the transistor included in each of the switch control units are both It is low temperature polysilicon material.

In a second aspect, embodiments of the present disclosure also provide an X-ray detection device, including:

Flat panel detector as described in any of the above.

In a third aspect, embodiments of the present disclosure also provide a driving method for a flat panel detector as described in any one of the above, including:

When the detection signal is read through the multiplexing circuit, a fixed potential is loaded on each of the holding capacitors.

The beneficial effects of this disclosure are as follows:

Embodiments of the present disclosure provide a flat panel detector, a driving method thereof, and an X-ray detection device. The flat panel detector includes a substrate. A plurality of data lines located on the substrate are connected to each data line respectively. A multiplexing circuit coupled to one end of each data line, and a plurality of holding capacitors coupled to the other end of each data line in one-to-one correspondence; in this case, one end of each data line is coupled to the multiplexing circuit, and the other end is coupled to the multiplexing circuit. A plurality of holding capacitors are coupled correspondingly. Also, individual holding capacitors are used to pass When the multiplexing circuit reads the detection signal of the coupled data line, it keeps the potential of other data lines at a fixed potential. Since each holding capacitor maintains the potential of other data lines at a fixed potential when reading the detection signal of the coupled data line through the multiplexing circuit, in this case, when the detection signal of the coupled data line is read through the multiplexing circuit During the signal process, noise from other data lines will not be introduced, thereby avoiding noise interference during the data reading process of the flat-panel detector and improving the image quality of the flat-panel detector.

Description of the drawings

Figure 1 is a schematic diagram of part of the circuit structure of a flat panel detector provided by an embodiment of the present disclosure;

Figure 2 is a timing diagram of the circuit structure shown in Figure 1;

Figure 3 is a schematic structural diagram of a flat-panel detector provided by an embodiment of the present disclosure;

Figure 4 is a schematic structural diagram of a flat-panel detector provided by an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram of a flat-panel detector provided by an embodiment of the present disclosure;

Figure 6 is a schematic structural diagram of a flat-panel detector provided by an embodiment of the present disclosure;

Figure 7 is a schematic diagram of one of the cross-sectional structures along the direction shown by MM in Figure 3;

Figure 8 is a schematic diagram of one of the cross-sectional structures along the direction shown in Figure 3;

Figure 9 is a schematic structural diagram of a flat-panel detector provided by an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of a flat panel detector provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. And the embodiments and features in the embodiments of the present disclosure may be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall be those to which this disclosure belongs. The usual meaning as understood by persons of average skill in the field. The use of "comprising" or "includes" and other similar words in this disclosure means that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things.

It should be noted that the sizes and shapes of the figures in the drawings do not reflect true proportions and are only intended to illustrate the present disclosure. And the same or similar reference numbers throughout represent the same or similar elements or elements with the same or similar functions.

In actual research, the present disclosure found that flat-panel detectors use a large number of readout chips (Read out Integrated Circuit, ROIC) for reading detection signals, resulting in higher costs. Moreover, due to the limitations of the bonding process, the product size cannot be effectively reduced. Combining Figures 1 and 2, you can consider adding a multiplex (MUX) unit to read the signal. Figure 1 is a schematic diagram of part of the circuit structure of the flat-panel detector, and Figure 2 is the corresponding circuit diagram of Figure 1. One of the timing diagrams, in which G1 represents the first row of gate lines, G2 represents the second row of gate lines, and G3 represents the third row of gate lines. However, there is mutual interference between different signal lines in the same MUX unit. Take the three MUX units 00 in Figure 1 as an example, including Mux01, Mux02 and Mux03. The three MUX units are used to control the signal acquisition of three columns of pixels respectively. When the first column of pixels is being collected, the TFTs of the other two columns of pixels are turned off. Due to the leakage current of the TFT due to process defects, the electrons on the two column signal lines in the off state will still leak through the corresponding TFT into the first column of signals being collected, eventually forming image noise.

In view of this, embodiments of the present disclosure provide a flat panel detector, its driving method and an X-ray detection device.

As shown in Figure 3, an embodiment of the present disclosure provides a flat panel detector, including:

The base substrate 10, a plurality of data lines D located on the base substrate 10, a multiplex selection circuit 20 respectively coupled to one end of each of the data lines D, and a multiplexing circuit 20 respectively coupled to each of the data lines D. The other end of the plurality of holding capacitors 30 is coupled in one-to-one correspondence, wherein each of the holding capacitors 30 is used to hold the The potential of the other data lines D is a fixed potential.

The above-mentioned flat panel detector provided by the embodiment of the present disclosure is coupled to one end of each data line D. The multiplexing circuit 20 is coupled to a plurality of holding capacitors 30 in one-to-one correspondence at the other end of each data line D, and each holding capacitor 30 is used to read the coupled data line D through the multiplexing circuit 20 . When detecting a signal, the potential of the other data line D is kept at a fixed potential. When the detection signal of the coupled data line D is read through the multiplexing circuit 20 , each holding capacitor 30 maintains the potential of the other data line D at a fixed potential. In this case, when the coupled data line D is read through the multiplexing circuit 20 During the signal detection process of the data line D, no noise from other data lines D will be introduced, thereby avoiding noise interference during the data reading process of the flat-panel detector and improving the image quality of the flat-panel detector.

In the embodiment of the present disclosure, as shown in FIG. 4 , each holding capacitor 30 includes a first plate 301 and a second plate 302 that are facing away from the base substrate 10 in sequence. The second plate 302 is in contact with the corresponding The other end of the data line D is coupled, the first plates 301 are connected to each other, and the potential is the fixed potential.

Still as shown in FIG. 4 , each holding capacitor 30 includes a first plate 301 and a second plate 302 that are facing away from the substrate substrate 10 in sequence. Each second plate 302 is coupled to the other end of the corresponding data line D. The first electrode plates 301 are connected to each other and have a fixed potential, where REF represents a fixed potential. In this way, the anti-noise capability of the flat panel detector is improved when the detection signal of the coupled data line D is read through the multiplexing circuit 20 .

In the embodiment of the present disclosure, the flat panel detector further includes a reading circuit 40 coupled to the multiplexing circuit 20 , where the reading circuit 40 reads the detection through the multiplexing circuit 20 When the signal is received, the reference potential of the reading circuit 40 is the fixed potential.

During specific implementation, each multiplexing circuit 20 includes a plurality of multiplexing units 201 , and each multiplexing unit 201 is coupled to one end of a plurality of data lines D. The flat panel detector also includes a reading circuit 40 coupled to the multiplexing circuit 20 . Each reading circuit 40 includes a plurality of reading units 400 coupled to a plurality of multiplexing units 201 in one-to-one correspondence. The number of the plurality of reading units 400 is the same as the number of the plurality of multiplexing units 201 , and they are arranged in one-to-one correspondence. In the exemplary embodiment shown in FIG. 5 , each multiplexing unit 201 is coupled to three data lines D, and one multiplexing circuit 20 is coupled to one reading circuit 40 . Of course, the number of multiplexing units 201 and the number of reading units 400 can also be set according to actual application needs, as well as each multiplexing unit. The number of data lines D coupled to the selection unit 201 is not limited here. In addition, in the embodiment of the present disclosure, the multiplexing circuit 20 is coupled to one end of each data line D, thereby simplifying the number of multiple reading units 400 in the reading circuit 40 and reducing the manufacturing cost of the flat panel detector. , while effectively reducing the size of the product and ensuring the thin and light design of the flat panel detector.

In the embodiment of the present disclosure, as still shown in FIG. 5 , each reading unit 400 in the reading circuit 40 may be a ROIC, and specifically may include an operational amplifier OP, an integrating capacitor CF, and a reset control switch INTRST; where, the operational amplifier OP The positive input terminal of the operational amplifier OP is used to receive the reference potential, the negative input terminal of the operational amplifier OP is coupled to the multiplexer, and the output terminal of the operational amplifier OP is coupled to the image signal output terminal Vout. The first terminal of the integrating capacitor CF is coupled to the negative input terminal of the operational amplifier OP, and the second terminal of the integrating capacitor CF is coupled to the output terminal of the operational amplifier OP. The first terminal of the reset control switch INTRST is coupled to the first terminal of the integrating capacitor CF, and the second terminal of the reset control switch INTRST is coupled to the second terminal of the integrating capacitor CF. In practical applications, the operational amplifier OP, the integrating capacitor CF and the reset control switch INTRST can be basically the same as those in the prior art. Those of ordinary skill in the art should understand that they have the same structure. They will not be described in detail here and should not be used. As a limitation of this disclosure.

In the embodiment of the present disclosure, the capacitance values of each holding capacitor 30 are the same. This ensures the uniformity of noise resistance of each holding capacitor 30 and ensures the image uniformity of the flat panel detector.

In the embodiment of the present disclosure, as still shown in FIG. 5 , the base substrate 10 includes a detection area AA and a peripheral area BB surrounding the detection area AA, and each of the data lines D points along the detection area AA. The peripheral area BB extends in the direction, and each holding capacitor 30 is disposed on a side close to the other end of the corresponding data line D.

In a specific implementation process, the base substrate 10 includes a detection area AA and a peripheral area BB surrounding the detection area AA. The distribution of the detection area AA and the peripheral area BB may be as shown in FIG. 5 . Since each data line D extends in the direction from the detection area AA to the peripheral area BB, each holding capacitor 30 is disposed on one side close to the other end of the corresponding data line D, that is, each holding capacitor 30 is disposed close to the corresponding data line. On the other side of D, in this case, while ensuring the anti-noise effect of the holding capacitor 30, the uniformity of each holding capacitor 30 against noise is ensured, and the image uniformity of the flat panel detector is ensured.

In the embodiment of the present disclosure, the plurality of holding capacitors 30 are located in the detection area AA or the peripheral area BB. Among them, FIG. 5 illustrates a situation in which multiple holding capacitors 30 are located in the peripheral area BB. During specific implementation, multiple holding capacitors 30 may also be located in the detection area AA. As shown in FIG. 6 , along the direction in which the detection area AA points to the peripheral area BB, a plurality of holding capacitors 30 may be arranged as the last row of the detection area AA. Of course, the specific positions of the multiple holding capacitors 30 can also be set according to actual application needs, which will not be described in detail here.

In the embodiment of the present disclosure, the detection area AA includes the gate layer 101, the gate insulating layer 102, the semiconductor layer 103, the first conductive layer 104, the interlayer insulating layer 105, and the second The conductive layer 106, the photoelectric sensing layer 107, the transparent wiring layer 108 and the bias electrode layer 109; each of the first electrode plates 301 and the first conductive layer 104 are made in the same layer, and each of the second electrode plates 302 It is made in the same layer as the bias electrode layer 109 .

During the specific implementation process, FIG. 7 is a schematic cross-sectional structural diagram along the direction shown by MM in FIG. 3 . The detection area AA includes the gate layer 101, the gate insulating layer 102, the semiconductor layer 103, the first conductive layer 104, the interlayer insulating layer 105, the second conductive layer 106, the photoelectric sensing layer 107, and the transparent trace in sequence facing away from the base substrate 10. Line layer 108 and bias electrode layer 109. In one exemplary embodiment, the material of the semiconductor layer 103 may be a low-temperature polysilicon semiconductor material. Alternatively, the material of the semiconductor layer 103 may also be a metal oxide semiconductor material, such as Indium Gallium Zinc Oxide (IGZO). In this way, the mobility of the corresponding transistor is guaranteed. The first conductive layer 104 may be a first source and drain electrode layer, and the second conductive layer 106 may be a second source and drain electrode layer. The photoelectric sensing layer 107 may include a P layer structure, an I layer structure, and an N layer structure facing away from the base substrate 10 in order. The bias electrode layer 109 can input a bias voltage to the photodetection device 901 in the flat panel detector. When the photodetection device 901 receives a light signal, it can generate an electrical signal through photoelectric conversion. The photodetection device 901 is, for example, Can be a photodiode (PIN). In addition, the first plate 301 and the first conductive layer 104 of each holding capacitor 30 are made in the same layer. In actual preparation, the same patterning process can be used to prepare the first plate 301 and the first conductive layer 104, thereby improving the process. preparation efficiency. Moreover, the second electrode plate 302 of each holding capacitor 30 is made in the same layer as the bias electrode layer 109. In actual preparation, the same patterning process can be used to prepare the second electrode plate 302 and the bias electrode layer 109. The electrode layer 109 is biased, thereby improving the process preparation efficiency.

In the embodiment of the present disclosure, the detection area AA also includes a first passivation layer 50 located between the transparent wiring layer 108 and the bias electrode layer 109 and facing away from the base substrate 10 in sequence. The flat layer 60 and the second passivation layer 70, the intermediate dielectric layer 303 between each of the first electrode plate 301 and the second electrode plate 302, and the interlayer insulating layer 105, the first passivation layer The layer 50 and at least one film layer in the second passivation layer 70 are made in the same layer.

During the specific implementation process, FIG. 8 is a schematic diagram of one of the cross-sectional structures along the direction shown as NN in FIG. 3 . The detection area AA also includes a first passivation layer 50, a flat layer 60 and a second passivation layer 70 located between the transparent wiring layer 108 and the bias electrode layer 109 and facing away from the base substrate 10 in sequence. The intermediate dielectric layer 303 between the plate 301 and the second electrode plate 302 is made in the same layer as at least one of the interlayer insulating layer 105, the first passivation layer 50 and the second passivation layer 70. Among them, the first passivation layer 50, the flat layer 60, the second passivation layer 70, the gate insulating layer 102 and the interlayer insulating layer 105 are made of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). ), which may be a single layer, multiple layers or composite layers. FIG. 8 shows a schematic structural diagram of a structure in which the intermediate dielectric layer 303 is formed in the same layer as the first passivation layer 50 , the flat layer 60 and the second passivation layer 70 . In this way, in actual preparation, the same patterning process can be used to prepare the intermediate dielectric layer 303 and the first passivation layer 50 , the flat layer 60 and the second passivation layer 70 , thereby improving the process preparation efficiency. Of course, a corresponding film layer structure can also be selected to prepare the intermediate dielectric layer 303 according to actual application requirements, which is not limited here. In addition, in addition to the above-mentioned film structure, the flat-panel detector according to the embodiment of the present disclosure can also be provided with other film structures according to actual application needs, such as adhesive layers, cover plates, etc. For details, please refer to the related art. The technical implementation will not be detailed here.

In the embodiment of the present disclosure, the flat panel detector further includes a plurality of binding electrodes 80 located in the peripheral area BB, and each first plate 301 passes through the first passivation layer 50 and the flat The via holes of layer 60 and the second passivation layer 70 are coupled to the transparent electrode layer and coupled to the plurality of bonding electrodes 80 .

During the specific implementation process, the flat panel detector also includes a plurality of binding electrodes 80 located in the peripheral area BB. The specific number of the multiple binding electrodes 80 can be set according to actual application needs, and is not limited here. Certainly. The first plate 301 of each holding capacitor 30 is coupled to the transparent electrode layer through via holes penetrating the first passivation layer 50 , the flat layer 60 and the second passivation layer 70 , and is coupled to the plurality of binding electrodes 80 . That is to say, the first plate 301 of each holding capacitor 30 can be coupled to the transparent electrode layer through the above-mentioned via holes, and finally coupled to the plurality of binding electrodes 80 . In this case, the required signals can be loaded to the corresponding first plate 301 through the plurality of binding electrodes 80, thereby improving the performance of the flat panel detector.

It should be noted that the aforementioned flat panel detector also includes a plurality of gate lines G intersecting the plurality of data lines D, and a plurality of detection units 90 defined by the plurality of data lines D and the plurality of gate lines G. , multiple detection units 90 are arranged in an array in the detection area AA. Each detection unit 90 includes a photoelectric detection device 901 and a switch control unit 902 used to control the photoelectric detection device 901 to collect data. In addition, the peripheral area BB also includes the system motherboard 100 and the gate driving circuit 101. The gate driving circuit 101 may be installed on one side or on both sides, which is not limited here. The system mainboard 100 can load required signals to the coupled circuits, thereby ensuring the performance of the flat panel detector.

In the embodiment of the present disclosure, the following two implementations can be used to arrange multiple binding electrodes 80, but are not limited to the following two implementations.

In a first implementation, as shown in Figure 9, the flat panel detector further includes a system mainboard 100 located in the peripheral area BB and a gate drive circuit 101 coupled to the system mainboard 100. A bonding electrode 80 is located on the gate driving circuit 101.

Still as shown in FIG. 9 , the flat panel detector also includes a system motherboard 100 located in the peripheral area BB and a gate driving circuit 101 coupled to the system motherboard 100 . A plurality of binding electrodes 80 are located on the gate driving circuit 101 . The gate driving circuit 101 includes a flexible circuit board, and the plurality of bonding electrodes 80 can be coupled to the system motherboard 100 through the vias H penetrating the flexible circuit board. In this case, the system motherboard 100 can connect to the system motherboard 100 through the plurality of bonding electrodes 80 . The first plate 301 of each holding capacitor 30 is loaded with a required voltage signal of a fixed potential. Since the wiring length between the first polar plate 301 and the plurality of binding electrodes 80 is relatively short, the control efficiency of the first polar plate 301 by the system mainboard 100 is improved.

In a second implementation, the flat panel detector further includes a system motherboard 100 located in the peripheral area BB coupled to the reading circuit 40 , and the plurality of binding electrodes 80 are located in the reading circuit 40 superior. Of course, multiple binding electrodes 80 can also be provided according to actual application needs, and there is no limitation here. Certainly.

In the embodiment of the present disclosure, as shown in FIG. 10 , the flat panel detector further includes a plurality of detection units 90 arranged in an array. Each of the detection units 90 includes a switch control unit 902 . The multiplexing circuit 20 It includes a plurality of switch selection units 200, wherein each switch selection unit 200 is coupled to one end of the corresponding data line D, an active layer of a transistor included in each switch selection unit 200, and each of the switch selection units 200. The active layers of the transistors included in the switch control unit 902 are all made of low-temperature polysilicon material.

Still as shown in FIG. 10 , the flat panel detector also includes a plurality of detection units 90 arranged in an array. Each detection unit 90 includes a photoelectric detection device 901 and a switch control unit 902 for controlling the switch detection device to collect data. Each multiplex selection unit 201 includes a plurality of switch selection units 200 for controlling conduction between a plurality of data lines D and the read circuit 40 . Each switch selection unit 200 is coupled to one end of the corresponding data line D. The active layer of the transistor included in each switch selection unit 200 and the active layer of the transistor included in each switch control unit 902 are both low-temperature polysilicon. Material. Of course, the specific number of multiple detection units 90 and multiple switch selection units 200 can be set according to actual application needs, and is not limited here.

In actual research, the present inventor found that when the active layer of each transistor in a flat panel detector is made of low-temperature polysilicon material, the carrier mobility of the corresponding device is about 100 times that of a-Si currently used. In this case , the turn-on resistance of each transistor in the embodiment of the present disclosure is small, and during the signal collection process, the resistance-capacitance delay (RC Delay) in the corresponding line is low, thereby ensuring the performance of the flat-panel detector.

It should be noted that the transistors included in each switch control unit 902 and the transistors included in each switch selection unit 200 may be of the same type. For example, both are P-type transistors; for another example, both are N-type. transistor. In addition, the types of transistors included in each switch control unit 902 and the transistors included in each switch selection unit 200 may be different. For example, the transistors included in each switch control unit 902 are P-type transistors, and the transistors included in each switch selection unit 200 are P-type transistors. The transistors included are N-type transistors; for another example, the transistors included in each switch control unit 902 are N-type transistors, and the transistors included in each switch selection unit 200 are P-type transistors. Of course, the type of each transistor can be set according to actual application needs, and is not limited here. Furthermore, the transistor mentioned above may be a TFT or a metal oxide semiconductor field effect transistor (Metal Oxide Scmiconductor, MOS), which is not limited here.

The working process of the flat panel detector provided by the embodiment of the present disclosure will be described below based on the structure of the flat panel detector shown in FIG. 10 . It should be noted that this embodiment is to better explain the present disclosure and does not limit the specific implementation of the present disclosure.

Still as shown in FIG. 10 , the flat panel detector includes a detection unit 90 defined by a gate line G and a data line D. Among them, one row of detection units 90 is correspondingly coupled to one gate line G, and one column of detection units 90 is correspondingly coupled to one data line D. The first multiplex selection unit 201 includes three switch selection transistors including MUX011, MUX012 and MUX013. Each detection unit 90 includes a photodiode and a switching control transistor for transmitting an electrical signal generated by the photodiode to the data line D. The process of X-ray detection by the detection unit 90 is the same as that in the prior art, and will not be described in detail here.

At the initial moment, all transistors in the flat-panel detector are turned off. At this time, the potentials of the Vp capacitor and the holding capacitor 30 are consistent with the reference potential of the reading circuit 40; when the flat-panel detector receives exposure, all photodiodes generate photogenerated electrons. And stored in the Vp capacitor; when the first row of gate lines G is turned on, part of the electrons in each Vp capacitor on this row are read out by the holding capacitor 30 and stored in the holding capacitor 30, and the other part is still stored in the Vp capacitor; then, Open the first column MUX011 in the first multiplex selection unit 201. At this time, the electrons in the Vp capacitor corresponding to the detection unit 90 in the first row and first column position, and in the holding capacitor 30 coupled to the first column MUX011 All the electrons are read out and transmitted to the ROIC for data processing. At the same time, the reference potential of the ROIC charges the Vp capacitor and the holding capacitor 30; because when MUX011 reads the electrons, both MUX012 and MUX013 are in a closed state, and because the holding capacitor The potential of 30 is the same fixed potential as the reference potential of ROIC, and the capacitance of the two is the same. Therefore, the transistors corresponding to MUX012 and MUX013 have no current leakage. In this case, no noise from other data lines D is introduced during the reading process of MUX011. Repeat the above steps until the detection signal of the entire flat-panel detector is read.

Based on the same inventive concept, an embodiment of the present disclosure also provides an X-ray detection device, including the above flat panel detector provided by an embodiment of the present disclosure. The problem-solving principle of this X-ray detection device is The foregoing flat-panel detector is similar. Therefore, the implementation of the X-ray detection device can refer to the implementation of the foregoing flat-panel detector, and repeated details will not be repeated. Moreover, other essential components of the X-ray detection device are all understood by those of ordinary skill in the art, and are not described in detail here, nor should they be used to limit the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure also provides a driving method using the flat panel detector provided by the embodiment of the present disclosure. The driving method includes:

When the detection signal is read through the multiplexing circuit 20 , a fixed potential is loaded on each of the holding capacitors 30 .

For the specific implementation process of the driving method, reference can be made to the foregoing description of relevant parts, and details will not be described again here.

Embodiments of the present disclosure provide a flat panel detector, a driving method thereof, and an X-ray detection device. The flat panel detector includes a base substrate 10, and a plurality of data lines D located on the base substrate 10, respectively connected with each other. A multiplexing circuit 20 coupled to one end of each data line D, and a plurality of holding capacitors 30 coupled to the other end of each data line D in one-to-one correspondence; in this case, one end of each data line D is coupled to The other end of the multiplexing circuit 20 is coupled to a plurality of holding capacitors 30 in one-to-one correspondence. Furthermore, each holding capacitor 30 is used to maintain the potential of other data lines D at a fixed potential when the detection signal of the coupled data line D is read through the multiplexing circuit 20 . When the detection signal of the coupled data line D is read through the multiplexing circuit 20 , each holding capacitor 30 maintains the potential of the other data line D at a fixed potential. In this case, when the coupled data line D is read through the multiplexing circuit 20 During the signal detection process of the data line D, no noise from other data lines D will be introduced, thereby avoiding noise interference during the data reading process of the flat-panel detector and improving the image quality of the flat-panel detector.

Although the preferred embodiments of the present disclosure have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this disclosure.

Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

A flat panel detector, including:

A base substrate, a plurality of data lines located on the base substrate, a multiplex selection circuit respectively coupled to one end of each of the data lines, and a one-to-one correspondence to the other end of each of the data lines. A plurality of coupled holding capacitors, wherein each of the holding capacitors is used to maintain the potential of the other data lines at a fixed potential when the detection signal of the coupled data line is read through the multiplexing circuit. .
The flat panel detector according to claim 1, wherein each holding capacitor includes a first plate and a second plate facing away from the substrate substrate in sequence, and the second plate is connected to the corresponding data line. The other end is coupled, the first plates are connected to each other and the potential is the fixed potential.
The flat panel detector according to claim 2, wherein the flat panel detector further includes a reading circuit coupled to the multiplexing circuit, and the reading circuit reads the data through the multiplexing circuit. When detecting a signal, the reference potential of the reading circuit is the fixed potential.
The flat panel detector according to claim 3, wherein the capacitance values of each of the holding capacitors are the same.
The flat panel detector according to claim 4, wherein the substrate includes a detection area and a peripheral area surrounding the detection area, and each of the data lines extends in a direction from the detection area to the peripheral area. , each holding capacitor is disposed on a side close to the other end of the corresponding data line.
The flat panel detector according to claim 5, wherein the plurality of holding capacitors are located in the detection area or the peripheral area.
The flat panel detector according to claim 6, wherein the detection area includes a gate layer, a gate insulating layer, a semiconductor layer, a first conductive layer, an interlayer insulating layer, and a second conductive layer in order facing away from the base substrate. layer, photoelectric induction layer, transparent wiring layer and bias electrode layer; each of the first electrode plates and the first conductive layer are made in the same layer, and each of the second electrode plates and the bias electrode layer Made on the same floor.
The flat panel detector according to claim 7, wherein the detection area further includes a The first passivation layer, the flat layer and the second passivation layer are between the transparent wiring layer and the bias electrode layer and are sequentially away from the base substrate, and each of the first electrode plate and the third passivation layer are The intermediate dielectric layer between the two electrode plates is made in the same layer as at least one film layer among the interlayer insulating layer, the first passivation layer and the second passivation layer.
The flat panel detector according to any one of claims 5 to 8, wherein the flat panel detector further includes a plurality of binding electrodes located in the peripheral area, and each of the first electrode plates passes through the first The passivation layer, the planarization layer and the via holes of the second passivation layer are coupled to the transparent electrode layer and coupled to the plurality of bonding electrodes.
The flat panel detector according to claim 9, wherein the flat panel detector further includes a system main board located in the peripheral area and a gate driving circuit coupled to the system main board, and the plurality of binding electrodes are located at on the gate drive circuit.
The flat panel detector according to claim 9, wherein the flat panel detector further includes a system motherboard located in the peripheral area and coupled to the reading circuit, and the plurality of binding electrodes are located in the reading circuit. superior.
The flat panel detector according to any one of claims 5 to 8, wherein the flat panel detector further includes a plurality of detection units arranged in an array, each of the detection units includes a switch control unit, and the multiplexing The circuit includes a plurality of switch selection units, wherein each switch selection unit is coupled to one end of the corresponding data line, an active layer of a transistor included in each switch selection unit, and each switch control unit The active layers of the included transistors are all low-temperature polysilicon materials.
An X-ray detection device, which includes:

The flat panel detector according to any one of claims 1-12.
The driving method of the flat panel detector according to any one of claims 1 to 12, which includes:

When the detection signal is read through the multiplexing circuit, a fixed potential is loaded on each of the holding capacitors.