WO2023206954A1 - 一种基于目标检测网络的寄生参数提取方法 - Google Patents

一种基于目标检测网络的寄生参数提取方法 Download PDF

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WO2023206954A1
WO2023206954A1 PCT/CN2022/121419 CN2022121419W WO2023206954A1 WO 2023206954 A1 WO2023206954 A1 WO 2023206954A1 CN 2022121419 W CN2022121419 W CN 2022121419W WO 2023206954 A1 WO2023206954 A1 WO 2023206954A1
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detection network
target detection
parasitic parameter
layout
loss
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陆生礼
蒋明月
梁天柱
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东南大学
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    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
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    • G06N3/00—Computing arrangements based on biological models
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  • the invention relates to the field of parasitic parameter extraction, and specifically relates to a parasitic parameter extraction method based on a target detection network.
  • Parasitic extraction is a one-step process at the backend of digital integrated circuit design that extracts the parasitic resistance and capacitance of interconnect lines from the completed layout.
  • process nodes advance, the impact of parasitic capacitance and resistance caused by interconnect lines on circuit timing gradually increases.
  • the larger the scale of integrated circuits the higher the requirements for the extraction capabilities and efficiency of parasitic parameter extraction tools.
  • Commonly used extraction methods can be divided into field solution methods and pattern matching methods.
  • the pattern matching method establishes a pattern library in advance based on the geometric structure and geometric parameters. When extracting, the actual layout is compared with the pattern library to obtain the resistance and capacitance values. This method is more suitable for large-scale circuits, but errors often occur due to pattern matching errors, and The establishment of a pattern library is time-consuming and laborious.
  • the present invention proposes a parasitic parameter extraction method based on a target detection network. Simplify the way to build the pattern library, classify and locate the geometric structure of the interconnection lines in the layout through the target detection network, and compare the network output results with the pattern library to achieve accurate pattern matching.
  • the present invention aims to provide a simple and optional solution for the establishment and pattern matching of parasitic parameter pattern libraries of digital integrated circuits.
  • the present invention adopts the following technical solution: a parasitic parameter extraction method based on a target detection network, generates a picture set and a mark file of similar layouts, creates a training set, optimizes the loss function, trains the target detection network, and combines other layouts with The image is input to the trained network, and the network will output pattern and coordinate information, compare it with the pattern library, locate the wire, and obtain the parasitic capacitance value.
  • Step 1 Establish a parasitic capacitance pattern library
  • Step 2 Generate pictures that conform to the characteristics of layout interconnection lines, and annotate them to build a data set
  • Step 3 Use the data set to train the target detection network, and optimize the target detection network by optimizing the loss function
  • Step 4 Use the trained target detection network to predict the layout image, and perform subsequent processing on the prediction results of the network to obtain the parasitic parameter values.
  • step 1 the specific steps of step 1 are: setting different colors to represent different conductor layers or conductor overlapping relationships, and respectively listing the capacitance formula lookup tables of the surface capacitance with respect to the geometric structure (including layer relationships and conductor spacing ranges on the same layer), Lookup table of the capacitance formula of the coupling capacitor with respect to the geometric structure (number of conductors in the same layer).
  • the specific steps of step 2 are: setting color blocks of different colors to represent different conductor layers or conductor overlapping relationships (overlapping relationships of conductors of different layers or overlapping relationships of conductors of the same layer), in the central area of the picture Randomly generate some color blocks of different colors, sizes, vertical or horizontal colors as the interference background. On the interference background, according to the proportion of the overlapping part of the actual layout to the wires, randomly generate the target color color blocks representing the overlapping relationship of the wires, and export The category and coordinate values of the target color patch are used as labels.
  • the loss function of the target detection network is optimized based on the specific application of area prediction.
  • the specific steps are: adding an area loss to the loss function of the original target detection network, namely target loss, category loss and prediction frame loss; After pre-training, hyperparameter evolution is performed on the coefficients before each loss to obtain the optimal coefficients for each loss.
  • step 4 includes: visualizing the three-dimensional structure of the multi-layer wire described in the layout file into a picture according to three views, in which the top view is used for surface capacitance extraction, the left view and the front view are used for coupling capacitance extraction, and the layout picture is divided according to the pattern size. into several smaller pictures as input to the target detection network.
  • the target detection network makes predictions on the layout pictures; the geometric structure is obtained from the prediction classification results, and compared with the pattern library, the capacitance calculation formula is obtained, and the wire is located based on the center coordinates of the prediction frame.
  • the geometric parameters (including overlapping area, length and width of the overlapping part) are obtained from the coordinates and size of the prediction frame, and then substituted into the formula to calculate the parasitic capacitance value of each wire.
  • the pattern matching process in the present invention uses a target detection network, which is a deep neural network used for target detection and can classify and locate targets in pictures. Taking the wire overlapping structure as the detection target and using the layout image containing only interconnection lines as the network input, the network can obtain the category of the wire, that is, the mode, and based on the prediction frame coordinates, the position and overlap area of the wire in the layout can be obtained , overlap width, overlap length and other geometric parameters. Since the target detection network has been developed to yolo v5, fast and accurate target detection can be achieved. The use of the network replaces complex matching algorithms and improves matching accuracy.
  • the pattern library in the present invention classifies patterns according to the geometric structure that affects the wire, and provides calculation formulas for the parasitic surface capacitance value and the parasitic coupling capacitance value according to the analytical method. The sum of the two is the parasitic capacitance value.
  • the specific geometric parameters Such as wire length, width, etc.
  • the pattern library established in this way is also suitable for various process sizes.
  • the parasitic capacitance value can be calculated by substituting geometric parameters such as the overlap area value into the capacitance analytical formula of the corresponding mode.
  • the present invention introduces the target detection network into the field of parasitic parameter extraction for the first time, there is no labeled layout picture set that can be used for training, so the present invention builds a self-built data set based on the characteristics of the layout interconnection lines.
  • the data set only contains interconnection lines, and according to the characteristics of interconnection lines in the real layout, a picture set of the required size can be automatically generated. This method effectively simplifies the data set while simulating layout images, and saves the huge workload of manual annotation.
  • Figure 1 is the design flow chart of the parasitic capacitance extraction method
  • Figure 2 shows a simplified parasitic surface capacitance pattern library
  • Figure 3 shows the structural design of the target detection network.
  • Figure 1 is the design flow chart of the parasitic capacitance extraction method.
  • the pattern library shown in Figure 2
  • network structure shown in Figure 3 (a), (b)
  • the overall algorithm framework includes three parts: data set establishment, network training, and layout extraction:
  • a layout containing only interconnecting lines is represented by some color blocks of different colors and different lengths.
  • the target color block and the interference color block are The proportions, the length and width of the color blocks, the distribution area of the color blocks in the picture, etc. need to be consistent with the real layout.
  • the modified loss function is:
  • the first three items in the formula are the loss functions of the original target detection network, that is, the target loss, category loss and prediction box loss. Weighted sum, the last term is the added area loss. Or redesign the data set and change the length range of the color blocks to optimize the training results until the network test results meet expectations.
  • the process of network prediction is the process of pattern matching. After wire matching is performed on the predicted values, the overlapping Parameters such as area, overlap width, overlap length, etc. are substituted into the calculation formula corresponding to the mode for calculation, and other required wire geometric parameters (including wire spacing, wire width) are directly read from the original layout file, and the parasitic capacitance is finally obtained. value.
  • Figure 2 is a simplified parasitic surface capacitance pattern library.
  • the pattern library described in this figure is for illustration only. It only considers one wire per layer, a total of five layers of metal from M0 to M4, and the surface capacitance is simplified to a plate capacitance. The actual pattern library will more complicated. Set different RGB values to distinguish different layers and layer overlapping relationships, and write the expression of the unit capacitance value to obtain a pattern library. Each layer overlapping relationship and its corresponding unit capacitance formula is a pattern. The layer spacing and dielectric constant values are input in advance, and then the overlapping area and layer relationship of the network output are corresponding to the pattern library, and then substituted into the capacitance expression to calculate the capacitance value. This is the pattern matching process of capacitance.
  • Figure 3 shows the structural design of the target detection network.
  • Figure 3(a) shows the internal structure of the network, using the YOLO v5s network model, which consists of four parts: input, backbone, neck and prediction.
  • the input end performs some processing on the original image and then inputs it into the network;
  • the backbone network is composed of Conv convolution, BN batch normalization, Leaky relu activation function and other modules, and performs core calculations on the feature map;
  • the neck network adds a cross-layer structure to enhance the The ability of network feature fusion;
  • the prediction end outputs network prediction results, including category information and prediction box information.
  • Figure 3(b) shows the external structure of the network, that is, the input and output design of the network.
  • the input and output of the network can be divided into a training process and a layout extraction process.
  • the training process takes the data set as input, and the output category, prediction box size, and prediction box center coordinates are used to calculate parameters indicating network accuracy such as precision, recall, and mean average precision (mAP).
  • mAP mean average precision
  • the size of the prediction box is also used to calculate the area accuracy.
  • a layout image is input, and the output category represents the layer relationship, that is, which two layers of metal overlap, the size of the prediction box represents the overlapping area, the side length of the prediction box represents the width and length of the overlapping part, and the center coordinate of the prediction box
  • the wire can be located, that is, the wire it is located on, or the overlapping layer relationship of the wires it is located on. It can be seen that the coordinates and size of the prediction frame determine the geometric parameters of many wires, so the error of the prediction frame must be very small.

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Abstract

本发明公开了一种基于目标检测网络的寄生参数提取方法，属于寄生参数提取领域。方法包括如下步骤：建立寄生电容模式库；创建符合版图互连线特点的数据集；使用自建数据集训练目标检测网络，通过修改损失函数对网络进行优化；用训练过的网络对版图图片进行预测，对网络的预测结果进行后续处理，得到寄生参数值。本发明旨在为数字集成电路寄生参数模式库建立和模式匹配提供了一种简单，供选择的解决方案。

Description

一种基于目标检测网络的寄生参数提取方法 技术领域
本发明涉及寄生参数提取领域，具体涉及一种基于目标检测网络的寄生参数提取方法。
背景技术
寄生参数提取是在数字集成电路设计后端的一步流程，它从已完成布局布线的版图中提取互连线的寄生电阻和电容。随着工艺节点的推进，互连线引起的寄生电容、电阻会对电路时序的影响逐渐增大。同时，集成电路的规模越大，对寄生参数提取工具的提取能力和效率也提出了更高的要求。常用提取方法可以分为场解法和模式匹配法。模式匹配法根据几何结构、几何参数提前建立模式库，提取时将实际版图对照模式库，可以得出电阻、电容值，此方法更合适于大规模电路，但常因模式匹配错误产生误差，而且模式库的建立费时费力。
人工智能在工业化的应用为提取工具开辟了一条新道路。使用聚类算法自动建立模式库，取代冗长的手工建立过程。另外，匹配过程应用神经网络进行分类，可以提升匹配的效率和准确度。然而，以往的版图研究视角均为截面图，将三维的版图结构分割成单位长度的二维寄生参数后累加，而事实上，若将每层版图视为一张图像，则可以应用图像处理的方法，直接提取一层的平面信息。
发明内容
针对上述现有技术的不足，本发明提出了一种基于目标检测网络的寄生参数提取方法。简化模式库建立方式，并通过目标检测网络对版图中互连线的几何结构进行分类和定位，将网络输出结果与模式库对照，来实现精确的模式匹配。本发明旨在为数字集成电路寄生参数模式库建立和模式匹配提供了一种简单，供选择的解决方案。
为实现上述目的，本发明采用如下技术方案：一种基于目标检测网络的寄生参数提取方法，生成类似版图的图片集和标记文件，创建训练集，优化损失函数，训练目标检测网络，将其他版图图片输入到训练过的网络，网络会输出模式和坐 标信息，比对模式库，定位导线，得到寄生电容值。
具体步骤包括：
步骤1：建立寄生电容模式库；
步骤2：生成符合版图互连线特点的图片，并标注构建数据集；
步骤3：使用所述数据集训练目标检测网络，通过优化损失函数对目标检测网络进行优化；
步骤4：用训练过的目标检测网络对版图图片进行预测，对网络的预测结果进行后续处理，得到寄生参数值。
优选的，步骤1的具体步骤为：设定不同颜色表示不同导线层或导线交叠关系，并分别列出面电容关于几何结构(包括层关系、同一层导线间距范围)的电容公式查找表，耦合电容关于几何结构(同一层导体数)的电容公式查找表。
优选的，步骤2的具体步骤为：以设定好不同颜色的色块表示不同导线层或导线交叠关系(不同层导线的交叠关系或同一层导线的交叠关系)，在图片中央区域随机生成一些不同颜色、尺寸、垂直或水平的色块作为干扰背景，在干扰背景上，按照实际版图的交叠部分占导线的比例，随机生成代表导线交叠关系的目标颜色色块，并导出目标色块的类别与坐标值作为标注。
优选的，步骤3中依据面积预测这一具体应用优化目标检测网络的损失函数，具体步骤为：在原目标检测网络的损失函数，即目标损失、类别损失和预测框损失，加入一项面积损失；预训练以后，对各项损失前的系数进行超参数进化，得到各损失的最优系数。
优选的，步骤4包括：将版图文件描述的多层导线三维结构按照三视图可视化为图片，其中俯视图用于面电容提取，左视图和主视图用于耦合电容提取，按照模式尺寸将版图图片划分成若干张较小的图片，作为目标检测网络输入，目标检测网络对版图图片做出预测；预测分类结果得到几何结构，与模式库对照，得到电容计算公式，由预测框中心坐标定位出导线，由预测框坐标、大小得到几何参数(包括交叠面积，交叠部分的长度、宽度)，代入公式计算得到每根导线的寄生电容值。
有益效果：
1、本发明中的模式匹配过程使用了目标检测网络，这种网络是用于目标检测的深度神经网络，可以对图片中的目标进行分类和定位。以导线交叠结构作为检测目标，以仅含有互连线的版图图片作为网络输入，网络即可得到导线的类别，即模式，且根据预测框坐标可以得到导线在版图中的位置、交叠面积、交叠宽度、交叠长度等几何参数。由于目标检测网络已经发展到yolo v5，可以实现快速而准确的目标检测。网络的使用替代了复杂的匹配算法，并提高匹配准确度。
2、本发明中的模式库按照影响导线的几何结构进行模式分类，按照解析方法给出寄生面电容值和寄生耦合电容值计算公式，两者相加即为寄生电容值，具体的几何参数(如导线长度、宽度等)仅作为公式中的变量，因此不需要依据几何参数再细分模式，可以极大程度地缩小模式库规模，这样建立的模式库也适用于各种工艺尺寸。在匹配过程，将几何参数例如交叠面积值代入相应模式的电容解析公式，可以算出寄生电容值。
3、本发明中，应用不同的颜色以区分不同的层或交叠关系，该方法与图神经网络配合，提供了一种简单实用的层关系识别算法。
4、由于本发明首次将目标检测网络引入寄生参数提取领域，尚无已标注的版图图片集可以用来训练，故本发明中依据版图互连线特点自建数据集。数据集仅含有互连线，并依照真实版图中互连线的特点，可自动生成所需规模的图片集。该方法在模拟版图图片的同时，有效简化数据集，并省去了人工标注的巨大工作量。
附图说明
图1为寄生电容提取方法设计流程图；
图2为简化的寄生面电容模式库；
图3为目标检测网络的结构设计。
具体实施方式
下面结合附图及实施例对本发明做进一步说明。
图1为寄生电容提取方法设计流程图，首先设计模式库(如图2所示)和网 络结构(如图3(a),(b)所示)，接着进行算法设计。整体算法框架包含数据集建立、网络训练、版图提取三个部分：
(1)数据集建立
首先建立目标检测网络使用的数据集，需要符合仅含有互连线的版图的特点，仅含有互连线的版图体现为一些不同颜色、不同长度的色块，同时目标色块与干扰色块的比例、色块的长宽范围、色块在图中的分布区域等需要与真实的版图一致。
(2)网络训练
然后使用该数据集，进行网络训练并验证，若测试结果不理想，则修改损失函数，修改后的损失函数为：
loss＝λ objl obj+λ clsl cls+λ boxl box+λ areal area#(1)式中前三项为原目标检测网络的损失函数，即目标损失、类别损失和预测框损失的加权和，最后一项为加入的面积损失。或重新设计数据集，更改色块的长度范围，以优化训练结果，直到网络测试结果达到预期。
(3)版图预测
用训练完成的网络对版图图片进行预测，给出的分类便是模式库中的模式，所以网络预测的过程，也就是进行了模式匹配的过程，再对预测值进行导线匹配后，将交叠面积、交叠部分宽度、交叠部分长度等参数代入模式对应的计算公式进行计算，并从原始版图文件中直接读取其他需要的导线几何参数(包括导线间距、导线宽度)，最终得到寄生电容值。
图2为简化的寄生面电容模式库，该图所述的模式库仅为了说明，只考虑每层一根导线，共M0～M4五层金属，且面电容简化为平板电容，实际模式库将更加复杂。设定不同的RGB值以区分不同的层和层交叠关系，并写出单位电容值的表达式，得到模式库，每种层交叠关系和它对应的单位电容公式就是一种模式。层间距和介电常数值提前输入，再将网络输出的交叠面积和层关系与模式库对应，代入电容表达式即可计算出电容值，这就是电容的模式匹配过程。
图3为目标检测网络的结构设计。其中图3(a)为网络内部结构，使用了YOLO  v5s的网络模型，由输入端(Input)、骨干网络(Backbone)、颈部网络(Neck)和预测端(Prediction)四个部分构成。输入端对原始图片进行一些处理后输入网络；骨干网络由Conv卷积，BN批归一化，Leaky relu激活函数等模块构成，对特征图进行核心计算；颈部网络加入跨层结构，增强了网络特征融合的能力；预测端输出网络预测结果，包括类别信息和预测框信息。
图3(b)为网络外部结构，即网络的输入和输出设计，对于网络的输入输出情况可分为训练过程和版图提取过程。训练过程以数据集作为输入，输出的类别、预测框大小和预测框中心坐标均用来计算如精确率、召回率、均值平均精度(Mean Average Precision,mAP)等表示网络准确率的参数，除此之外，由于使用网络完成的任务有预测交叠面积，故预测框大小还要用以计算面积准确率。对于版图提取过程，输入版图图片，输出的类别表示层关系，即哪两层金属相交叠，预测框大小表示交叠面积，预测框的边长表示交叠部分的宽度和长度，预测框中心坐标可定位导线，即所在导线，或所在的导线交叠层关系。可见，预测框的坐标、大小决定了诸多导线的几何参数，所以预测框的误差必须做到很小。
以上实施例仅为说明本发明的技术思想，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想在所公开技术方案基础上所做的任何改动，均落入本发明保护范围之内。

Claims (6)

  1. 一种基于目标检测网络的寄生参数提取方法，其特征在于，包括如下步骤：
    步骤1：建立寄生电容模式库；
    步骤2：生成符合版图互连线特点的图片，并标注构建数据集；
    步骤3：使用所述数据集训练目标检测网络，通过优化损失函数对目标检测网络进行优化；
    步骤4：用训练过的目标检测网络对版图图片进行预测，对网络的预测结果进行后续处理，得到寄生参数值。
  2. 根据权利要求1所述的一种基于目标检测网络的寄生参数提取方法，其特征在于，步骤1的具体步骤为：设定不同颜色表示不同导线层、不同层导线的交叠关系或同一层导线的交叠关系，并列出一张几何结构对应于电容公式的查找表构建寄生电容模式库。
  3. 根据权利要求1所述的一种基于目标检测网络的寄生参数提取方法，其特征在于，步骤2的具体步骤为：以设定好不同颜色表示不同导线层的色块，在图片中随机生成一些不同颜色、不同尺寸、垂直或水平的色块作为干扰背景，在干扰背景上随机生成代表不同交叠关系的目标颜色色块，并导出目标色块的模式类别与坐标值作为标注。
  4. 根据权利要求3所述的一种基于目标检测网络的寄生参数提取方法，其特征在于，目标色块与干扰色块的数量比例设置在实际版图情况的比例值附近，色块长度、宽度范围参照真实导线长度、宽度取值范围，色块在图中的分布集中在中央区域，色块形状为长方形。
  5. 根据权利要求1所述的一种基于目标检测网络的寄生参数提取方法，其特征在于，步骤3中依据面积预测这一具体应用优化目标检测网络的损失函数，具体步骤为：在原目标检测网络的损失函数，即目标损失、类别损失和预测框损失，加入一项面积损失；预训练以后，对各项损失前的系数进行超参数进化，得到各损失的最优系数。
  6. 根据权利要求1所述的一种基于目标检测网络的寄生参数提取方法，其特征在于，步骤4包括：将版图文件可视化为图片，作为目标检测网络输入，目标检测网络对版图图片做出预测；预测分类结果与模式库对照，得到电容计算公 式，由预测框中心坐标定位出导线，由预测框坐标、大小得到交叠面积、交叠部分宽度、交叠部分长度，代入公式计算得到每根导线的寄生电容值。
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